02/2005
ACD2206
CATV/TV/Video Downconverter
with Dual Synthesizer
Data Sheet - Rev 2.1
Figure 1: Downconverter Block Diagram
FEATURES
• Integrated Downconverter
• Integrated Dual Synthesizer
• 256 QAM Compatibility
• Single +5 V Power Supply Operation
• Low Noise Figure: 8 dB
• High Conversion Gain: 31 dB
• Low Distortion: -53 dBc
• Three-Wire Interface
• Small Size
• -40 °C to +85 °C
• RoHS-Compliant Package Option
APPLICATIONS
• Set Top Boxes
• CATV Video Tuners
• Digital TV Tuners
• CATV Data Tuners
• Cable Modems
S8 Package
28 Pin SSOP
PRODUCT DESCRIPTION
The ACD2206 uses both GaAs and Si technology
to provide the downconverter and dual synthesizer
functions in a double conversion tuner gain block,
local oscillator, balanced mixer, IF Amplifier, and
dual synthesizer. The specifications meet the
requirements of CATV/TV/Video and Cable Modem
Data applications. The ACD2206 is supplied in a 28
lead SSOP package and requires a single +5 V
supply voltage. The IC is well suited for applications
where small size, low cost, low auxiliary parts count,
and no-compromise performance is important. It
provides for cost reduction by lowering the
component and packaged IC count and decreasing
the amount of labor-intensive production alignment
steps, while significantly improving performance
and reliability.
Figure 2: Dual Synthesizer Block Diagram
RF2: 64/65
Prescaler
18 Bit RF2
N Counter
RF2
Phase
Detector
RF2
Charge
Pump
RF1
Phase
Detector
RF1
Charge
Pump
15 Bit RF2
R Counter
15 Bit RF1
R Counter
18 Bit RF1
N Counter
RF1: 64/65
Prescaler
Oscillator
22 Bit
Data Registar
CPU
CPDRFD
REFIN
REFOUT
RFU
Clock
Data
Enable
V
IF
+IF
OUT
+
OSC
OUT
T
CKT
RF
IN
+
Phase Splitter
Low Noise
Amplifier Mixer
RF
IN
-
V
IF
+IF
OUT-
2Data Sheet - Rev 2.1
02/2005
ACD2206
Figure 3: Pinout
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
RFIN+ VIF +IFOUT+
VSS
OSCGND
EN
DATA
TCKT
ISET
CLK
GND
REFIN
REFOUT
VSS VSS
GND
VSS
GND
RFD
OSCOUT
CPD
V
SUP
CPU
GND
RFU
VSYN
RFIN-
OSCGND
VIF +IFOUT-
Data Sheet - Rev 2.1
02/2005 3
ACD2206
NIP EMAN NOITPIRCSED NIP EMAN NOITPIRCSED
1FR
+NI
retrevnocnwoD
tupnIFRlaitnereffiD 82V
FI
FI+
+TUO
reifilpmAFIlaitnereffiD
ylevitcudnI,tuptuO
V+otdelpuoc
DD
2FR
-NI
retrevnocnwoD
tupnIFRlaitnereffiD 72 V
FI
FI+
TUO
-
reifilpmAFIlaitnereffiD
ylevitcudnI,tuptuO
V+otdelpuoc
DD
3DNG dnuorGretrevnocnwoD
)detcennocebtsuM( 62DNG dnuorGretrevnocnwoD
)detcennocebtsuM(
4I
TES
trebliGretrevnocnwoD
ecruoStnerruClleC
rotsiseR
52V
PUS
ylppuSretrevnocnwoD
V+(
DD
)
5T
TKC
troPtupnIrotallicsO
)noitcennoctiucricknaT( 42CSO
TUO
tuptuOrotallicsO
otdetcennoC(
)tupnIFRrezisehtnyS
6CSO
DNG
tiucriCknaTrotallicsO
ebottoN(dnuorG
rehtoynaotdetcennoc
)dnuorgtiucric
32DNG dnuorGretrevnocnwoD
)detcennocebtsuM(
7CSO
DNG
6niPsaemaS22DNG dnuorGretrevnocnwoD
)detcennocebtsuM(
8V
SS
dnuorGrezisehtnyS
)deriuqeR( 12V
SS
dnuorGrezisehtnyS
)deriuqeR(
9V
SS
dnuorGrezisehtnyS
)deriuqeR( 02V
SS
dnuorGrezisehtnyS
)deriuqeR(
01NEelbanEecafretnIeriW-391FR
D
rezisehtnyS
tupnIFRretrevnocnwoD
11ATADataDecafretnIeriW-381PC
D
rezisehtnyS
retrevnocnwoD
tuptuOpmuPegrahC
21KLCkcolCecafretnIeriW-371PC
U
retrevnocpUrezisehtnyS
tuptuOpmuPegrahC
31FER
NI
tupnIecnerefeRlatsyrC61FR
U
retrevnocpUrezisehtnyS
tupnIFR
41FER
TUO
tuptuOecnerefeRlatsyrC51V
NYS
ylppuSrezisehtnyS
V+(
DD
)
Table 1: Pin Description
4Data Sheet - Rev 2.1
02/2005
ACD2206
RETEMARAP NIM PYT XAM TINU
seicneuqerFretrevnocnwoD
)1(
)FR(tupnIFR
)FI(tuptuOFI
)OL(rotallicsOlacoL
009
53
568
-
-
-
0021
051
0531
zHM
seicneuqerFrezisehtnyS
FR(rezisehtnySretrevnocpU
U
)
FR(rezisehtnySretrevnocnwoD
D
)
FER(rotallicsOecnerefeR
NI
)
rotceteDesahP
004
004
2
-
-
-
4
-
0012
0041
02
01
zHM
V:egatloVylppuS
DD
)82,72,52,51snip(57.4+5+52.5+CDV
T:erutarepmeTgnitarepOtneibmA
A
04--58+C°
ELECTRICAL CHARACTERISTICS
Table 2: Absolute Minimum and Maximum Ratings
Stresses in excess of the absolute ratings may cause permanent damage.
Functional operation is not implied under these conditions. Exposure to absolute
ratings for extended periods of time may adversely affect reliability.
The device may be operated safely over these conditions; however, parametric
performance is guaranteed only over the conditions defined in the electrical
specifications.
Table 3: Operating Ranges
Notes:
(1) Mixer operation is possible beyond these frequencies with slightly reduced
performance.
RETEMARAP NIM XAM TINU
)82&72,52snip(egatloVylppuS
)51nip(
-
-
9+
5.6+ CDV
61,41hguorht01snipnoegatloV
Vhtiw91hguorht
SS
V0= 3.0-V
NYS
3.0+CDV
)5&2,1snip(segatloVtupnI-0CDV
)2&1snip(rewoPtupnI
)5nip(
)91&61,31snip(
-
-
-
01+
71+
02+
mBd
erutarepmeTegarotS55-051+C°
erutarepmeTgniredloS-062C°
emiTgniredloS-4ceS
,ecnadepmIlamrehT θ
CJ
-04°W/C
Data Sheet - Rev 2.1
02/2005 5
ACD2206
RETEMARAP NIM PYT XAM TINU
niaGnoisrevnoC
)1(
8213- Bd
erugiFesioNBSS
)1(
-801Bd
noitaludoMssorC
,)1()4(,)2(
-95-- cBd
3
dr
noitrotsiDnoitaludomretnIredrO
)3DMI(
)4(,)3(,)1(
-- 35-cBd
3enoT-2
dr
tnioPtpecretnItupnIredrO
)3PII(
,)1()4(,)3(
01--- mBd
)tesffOzHK01@(esioNesahPOL
)1(
-09-5.58-zH/cBd
)42nip(rewoPtuptuOOL
)1(
-5-- mBd
tuptuOFI@suoirupS
scinomraHdnaslangiSOL
lennahCtuptuOnihtiWstaeB
zHM002ot2morfstaeBrehtO
suoirupSrehtO
-
-
-
-
01-
07-
05-
01-
-
-
-
-
mBd
cBd
mBd
mBd
)82&72nip(tnerruCylppuSFI
)4(,)1(
-011- Am
ylppuSrexiMdnarettilpSesahP,csO
)52nip(tnerruC -07- Am
noitpmusnoCrewoP-009-Wm
RETEMARAP NIM PYT XAM TINU STNEMMOC
ytivitisneStupnIralacserP
FR:retrevnocpU
U
)61nip(
)1(
FR:retrevnocnwoD
D
)91nip(
)2(
7-
31-
-
-
02+
02+
mBd
)ycneuqerfgnitareporevo(
)31nip(ytivitisneSrotallicsOecnerefeR-5.0-V
p-p
tnerruCtuptuOpmuPegrahC
)3(
KNIS
ECRUOS
-
-
52.1
52.1-
-
-Am
tnerruCylppuS-5305Am
noitpmusnoCrewoP-561052Wm
Table 4: Electrical Specifications - Downconverter Section
(TA = 25 ⋅C, VDD = +5 VDC, RFIN = 1087 MHz, IFOUT = 45 MHz)
Notes:
(1) As measured in ANADIGICS test fixture.
(2) Two tones: 1085 and 1091 MHz, -40 dBm each, 1091 MHz tone AM-modulated 99% at 15 kHz.
(3) Two tones: 1085 and 1091 MHz, -30 dBm each.
(4) R1 = 0 Ohms
Table 5: Electrical Specifications - Synthesizer Section
(TA = +25 ⋅C, VDD = +5 VDC)
Notes:
(1) Measured at 250 kHz comparison frequency.
(2) Measured at 62.5 kHz comparison frequency.
(3) CPU and CPD = Vcc/2.
6Data Sheet - Rev 2.1
02/2005
ACD2206
DATA N20: MSB N19 N10 N9 C2 C1: LSB
(R20: MSB) (R19) R10 (R9) (C2) (C1: LSB)(R8)
CLOCK
LE
LE
OR
t
CS
t
CH
t
CWH
t
ES
t
EW
t
CWL
RETEMARAP NIM PYT XAM TINU
V:tupnIhgiHcigoL
H
)21,11,01snip(0.2--V
V:tupnIwoLcigoL
L
)21,11,01snip(--8.0V
noitpmusnoCtnerruCtupnIcigoL
)21,11,01snip( -- 10.0Am
t:emiTpUteSkcolCotataD
SC
05-- sn
t:emiTdloHkcolCotataD
HC
01-- sn
t:hgiHhtdiWesluPkcolC
HWC
05-- sn
t:woLhtdiWesluPkcolC
LWC
05-- sn
t:emiTputeSelbanEdaoLotkcolC
SE
05-- sn
t:htdiWesluPelbanEdaoL
WE
05-- sn
t:emiTesiR
R
-01- sn
t:emiTllaF
F
-01- sn
Figure 4: Serial Data Input Timing
Table 6: Digital Interface Specifications
(TA = 25 ⋅C, VDD = +5 VDC, ref. Figure 4)
Data Sheet - Rev 2.1
02/2005 7
ACD2206
PERFORMANCE DATA
Figure 5: Typical Upconverter Prescalar
Sensitivity vs. Supply Voltage
(TA = +25 °C, fLO1 = 2100 MHz)
Figure 6: Typical Upconverter Prescalar
Sensitivity vs. Local Oscillator Frequency
(TA = +25 °C, VDD = +5 V)
Figure 8: Typical Downconverter Prescalar
Sensitivity vs. Local Oscillator Frequency
(TA = +25 °C, VDD = +5 V)
Figure 7: Typical Downconverter Prescalar
Sensitivity vs. Supply Voltage
(TA = +25 °C, fLO2 = 1000 MHz)
Figure 9: Typical Local Oscillator
Output Power vs. Supply Voltage
(TA = +25 °C, fLO2 = 1042 MHz)
-9.0
-8.5
-8.0
-7.5
-7.0
4.7 4.8 4.9 5.0 5.1 5.2 5.3
Supply Voltage (V)
Prescalar Sensitivity (dBm)
-35
-30
-25
-20
-15
-10
-5
500 700 900 1100 1300 1500 1700 1900 2100
LO1 Frequency (MHz)
Prescalar Sensitivity (dBm)
-18.0
-17.5
-17.0
-16.5
-16.0
4.7 4.8 4.9 5.0 5.1 5.2 5.3
Supply Voltage (V)
Prescalar Sensitivity (dBm)
-24
-22
-20
-18
-16
-14
-12
400 600 800 1000 1200 1400
LO2 Frequency (MHz)
Prescalar Sensitivity (dBm)
-7.0
-6.5
-6.0
-5.5
-5.0
-4.5
4.7 4.8 4.9 5.0 5.1 5.2 5.3
Supply Voltage (V)
Output Power (dBm)
8Data Sheet - Rev 2.1
02/2005
ACD2206
TCELES
STIB ROFRETSIGERNOITANITSED
ATADLAIRES
S
2
S
1
00 2LLProfretsigeRrediviDecnerefeR
01 2LLProfretsigeRrediviDniaM
10 1LLProfretsigeRrediviDecnerefeR
11 1LLProfretsigeRrediviDniaM
EDIVID
ROITAR
R
51
R
41
R
31
R
21
R
11
R
01
R
9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
3 0000000000000 11
4 000000000000 100
- ---------------
76723 111111111111111
22 12 02 91 81 71 61 51 41 31 21 11 01 9 8 7 6 5 4 3 2 1
edoMmargorPR,oitaRediviDrediviDecnerefeRtceleS
D
5
D
4
D
3
D
2
D
1
R
51
R
41
R
31
R
21
R
11
R
01
R
9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
S
2
S
1
LOGIC PROGRAMMING
Notes:
Divide ratios less than 3 are prohibited.
LSBMSB
Synthesizer Register Programming
The ACD2206 includes two PLL synthesizers. Each
synthesizer contains programmable Reference and
Main dividers, which allow a wide range of local
oscillator frequencies. The 22-bit registers that control
the dividers are programmed via a shared three-wire
bus, consisting of Data, Clock and Enable lines.
The data word for each register is entered serially
in order with the most significant bit (MSB) first and
the least significant bit (LSB) last. The rising edge
of the Clock pulse shifts each data value into the
register. The Enable line must be low for the duration
of the data entry, then set high to latch the data into
the register. (See Figure 4.)
Register Select Bits
The two least significant bits of each register are
register select bits that determine which register is
programmed during a particular data entry cycle.
Table 7 indicates the register select bit settings used
to program each of the available registers.
Table 7: Register Select Bits
Table 9: Reference Divider R Counter Bits
Table 8: Reference Divider Registers
Reference Divider Programming
The reference divider register for each synthesizer
consists of fifteen divider bits, five program mode
bits and the two register select bits, as shown in
Table 8. The fifteen divider bits allow a divide ratio
from 3 to 32767, inclusive, as shown in Table 9.
Data Sheet - Rev 2.1
02/2005 9
ACD2206
RAV NOITINIFED
f
OCV
egatlovlanretxefoycneuqerftuptuoderiseD
)OCV(rotallicsodellortnoc
B)7402ot3(retnuocBfooitarediviD
A)B<A,P<A<0(retnuocAfooitarediviD
f
CSO
rolatsyrcecnereferlanretxefoycneuqerF
rotallicso
R)76723ot3(retnuocRfooitarediviD
P)46=P(ralacserpfosuludomteserP
AFOEULAV
RETNUOC
A
7
A
6
A
5
A
4
A
3
A
2
A
1
0 0000000
1 000000 1
- -------
721 1111111
BFOEULAV
RETNUOC
B
11
B
01
B
9
B
8
B
7
B
6
B
5
B
4
B
3
B
2
B
1
3 000000000 11
4 00000000 100
- -----------
7402 11111111111
22 12 02 91 81 71 61 51 41 31 21 11 01 9 8 7 6 5 4 3 2 1
margorP
edoM retnuoCBretnuoCAtceleS
C
2
C
1
B
11
B
01
B
9
B
8
B
7
B
6
B
5
B
4
B
3
B
2
B
1
A
7
A
6
A
5
A
4
A
3
A
2
A
1
S
2
S
1
Main Divider Programming
The main divider register for each synthesizer
consists of seven A counter bits, eleven B counter
bits, two program mode bits and the two register
select bits, as shown in Table 10. The main divider
divide ratio, N, is determined by the values in the A
and B counters. The eleven B Counter bits and
allowed values are shown in Table 11, and the seven
A Counter bits and allowed values are shown in
Table 10: Main Divider Registers
Table 12: Main Divider A Counter Bits
Notes:
B > A, A < P
LSB
MSB
Table 11: Main Divider B Counter Bits
Notes:
B > A, Divide ratios less than 3 are prohibited.
Table 12. Note that there are some limitations on
the ranges of the values for each counter.
Pulse Swallow Function
The VCO output frequency for the local oscillator is
computed using the following equation; the
variables are defined in Table 13:
fVCO = N x fOSC/R, where N = [(P x B) + A]
Table 13: Variable Definitions
10 Data Sheet - Rev 2.1
02/2005
ACD2206
(1)
(2)
VCO INPUT VOLTAGE
VCO OUTPUT
FREQUENCY
S
2
S
1
D
1
00 ytiraloProtceteDesahP2LLP
10 ytiraloProtceteDesahP1LLP
Table 15: Phase Detector Polarity Selection
Programmable Modes
Each register contains bits set aside for programming
different modes of operation in the synthesizers.
Currently, the only programmable mode is the polarity
of the phase detector in each of the synthesizers. Bit
D1 in each reference divider register controls this
feature. Bits D2 through D5 in the reference divider
registers and bits C1 and C2 in the main divider
registers are reserved bits that should be set to
logic low for proper operation of the synthesizer.
Table 14: Phase Detector Polarity Bit
Figure 10: VCO Characteristics
Setting Phase Detector Polarity
Table 14 shows how bit D1 of each reference divider
register controls the polarity of the phase detector
associated with each PLL. The correct setting is
determined by using Table 15 and Figure 10.
Synthesizer Programming Example
The following example for programming the two synthesizers in the ACD2206 details the calculations used to
determine the required value of each bit in all four registers:
Requirements
Desired CATV input channel: “HHH” - 499.25 MHz picture carrier (501 MHz digital channel center frequency)
(Second) IF picture carrier output frequency: 45.75 MHz (44 MHz digital channel center frequency)
First IF frequency: 1087.75 MHz
Phase detector comparison frequency for down converter (also tuning increment): 62.5 KHz
Phase detector comparison frequency for up converter: 250 KHz
Crystal reference oscillator frequency: 4 MHz
Calculation of Reference Divider Values
The value for each reference divider is calculated by dividing the reference oscillator frequency by the desired
phase detector comparison frequency:
R = fOSC / fPD
For the down converter, the 4 MHz crystal oscillator frequency and the 62.5 KHz phase detector comparison
frequency are used to yield RPLL2 = 4 MHz / 62.5 KHz = 64, and so the bit values for the down converter
R counter are RPLL2 = 000000001000000.
D
1
ESAHP
ROTCETED
YTIRALOP
OCV
SCITSIRETCARAHC
)01ERUGIFEES(
0evitageN)2(evruc
1evitisoP)1(evruc
Data Sheet - Rev 2.1
02/2005 11
ACD2206
22 12 02 91 81 71 61 51 41 31 21 11 01 9 8 7 6 5 4 3 2 1
edoMmargorPretnuoCRrediviDecnerefeRtceleS
D
5
D
4
D
3
D
2
D
1
R
51
R
41
R
31
R
21
R
11
R
01
R
9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
S
2
S
1
0000 100000000 100000000
000000000000000 10000 10
22 12 02 91 81 71 61 51 41 31 21 11 01 9 8 7 6 5 4 3 2 1
margorP
edoM retnuoCBrediviDniaMretnuoCArediviDniaMtceleS
C
2
C
1
B
11
B
01
B
9
B
8
B
7
B
6
B
5
B
4
B
3
B
2
B
1
A
7
A
6
A
5
A
4
A
3
A
2
A
1
S
2
S
1
0 0 00 100000 1000100000 0 1
0 0 0000 11000 110001100 1 1
LSBMSB
LSB
MSB
For the up converter, the 4 MHz crystal oscillator frequency and the 250 KHz phase detector comparison
frequency are used to yield RPLL1 = 4 MHz / 250 KHz = 16, and so the bit values for the up converter R counter
are RPLL1 = 000000000010000.
Calculation of Main Divider Values
The values for the A and B counters are determined by the desired VCO output frequency for the local
oscillator and the phase detector comparison frequency:
N = fVCO / f PD B = trunc(N / P) A = N - (B x P)
The down converter local oscillator frequency will be 1087.75 MHz - 45.75 MHz = 1042 MHz in this example.
The main divider ratio for the down converter, then, is NPLL2 = 1042 MHz / 62.5 KHz = 16672. Since P = 64 in the
ACD2206, BPLL2 = trunc(16672 / 64) = 260, and APLL2 = 16672 - (260 x 64) = 32. These results give bit values of
BPLL2 = 00100000100 and APLL2 = 0100000 for the B and A counters.
The up converter local oscillator frequency will be 499.25 MHz + 1087.75 MHz = 1587 MHz in this example.
Therefore, NPLL1 = 1587 MHz / 250 KHz = 6348, BPLL1 = trunc(6348 / 64) = 99, and APLL1 = 6348 - (99 x 64) = 12.
These results give bit values of BPLL1 = 00001100011 and APLL1 = 0001100 for the B and A counters.
Phase Detector Polarity
Assuming the VCO for the up converter has a negative slope, the phase detector polarity for PLL1 should be
negative, and D1PLL1 = 1. If the VCO for the down converter has a positive slope, the phase detector polarity for
PLL2 should be positive, and D1PLL2 = 0.
In summary, for this example, the four register programming words are shown in Tables 16 and 17:
Table 16: PLL1 and PLL2 Main Divider Register Bits
for Synthesizer Programming Example
Table 17: PLL1 and PLL2 Reference Divider Register Bits
for Synthesizer Programming Example
12 Data Sheet - Rev 2.1
02/2005
ACD2206
NIP NOITCNUF
1kcolC
2ataD
3dnuorG
4elbanE
5CDV5+
6CDV03+
NIP NOITCNUF
FRtupnIFRretrevnocnwoD
FRtupnIFRretrevnocnwoD
FI)dednEelgniS(tuptuOFI
tuOCFAtiucriCgninuTrotallicsOoT
nIOLFRrezisehtnyS
U
tupnI
APPLICATION INFORMATION
Figure 11: PC Board Layout Top View
Figure 13: PC Board Layout Bottom View
Figure 12: PC Board Layout Mid View
Figure 14: Evaluation Fixture
Table 18: J1 Header Pinout Table 19: Fixture Pinout
Balun
J1
RF IF
AFC
Out
LO
In
RF
1
4MHz Xtal
ACD2206
Data Sheet - Rev 2.1
02/2005 13
ACD2206
227
16
15
1
14
22
24
25
23
21
20
19
18
17
28
26
9
8
7
10
6
11
5
12
4
13
3
RF
IN+
OSC
GND
OSC
GND
T
CKT
I
SET
GND
RF
IN-
DATA
CLK
REF
IN
REF
OUT
V
SYN
V
SS
GND
V
SS
GND
RF
D
CP
D
V
SUP
OSC
OUT
CP
U
V
IF
+I
F
OUT-
RF
U
V
IF
+IF
OUT+
V
SS
V
SS
EN
GND
C20
R7
D1
ACD2206
R1
C2
C3
L1
C8
C21C23
C22
L3
C24
C12C11C10
R8 L2
R9
C13
R10
C14
C15
R11
C17
C16
R13
RF
C1
RF
C9
+5V
R6
X1
C7
LO
IN
DT1
IF
+5V
R12
AFC
OUT
Q1
C18C19
+30V
R2
R3
R4
C4 C5 C6
1
6
5
4
3
2
J1
+30V
+5V
R5
Figure 15: Evaluation Fixture Schematic
14 Data Sheet - Rev 2.1
02/2005
ACD2206
#METI EULAV EZIS NOITPIRCSED #TRAP YTQ RODNEV
,2C,1C
02C
Fp0013060roticapac-pihC
V05J101GOC93MRG
3
ataruM
3CFp93060roticapac-pihC
V05C090GOC93MRG
1
ataruM
8C,7CFp033060roticapac-pihC
V05J003GOC93MRG
2
ataruM
21CFu022AVV01
seireS
roticapaC
DN-TC0402ECP
1
YEK-IGID
,11C,9C
,12C,41C
22C
Fu1.3060roticapac-pihC
V61Z401V5Y93MRG
5
ataruM
32C,01CFp00013060roticapac-pihC
V05K201R7X93MRG
2
ataruM
71C,51CFp00743060roticapac-pihC
V52K274R7X93MRG
2
ataruM
61CFu13060dael-laidaR
roticapac-pihC
050-K-501-R7X-311EPR
1
ataruM
81CFu10.3060roticapac-pihC
V52K301R7X93MRG
1
ataruM
91CFu01V53
TNAT
.paCseireSET
DN-TC6016SCP
1
YEK-IGID
42CFp513060roticapac-pihC
V05J051GOC93MRG
1
ataruM
31CFp00653060roticapac-pihC
V05K265R7X93MRG
1
ataruM
,5C,4C
6C
Fp333060roticapac-pihC
V05J033GOC93MRG
3
ataruM
8R153060rotsiseRpihC
015JYSG3-JRE
1
cinosanaP
5RK013060rotsiseRpihC
301JYSG3-JRE
1
cinosanaP
4R,3R,2RK23060rotsiseRpihC
202JYSG3-JRE
3
cinosanaP
21RK13060rotsiseRpihC
201JYSG3-JRE
1
cinosanaP
11RK7.23060rotsiseRpihC
272JYSG3-JRE
1
cinosanaP
7RK33060rotsiseRpihC
203JYSG3-JRE
1
cinosanaP
31RK223060rotsiseRpihC
322JYSG3-JRE
1
cinosanaP
01RK2.83060rotsiseRpihC
228JYSG3-JRE
1
cinosanaP
Table 20: Evaluation Fixture Parts List
Data Sheet - Rev 2.1
02/2005 15
ACD2206
#METI EULAV EZIS NOITPIRCSED #TRAP YTQ RODNEV
9R,6R,1R03060rotsiseRpihC
3060CZ
3
DCR
1LHn6.55080rotcudnI
CB-X050-SC5080
1
tfarclioC
2LHn865080rotcudnI
CB-X086-SC5080
1
tfarclioC
3LHn0725080rotcudnI
CB-X172-SC5080
1
tfarclioC
1D542VS1edoidrotcaraV
542VS1
1
abihsoT
1TD1:4remrofsnarT
2-1-4CTE
1
.cnI,MOC-A/M
aciremAhtroN
1QV03
DMS
32-TOSNPNrotsisnarT
.lraD
DN-TC31ATMMF
1
YEK-IGID
1XZHM4latsyrC
DN-TC8162ES
1YEK-IGID
Table 20: Evaluation Fixture Parts List continued
16 Data Sheet - Rev 2.1
02/2005
ACD2206
PACKAGE OUTLINE
Figure 16: S8 Package Outline - 28 Pin SSOP
Data Sheet - Rev 2.1
02/2005 17
ACD2206
NOTES
18 Data Sheet - Rev 2.1
02/2005
ACD2206
NOTES
Data Sheet - Rev 2.1
02/2005 19
ACD2206
NOTES
20
IMPORTANT NOTICE
ANADIGICS, Inc. reserves the right to make changes to its products or to discontinue any product at any time without
notice. The product specifications contained in Advanced Product Information sheets and Preliminary Data Sheets are
subject to change prior to a product’s formal introduction. Information in Data Sheets have been carefully checked and are
assumed to be reliable; however, ANADIGICS assumes no responsibilities for inaccuracies. ANADIGICS strongly urges
customers to verify that the information they are using is current before placing orders.
WARNING
ANADIGICS products are not intended for use in life support appliances, devices, or systems. Use of an ANADIGICS
product in any such application without written consent is prohibited.
ANADIGICS, Inc.
141 Mount Bethel Road
Warren, New Jersey 07059, U.S.A
Tel: +1 (908) 668-5000
Fax: +1 (908) 668-5132
URL: http://www.anadigics.com
E-mail: Mktg@anadigics.com
Data Sheet - Rev 2.1
02/2005
ACD2206
ORDERING INFORMATION
REBMUNREDRO ERUTAREPMET
EGNAR
EGAKCAP
NOITPIRCSED GNIGAKCAPTNENOPMOC
1P8S6022DCA04-° 58+otCC°POSSniP82leerrepseceip0053,leeR&epaT
0P8S6022DCA04-° 58+otCC°POSSniP82ebutrepseceip05,sebuT
1P8SR6022DCA04-° 58+otCC°tnailpmoC-SHoR
POSSniP82 leerrepseceip0053,leeR&epaT
