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Renesas Technology Home Page: http://www.renesas.com
Renesas Technology Corp.
Customer Support Dept.
April 1, 2003
To all our customers
Cautions
Keep safety first in your circuit designs!
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Hitachi 16-Bit Single-Chip Microcomputer
H8S/2282 Series
H8S/2282F-ZTATTM
HD64F2282
H8S/2282
HD6432282
H8S/2281
HD6432281
Hardwa re Manual
ADE-602-241
Rev 1.0
02/13/02
Hitachi, Ltd.
Rev. 1.0, 02/02, Page ii of xxviii
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi’s or any third party’s
patent, copyright , trademark, or other intellectual propert y rights for information c ontained in
this docum ent. Hitachi bears no responsibility for problems tha t may a rise with third party’s
rights, including intellectual property right s, in connection with use of the information
contained in this document.
2. Products and product specifications ma y be subject to change without noti ce. Confirm t hat you
have received t he latest product sta ndards or specifications before final design, purchase or
use.
3. Hitachi makes every a t tempt to ensure tha t its products are of high quality and reliability.
However, c ontact Hitachi’s sales office before using the product in an a pplication that
demands especially high quality and reliability or where its failure or malfunction may directly
threaten human l ife or cause risk of bodily i njury, such as aerospace, aeronautics, nuclear
power, combus tion cont rol , trans port at ion , traffic, safety equipmen t or medic al equip me nt for
life support.
4. Design your application so that the product is used wit hin the ra nges guarant eed by Hitachi
particularly for maximum rating, operating supply voltage range, heat radiation characteristics,
installation conditions and other characteristics. Hitachi bears no responsibility for failure or
damage when used beyond the guaranteed ranges. Even within the guaranteed ranges,
consider normally fore seeable fai lure rates or failure modes in semiconductor devices and
employ systemic measures such a s fail-safe s, so t hat the equi pment incorpora ting Hitachi
product does not ca use bodily injury, fire or othe r consequential dama ge due t o operation of
the Hitachi product.
5. Thi s produc t is not designed t o be radiation resistant .
6. No one i s permitted to reproduce or duplicate, in any form, the whole or part of this document
without wri tten approval from Hitachi.
7. Contact Hitachi’s sales office for any questions regarding t his doc ument or Hitachi
semiconductor products.
Rev. 1.0, 02/02, Pag e iii of xxviii
General Precau t ions on the Handling of Produ cts
1. Treatment of NC Pins
Note: Do not connect anything to the NC pins.
The NC (not conne cted) pins are not connected to any of the internal circuitry; they are
used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.
2. Treatment of Unused Input Pins
Note: Fix all unused input pins to high or low l e vel.
Generally, the input pins of CMOS product s are high-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a pass-
through current fl ows int ernally, and a malfunction may occur.
3. Processing before Initialization
Note: When powe r is fi rst suppl ied, the product’s state is undefined. The states of internal
circuits are undefi ned unti l full power is suppl i ed throughout the chip and a low le vel is
input on t he reset pin. During the period where the states a re undefi ned, the regist e r
settings a nd the out put state of each pin are also undefined. Design your system so that it
does not malfunction because of processing while it i s in t hi s undefi ned state. For those
products which have a reset function, reset the LSI immediately after the power supply has
been turned on.
4. Prohibition of access to undefi ned or reserved addre ss
Note: Access to undefined or reserved addresses is prohibited.
The undefined or reserved addre sses may be used to e xpand functions, or test re gisters
may have been be allocated to these address. Do not access these registers: the system’s
operation is not guarant ee d if they are access ed .
Rev. 1.0, 02/02, Page iv of xxviii
Conf igur at io n of th is Manua l
This manual comprises the following items:
1. Precautions in Relation to this Product
2. Configuration of this Ma nual
3. Overview
4. Table of Contents
5. Summary
6. Description of Functional Modules
• CPU and System-Control Modules
• On-chip Peri pheral Modules
The configuration of the functional description of each module differs according t o the
module. However, the generic style includes the following items:
i) Features
ii) I/O pins
iii) Description of Registers
iv) Description of Operation
v) Usage: Points for Caution
When designing an application system that includes this LSI, take the points for caution into
account. Each section includes poi nts for caut i on in relation to the descriptions given, and points
for caut i on in usage are gi ven, a s required, as the fi nal part of each section.
7. Li st of Registers
8. El ectrical Characteristics
9. Appendix
• Product-typ e cod es and external dimensions
• Major revisions or adde nda in this version of the manual (only for revised ve rsions)
The history of revisions is a summary of sections t hat have bee n revised a nd sections t hat have
been added to earlier versions. This does not include all of the revised contents. For details,
confirm by referring t o the main de scription of this m anual.
10.Appendix/Appendices
Rev. 1.0, 02/02, Page v of xxviii
Preface
This LSI i s a single-chip mi crocomputer made up of the high-speed H8S/2000 CPU as its core,
and the p eripheral fun ctions r equire d to co nfigure a sys tem.
This LSI i s equi pped with ROM, RAM, a 16-bit timer pul se uni t, a wa tchdog timer, seri al
communication interfaces, the Hitachi cont roller area network, an A/D converter, a motor cont rol
PWM time r, an LCD control ler/driver (L CD), a clock pulse gene rator, and I/O ports as on-chip
peripheral modules. This LSI is suitable for use as an embedded processor for high-level control
systems. Its on-chip ROM is flash memory (F-ZTATTM*) that provi des flexibility as it can be
reprogramme d in no time to cope with all situa tions from the early stages of mass production to
full-scale mass production. T his is particularly a pplicable to application devices with
specifications that will most probably c hange.
Note: * F-ZTATTM is a trademark of Hitachi, Ltd.
Target Use rs: This manual was wri tten for users who will be using the H8S/2282 Series in the
design of application systems. Target users are expected to understand the
fundamentals of electrical ci rcuits, logi cal circui t s, and mi c rocompute rs.
Objective: This manual was written to explain the hardware functions and electrical
characteristi cs of the H8S/2 282 S eries to th e target users.
Refer to the H8S/2600 Series, H8S/2000 Series Programming Manual for a
detailed description of the instruction set.
Notes on rea d ing t his manual:
• In order to understand the overall functions of the chip
Read the manual ac cording to the conte nts. This manual ca n be roughly categoriz ed into parts
on the CPU, system control functions, peripheral functions and electrical characteristics.
• In order to understand t he details of t he CPU's functi ons
Read the H8S/2600 Series, H8S/2000 Series Programming Manua l.
• In order to understand t he details of a register when its name is known
Read the index that is the final part of the manual to find the page number of the entry on the
register. The addresses, bits, and initial values of the registers are summarized in section 20,
List of Registe rs.
Examples: Register name: The following notation is used for c a ses when the same or a
similar function, e.g. serial communication interfaces, is
implemented on more than one channel:
XXX_N (XXX i s the registe r name and N is the c han nel
number)
Bit orde r: The MSB is on t he left and t he LSB is on the right .
Rev. 1.0, 02/02, Page vi of xxviii
Number not ation: Binary is B'xxxx, hexade c imal is H'xxxx, decimal is xxxx
Signal notation: An overbar is added to a low-ac tive signal:
[[[[
Related Manuals: The latest versions of a l l related manuals are available from our web site.
Please ensure you ha ve the latest versions of all documents you require.
http://www.hitachisemiconductor.com/
H8S/2282 Series manual s:
Manual Title ADE No.
H8S/2282 Series Hardware M anual This manual
H8S/2600 Series, H8S/2000 Series Programming M anual ADE-602-083
User's manuals for development tools:
Manual Title ADE No.
H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor
User's Manual ADE-702-247
H8S, H8/300 Series Simulator/Debugger (for Windows) User ’s Manual ADE-702-085
H8S, H8/300 Series Hitachi Embedded Workshop, Hitachi Debugging
Interface Tutorial ADE-702-231
Hitachi Em bedded Workshop User's Manual ADE-702-201
Rev. 1.0, 02/02, Page vii of xxviii
Contents
Section 1 Overview........................................................................................1
1.1 Overview.....................................................................................................................1
1.2 Internal Block Diagram................................................................................................2
1.3 Pin Arrangement..........................................................................................................3
1.4 Pin Functions...............................................................................................................4
Section 2 CPU................................................................................................9
2.1 Features.......................................................................................................................9
2.1.1 Differences bet ween H8S/2600 CPU and H8S/2000 CPU .................................10
2.1.2 Differences from H8/300 CPU.........................................................................11
2.1.3 Differences from H8/300H CPU ......................................................................11
2.2 CPU Operating Modes.................................................................................................12
2.2.1 Normal Mode..................................................................................................12
2.2.2 Advanced Mode.............................................................................................13
2.3 Address Space..............................................................................................................16
2.4 Register Configura tion.................................................................................................17
2.4.1 General Registers.............................................................................................18
2.4.2 Program Counter (PC).....................................................................................19
2.4.3 Extended Control Register (EXR)....................................................................19
2.4.4 Condition-Code Register (CCR).......................................................................20
2.4.5 Initial Values of CPU Registers........................................................................22
2.5 Data Formats................................................................................................................23
2.5.1 General Register Data Formats.........................................................................23
2.5.2 Memory Data Formats.....................................................................................25
2.6 Instruction Set..............................................................................................................26
2.6.1 Table of Instructions Classified by Function.....................................................27
2.6.2 Basic Instruction Formats ................................................................................36
2.7 Addressing Mod es and Eff ectiv e Address Ca lcula tion ..................................................38
2.7.1 Register Direct—Rn........................................................................................38
2.7.2 Register Indirect—@ERn................................................................................38
2.7.3 Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn).............38
2.7.4 Register Indirect with Post-Increment or Pre-Decrement
—@ERn + or @-ER n......................................................................................39
2.7.5 Ab s o l ute Ad dres s —@a a:8, @aa:16, @aa:24, or @ aa:32..................................39
2.7.6 Immediate—#xx:8, #xx:16, or #xx:32..............................................................40
2.7.7 Program-Count er Relative—@(d: 8, PC) or @(d:16, PC)..................................40
2.7.8 Memory Indirect—@@aa:8.............................................................................40
2.7.9 Effective Address Calculation..........................................................................41
2.8 Processing States..........................................................................................................44
Rev. 1.0, 02/02, Page viii of xxviii
2.9 Usage Note..................................................................................................................45
2.9.1 Note on Bit Manipulation Instructions..............................................................45
Section 3 MCU Operating Modes.................................................................. 47
3.1 Operating Mode Selection............................................................................................47
3.2 Register Descriptions...................................................................................................47
3.2.1 Mode Control Regist er (MDCR)......................................................................47
3. 2.2 System Contr ol Register (SYSC R) ....................................................................48
3.3 Pin Functions in Each Operating Mode .........................................................................49
3.4 Address Map................................................................................................................50
Section 4 Exception Handling........................................................................ 51
4.1 Exception Handling Types and Priority ........................................................................51
4.2 Exception Sources and Exception Vector Ta ble............................................................51
4.3 Reset ...........................................................................................................................53
4.3.1 Res et Exc e p tion Han dling................................................................................53
4.3.2 Interrupts after Reset .......................................................................................55
4.3.3 State of On-Chip Peripheral Modules after Reset Release.................................55
4.4 Traces..........................................................................................................................56
4.5 Interrupts.....................................................................................................................56
4.6 Trap Instruction ...........................................................................................................57
4.7 Stack Status after Exception Handling..........................................................................58
4.8 Usage Note.................................................................................................................. 59
Section 5 Interrupt Controller ........................................................................ 61
5.1 Features.......................................................................................................................61
5.2 Input/Output Pins.........................................................................................................63
5.3 Register Descriptions...................................................................................................63
5.3.1 Interrupt Priority Registers A t o G, J, K, M
(IPRA to IPRG, IPRJ, IPRK, IPRM)................................................................64
5.3.2 IRQ Enable Register (IER) ..............................................................................65
5.3.3 IRQ Sense Control Registers H and L (ISCRH, ISCRL)...................................66
5.3.4 IRQ Status Register (ISR) ................................................................................68
5.4 Interrupt Sources..........................................................................................................69
5.4.1 External Interrupts...........................................................................................69
5.4.2 Internal Int errupts............................................................................................70
5.5 Interrupt Exception Handling Vector Table ..................................................................70
5.6 Interrupt Control Modes and Interrupt Operation..........................................................73
5.6.1 Interrupt Control Mode 0.................................................................................73
5.6.2 Interrupt Control Mode 2.................................................................................75
5.6.3 Interrupt Exception Handling Sequence ...........................................................76
5.6.4 Interrupt Response Times................................................................................78
5.7 Usage Notes.................................................................................................................79
Rev. 1.0, 02/02, Page ix of xxviii
5.7.1 Contention between Interrupt Generation and Disabli ng...................................79
5.7.2 Instructions that Disa ble Interrupts...................................................................80
5.7.3 When Interrupts Are Disabled..........................................................................80
5. 7.4 Inte rrup t s durin g Exec uti o n of EE PMOV Inst r uction........................................81
5.7.5 IRQ Interrupts .................................................................................................81
Section 6 Bus Controller................................................................................83
6.1 Bas ic Timin g ...............................................................................................................8 3
6.1.1 On-Chip Memory Access Timing (ROM, RAM)..............................................83
6.1.2 On-Chip Pe ripheral Module Access Timing .....................................................84
6.1.3 On-Chip HCAN Module Access Timing..........................................................85
6.1.4 On-Chip PW M, LCD, Ports H and J Module Access T iming............................85
Section 7 I/O Ports.........................................................................................87
7.1 Port 1...........................................................................................................................91
7.1.1 Port 1 Data Direction Register (P1DDR)..........................................................91
7.1.2 Port 1 Data Register (P1DR)............................................................................91
7.1.3 Port 1 Register (PORT1)..................................................................................92
7.1.4 Pin Functions...................................................................................................92
7.2 Port 3...........................................................................................................................101
7.2.1 Port 3 Data Direction Register (P3DDR)..........................................................101
7.2.2 Port 3 Data Register (P3DR)............................................................................101
7.2.3 Port 3 Register (PORT3)..................................................................................102
7.2.4 Port 3 Open-Drain Control Register (P3ODR)..................................................102
7.2.5 Pin Functions...................................................................................................103
7.3 Port 4...........................................................................................................................105
7.3.1 Port 4 Register (PORT4)..................................................................................105
7.4 Port A..........................................................................................................................106
7. 4.1 Port A Data Direc ti on Regi ste r (PADDR) ........................................................106
7. 4.2 Port A Data Registe r (PADR ) ..........................................................................106
7.4.3 Port A Register (PORTA)................................................................................107
7. 4.4 Port A Open Drain Contr o l Regi ste r (PAODR) ................................................107
7.4.5 Pin Functions...................................................................................................107
7.5 Port B..........................................................................................................................108
7.5.1 Port B Data Direction Register (PBDDR).........................................................108
7.5.2 Port B Data Register (PBDR) ...........................................................................109
7.5.3 Port B Register (PORTB).................................................................................109
7.5.4 Port B Open Drain Control Register (PBODR).................................................109
7.5.5 Pin Functions...................................................................................................110
7.6 Port C..........................................................................................................................110
7.6.1 Port C Data Direction Register (PCDDR).........................................................111
7.6.2 Port C Data Register (PCDR) ...........................................................................111
7.6.3 Port C Register (PORTC).................................................................................111
Rev. 1.0, 02/02, Page x of xxviii
7.6.4 Port C Open Drain Control Register (PCODR).................................................112
7.6.5 Pin Functions ..................................................................................................112
7.7 Port D..........................................................................................................................113
7. 7.1 Port D Data Direc ti on Regi ste r (PDDDR) ........................................................113
7. 7.2 Port D Data Registe r (PDDR )..........................................................................113
7.7.3 Port D Register (PORTD)................................................................................115
7.7.4 Pin Functions ..................................................................................................115
7.8 Port F ..........................................................................................................................116
7. 8.1 Port F Data Direc ti on Regi ste r (PFDDR) .........................................................116
7. 8.2 Port F Data Registe r ( PFDR ) ...........................................................................117
7.8.3 Port F Register (PORTF).................................................................................117
7.8.4 Pin Functions ..................................................................................................118
7.9 Port H..........................................................................................................................120
7. 9.1 Port H Data Direc ti on Regi ste r (PHDDR) ........................................................120
7. 9.2 Port H Data Registe r (PHDR )..........................................................................120
7.9.3 Port H Register (PORTH)................................................................................121
7.9.4 Pin Functions ..................................................................................................121
7.10 Port J...........................................................................................................................124
7. 10. 1 Port J Data Direc ti on Regi ste r (PJDDR)...........................................................124
7. 10. 2 Port J Data Regist er (PJDR ).............................................................................124
7.10.3 Port J Register (PORTJ) ..................................................................................125
7.10.4 Pin Functions ..................................................................................................125
7.11 Pin Switch Function.....................................................................................................128
7.11.1 Transport Register (TRPRT)............................................................................128
7.11.2 Reading of Port Registers by Switching the Pin................................................128
Section 8 16-Bit Timer Pulse Unit (TPU) ...................................................... 131
8.1 Features.......................................................................................................................131
8.2 Input/Output Pins.........................................................................................................135
8.3 Register Descriptions...................................................................................................136
8.3.1 Timer Control Register (TCR).........................................................................137
8.3.2 Timer Mode Register (TMDR) ........................................................................140
8.3.3 Timer I/O Control Register (TIOR)..................................................................142
8.3.4 Timer Interrupt Enable Register (TIER)...........................................................150
8.3.5 Timer Status Register (TSR)............................................................................153
8.3.6 Timer Count er (TCNT)....................................................................................155
8.3.7 Timer General Register (TGR).........................................................................156
8.3.8 Timer Start Register (TSTR) ............................................................................156
8.3.9 Timer Synchro Register (TSYR)......................................................................157
8.4 Operation.....................................................................................................................158
8.4.1 Basic Functions...............................................................................................158
8.4.2 Synchronous Operation ...................................................................................164
8.4.3 Buffer Opera tion .............................................................................................165
Rev. 1.0, 02/02, Page xi of xxviii
8.4.4 PWM Modes...................................................................................................169
8.4.5 Phase Counting Mod e......................................................................................174
8.5 Interrupts.....................................................................................................................181
8.6 A/D Converter Activation ............................................................................................182
8.7 Op er ation Timin g.........................................................................................................183
8.7.1 Input/Outpu t Timin g........................................................................................183
8.7.2 Interrupt Signal Timing....................................................................................187
8.8 Usage Notes .................................................................................................................190
8.8.1 Module Stop Mode Setting ..............................................................................190
8.8.2 Input Cloc k Restrictions...................................................................................190
8.8.3 Caution on Period Setting................................................................................191
8.8.4 Contention be twee n TCNT Wri te and Cle ar Oper ations...................................191
8.8.5 Contention be twee n TCNT Wri te and Incr ement Operat ions ............................192
8.8.6 Contention be twee n TGR Wr ite and Compar e Match.......................................193
8.8.7 Contention between Buffer Regi ster Wri te and Compare Match .......................194
8.8.8 Contention be twee n TGR Re ad and Input Cap tur e............................................195
8.8.9 Contention be twee n TGR Wr ite and Input Cap ture...........................................196
8.8.10 Contention bet ween Buffer Re gister Write and Input Capture...........................197
8.8.11 Contention bet ween Ove rflow/Underflow and Counter Clea ring.......................198
8.8.12 Contention between TCNT Write and Overflow /Underflow .............................199
8.8.13 Multiplexing of I/O Pins..................................................................................199
8.8.14 Interrupts in Module Stop Mode.......................................................................199
8.8.15 Interrupts in Subactive Mode/Watch Mode.......................................................199
Section 9 Watchdog Timer.............................................................................201
9.1 Features.......................................................................................................................201
9.2 Register Descriptions...................................................................................................203
9.2.1 Timer Count er 0 and 1 (TCNT_0 and TCNT_1)...............................................203
9.2.2 Timer Control/Status Register 0 and 1 (TCSR_0 and TCSR_1) ........................203
9.2.3 Reset Control/Status Register (RSTCSR).........................................................207
9.3 Operation.....................................................................................................................208
9.3.1 Wa tch dog Timer Mo de....................................................................................208
9.3.2 In terval Timer Mo de........................................................................................210
9.4 Interrupts.....................................................................................................................211
9.5 Usage Notes .................................................................................................................211
9.5.1 No tes on Re gister Access.................................................................................211
9.5.2 Contention be twee n Timer Count er (TCN T) Wr it e and Increment ....................212
9.5.3 Changing Value of CKS2 to CKS0 ..................................................................213
9.5.4 Switching between Watchdog Timer Mode and Interval Timer Mode...............213
9.5.5 Internal Reset in Watchdog Timer Mode..........................................................213
9. 5.6 OVF Fla g Clearing in Interval Time r Mode......................................................213
Rev. 1.0, 02/02, Page xii of xxviii
Section 10 Serial Communication Interf ace (SCI).......................................... 215
10.1 Features.......................................................................................................................215
10.2 Input/Output Pins.........................................................................................................217
10.3 Register Descriptions...................................................................................................217
10.3.1 Receive Shift Register (RSR) ...........................................................................218
10.3.2 Receive Data Register (RDR)..........................................................................218
10.3.3 Transmit Data Register (TDR).........................................................................218
10.3.4 Transmit Shift Register (TSR) .........................................................................218
10.3.5 Serial Mode Register (SMR)............................................................................219
10.3.6 Serial Control Register (SCR)..........................................................................223
10.3.7 Serial Status Register (SSR).............................................................................226
10.3.8 Smart Card Mode Register (SCMR).................................................................230
10.3.9 Bit Rate Re gister (BRR)..................................................................................231
10.4 Operation in Asynchronous Mode................................................................................238
10.4.1 Data Transfer Format.......................................................................................238
10.4.2 Receive Data Sampling Timing and Reception Margin
in Asynchro nous Mo de...................................................................................240
10.4.3 Clock..............................................................................................................241
10.4.4 SCI Initialization (Asynchronous Mode)..........................................................242
10.4.5 Data Transmission (Async hronous Mode)........................................................243
10.4.6 Serial Data Reception (Asynchronous Mode)...................................................245
10.5 Multiproc essor Commun icat ion Func tion.....................................................................249
10.5.1 Multiprocessor Serial Data Transmission.........................................................251
10.5.2 Multiprocessor Serial Data Reception..............................................................252
10.6 Operation in Cl ocked Synchronous Mode .....................................................................255
10.6.1 Clock..............................................................................................................255
10.6.2 SCI Initialization (Clocke d Synchronous Mode)...............................................256
10.6.3 Serial Data T ransmission (Cloc ked Sync hronous Mode) ..................................257
10.6.4 Serial Data Reception (Cl ocked Synchronous Mode)........................................260
10.6.5 Simultaneous Serial Data Transmission and Reception
(Clocke d Synchronous Mode)..........................................................................262
10.7 Operation in Smart Card Interface................................................................................264
10.7.1 Pin Connection Example .................................................................................264
10.7.2 Data Format (Except for Block Transfer Mode) ...............................................265
10.7.3 Block Tran s fer Mod e.......................................................................................266
10.7.4 Receive Data Sampling Timing and Reception Margin
in S mart Card Interface Mode.........................................................................267
10.7.5 Initialization....................................................................................................268
10.7.6 Data Transmission (Except for Block Transfer Mode)......................................268
10.7.7 Serial Data Reception (Except for Block Transfer Mode).................................272
10.7.8 Clock Output Control ......................................................................................273
10.8 Interrupts.....................................................................................................................275
10.8.1 Interrupts in Normal Serial Communication Interface Mode.............................275
Rev. 1.0, 02/02, Page xiii of xxviii
10.8.2 Interrupts in Smart Card Interface Mode ..........................................................276
10.9 Usage Notes .................................................................................................................276
10.9.1 Module Stop Mode Setting ..............................................................................276
10.9.2 Break Detection and Processing.......................................................................276
10.9.3 Mark State and Break Detection .......................................................................277
10.9.4 Receive Error Flags and Transmit Operations
(Clocke d Synchronous Mode Only)..................................................................277
Section 11 Hitachi Controller Area Network (HCAN)....................................279
11.1 Features.......................................................................................................................279
11.2 Input/Output Pins.........................................................................................................281
11.3 Register Descriptions...................................................................................................281
11.3.1 Master Control Register (MCR).......................................................................282
11.3.2 General Status Register (GSR).........................................................................283
11.3.3 Bit Configuration Register (BCR)....................................................................285
11.3.4 Mailbox Configuration Register (MBCR).........................................................287
11.3.5 Tran smi t Wait Register (TX PR).......................................................................288
11.3.6 Transmit Wait Cancel Register (TXCR)...........................................................289
11.3.7 Tra nsmit Acknowledge Re gister (T XACK)......................................................290
11.3.8 Abort Acknowle dge Regi ster (ABACK) ..........................................................291
11.3.9 Receive Complete Register (RXPR).................................................................292
11.3.10 Remote Request Register (RFPR)....................................................................293
11.3.11 Int errupt Regi ster (IRR)...................................................................................294
11.3.12 Mailbox Interrupt Mask Re gister (MBIMR).....................................................298
11.3.13 Interrupt Mask Register (IMR).........................................................................299
11.3.14 Receiv e Error Count er (RE C) ..........................................................................300
11.3.15 T ransmit E rror Counter (TEC).........................................................................300
11. 3. 16 Un r e a d Message Status Registe r ( UMSR ) ........................................................301
11. 3. 17 Loca l Acce pta nce Filte r Masks (LAFML, LAFMH).........................................302
11.3.18 Message Control (MC0 to MC15)....................................................................304
11.3.19 Message Data (MD0 to MD15)........................................................................306
11.4 Operation.....................................................................................................................307
11.4.1 Hardware and Software Resets .........................................................................307
11.4.2 Initialization after Hardware Reset...................................................................307
11.4.3 Message Transmission.....................................................................................313
11.4.4 Message Reception..........................................................................................316
11.4.5 HCAN Sleep Mode..........................................................................................319
11.4.6 HCAN Halt Mode............................................................................................322
11.5 Interrupts.....................................................................................................................323
11.6 CAN Bus Interface.......................................................................................................324
11.7 Usage Notes .................................................................................................................324
11.7.1 Module Stop Mode Setting ..............................................................................324
11.7.2 Reset...............................................................................................................324
Rev. 1.0, 02/02, Page xiv of xxviii
11.7.3 HCAN Sleep Mode .........................................................................................325
11.7.4 Interrupts.........................................................................................................325
11.7.5 Error Counters .................................................................................................325
11.7.6 Register Access...............................................................................................325
11.7.7 HCAN Medium-Speed Mode...........................................................................325
11.7.8 Register Hold in Standby Modes......................................................................325
11.7.9 Us ag e o f B it Manipulation Instruc tions............................................................325
Section 12 A/D Converter .............................................................................. 327
12.1 Features.......................................................................................................................327
12.2 Input/Output Pins.........................................................................................................329
12.3 Register Descriptions...................................................................................................330
12. 3. 1 A/D Dat a Regi ste rs A to D (ADDRA to ADDR D) ...........................................330
12.3.2 A/D Control/Status Register (ADCSR) ............................................................331
12.3.3 A/D Control Register (ADCR) .........................................................................333
12.4 Operation.....................................................................................................................334
12.4.1 Single Mode....................................................................................................334
12.4.2 Scan Mode......................................................................................................334
12.4.3 Input Sampling and A/D Conve rsion Time .......................................................335
12.4.4 External Trigger Input Timing.........................................................................337
12.5 Interrupts.....................................................................................................................337
12.6 A/D Conversion Precision Definitions..........................................................................338
12.7 Usage Notes.................................................................................................................340
12.7.1 Module Stop Mode Setting..............................................................................340
12.7.2 Permissible Signal Source Impedance..............................................................340
12.7.3 Influences on Absolute Precision.....................................................................340
12.7.4 Range of Analog Power Supply and Other Pin Settings....................................341
12.7.5 No tes on Bo ard D e s i g n....................................................................................341
12.7.6 Notes on Noise Countermeasure s.....................................................................341
Section 13 Motor Control PWM Timer (PWM)............................................. 343
13.1 Features.......................................................................................................................343
13.2 Input/Output Pins.........................................................................................................346
13.3 Register Descriptions...................................................................................................346
13.3.1 PWM Control Register_1, 2 (PWCR_1, PWCR_2) ..........................................347
13.3.2 PWM Output Control Re gi ster_1, 2 (PWOCR_1, PWOCR_2).........................347
13.3.3 PWM Polarity Register_1, 2 (PW PR_1, PW PR_2) ...........................................349
13.3.4 PWM Counter_1, 2 (PWCNT_1, PWCNT_2)..................................................349
13.3.5 PWM Cycle Register_1, 2 (PWCYR_1, PWCYR_2)........................................350
13.3.6 PWM Duty Register_1A, 1C, 1E, 1G
(PWDT R_1A, PW DTR_1C, PWDTR_1E, PWDTR_1G).................................350
13.3.7 PWM Buffer Register_1A, 1C, 1E , 1G
(PWBFR_1A, PWBFR_1C, PWBFR_1E, PWBFR_1G) ..................................352
Rev. 1.0, 02/02, Page xv of xxviii
13.3.8 PWM Du ty Reg ister_2A to 2H (P WDTR _2A to PWDTR_2H ).........................353
13.3.9 PWM Buffer Register_2A to 2D (PWBFR2_A t o PWBFR_2D).......................355
13.4 Bus Master Interface ....................................................................................................357
13.4.1 16-Bit Data Regi sters .......................................................................................357
13.4.2 8-Bit Data Regi sters.........................................................................................357
13.5 Operation.....................................................................................................................358
13.5.1 PWM Channel 1 Operation..............................................................................358
13.5.2 PWM Channel 2 Operation..............................................................................359
13.6 Interrupts.....................................................................................................................360
13.7 Usage Note..................................................................................................................360
Section 14 LCD Controller/Driver (LCD)......................................................363
14.1 Features.......................................................................................................................363
14.2 Input/Output Pins.........................................................................................................364
14.3 Register Descriptions....................................................................................................365
14.3.1 LCD Port Control Register (LPCR)..................................................................365
14.3.2 LCD Control Register (LCR)...........................................................................367
14.3.3 LCD Control Re gister 2 (L CR2) ......................................................................368
14.4 Operation.....................................................................................................................369
14.4.1 Settings u p to LC D Dis p lay .............................................................................369
14.4.2 Relationship between LCD RAM and Display..................................................370
14.4.3 Operation in Power-Down Modes....................................................................374
14.4.4 Boosting the LCD Dri ve Power Supply............................................................375
Section 15 RAM ............................................................................................377
Section 16 Flash Memory (F-ZTAT Version).................................................379
16.1 Features.......................................................................................................................379
16.2 Mo d e Trans i tions.........................................................................................................38 0
16.3 Block Configuration.....................................................................................................383
16.4 Input/Output Pins.........................................................................................................385
16.5 Register Descriptions...................................................................................................385
16.5.1 Flash Memory Control Regi ster 1 (FLMCR1)..................................................386
16.5.2 Flash Memory Control Regi ster 2 (FLMCR2)..................................................387
16.5.3 Erase Block Register 1 (EBR1)........................................................................387
16.5.4 RAM Emulation Register (RAMER)................................................................388
16.5.5 Flash Memory Power Control Register (FLPWCR)..........................................389
16.6 On-Board Programming Modes....................................................................................389
16.6.1 Boot Mode ......................................................................................................389
16.6.2 Programming/Erasi ng in User Progra m Mode ..................................................391
16.7 Flash Memory E mul ation in RAM................................................................................393
16.8 Flash Me mory Programm i ng/Erasing ...........................................................................395
16.8.1 Program/Program-Verify .................................................................................395
Rev. 1.0, 02/02, Page xvi of xxviii
16.8.2 Erase/Erase-Verify ..........................................................................................397
16.8.3 Inte rrupt Handling when Programming/Erasing Fl ash Memory ........................397
16.9 Program/Erase Protection.............................................................................................399
16.9.1 Hardware Protection........................................................................................399
16.9.2 Software Protection.........................................................................................399
16.9.3 Error Protection...............................................................................................399
16.10 Programmer Mode.......................................................................................................400
16.11 Power-Down States for Flash Memory.........................................................................400
16.12 Flash Me mory and Power-Down Modes.......................................................................400
Section 17 Mask ROM .................................................................................. 401
Section 18 Clock Pulse Generator.................................................................. 403
18.1 Register Descriptions...................................................................................................404
18.1.1 System Clock Control Register (SCKCR)........................................................404
18.1.2 Low-Power Control Register (LPWRCR)........................................................406
18.2 Oscillator.....................................................................................................................407
18.2.1 Connecting a Crystal Re sonator.......................................................................407
18.2.2 External Clock Input........................................................................................408
18.3 PLL Circuit..................................................................................................................409
18.4 Subclock Divider.........................................................................................................409
18.5 Medium-Speed Clock Divider......................................................................................409
18.6 Bus Master Clock Selection Circuit..............................................................................410
18.7 Usage Notes.................................................................................................................410
18.7.1 Note on Crystal Resonator...............................................................................410
18.7.2 Note on Board Design .....................................................................................410
Section 19 Power-Down Modes ..................................................................... 413
19.1 Register Descriptions...................................................................................................417
19.1.1 Standby Control Register (SBYCR).................................................................417
19.1.2 Low-Power Control Register (LPWRCR)........................................................418
19.1.3 Module Stop Control Regi sters A to D (MSTPCRA to MSTPCRD).................420
19.2 Medium-Speed Mode...................................................................................................422
19.3 Sleep Mode ..................................................................................................................423
19.3.1 Transition to Sleep Mode .................................................................................423
19.3.2 Clearing Sleep Mode.......................................................................................423
19.4 Software Standby Mode...............................................................................................424
19.4.1 Tra nsition t o Software Standby Mode ..............................................................424
19.4.2 Clearing Software Standby Mode.....................................................................424
19.4.3 Setting Oscillation Stabilization Time
after Clearing Software Standby Mode.............................................................425
19.4.4 Software Standby Mode Application Example .................................................426
19.5 Hardware Standby Mode..............................................................................................427
Rev. 1.0, 02/02, Page xvii of xxviii
19.5.1 Tra nsition t o Hardware Standby Mode.............................................................427
19.5.2 Clearing Hardware Sta ndby Mode ...................................................................427
19.5.3 Hardware Standby Mode Timings....................................................................427
19.6 Module Stop Mode.......................................................................................................428
19.7 Watch Mode ................................................................................................................429
19.7.1 Tran siti o n to Wat ch Mode ...............................................................................429
19.7.2 Canceling Watch Mode....................................................................................429
19.8 Subsleep Mode.............................................................................................................430
19.8.1 Transition to Subsleep Mode............................................................................430
19.8.2 Canceling Subsleep Mode................................................................................430
19.9 Subactive Mode...........................................................................................................430
19.9.1 Transition to Subactive Mode ..........................................................................430
19.9.2 Canceling Subactive Mode...............................................................................431
19.1 0 Dire ct Tran sitio n s.........................................................................................................431
19.10.1 Dire ct Transitions from High-Speed Mode to Subactive Mode .........................431
19.10.2 Dire ct Transitions from Subactive Mode to High-Speed Mode .........................431
19.11 ø Clock Output Disabling Function...............................................................................432
19.12 Usage Notes.................................................................................................................432
19.12.1 I/O Port Status.................................................................................................432
19.12.2 Curre nt Di ssipation duri ng Osci llation Stabilization Wa it Period......................432
19.12.3 On-Chip Peripheral Module Interrupt...............................................................432
19.12.4 Writing to MSTPCR........................................................................................433
Section 20 List of Registers............................................................................435
20.1 Register Addresses (Address Order).............................................................................435
20.2 Register Bits ................................................................................................................449
20.3 Register States in Each Operating Mode.......................................................................465
Section 21 Electrical Characteristics (Preliminary).........................................479
21.1 Absolute Maximum Ratings.........................................................................................479
21.2 DC Characteristics.......................................................................................................480
21.3 AC Characteristics.......................................................................................................483
21.3.1 Clock Ti min g ..................................................................................................483
21.3.2 Control Signal Timing.....................................................................................485
21.3.3 Timing of On-Chip Supporting Modul e s..........................................................487
21.4 A/D Conversion Characteristics....................................................................................492
21.5 Flash Me mory Chara cteristics ......................................................................................493
21.6 LCD Characteristics.....................................................................................................495
Appendix .....................................................................................................497
A. I/O Port States in Each Pin State...................................................................................497
B. Product Lineup.............................................................................................................498
C. Package Dimensions ....................................................................................................498
Rev. 1.0, 02/02, Page xviii of xxviii
Index ..................................................................................................... 499
Rev. 1.0, 02/02, Page xix of xxviii
Figures of Contents
Section 1 Ov erview
Figure 1.1 Internal Block Diagr am.............................................................................................2
Figure 1.2 Pin Arrangement.......................................................................................................3
Section 2 CPU
Figure 2.1 Exception Vector Table (Normal Mode)..................................................................13
Figure 2.2 Stack Structure in Normal Mode .............................................................................13
Figure 2.3 Exception Vector Table (Advan ced Mode)..............................................................14
Figure 2.4 Stack Structure in Advanced Mode..........................................................................15
Figure 2.5 Memory Map..........................................................................................................16
Figure 2.6 CPU Registers ........................................................................................................17
Figure 2.7 Usage of General Registers.....................................................................................18
Figure 2.8 Stack Status............................................................................................................19
Figure 2.9 Gen eral Register Data Formats (1) ..........................................................................23
Figure 2.9 Gen eral Register Data Formats (2) ..........................................................................24
Figure 2.10 Memory Data For mats ..........................................................................................25
Figure 2.11 In struction Formats (Examples).............................................................................37
Figure 2.12 Branch Addr ess Specifi cation in Memory Indir ect Mode .......................................41
Fig ure 2 .1 3 State Transitions ...................................................................................................4 5
Section 3 MCU Op erating Mo des
Figure 3.1 Address Map ..........................................................................................................50
Section 4 Exception Handling
Figure 4.1 Reset Sequen ce (Advanced Mode with On-chip ROM Enabled) ..............................54
Figure 4. 2 Reset Sequence (Advanced Mode wit h On-chi p ROM Disabled:
Cannot be Used in th is LSI).....................................................................................55
Figure 4.3 Stack Status after Exception Handling.....................................................................58
Figure 4.4 Operation wh en SP Value Is Odd............................................................................59
Section 5 Interrupt Controller
Figure 5.1 Block Diagram of Interrupt Controller.....................................................................62
Figure 5.2 Block Diagram of Interrupts IRQ5 to IRQ0.............................................................69
Figure 5. 3 Fl owchart of Pr ocedure up to Interrupt Accep tance in Interrupt C ontrol Mode 0 .....74
Fi g ure 5.4 Flowchart of Proced u re Up to Int errupt A ccep tance in Con trol M ode 2....................76
Fig ure 5 .5 I nterrupt Exc eption Handling..................................................................................77
Figure 5.6 Contention between Interrupt Gener ation and Disabling..........................................80
Section 6 B us Controller
Figure 6.1 On-Chip Memor y Access Cycle..............................................................................83
Figure 6.2 On-Chip Peripheral Module Access Cycle...............................................................84
Figure 6.3 On-Chip HCAN Module Access Cycle (Wait States Inserted)..................................85
Figure 6.4 On-Chip PWM, LCD, Ports H and J Module Access Cycle......................................85
Rev. 1.0, 02/02, Page xx of xxviii
Section 8 16-Bit Timer Pulse Unit (TPU)
Figure 8.1 Block Diagram of TPU .........................................................................................134
Figure 8.2 Example of Counter Operation Setting Pr ocedure..................................................158
Figure 8. 3 Free-Running Counter Operation ..........................................................................159
Figure 8.4 Per iodic Counter Operation...................................................................................160
Figur e 8.5 Example of Setting Procedure for Waveform Output by Compare Match...............160
Figure 8.6 Example of 0 Output/1 Output Operation ..............................................................161
Figure 8.7 Example of Toggle Output Operation....................................................................161
Figure 8.8 Example of Input Capture Operation Setting Pr ocedure.........................................162
Figure 8.9 Example of Input Capture Operation .....................................................................163
Figure 8.10 Example of Syn chronous Operation Settin g Procedure.........................................164
Figure 8.11 Example of Syn chronous Operation ....................................................................165
Figure 8.12 Compare Match Buffer Operation .......................................................................166
Figure 8.13 In put Capture Buffer Oper ation...........................................................................166
Figure 8. 14 Example of Buffer Operation Settin g Procedur e ..................................................167
Figure 8. 15 Example of Buffer Operation (1).........................................................................167
Figure 8. 16 Example of Buffer Operation (2).........................................................................168
Figure 8.17 Example of PWM Mode Setting Pr ocedur e..........................................................171
Figure 8.18 Example of PWM Mode Oper ation (1)................................................................171
Figure 8.19 Example of PWM Mode Oper ation (2)................................................................172
Figure 8.20 Example of PWM Mode Oper ation (3)................................................................173
Figure 8.21 Example of Phase Counting Mode Setting Procedure ...........................................174
Figure 8.22 Example of Phase Counting Mode 1 Operation....................................................175
Figure 8.23 Example of Phase Counting Mode 2 Operation....................................................176
Figure 8.24 Example of Phase Counting Mode 3 Operation....................................................177
Figure 8.25 Example of Phase Counting Mode 4 Operation....................................................178
Figure 8.26 Phase Countin g Mode Application Example........................................................180
Figure 8.27 Count Timing in In ternal Clock Operation...........................................................183
Figure 8.28 Count Timing in External Clock Operation..........................................................183
Figure 8.29 Output Compare Output Timing..........................................................................184
Figure 8.30 In put Captur e In put Signal Timing......................................................................184
Figure 8.31 Counter Clear Timing (Compare Match ) .............................................................185
Figure 8.32 Counter Clear Timing (Input Capture).................................................................185
Figure 8.33 Buffer Operation Timin g (Compare Match ).........................................................186
Figure 8.34 Buffer Operation Timing (Input Captur e) ............................................................186
Figure 8. 35 TGI Interrupt Ti ming (Com pare Mat ch) ..............................................................187
Figure 8. 36 TGI Interrupt Ti ming (Input Capture)..................................................................187
Figure 8. 37 TCIV Interrupt Setting Timing............................................................................188
Figure 8. 38 TCIU Interrupt Setting Timing............................................................................188
Figure 8.39 Timing for Status Flag Clearin g by CPU..............................................................189
Figure 8.40 Phase Differ ence, Overlap, and Pulse Width in Phase Counting Mode .................190
Figure 8.41 Contention between TCNT Write and Clear Oper ations.......................................191
Figure 8.42 Contention between TCNT Write and Incr ement Operation s................................192
Rev. 1.0, 02/02, Page xxi of xxviii
Figure 8.43 Contention between TGR Write and Compare Match ...........................................193
Figure 8.44 Contention between Buffer Register Write and Compar e Match...........................194
Figure 8.45 Contention between TGR Read and In put Capture...............................................195
Figure 8. 46 Contention between T GR Write and Input Capture..............................................196
Figure 8.47 Contention between Buffer Register Write and Input Capture..............................197
Figure 8.48 Contention between Overflow and Coun ter Clearin g ...........................................198
Figure 8.49 Contention between TCNT Write and Overflow..................................................199
Section 9 Watchdog Ti mer
Figure 9.1 Block Diagram of WDT_0....................................................................................202
Figure 9.2 Block Diagram of WDT_1....................................................................................202
Figure 9.3 (a) WDT_0 Operation in Watchdog Timer Mode...................................................209
Figure 9.3 (b) WDT_1 Operation in Watch dog Timer Mode...................................................209
Figure 9.4 Operation in Interval Timer Mode.........................................................................210
Figure 9.5 Writing to TCNT, TCSR, and RSTCSR (example for WDT0) ...............................212
Figure 9.6 Contention between TCNT Write and Increment ...................................................212
Sec t i on 10 Serial Communication Inter f ace (SCI)
Figure 10.1 Block Diagram of SCI.........................................................................................216
Fig ur e 10. 2 Dat a For ma t in Asynchron ous Communi cati on
(Example with 8-Bit Data, Parity, Two Stop Bits)................................................238
Figure 10.3 Receive Data Samplin g Timin g in Asyn chron ous Mode.......................................240
Figur e 10.4 Relationship between Output Clock and Transfer Data Phase
(A synchronous Mode ).........................................................................................241
Figure 10.5 Sample SCI Initialization Flowchart....................................................................242
Figure 10. 6 Example of Operation in Transmission in Asynchr onous Mode
(Example with 8-Bit Data, Parity, One Stop Bit)..................................................243
Figure 10.7 Sample Ser ial Transmission Flowchart................................................................244
Fi g ure 1 0.8 Exa mp le of SCI O p era tion in Recep ti on
(Example with 8-Bit Data, Parity, One Stop Bit)..................................................245
Figure 10.9 Sample Serial Reception Data Flowchart (1)........................................................247
Figure 10.9 Sample Serial Reception Data Flowchart (2)........................................................248
Figure 10.10 Example of Communication Using Multiprocessor For mat
(Transmi s sion of Data H'AA to Receiving Stati on A ).........................................250
Figure 10.11 Sample Multiprocessor Serial Transmission Flowchart......................................251
Fi g ure 1 0.1 2 Examp le of SCI Op er ation in Reception
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit).............................252
Fi g ure 1 0.1 3 Samp le Mul tiprocessor Ser ial Recepti on F lowchart (1)......................................253
Fi g ure 1 0.1 3 Samp le Mul tiprocessor Ser ial Recepti on F lowchart (2)......................................254
Figure 10.14 Data Format in Synchron ous Communication (for LSB-First)............................255
Figure 10.15 Sample SCI Initialization Flowchart..................................................................256
Figure 10.16 Sample SCI Transmission Operation in Clocked Syn chron ous Mode..................258
Figure 10.17 Sample Serial Transmission Flowchart..............................................................259
Fi g ure 1 0.1 8 Examp le of SCI Op er ation in Reception ............................................................260
Rev. 1.0, 02/02, Page xxii of xxviii
Fi g ure 1 0.1 9 Samp le Ser ial Recepti on F lowchar t ...................................................................261
Fi g ure 1 0.2 0 Samp le Flowchart of Si mu ltaneou s S er ial Tran sm it and Receive Op erations......263
Figure 10.21 Schematic Diagram of Smart Card Interface Pin Connections ............................264
Figure 10.22 Normal Smart Car d Inter face Data Format.........................................................265
Fig ur e 10. 2 3 Dir ect Conven ti on (SDI R = SI NV = O/
(
= 0)....................................................265
Figure 10.24 In verse C on venti on (SDI R = SINV = O/
(
= 1)..................................................266
Fi g ure 1 0. 2 5 Recei ve Data Sampling Timing in Smart Car d Mode
(Using Clock of 372 Times the Transfer Rate) ...................................................267
Figure 10.26 Retransfer Operation in SCI Transmit Mode......................................................269
Figure 10.27 TEND Flag Generation Timing in Tran smission Operation................................270
Figure 10.28 Example of Transmission Processing Flow........................................................271
Fi g ure 1 0.2 9 Retrans fer Operation in S C I Receive Mode........................................................272
Figure 10.30 Example of Reception Pr ocessing Flow.............................................................273
Figure 10.31 Timin g for Fixing Clock Output Level ...............................................................273
Figure 10.32 Clock Halt and Restar t Procedur e......................................................................274
Section 11 Hitachi Controller Area Network (HCAN)
Figure 11.1 HCAN Block Diagram........................................................................................280
Figure 11.2 Message Con trol Register Configuration .............................................................304
Figure 11.3 Standard Format .................................................................................................304
Figure 11.4 Extended Format.................................................................................................304
Figure 11.5 Message Data Con figuration ...............................................................................306
Figure 11.6 Hardware Reset Flowchart..................................................................................308
Figure 11.7 Softwar e Reset Flowchart ...................................................................................309
Figure 11.8 Detailed Descr iption of One Bit ..........................................................................310
Figure 11.9 Tran smission Flowchart......................................................................................313
Figure 11.10 Transmit Message Cancellation Flowchart .........................................................315
Fi g ure 1 1.1 1 Recepti on F lowchar t .........................................................................................316
Figure 11.12 Unread Message Overwrite Flowch art...............................................................319
Figure 11.13 HCAN Sleep Mode Flowch art...........................................................................320
Figure 11.14 HCAN Halt Mode Flowchart.............................................................................322
Figure 11. 15 Hi gh-Speed In t erface Using PCA82C250..........................................................324
Section 12 A/D Converter
Figure 12.1 Block Diagram of A/D Converter........................................................................328
Figure 12.2 A/D Con ver sion Timing......................................................................................335
Fig ure 12 .3 Ex ternal Trig g er Input Timing.............................................................................337
Figure 12.4 A/D Con ver sion Precision Definitions.................................................................339
Figure 12.5 A/D Con ver sion Precision Definitions.................................................................339
Figure 12.6 Example of Analog Input Circuit.........................................................................340
Figure 12.7 Example of Analog In put Protection Cir cuit........................................................342
Figure 12.8 Analog In put Pin Equivalent Circuit....................................................................342
Rev. 1.0, 02/02, Page xxiii of xxviii
Section 13 Motor Control PWM Timer (PWM)
Figure 13.1 Block Diagram of PWM Channel 1.....................................................................344
Figure 13.2 Block Diagram of PWM Channel 2.....................................................................345
Figure 13.3 Cycle Register Compare Match...........................................................................350
Section 14 LCD Controller/Driver (LCD)
Figure 14.1 Block Diagram of LCD Controller/Driver ............................................................364
Figure 14.2 LCD RAM Map (1/4 Duty).................................................................................370
Figure 14.3 LCD RAM Map (1/3 Duty).................................................................................371
Figure 14.4 LCD RAM Map (Static Mode)............................................................................371
Figure 14.5 Output Waveforms for Each Duty Cycle (A Waveform)......................................372
Figure 14.6 Output Waveforms for Each Duty Cycle (B Wavefor m) ......................................373
Figure 14.7 Connection of External Split-Resistance..............................................................375
Section 16 Flash Memory (F-ZTAT Ver sion)
Figure 16.1 Block Diagram of Flash Memory........................................................................380
Figure 16.2 Flash Memory State Tran sition s..........................................................................381
Figure 16.3 Boot Mode..........................................................................................................382
Figure 16.4 User Program Mode............................................................................................383
Figure 16.5 Flash Memory Block Con figur ation ....................................................................384
Figure 16.6 Programming/Erasing Flowch art Example in User Program Mode.......................392
Figure 16.7 Flowchart for Flash Memor y Emulation in RAM.................................................393
Figure 16.8 Example of RAM Over lap Operation...................................................................394
Figure 16.9 Program/Pr ogram-Ver ify Flowchart ....................................................................396
Figure 16.10 Erase/Erase-Verify Flowchart............................................................................398
Section 17 Mask ROM
Figure 17. 1 Block Dia gram of 128-Kbyt e Mask ROM (HD6432282) .....................................401
Figure 17. 2 Block Dia gram of 64-Kbyt e Mask ROM (HD6432281).......................................401
Section 18 Clock Pulse Generator
Figure 18.1 Block Diagram of Clock Pulse Generator ............................................................403
Figure 18.2 Connection of Crystal Resonator (Example)........................................................407
Figure 18.3 Crystal Resonator Equivalent Circuit...................................................................407
Figure 18.4 External Clock In put (Examples) .........................................................................408
Figure 18.5 External Clock In put Timing...............................................................................409
Figure 18.6 Note on Board Design of Oscillator Cir cuit .........................................................410
Figure 18.7 External Circuitry Recommen ded for PLL Cir cuit ...............................................411
Sec t i on 19 Power - Down Modes
Figure 19.1 Mode Transition Diagram ...................................................................................414
Figure 19.2 Medium-Speed Mode Tran sition and Clearan ce Timing.......................................422
Figure 19.3 Software Standby Mode Application Example.....................................................426
Figure 19.4 Timing of Transition to Hardware Standby Mod e ................................................427
Figure 19. 5 Timing of Recovery from Hardware St andby Mode.............................................428
Rev. 1.0, 02/02, Page xxiv of xxviii
Section 21 Electrical Characteristics (Preliminary)
Figure 21.1 Output Load Cir cuit............................................................................................483
Figure 21.2 System Clock Timin g..........................................................................................484
Figure 21.3 Oscillation Stabilization Timing..........................................................................484
Figure 21.4 Reset Input Timing .............................................................................................485
Figure 21.5 In terrupt Input Timing ........................................................................................486
Figure 21.6 I/O Por t In put/Output Timing..............................................................................489
Figure 21.7 TPU Input/Output Timing...................................................................................489
Figure 21.8 TPU Clock Input Timing.....................................................................................490
Figure 21.9 SCK Clock In put Timing ....................................................................................490
Figure 21.10 SCI Input/Output Timing (Clock Synchron ous Mode) .......................................490
Figure 21.11 A/D Converter External Trigger Input Timing...................................................490
Figure 21.12 HCAN Input/Output Timing..............................................................................491
Figure 21.13 Motor Control PWM Output Timing.................................................................491
Appendix
Figure C. 1 FP-100A Pa ckage Dimensions..............................................................................498
Rev. 1.0, 02/02, Page xxv of xxviii
Tables of Content s
Section 2 CPU
Table 2.1 Instruction Classification........................................................................................26
Table 2.2 Operation Notation.................................................................................................27
Table 2.3 Data Transfer In struction s.......................................................................................28
Table 2.4 Arithmetic Operation s In structions (1)....................................................................29
Table 2.4 Arithmetic Operation s In structions (2)....................................................................30
Table 2.5 Logic Oper ation s In struction s.................................................................................31
Table 2.6 Shift Instr uctions....................................................................................................31
Table 2.7 Bit Manipulation Instruction s (1)............................................................................32
Table 2.7 Bit Manipulation Instruction s (2)............................................................................33
Table 2.8 Br anch Instructions.................................................................................................34
Table 2.9 System Control Instruction s....................................................................................35
Table 2.10 Block Data Tr ansfer In struction s.........................................................................36
Table 2.11 Addressing Modes..............................................................................................38
Table 2.12 Absolute Address Access Ranges........................................................................39
Table 2.13 Effective Address Calculation (1) .......................................................................42
Table 2.13 Effective Address Calculation (2) .......................................................................43
Section 3 MCU Op erating Mo des
Table 3.1 MCU Operating Mode Selection.............................................................................47
Section 4 Exception Handling
Table 4.1 Exception Types and Prior ity..................................................................................51
Table 4.2 Exception Han dling Vector Table...........................................................................52
Table 4.3 Status of CCR and EXR after Trace Exception Handling.........................................56
Table 4.4 Status of CCR an d EXR after Trap Instruction Exception Handling.........................57
Section 5 Interrupt Controller
Table 5.1 Pin Configur ation...................................................................................................63
Table 5. 2 Interrupt Sources, Vector Addr esses, an d In terrupt Priorities...................................71
Table 5. 3 Interrupt Control Modes .........................................................................................73
Table 5.4 Interrupt Respon se Times.......................................................................................78
Table 5.5 Number of States in Interrupt Handling Routin e Execution Status...........................79
Section 7 I/O Ports
Table 7.1 Port Fun ctions (1) ...................................................................................................88
Table 7.1 Port Fun ctions (2) ...................................................................................................89
Table 7.1 Port Fun ctions (3) ...................................................................................................90
Table 7.2 Pins of Register s to be Read and PWM Output by Switching Pins.........................129
Section 8 16-Bit Timer Pulse Unit (TPU)
Table 8.1 TPU Functions (1)................................................................................................132
Table 8.1 TPU Functions (2)................................................................................................133
Rev. 1.0, 02/02, Page xxvi of xxviii
Table 8.2 Pin Configur ation.................................................................................................135
Table 8.3 CCLR0 to CCLR2 (Ch annel 0).............................................................................138
Table 8.4 CCLR0 to CCLR2 (Ch annels 1 and 2)..................................................................138
Table 8.5 TPSC0 to TPSC2 (Chann el 0)...............................................................................139
Table 8.6 TPSC0 to TPSC2 (Chann el 1)...............................................................................139
Table 8.7 TPSC0 to TPSC2 (Chann el 2)...............................................................................140
Table 8.8 MD0 to MD3 .......................................................................................................141
Table 8.9 TIORH_0.............................................................................................................143
Table 8.10 TIORL_0..........................................................................................................144
Table 8.11 TIOR_1............................................................................................................145
Table 8.12 TIOR_2............................................................................................................146
Table 8.13 TIORH_0.........................................................................................................147
Table 8.14 TIORL_0..........................................................................................................148
Table 8.15 TIOR_1............................................................................................................149
Table 8.16 TIOR_2............................................................................................................150
Table 8.17 Register Combinations in Buffer Operation.......................................................166
Table 8.18 PWM Output Registers and Output Pin s ...........................................................170
Table 8.19 Phase Countin g Mode Clock In put Pins............................................................174
Table 8.20 Up/Down-Count Conditions in Phase Counting Mode 1....................................175
Table 8.21 Up/Down-Count Conditions in Phase Counting Mode 2....................................176
Table 8.22 Up/Down-Count Conditions in Phase Counting Mode 3....................................177
Table 8.23 Up/Down-Count Conditions in Phase Counting Mode 4....................................178
Table 8. 24 TPU Interrupts..................................................................................................181
Section 9 Watchdog Ti mer
Table 9.1 WDT Interrupt Source..........................................................................................211
Sec t i on 10 Serial Communication Inter f ace (SCI)
Table 10.1 Pin Con figur ation.............................................................................................217
Table 10.2 The Relationships between The N Setting in BRR and Bit Rate B .....................231
Table 10.3 BRR Settings for Various Bit Rates (Asyn chron ous Mode) (1)..........................232
Table 10.3 BRR Settings for Various Bit Rates (Asyn chron ous Mode) (2)..........................233
Table 10.3 BRR Settings for Various Bit Rates (Asyn chron ous Mode) (3)..........................234
Table 10.4 Maximum Bit Rate for Each Frequency (Asyn chron ous Mode).........................235
Table 10.5 Maximum Bit Rate with External Clock Input (Asynchron ous Mode)................235
Table 10.6 BRR Settings for Various Bit Rates (Clocked Syn chron ous Mode)....................236
Table 10.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)....236
Table 10.8 Examples of Bit Rate for Various BRR Settings (Smart Card In terface Mode)
(Whe n n = 0 and S = 37 2 ).................................................................................237
Table 10. 9 Maximum Bi t Rate at Vari ous Fr equencies (Smart Card Interface Mode)
(when S = 372).................................................................................................237
Table 10.10 Serial Transfer Formats (Asynchron ous Mode) .................................................239
Table 10.11 SSR Status Flags and Receive Data Handling....................................................246
Table 10.12 SCI Interrupt Sour ces .......................................................................................275
Rev. 1.0, 02/02, Page xxvii of xxviii
Table 10.13 SCI Interrupt Sour ces........................................................................................276
Section 11 Hitachi Controller Area Network (HCAN)
Table 11.1 Pin Con figur ation .............................................................................................281
Table 11.2 Limits for the Settable Value.............................................................................310
Table 11.3 Setting Range for TSEG1 and TSEG2 in BCR ..................................................311
Table 11.4 HCAN Interrupt Sources...................................................................................323
Section 12 A/D Converter
Table 12.1 Pin Con figur ation .............................................................................................329
Ta ble 12. 2 Anal og Input Channels and Correspon ding ADDR Regist ers.............................330
Table 12.3 A/D Conversion Time (Single Mode) ................................................................336
Table 12.4 A/D Conversion Time (Scan Mode)..................................................................336
Table 12.5 A/D Converter Interrupt Sour ce........................................................................337
Table 12.6 Analog Pin Specifications.................................................................................342
Section 13 Motor Control PWM Timer (PWM)
Table 13.1 Pin Con figur ation .............................................................................................346
Table 13. 2 PWM Interrupt Sour ces ....................................................................................360
Section 14 LCD Controller/Driver (LCD)
Table 14.1 Pin Con figur ation .............................................................................................364
Table 14.2 Selection of the Duty Cycle and Common Function s.........................................366
Table 14.3 Selection of Segment Drivers............................................................................366
Table 14.4 Selection of the Operating Clock an d Frame Frequen cy.....................................368
Table 14.5 Output Levels...................................................................................................374
Table 14.6 Power-Down Modes an d Display Oper ation......................................................374
Section 16 Flash Memory (F-ZTAT Ver sion)
T able 16.1 Diffe renc es betwee n Boot Mode and Use r Pr ogram M ode.................................381
Table 16.2 Pin Con figur ation .............................................................................................385
Table 16.3 Setting On -Board Programming Modes.............................................................389
Table 16.4 Boot Mode Oper ation .......................................................................................391
Table 16.5 System Clock Frequen cies for which Automatic Adjustment
of LSI Bit Rate is Possible ................................................................................391
Table 16.6 Flash Memory Oper atin g States ........................................................................400
Section 18 Clock Pulse Generator
Table 18.1 Damping Resistance Value...............................................................................407
Table 18.2 Crystal Resonator Characteristics......................................................................407
Table 18.3 External Clock In put Condition s.......................................................................408
Sec t i on 19 Power - Down Modes
Table 19.1 Power-Down Mode Transition Condition s ........................................................415
Table 19.2 LSI Internal States in Each Mode......................................................................416
Table 19.3 Oscillation Stabilization Time Settings..............................................................425
Table 19.4 ø Pin State in Each Pr ocessing State..................................................................432
Rev. 1.0, 02/02, Page xxviii of xxviii
Section 21 Electrical Characteristics (Preliminary)
Table 21.1 Absolute Maximum Ratings .............................................................................479
Table 21.2 DC Char acteristics............................................................................................480
Table 21.3 Permissible Output Currents.............................................................................482
Table 21.4 Clock Timing...................................................................................................483
Table 21.5 Con trol Signal Timing......................................................................................485
Table 21. 6 Timing of On-Chip Supporting Modules...........................................................487
Table 21.7 A/D Con version Characteristics........................................................................492
Table 21.8 Flash Memory Character istics...........................................................................493
Table 21.9 LCD Characteristics — Prelimin ary —.............................................................495
Rev. 1.0, 02/02, page 1 of 502
Section 1 Overview
1.1 Overview
• High-speed H8S/2000 central processing unit with an internal 16-bit arc hitecture
Upward-compatible wit h H8/300 a nd H8/300H CPUs on an obj ect level
Sixteen 16-bit general registers
65 basic instructions
• Various periphe ral functions
16-bit time r-pulse unit (TPU)
Watchdog timer (WDT)
Asynchronous or clocked synchronous serial c ommunication int e rface (SCI)
Hitachi controller area network (HCAN)
10-bit A/D converter
Motor control PWM ti mer (PWM)
LCD controller /dri ver (LCD)
Clock pul se genera t or
• On-chip me mory
ROM Model ROM RAM Remarks
F-ZTAT Version HD64F2282 128k 4k Under
development
Mask ROM
Version HD6432282
HD6432281 128k
64k 4k
4k In planning
In planning
• General I/O ports
• I/O pins: 64
• Input-only pi ns: 8
• Supports var ious pow er- dow n sta tes
• Compact package
Package (Code) Body Size Pin Pitch
QFP-100 FP-100A 14.0 × 20.0 mm 0.65 mm
Rev. 1.0, 02/02, page 2 of 502
1.2 Internal Block Diagram
PWMV
CC
PWMV
CC
PWMV
SS
PWMV
SS
LPV
CC
V
CC
V
CC
V
SS
V
SS
V
SS
V
CL
V1
V2
V3
AV
CC
AV
SS
P47/AN7
P46/AN6
P45/AN5
P44/AN4
P43/AN3
P42/AN2
P41/AN1
P40/AN0
HRxD/
HTxD
PH7/PWM1H
PH6/PWM1G
PH5/PWM1F
PH4/PWM1E
PH3/PWM1D
PH2/PWM1C
PH1/PWM1B
PH0/PWM1A
PJ7/PWM2H
PJ6/PWM2G
PJ5/PWM2F
PJ4/PWM2E
PJ3/PWM2D
PJ2/PWM2C
PJ1/PWM2B
PJ0/PWM2A
PF7/
PF6/SEG24
PF5/SEG23
PF4/SEG22
PF3/ /
PF2/SEG21
P17/TIOCB2/TCLKD
P16/TIOCA2/
P15/TIOCB1/TCLKC
P14/TIOCA1/
P13/TIOCD0/TCLKB
P12/TIOCC0/TCLKA
P11/TIOCB0
P10/TIOCA0
RAM
TPU
3 channels
SCI 2 channels
PWM
MD2
MD0
EXTAL
XTAL
PLLCAP
PLLV
SS
NMI
FWE*
H8S/2000 CPU
PA7/SEG28
PA6/SEG27
PA5/SEG26
PA4/SEG25
PA3/COM4
PA2/COM3
PA1/COM2
PA0/COM1
Port A
PB7/SEG20
PB6/SEG19
PB5/SEG18
PB4/SEG17
PB3/SEG16
PB2/SEG15
PB1/SEG14
PB0/SEG13
Port B
PC7/SEG12
PC6/SEG11
PC5/SEG10
PC4/SEG9
PC3/SEG8
PC2/SEG7
PC1/SEG6
PC0/SEG5
PD7/SEG4
PD6/SEG3
PD5/SEG2
PD4/SEG1
Port CPort D
P35/SCK1/
P34/RxD1
P33/TxD1
P32/SCK0/
P31/RxD0
P30/TxD0
Port 3
Port 4
Port H Port J
Port FPort 1
PLL
Clock pulse
generator
Interrupt controller
ROM
(Mask ROM,
flash memory)
WDT 2 channels
LCD
HCAN 1 channel
10-bit A/D converter
Peripheral address bus
Peripheral data bus
Bus controller
Internal address bus
Internal data bus
Note: The FWE pin is provided only in the flash memory version.
The NC pin is provided only in the mask ROM version.
φ
Figure 1.1 Inter nal Block Diagram
Rev. 1.0, 02/02, page 3 of 502
1.3 Pin Arran gem ent
PJ3/PWM2D
PJ2/PWM2C
PJ1/PWM2B
PJ0/PWM2A
PH7/PWM1H
PH6/PWM1G
PH5/PWM1F
PH4/PWM1E
PWMV
CC
PWMV
SS
PH3/PWM1D
PH2/PWM1C
PH1/PWM1B
PH0/PWM1A
PA3/COM4
PA2/COM3
PA1/COM2
PA0/COM1
PA7/SEG28
PA6/SEG27
Top view
(FP-100A)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
P30/TxD0
PF3/ /
PF7/φ
V
CC
XTAL
EXTAL
V
SS
FWE
V
CL
PLLV
SS
PLLCAP
NMI
MD0
MD2
P17/TIOCB2/TCLKD
P16/TIOCA2/
P15/TIOCB1/TCLKC
P14/TIOCA1/
P13/TIOCD0/TCLKB
P12/TIOCD0/TCLKA
P11/TIOCB0
P10/TIOCA0
PJ7/PWM2H
PJ6/PWM2G
PJ5/PWM2F
PJ4/PWM2E
PWMV
CC
PWMV
SS
P31/RxD0
P32/SCK0/
P33/TxD1
P34/RxD1
P35/SCK1/
HRxD/
HTxD
P40/AN0
P41/AN1
P42/AN2
P43/AN3
P44/AN4
P45/AN5
P46/AN6
P47/AN7
AV
CC
AV
SS
V1
V2
V3
V
SS
V
CC
PD4/SEG1
PD5/SEG2
PD6/SEG3
PD7/SEG4
PC0/SEG5
PC1/SEG6
PC2/SEG7
PC3/SEG8
PC4/SEG9
PC5/SEG10
PC6/SEG11
PC7/SEG12
PB0/SEG13
PB1/SEG14
PB2/SEG15
PB3/SEG16
LPV
CC
V
SS
PB4/SEG17
PB5/SEG18
PB6/SEG19
PB7/SEG20
PF2/SEG21
PF4/SEG22
PF5/SEG23
PF6/SEG24
PA4/SEG25
PA5/SEG26
Figure 1.2 Pin Arrangement
Rev. 1.0, 02/02, page 4 of 502
1.4 Pin Functions
Type Symbol Pin NO. I/O Function
Power
Supply VCC 2
77 Input Power supply pins. Connect all t hese pins to t he
system power supply.
PWMVCC 42
52 Input Power supply pins for the ports H, J, and the
motor cont ro l P WM time r.
LPVCC 19 Input Power supply pins f or the port s A to D and F (PF2
and PF4 to PF6).
V1
V2
V3
98
99
100
Input Power supply pins for the LCD controller /driver.
These pins are inter nally connected to the power-
supply dividing resistors and in normal use are
open-circuit. When power is supplied, the stat e is
LPVCC ≥ V1 ≥ V2 ≥ V3 ≥ VSS.
VSS 1
20
74
Input Ground pins. Connect all these pins to the syst em
power supply (0V).
PWMVSS 41
51 Input Power supply pins for the ports H, J, and the
motor cont rol PWM timer. Connect all these pins
to the system power supply (0V).
VCL 71 Output External capacit ance pin f or internal power-down
power supply. Connect this pin t o VSS via a 0.1-
µF capacitor ( placed close to the pins).
Clock PLLVSS 70 Input On-chip PLL os cillator ground pin.
PLLCAP 69 O utput External capacit ance pin for an on-chip PLL
oscillator.
XTAL 76 Input For connection to a crystal resonator . For
examples of crystal r esonator connection and
external clock input, see section 18, Clock Pulse
Generator.
EXTAL 75 Input For connect ion to a crystal resonator.( An
external clock can be supplied from the EXTAL
pin.) For exam ples of crystal resonat or
connection and external clock input, see section
18, Clock Pulse Gener ator.
φ78 O utput Supplies the system clock to ext er nal devices.
Operating
mode
control
MD2
MD0 65
66 Input Set the operating mode. Inputs at these pins
should not be changed during operation.
System
control
5(6
73 Input Reset input pin. When this pin is low, the chip is
reset.
67%<
68 Input When t his pin is low, a transition is m ade to
hardware standby mode.
Rev. 1.0, 02/02, page 5 of 502
Type Symbol Pin NO. I/O Function
System
control FWE 72 I nput Pin for use by flash m emory. This pin is only used
in the flash memory version.
Interrupts NMI 67 Input Nonmaskable int errupt pin. If this pin is not used,
it should be fixed-high.
,54
,54
,54
,54
,54
,54
85
82
79
86
63
61
Input These pins reque st a maskable interru pt .
16-bit
timer-
pulse unit
TCLKA
TCLKB
TCLKC
TCLKD
59
60
62
64
Input These pins input an exter nal clock.
TIOCA0
TIOCB0
TIOCC0
TIOCD0
57
58
59
60
Input/
Output TGRA_0 to TGRD_0 input capt ure input/output
compare output/PWM output pins.
TIOCA1
TIOCB1 61
62 Input/
Output TGRA_1 to TGRB_1 input capt ure input/output
compare output/PWM output pins.
TIOCA2
TIOCB2 63
64 Input/
Output TGRA_2 to TGRB_2 input capt ure input/output
compare output/PWM output pins.
Serial
communi-
cation
TxD1
TxD0 83
80 Output Data output pins
Interface
(SCI)/ RxD1
RxD0 84
81 Input Data input pins
smart card
interface SCK1
SCK0 85
82 Input/
Output Clock input/ output pins
HCAN HTxD 87 O utput CAN bus transmission pin
HRxD 86 I nput CAN bus reception pin
A/D
converter AN7
AN6
AN5
AN4
AN3
AN2
AN1
AN0
95
94
93
92
91
90
89
88
Input Analog input pins
$'75*
79 Input Pin for input of an external trigger to start A/D
conversion
Rev. 1.0, 02/02, page 6 of 502
Type Symbol Pin NO. I/O Function
A/D
converter AVCC 96 Input P ower supply pin for the A/D conve r ter. When the
A/D converter is not used, connect this pin to the
system power supply (+5V).
AVSS 97 Input The ground pin f or the A/D converter. Connect
this pin to the system power supply (0V).
Motor
control
PWM
timer
PWM1H
PWM1G
PWM1F
PWM1E
PWM1D
PWM1C
PWM1B
PWM1A
46
45
44
43
40
39
38
37
Output PWM_1 pulse output pin
PWM2H
PWM2G
PWM2F
PWM2E
PWM2D
PWM2C
PWM2B
PWM2A
56
55
54
53
50
49
48
47
Output PWM_2 pulse output pin
LCD
controller/
driver
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
32
31
30
29
28
27
26
25
24
23
22
21
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
Output Output pins for the LCD-segment-driving signals.
Rev. 1.0, 02/02, page 7 of 502
Type Symbol Pin NO. I/O Function
LCD
controller/
driver
COM4
COM3
COM2
COM1
36
35
34
33
Output Output pins for the LCD-common-driving signals.
I/O p ort s P17
P16
P15
P14
P13
P12
P11
P10
64
63
62
61
60
59
58
57
Input/
Output Eight input/output pins
P35
P34
P33
P32
P31
P30
85
84
83
82
81
80
Input/
Output Six input/output pins
P47
P46
P45
P44
P43
P42
P41
P40
95
94
93
92
91
90
89
88
Input Eight input pins
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
32
31
30
29
36
35
34
33
Input/
Output Eight input/output pins
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
24
23
22
21
18
17
16
15
Input/
Output Eight input/output pins
Rev. 1.0, 02/02, page 8 of 502
Type Symbol Pin NO. I/O Function
I/O p ort s PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
14
13
12
11
10
9
8
7
Input/
Output Eight input/output pins
PD7
PD6
PD5
PD4
6
5
4
3
Input/
Output Four input/output pins
PF7
PF6
PF5
PF4
PF3
PF2
78
28
27
26
79
25
Input/
Output Six input/output pins
PH7
PH6
PH5
PH4
PH3
PH2
PH1
PH0
46
45
44
43
40
39
38
37
Input/
Output Eight input/output pins
PJ7
PJ6
PJ5
PJ4
PJ3
PJ2
PJ1
PJ0
56
55
54
53
50
49
48
47
Input/
Output Eight input/output pins
Rev. 1.0, 02/02, page 9 of 502
Section 2 CPU
The H8S/2000 CPU is a high-speed central processing unit with a n internal 32-bit architecture t hat
is upwa rd-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit
general re gisters, c an address a 16-Mbyte li near address spac e, and is ideal for realtime control.
This section de scribes the H8S/2000 CPU. The usable mode s and address spaces di ffer depe nding
on the product. For details on each product, refer to sec tion 3, MCU Operating Mode s.
2.1 Features
• Upward-compatible wi t h H8/300 and H8/300H CPUs
Can execute H8/300 an d H8/300H CPUs object progra ms
• General-register architecture
Sixteen 16-bit general registers a lso usabl e as sixteen 8-bit registers or eight 32-bit registers
• Sixty-five basic instructions
8/16/32-bit arithmetic and log ic instruc tions
Multiply and divide instruct i ons
Powerful bit-manipulation i nstructions
• Eight address ing modes
Register dire ct [Rn]
Register indirect [@ERn]
Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)]
Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]
Absolute ad d ress [ @aa:8, @aa:16, @aa:24, or @a a:32]
Immediate [#xx:8, #xx: 16, or #xx:32]
Program-counter re lative [@ (d:8,PC) or @(d:16,PC)]
Memory indirect [ @@aa:8]
• 16-Mbyt e addr ess space
Program: 16 Mbytes
Data: 16 Mbytes
• High-speed opera tion
All frequently-use d instructions execute in one or two states
8/16/32-bit reg ister -reg ist er add /subtr ac t : 1 state
8 × 8-bit regi ste r-register multiply : 12 states
16 ÷ 8-bit register-re gister divi de : 12 states
16 × 16-bi t registe r-register multiply : 20 states
32 ÷ 16-bi t register-regist er divide : 20 states
CPUS212A_000620020200
Rev. 1.0, 02/02, page 10 of 502
• Two CPU operating modes
Normal mode*
Advanced mode
• Power-down state
Transition to power-down state by SLEEP instruct i on
CPU clock speed select i on
Note:* Normal mode is not available in this LSI.
2.1.1 Differences between H 8S/2600 CPU and H8S/2000 CP U
The differe nces between the H8S/2600 CPU and the H8S/2000 CPU are shown below.
• Register configuration
The MAC register i s supported by the H8S/2600 CPU only.
• Basic instructions
The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported by t he H8S/2600
CPU only.
• The number of execution states of the MULXU and MULXS instructions;
Execution States
Instruction Mnemonic H8S/2600 H8S/2000
MUL XU MUL XU.B Rs, Rd 3 12
MUL XU.W Rs, ERd 4 20
MULXS MULXS.B Rs, Rd 4 1 3
MULXS.W Rs, ERd 5 21
In addition, there are diffe rences in address space, CCR a nd EXR register functions, a nd power-
down modes, etc., depend ing on the model .
Rev. 1.0, 02/02, page 11 of 502
2.1.2 Differences from H8/3 00 C PU
In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements:
• More general regi ste rs and control registers
Eight 16-bit expanded regi ste rs, and one 8-bit a nd two 32-bit control registers, have been
added.
• Expanded address space
Normal mode supports the same 64-kbyte address space as the H8/300 CPU.
Advanced mode supports a maximum 16-Mbyte addre ss space.
• Enhanc ed address ing
The addressing modes have been enhanced to make effective use of the 16-Mbyte address
space.
• Enhanc ed instru ctions
Addressing modes of bit-manipulation instructions have bee n enhanced.
Signed mul tiply and divi de instruc tions have been added.
Two-bit shift instructions ha ve been added.
Instructions for saving and restori ng multiple registers have been a dded.
A test and set instruction has been added.
• Higher speed
Basic instructions execute twice as fast.
2.1.3 Differences from H8/300H CP U
In comparison to the H8/300H CPU, the H8S/ 2000 CPU has the followi ng enhanc ements:
• Additional cont rol register
One 8-bit and two 32-bit cont rol regist e rs have been adde d.
• Enhanc ed instru ctions
Addressing modes of bit-manipulation instructions have bee n enhanced.
Two-bit shift instructions ha ve been added.
Instructions for saving and restori ng multiple registers have been a dded.
A test and set instruction has been added.
• Higher speed
Basic instructions execute twice as fast.
Rev. 1.0, 02/02, page 12 of 502
2.2 CPU Op erat in g Modes
The H8S/2000 CPU has two ope rating m odes: normal and advanced. Normal mode support s a
maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address
space. The mode is selected by the mode pins.
2.2.1 Normal Mode
The exception vector table and stack have the same structure as in the H8/300 CPU.
• Address Space
A maximum address space of 64 kbytes can be accessed.
• Extended Registers (En)
The extended regi sters (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit
segments of 32-bit registers. Whe n En is used as a 16-bit register it can contai n any val ue, e ve n
when the corresponding general re gister (Rn) is used as an a ddress regi ster. If the general
register is referenced in t he regist e r indirect a ddressing mode wit h pre-decrement (@ –Rn) or
post-increment (@Rn+ ) and a carry or borrow occurs, however, the value in the corresponding
extended re gister (E n) will be a ffected.
• Instruction Set
All instruc tions and addressing modes can be used. Only the lower 16 bits of effective
addresses (EA) are val id.
• Exception Vector Table and Memory Indirect Branch Addresses
In normal mode the to p area sta rting at H'0000 is al lo cated to th e excep tion v ector ta ble. One
branch address is st ored per 16 bits. The e xception vector table in normal mode is shown in
figure 2.1. For details of the exception vector table, see section 4, Exception Handling.
The memory i ndirect addressing m ode (@@aa:8) employed in the JMP and JSR i nst ructions
uses an 8-bit absolute address included in the instruction code to specify a memory operand
that contains a branch a ddress. In normal mode the operand is a 16-bit word operand,
providing a 16-bit branc h address. Branch addresses c an be stored in t he top area from H'0000
to H'00FF. Note that this area is also used for the exception vector table.
• Stack Structure
When the program counter (PC) i s pushed onto the stack in a subroutine call, and t he PC,
condition-code register (CCR), and e xtended control regi ster (EXR) are pushed onto the sta ck
in exception handling, they are stored as shown in fi gure 2.2. EXR is not pushed onto the
stack in interrupt control mode 0. For details, see section 4, Exception Handling.
Note: Normal mod e is no t available in th is LS I .
Rev. 1.0, 02/02, page 13 of 502
H'0000
H'0001
H'0002
H'0003
H'0004
H'0005
H'0006
H'0007
H'0008
H'0009
H'000A
H'000B
Exception vector 1
Exception vector 2
Exception vector 3
Exception vector 4
Exception vector 5
Exception vector 6
Exception
vector table
Figure 2.1 Exception Vector Table (Normal Mode)
PC
(16 bits) EXR*
1
Reserved*
1
,*
3
CCR
CCR*
3
PC
(16 bits)
SP SP
(SP*
2
1. When EXR is not used it is not stored on the stack.
2. SP when EXR is not used.
3. lgnored when returning.
Notes:
(b) Exception Handling(a) Subroutine Branch
)
Figure 2.2 Stack Structure in Normal Mode
2.2.2 Advanced Mode
• Address Space
Linear access is provided to a 16-Mbyte maxi mum address space is provi ded.
• Extended Registers (En)
The extended regi sters (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit
segments of 32-bit registers or a ddress re gisters.
• Instruction Set
All instruc tions and addressing modes can be used.
Rev. 1.0, 02/02, page 14 of 502
• Exception Vector Table and Memory Indirect Branch Addresses
In advanced m ode, the top a rea sta rting at H'00000000 i s allocated to the exception ve ctor
table in units of 32 bits. In each 32 bits, the uppe r 8 bits are ignore d and a branch a ddress is
stored in the lower 24 bit s (figure 2. 3). For details of t he exception vector ta ble, se e section 4,
Exception Handling.
H'00000000
H'00000003
H'00000004
H'0000000B
H'0000000C
H'00000010
H'00000008
H'00000007
Reserved
Reserved
Reserved
Reserved
Reserved
Exception vector 1
Exception vector 2
Exception vector 3
Exception vector 4
Exception vector table
Exception vector 5
Figure 2.3 Exception Vector Table (Advance d Mode)
The memory i ndirect addressing m ode (@@aa:8) employed in the JMP and JSR i nst ructions
uses an 8-bit absolute address included in the instruction code to specify a memory operand
that contains a branch a ddress. In advanced mode t he opera nd is a 32-bit longword operand,
providing a 32-bit branc h address. The upper 8 bits of t hese 32 bits is a reserved are a that is
regarded as H'00. Branc h addresses can be stored i n the a rea from H'00000000 to H'000000FF.
Note that the first part of this range is also the exception vector table.
• Stack Structure
In advanced m ode, when the program counter (PC) i s pushed onto the stack i n a subroutine
call, and the PC, condition-code re gister (CCR), and e xtended control registe r (EXR) are
pushed onto the stack in exception ha ndling, the y are stored as shown in figure 2.4. W hen
EXR is invalid, it is not pushed onto the stack. For details, see section 4, Exception Handling.
Rev. 1.0, 02/02, page 15 of 502
PC
(24 bits)
EXR*
1
Reserved*
1
,*
3
CCR
PC
(24 bits)
SP SP
(SP*
2
Reserved
(a) Subroutine Branch (b) Exception Handling
Notes:1. When EXR is not used it is not stored on the stack.
2. SP when EXR is not used.
3. Ignored when returning.
)
Figure 2.4 Stack Structure in Advanced Mode
Rev. 1.0, 02/02, page 16 of 502
2.3 Address Space
Figure 2. 5 shows a memory map for t he H8S/2000 CPU. The H8S/2000 CPU provide s linear
access to a maximum 64-kbyte address spac e in normal mode, and a maximum 16-Mb yte
(architectura ll y 4-Gbyte) address space in adv anced mod e. The usable modes and address spaces
differ depending on the product. For details on each product, refer to section 3, MCU Operating
Modes.
H'0000
H'FFFF
H'00000000
H'FFFFFFFF
H'00FFFFFF
64 kbytes 16 Mbytes
Program area
Data area
(b) Advanced Mode
(a) Normal Mode*
Note: * Normal mode is not available in this LSI.
Figure 2.5 Memory Map
Rev. 1.0, 02/02, page 17 of 502
2.4 Register Configuration
The H8S/2000 CPU has the int ernal registers shown in fi gure 2.6. There a re two type s of registers;
general re gisters and control re gisters. T he cont rol registe rs are a 24-bit program counte r (PC), an
8-bit extended cont rol regi ster (EXR), and an 8-bit condit ion code register (CCR).
T I2I1I0
EXR
76543210
PC
23 0
15 0 7 0 7 0
E0
E1
E2
E3
E4
E5
E6
E7
R0H
R1H
R2H
R3H
R4H
R5H
R6H
R7H
R0L
R1L
R2L
R3L
R4L
R5L
R6L
R7L
SP
PC
EXR
T
I2 to I0
CCR
I
: Stack pointer
: Program counter
: Extended control register
: Trace bit
: Interrupt mask bits
: Condition-code register
: Interrupt mask bit
: User bit or interrupt mask bit
: Half-carry flag
: User bit
: Negative flag
: Zero flag
: Overflow flag
: Carry flag
ER0
ER1
ER2
ER3
ER4
ER5
ER6
ER7 (SP)
IUIHUNZVC
CCR
76543210
UI
H
U
N
Z
V
C
General Registers (Rn) and Extended Registers (En)
Control Registers (CR)
Legend
----
Figure 2.6 CPU Registers
Rev. 1.0, 02/02, page 18 of 502
2.4.1 General Registers
The H8S/2000 CPU has eight 32-bit general registe rs. These general re gisters are all functionally
identical and can be used as both address registers and data registers. When a general register is
used as a data register, it ca n be accessed as a 32-bit, 16-bi t, or 8-bi t register. Figure 2. 7 illustra tes
the usage of the general registers. Whe n the general registers are used as 32-bit registers or address
registers, they are designated by the letters ER (ER0 to ER7).
The ER regi sters di vide into 16-bit general registe rs designated by the letters E (E0 to E7) and R
(R0 to R7). These registers are functionally equivale nt, provi ding a maximum of sixteen 16-bit
regis ters. Th e E reg is ters (E0 to E7 ) are also ref er red to as extend ed reg isters .
The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and
RL (R0L to R7L). These regi sters are functionally equivalent, providing a maximum of sixteen 8-
bit registers.
The usage of each register can be selected independently.
General register ER7 has the function of stack pointer (SP) in addition to its general-register
function, a nd is used implicitly in exc e ption handling and subroutine calls. Figure 2.8 shows the
stack.
• Address registers
• 32-bit registers • 16-bit registers • 8-bit registers
ER registers
(ER0 to ER7)
E registers (extended registers)
(E0 to E7)
R registers
(R0 to R7)
RH registers
(R0H to R7H)
RL registers
(R0L to R7L)
Figure 2.7 Usage of General Registers
Rev. 1.0, 02/02, page 19 of 502
SP (ER7)
Free area
Stack area
Fi g ure 2. 8 Stack Status
2. 4.2 Progra m Counter (PC)
This 24-bit counter i ndicates the address of the next instruction the CPU wil l execute . The length
of all CPU i nstructions i s 2 byte s (one word), so t he least significant PC bit i s ignored. (When a n
instruction is fetched, the least significant PC bit is regarded as 0).
2.4.3 Extended Control Register (EXR)
EXR is an 8-bit re gister t hat manip u late s th e LDC, STC, ANDC, ORC, and XORC in st ruc ti o ns.
When these instructi ons, except for t he STC instruction, are executed, a ll interrupt s including NMI
will be masked for three states after execution is completed.
Bit Bit Name Initial Value R/W Description
7T 0 R/WTrace Bit
When this bit is set to 1, a trace exception is
generated each tim e an instruction is executed.
When this bit is clear ed to 0, instructions are
executed in sequence.
6
5
4
3
−1−Reserved
They are al wa ys read as 1.
2
1
0
I2
I1
I0
1
1
1
R/W
R/W
R/W
These bits designat e the interrupt mask level (0 to
7). For details, refer to section 5, Interrupt
Controller.
Rev. 1.0, 02/02, page 20 of 502
2. 4.4 Condit i o n- Code Re gist er (CCR)
This 8-bit register contains int ernal CPU status information, including an interrupt mask bit (I) a nd
half-carry (H), negative (N), ze ro (Z), ove rflow (V), and carry (C) flags.
Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC
instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch
(Bcc) instructions.
Rev. 1.0, 02/02, page 21 of 502
Bit Bit Name Initial Value R/W Description
7 I 1 R/W Interrupt Mask Bit
Masks interrupts other than NMI when set to 1.
NMI is accepted regar dless of the I bit setting.
The I bit is set to 1 by hardware at the start of an
exception-handling sequence. For det ails, refer to
sec tion 5, Interrupt Co ntro ller.
6 UI Undefined R/W User Bit or Interrupt M ask Bit
Can be written and read by softwar e using the
LDC, STC, ANDC, ORC, a nd XORC instruction s .
This bit cannot be used as an interrupt m ask bit in
this LSI.
5 H Undefined R/ W Half-Carry Flag
When t he ADD.B, ADDX.B, SUB.B, SUBX.B,
CMP.B, or NEG.B instruction is executed, this
flag is set to 1 if there is a carry or borrow at bit 3,
and cleared to 0 otherwise. When t he ADD.W,
SUB.W, CMP.W, or NEG.W instructio n is
executed, the H flag is set to 1 if there is a carry
or borrow at bit 11, and clear ed to 0 otherwise.
When the ADD.L, SUB.L, CMP.L, or NEG. L
instruction is executed, the H flag is set to 1 if
there is a carr y or bor r ow at bit 27, and cleared to
0 otherwise.
4 U Undefined R/ W User Bit
Can be written and read by softwar e using the
LDC, STC, ANDC, ORC, a nd XORC instruction s .
3 N Undefined R/ W Negative Flag
Stores the value of t he most significant bit of data
as a sign bit.
2 Z Undefined R/W Zero Flag
Set to 1 to indicate zero data, and cleared to 0 to
indicate non-zero data .
1 V Undefined R/ W Overflow Flag
Set to 1 when an arithmetic overf low occurs, and
cleared to 0 at ot her times.
Rev. 1.0, 02/02, page 22 of 502
Bit Bit Name Initial Value R/W Description
0 C Undefined R/W Car r y Flag
Set to 1 when a carry occurs, and clear ed to 0
otherwise. Used by:
• Add inst r uctions, to indicate a carry
• Subtract instructions, to indicate a borrow
• Shift and rotate instructions, to indicate a
carry
The carry flag is also used as a bit accum ulator
by bit manipulation instructions.
2. 4.5 Initial Val ues of CPU Register s
Reset e xception handl ing loads the CPU's program counter (PC) from the vector t able, clears the
trace bit in E XR to 0, and sets the interrupt ma sk bits in CCR and EXR to 1. The other CCR bits
and the general registers are not initialized. In particular, the stack pointer (ER7) is not initialized.
The stack poi nter should t herefore be initialized by an MOV.L instruc t ion executed immediately
aft er a reset.
Rev. 1.0, 02/02, page 23 of 502
2.5 Data Form ats
The H8S/2000 CPU ca n proc e ss 1-bit , 4-bit (BCD), 8-bit (byte ), 16-bit (word), and 32-bit
(longword) data. Bit-manipulation instructions ope rate on 1-bit data by accessing bit n (n = 0, 1, 2,
…, 7) of byte o peran d dat a. The DAA and DAS decimal-adjust inst ruc ti o ns treat b yte data as t wo
digits of 4-bit BCD data.
2.5.1 General Regi ster Data Formats
Figure 2. 9 shows the data formats in general registers.
70
70
MSB LSB
MSB LSB
7043
Don't care
Don't care
Don't care
7043
70
Don't care
65432710
70
Don't care 65432710
Don't care
RnH
RnL
RnH
RnL
RnH
RnL
Data Type Register Number Data Format
Byte data
Byte data
4-bit BCD data
4-bit BCD data
1-bit data
1-bit data
Upper Lower
Upper Lower
Figure 2.9 General Register Data Formats (1)
Rev. 1.0, 02/02, page 24 of 502
15 0
MSB LSB
15 0
MSB LSB
31 16
MSB
15 0
LSB
En Rn
ERn
En
Rn
RnH
RnL
MSB
LSB
: General register ER
: General register E
: General register R
: General register RH
: General register RL
: Most significant bit
: Least significant bit
Data Type Data FormatRegister Number
Word data
Word data
Rn
En
Longword data
Legend
ERn
Figure 2.9 General Register Data Formats (2)
Rev. 1.0, 02/02, page 25 of 502
2.5.2 Memory Data Formats
Figure 2. 10 shows the data formats in memory. The H8S/2000 CPU can access word dat a and
longword data in memory, howeve r word or longword data must begin a t an e ven address. If an
attempt is made to access word or longword data at an odd address, an address error does not
occur, however the least significant bit of the address is regarded as 0, so access begins the
preceding ad dress . This also app lies to ins tr uction fetches.
When ER7 is used as a n address register to access t he stack, the operand size should be word or
longword.
70
76 543210
MSB LSB
MSB
MSB
LSB
LSB
Data Type Address
1-bit data
Byte data
Word data
Address L
Address L
Address 2M
Address 2M+1
Longword data Address 2N
Address 2N+1
Address 2N+2
Address 2N+3
Data Format
Figure 2.10 Memory Data Formats
Rev. 1.0, 02/02, page 26 of 502
2.6 Instruction Set
The H8S/2000 CPU has 65 instructions. The instructions are classified by function in t able 2.1.
Tabl e 2.1 Instr ucti o n Classi ficatio n
Function Instructions Size Types
Da ta transfer M OV B/W/L 5
POP*1, PUSH*1W/L
LDM, STM L
MOVFPE*3, MOVTPE*3B
Arithmet ic ADD, SUB, CMP, NEG B/W/ L 19
operations ADDX, SUBX, DAA, DAS B
INC, DEC B/W/L
ADDS, SUBS L
MULXU, DIVXU, MULXS, DIVXS B/W
EXTU, EXTS W/ L
TAS*4B
Logic operations AND, OR, XO R, NOT B/W/L 4
Shift SHAL , SHAR, SHLL, SHLR, RO TL, ROTR, ROTXL, ROTXR B/W/ L 8
Bit manipulation BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND,
BIAND, BO R, BIOR, BXOR, BIXOR B14
Branch Bcc*2, JMP, BSR, JSR, RTS — 5
System contr ol TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP — 9
Block d ata transfe r EEPMOV — 1
Total: 65
Not e s: B-b y te ; W- word ; L - lo ngword.
1. PO P.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn,
@-SP. POP.L ERn and PUSH.L ERn are identical t o MOV.L @SP+, ERn and MOV.L
ERn, @-SP.
2. Bcc is the general name for condit ional branch instructions.
3. Cannot be used in this LSI.
4. Only regist er ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
Rev. 1.0, 02/02, page 27 of 502
2. 6.1 Tabl e of Instr uc tio ns Cl a ssifie d by Func tio n
Tables 2-3 to 2.10 summarizes the instructions in each functional category. The notation used in
tables 2-3 to 2-10 is define d below.
Table 2.2 O peration Notation
Symbol Description
Rd General r egister (destinat ion)*
Rs General register (s ource)*
Rn General regis ter*
ERn General register (32- bit register)
(EAd) Destination oper and
(EAs) Source operand
EXR Extended control register
CCR Condition-code regis ter
N N (negative) flag in CCR
Z Z (zero) flag in CCR
V V (o verf low) flag in CCR
C C (carry) flag in CCR
PC Prog r am counter
SP Stack pointer
#IMM Immediate data
disp Displacement
+ Addition
– Subtraction
×Multiplication
÷ Division
∧Logical AND
∨Logical OR
⊕Logical XO R
→Move
¬ NOT (logical com pl eme nt )
:8/:16/:24/:32 8-, 16-, 24-, or 32-bit lengt h
Note: *G eneral registers include 8-bit registers (R0H t o R7H, R0L t o R7L) , 16-bit registers (R0 to
R7, E0 to E7), and 32-bit register s (ER0 to ER7).
Rev. 1.0, 02/02, page 28 of 502
Table 2.3 Data Transfer Instructions
Instruction Size*Function
MOV B/W/L (EAs) → Rd , Rs → (EAd)
Moves dat a between two general registers or between a general register
and mem ory, or moves im mediate dat a to a general r egister.
MOVFPE B Cannot be used in this LSI.
MOVTPE B Cannot be used in this LSI.
POP W/L @SP+ → Rn
Pops a general register fr om the stack. POP.W Rn is ident ical to MOV.W
@SP+, Rn. POP.L ERn is identical to MOV. L @SP+, ERn.
PUSH W/L Rn → @–S P
Pushes a general register onto t he stack. PUSH.W Rn is identical to
MOV.W Rn, @– SP. PUSH. L ERn is identical to MOV.L ERn, @–SP.
LDM L @SP+ → Rn (register list)
Pops two or more general registers from the stack.
STM L Rn (register list) → @–S P
Pushes two or more gener al registers onto the stack.
Note: * Refers t o the oper and size.
B: Byte
W: Word
L: Longword
Rev. 1.0, 02/02, page 29 of 502
Tabl e 2.4 Ar i t hmetic Opera tions Inst r uctions ( 1)
Instruction Size*Function
ADD
SUB B/W/L Rd ± Rs → Rd, Rd ± # IMM → Rd
Performs addition or subtraction on data in two general registers, or on
immediate data and dat a in a general regist er (immediate byte dat a
cannot be subtracted from byte data in a general register. Use the SUBX
or ADD instruction.)
ADDX
SUBX BRd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd
Performs addition or subtraction with carry on byte dat a in t wo general
registers, or on immediate data and data in a general register.
INC
DEC B/W/L Rd ± 1 → Rd , Rd ± 2 → Rd
Increments or decrements a general register by 1 or 2. (Byte oper ands
can be incremented or decremented by 1 only.)
ADDS
SUBS LRd ± 1 → Rd , Rd ± 2 → Rd, Rd ± 4 → Rd
Adds or subt r acts the value 1, 2, or 4 to or from dat a in a 32-bit register.
DAA
DAS BRd decim al adjust → Rd
Decimal-adjusts an addition or subtraction result in a general register by
referring to the CCR to produce 4-bit BCD data.
MULXU B/W Rd × Rs → Rd
Performs unsigned multiplication on data in two general registers: either
8 bits × 8 bits → 16 bits or 16 bits ×
16 bits → 32 bits.
MULXS B/W Rd × Rs → Rd
Performs signed multiplication on data in two general registers: either 8
bits × 8 bi t s → 16 bits or 16 bits ×
16 bits → 32 bits.
DIVXU B/W Rd ÷ Rs → Rd
Performs unsigned division on data in two general registers: either 16
bits ÷ 8 bits → 8-bit quotient and 8- bit remainder or 32 bits ÷ 16 bits →
16-bit quotient and 16-bit remainder.
Note: * Refers t o the oper and size.
B: Byte
W: Word
L: Longword
Rev. 1.0, 02/02, page 30 of 502
Tabl e 2.4 Ar i t hmetic Opera tions Inst r uctions ( 2)
Instruction Size*1Function
DIVXS B/W Rd ÷ Rs → Rd
Performs signed division on data in two general registers: either 16 bits ÷
8 bits → 8-bit quotient and 8- bit remainder or 32 bits ÷ 16 bits → 16-bit
quotient and 16-bit remainder.
CMP B/W/L Rd – Rs, Rd – #IMM
Compares data in a general register with data in another general regist er
or with immed ia te data, a n d sets CCR bits acc or din g t o the re s u lt.
NEG B/W/L 0 – Rd → Rd
Takes the t wo's complement (arithmetic complement) of data in a
general regist er.
EXTU W/L Rd (zero extension) → Rd
Extends t he lower 8 bits of a 16-bit regist er to wor d size, or the lower 16
bits of a 32-bit register t o longword size, by padding with zeros on the
left.
EXTS W/L Rd (s ig n extension ) → Rd
Extends t he lower 8 bits of a 16-bit regist er to wor d size, or the lower 16
bits of a 32-bit register t o longword size, by extending the sign bit.
TAS*2B @ER d – 0, 1 → (<bit 7> of @ERd)
Tests m emory contents, and sets the most significant bit (bit 7) to 1.
Note: 1.Refers to the operand size.
B: Byte
W: Word
L: Longword
2. Only regist er ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
Rev. 1.0, 02/02, page 31 of 502
Table 2.5 Logi c Operations Instr uc tions
Instruction Size*Function
AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #I MM → Rd
Performs a logical AND oper ation on a general r egister and another
general regist er or immediate data.
OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
Performs a logical OR oper ation on a general register and another
general regist er or immediate data.
XOR B/W/L Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
Performs a logical exclusive OR operation on a gener al register and
another general register or immediate data.
NOT B/W/L ¬ (Rd) → (Rd)
Takes the one's complement of general register contents.
Note: * Refers t o the oper and size.
B: Byte
W: Word
L: Longword
Tabl e 2.6 Shi ft Inst r uc tio ns
Instruction Size*Function
SHAL
SHAR B/W/L Rd (shift) → Rd
Performs an arithmetic shift on general register contents.
1-bit or 2-bit shifts ar e possible.
SHLL
SHLR B/W/L Rd (shift) → Rd
Performs a logical shift on general register cont ents.
1-bit or 2-bit shifts ar e possible.
ROTL
ROTR B/ W/L Rd (r otate) → Rd
Rotates gene ral registe r con ten ts.
1-bit or 2-bit rotations ar e possible.
ROTXL
ROTXR B/ W/L Rd (r otate) → Rd
Rotates general register contents through the carry flag.
1-bit or 2-bit rotations ar e possible.
Note: * Refers t o the oper and size.
B: Byte
W: Word
L: Longword
Rev. 1.0, 02/02, page 32 of 502
Tabl e 2.7 Bi t Mani pulat i o n Instruc tio ns ( 1)
Instruction Size*Function
BSET B 1 → (<bit-No.> of <EAd>)
Sets a specif ied bit in a gener al register or m emory operand to 1.
The bit num ber is specified by 3-bit immediate data or the lower three
bits of a general register.
BCLR B 0 → (<bit-No.> of <EAd>)
Clears a specified bit in a general regist er or m emory oper and to 0.
The bit num ber is specified by 3-bit immediate data or the lower three
bits of a general register.
BNOT B ¬ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)
Inverts a specified bit in a general r egister or mem ory operand.
The bit num ber is specified by 3-bit immediate data or the lower three
bits of a general register.
BTST B ¬ (<bit-No.> of <EAd>) → Z
Tests a specified bit in a general register or m emory oper and and sets or
clears the Z flag accordingly.
The bit num ber is specified by 3-bit immediate data or the lower three
bits of a general register.
BAND
BIAND
B
B
C ∧ (<bit-No.> of <EAd>) → C
ANDs the carr y flag with a specified bit in a general regist er or memory
operand and stores the result in t he carry flag.
C ∧ ¬ (<bit-No.> of <EAd>) → C
ANDs the carry flag with the inverse of a specified bit in a general
register or m emory oper and and stor es the r esult in t he carry flag.
The bit num ber is specified by 3-bit immediate data.
BOR
BIOR
B
B
C ∨ (<bit-No.> of <EAd>) → C
ORs the carry flag wit h a specified bit in a general register or memor y
operand and stores the result in t he carry flag.
C ∨ ¬ (<bit-No.> of <EAd>) → C
ORs the carry flag wit h the inverse of a specified bit in a general register
or memory operand and sto res the resul t in the carry flag.
The bit num ber is specified by 3-bit immediate data.
Note: * Refers t o the oper and size.
B: Byte
Rev. 1.0, 02/02, page 33 of 502
Tabl e 2.7 Bi t Mani pulat i o n Instruc tio ns ( 2)
Instruction Size*Function
BXOR
BIXOR
B
B
C ⊕ (<bit-No.> of <EAd>) → C
XORs the carry f lag with a specified bit in a general register or memor y
operand and stores the result in t he carry flag.
C ⊕ ¬ (<bit-No.> of <EAd>) → C
XORs the carry f lag with t he inver se of a specified bit in a general
register or m emory oper and and stor es the r esult in t he carry flag.
The bit num ber is specified by 3-bit immediate data.
BLD
BILD
B
B
(<bit-No.> of <EAd>) → C
Transfers a specified bit in a general r egister or memory oper and to the
carry flag.
¬ (<bit-No.> of <EAd>) → C
Transfers the inverse of a specified bit in a general register or memory
operand to the carry flag.
The bit num ber is specified by 3-bit immediate data.
BST
BIST
B
B
C → (<bit-No.> of <EAd>)
Transfers the car r y flag value to a specified bit in a general register or
memory oper and.
¬ C → (<bit-No.> of <EAd>)
Transfers the inverse of the carry flag value t o a specified bit in a general
register or memory oper and.
The bit num ber is specified by 3-bit immediate data.
Note: * Refers t o the oper and size.
B: Byte
Rev. 1.0, 02/02, page 34 of 502
Tabl e 2.8 Br a nc h Instructions
Instruction Size Function
Bcc — Branches t o a specified address if a specified condition is true. The
branching conditions are listed below.
Mnemonic Description Condition
BRA(BT) Always (t rue) Always
BRN(BF) Never (false) Never
BHI High C ∨ Z = 0
BLS Low or same C ∨ Z = 1
BCC(BHS) Car ry clear
(hi g h o r s ame) C = 0
BCS(BLO) Carry set (low) C = 1
BNE Not equal Z = 0
BEQ Equal Z = 1
BVC Overflow clear V = 0
BVS Overflow set V = 1
BPL Plus N = 0
BMI Minus N = 1
BGE Greate r or equal N ⊕ V = 0
BLT Less than N ⊕ V = 1
BGT Greater than Z∨(N ⊕ V) = 0
BLE Less or equal Z∨(N ⊕ V) = 1
JMP — Branches unconditionally to a specified address.
BSR — Branches t o a subroutine at a specified address.
JSR — Branches to a subrout ine at a specified address.
RTS — Returns from a subroutine
Rev. 1.0, 02/02, page 35 of 502
Tabl e 2.9 Syst e m Contro l Instr uctions
Instruction Size*Function
TRAPA — Starts trap- instruction exception handling.
RTE — Returns from an exception-handling r outine.
SLEEP — Causes a t r ansition to a power-down state.
LDC B/W (EAs) → CCR, (EAs) → EXR
Moves t he sour ce operand cont ents or immediate dat a to CCR or EXR.
Although CCR and EXR are 8-bit registers, word- s ize transfers are
performed between t hem and memory. The upper 8 bits are valid.
STC B/W CCR → (EAd), EXR → (EAd)
Transfers CCR or EXR contents to a general r egister or memory.
Although CCR and EXR are 8-bit registers, word- s ize transfers are
performed between t hem and memory. The upper 8 bits are valid.
ANDC B CCR ∧ #IMM → CCR, EXR ∧ #I MM → EXR
Logically ANDs the CCR or EXR contents with immediate data.
ORC B CCR ∨ #IMM → CCR, EXR ∨ #IM M → EXR
Logically ORs the CCR or EXR c ontents with immediate data.
XORC B CCR ⊕ #IMM → CCR, EXR ⊕ #I MM → EXR
Logically XORs the CCR or EXR c o ntents with immediate data.
NOP — PC + 2 → PC
Only increm ents the program counter.
Note: * Refers t o the oper and size.
B: Byte
W: Word
Rev. 1.0, 02/02, page 36 of 502
Tabl e 2.1 0 Bl o c k Data Transfe r Instr uc ti ons
Instruction Size Function
EEPMOV. B — if R4L ≠ 0 t hen
Repeat @ER5+ → @ER 6 +
R4L–1 → R4L
Until R4 L = 0
else next;
EEPMOV.W — if R4 ≠ 0 then
Repeat @ER5+ → @ER 6 +
R4–1 → R4
Unt il R4 = 0
else next;
Transfers a data block. St arting from the address set in ER5, tr ansfers
data for the number of byt es set in R4L or R4 to the addr ess locat ion set
in ER6.
Execution of the next instruction begins as soon as the transfer is
completed.
2.6.2 Basic Instruc tion Formats
This LSI i nstructions consist of 2-byte (1-word) units. An instruction consists of an operation field
(op field), a regi ster fie ld (r field), a n effec tive address extension (EA fie l d), and a condition field
(cc).
Figure 2. 11 shows exam ples of instruction formats.
Rev. 1.0, 02/02, page 37 of 502
• Operation Field
Indicates the funct ion of the instruct ion , the addressin g mode, and the operatio n to be carried
out on the operand. The ope ration field alwa ys includes the first four bits of t he instruction.
Some instructions have two operation fi elds.
• Register Field
Specifies a general register. Address registers are specified by 3 bits, and data registers by 3
bits or 4 bits. Some instructions ha ve two regi ster fields. Some have no registe r field.
• Effective Address Extension
8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement.
• Condition Field
Specifies the branching condition of Bcc instructions.
op
op rn rm
NOP, RTS, etc.
ADD.B Rn, Rm, etc.
MOV.B @(d:16, Rn), Rm, etc.
rn rm
op
EA(disp)
op cc EA(disp) BRA d:16, etc.
(1) Operation field only
(2) Operation field and register fields
(3) Operation field, register fields, and effective address extension
(4) Operation field, effective address extension, and condition field
Fig ure 2.11 Instruction Formats (Examples)
Rev. 1.0, 02/02, page 38 of 502
2.7 Add ressi ng Mod es and Ef f ective Address Calcul at i on
The H8S/2000 CPU supports the eight addressing m odes l i sted in table 2.11. Each instruction uses
a subset of these addressing modes. Arithmetic and logic instructions can use the register direct
and immediate modes. Data transfer i nstructions can use all addressing modes except program-
counter rel ative and memory i ndirect. Bit m a nipulation instructi ons use re gister direct, re gister
indirect, or the absolute addressing mode to specify an operand, and register direct (BSET, BCLR,
BNOT, and BTST instructions) or immediate (3-bit) addressing mode to specify a bit number in
the operand.
Tabl e 2.1 1 Addressing Mode s
No. Addressing Mode Symbol
1 Register direct Rn
2 Register indirect @ERn
3 Register indirect with displacement @(d:16,ERn) /@(d:32,ERn)
4Register indirect with post-increment
Register indirect with pre-decr ement @ERn+
@–ERn
5 Absolute address @aa:8/@aa:16/@aa:24/@aa: 32
6 Immediate #xx:8/#xx:16/#xx:32
7 Program-coun te r relative @(d:8,PC)/ @(d:16 ,PC)
8 Memory indirect @@aa:8
2.7.1 Register Direct—Rn
The registe r field of the i nstruction specifies an 8-, 16-, or 32-bit genera l register cont aining the
operand. R0H to R7H and R0L to R7L can be specified as 8-bit regi sters. R0 t o R7 a nd E0 to E 7
can be specified as 16-bit re gi sters. ER0 to ER7 can be specified as 32-bit regi sters.
2.7.2 Register Indirect—@ERn
The register field of the instruction code specifies an address register (ERn) which contains the
address of the opera nd on memory. If t he addre ss is a progra m instruction a ddress, the l ower 24
bits are valid and t he upper 8 bits are al l assum ed to be 0 (H'00).
2.7.3 Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn)
A 16-bi t or 32-bit displacem e nt conta ined in the i nstruction is adde d to an a ddress regi ster (ERn)
specified by the register field of the instruction, and the sum gives the address of a memory
operand. A 16-bit displacement i s sign-extended whe n added.
Rev. 1.0, 02/02, page 39 of 502
2.7.4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn
Register indir ec t with po st -inc re ment— @ERn+: The register field of the instruction code
specifies an address register (ERn) which contains the address of a memory operand. After the
operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the
address register. The value added is 1 for byte access, 2 for word transfer i nstruction, or 4 for
longword tra nsfer i nstruction. For the word or longword transfer instructions, the register value
should be even.
Register indir ec t with pre - decre ment — @-ERn: The value 1, 2, or 4 is subtracted from an
address register (ERn) spe c ified by the registe r field in the instruction code, and the result is the
address of a memory operand. The result i s also st ored in t he address register. The value
subtracted i s 1 for byte access, 2 for word transfer instruct i on, or 4 for l ongword t ransfer
instruction. For t he word or longword transfer instruc tions, the re gi ster value should be even.
2.7.5 Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32
The instruction code contains the absolute address of a memory operand. The absolute address
may be 8 bits long (@aa:8), 16 bits l ong (@aa:16), 24 bits long (@aa:24), or 32 bits long
(@aa:32). Table 2.12 indicates the accessible absolute address ranges.
To access data, the absolute address should be 8 bit s (@aa:8), 16 bits (@aa:16), or 32 bits
(@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF).
For a 16-bit absolut e address the upper 16 bits are a sign extension. A 32-bit absolute address can
access the entire address space.
A 24-bi t absolute address (@ aa:24) indicates t he addre ss of a program i nstruction. The uppe r 8
bits are all as s u med to be 0 (H'00).
Tabl e 2.1 2 Absol ut e Addre ss Access Ranges
Absol ute Address Norm al Mode*Advanced Mod e
Data address 8 bits (@aa:8) H'FF00 to H'FFFF H'FFFF00 to H'FFFFFF
16 bits (@aa:16) H '0000 to H'FFFF H'000000 to H'007FFF,
H'FF8000 to H'FFF FFF
32 bits (@aa:32) H'000000 to H'FFFFFF
Prog ram instructio n
address 24 bits (@aa:24)
Note: Normal m ode is not available in t his LSI .
Rev. 1.0, 02/02, page 40 of 502
2.7.6 Immediate—#xx:8, #xx:16, or #xx:32
The instruction contains 8-bi t (#xx:8), 16-bit (#xx:16), or 32-bit (#xx: 32) immediate data as an
operand.
Th e ADDS, SUBS, I NC, and DEC in stru ction s contai n imm edia te data imp li ci t ly. So me bit
manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit
number. The TRAPA i nstruction contains 2-bit immediate data in its instruct ion code , specifying a
vector address.
2.7.7 Program-Counter Relati ve—@(d:8, PC) or @(d:16, PC)
This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in
the instruction is sign-extended and added to the 24-bit PC contents to generate a branch address.
Only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0
(H'00). The PC value to which the displacement is added is the address of the first byte of the next
instruction, so t he possible bra nching ra nge is –126 to +128 byte s (–63 to +64 words) or –32766 to
+32768 byte s (–16383 to +16384 words) from the branch instruct ion. The result ing value should
be an even number.
2. 7.8 Me mor y Indire c t—@@ aa:8
This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit
absolute addre ss spe cifying a me m ory operand. This me mory opera nd contai ns a branch address.
The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255
(H'0000 to H'00FF in normal mode, H'000000 to H'0000FF i n advanced m ode). In normal mode,
the memory operand i s a word operand and the branch a ddress is 16 bits long. In advanced mode,
the memory operand i s a longword operand, t he first byte of which is assumed to be 0 (H'00).
Note that the first part of t he addre ss range is also t he exception vector area. For further details,
refer to section 4, Exception Handling.
If an odd address is specified in word or longword memory a ccess, or as a branch addre ss, the
least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched
at the address preceding the specified address. (For further information, see section 2.5.2, Memory
Dat a Format s.)
Note: Normal mode is not available in this LSI.
Rev. 1.0, 02/02, page 41 of 502
Specified
by @aa:8 Specified
by @aa:8
Branch address
Branch address
Reserved
(a) Normal Mode
*
(a) Advanced Mode
Note: * Normal mode is not available in this LSI.
Fi g ure 2.12 Br a nch Addre ss Spec i f ic ati on in Memory Indirect Mode
2.7.9 Effe ctive Address Calcul ation
Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal
mode the upper 8 bit s of the effective address a re ignore d in order to gene rate a 16-bit address.
Note : Normal mode is not available in this LSI.
Rev. 1.0, 02/02, page 42 of 502
Table 2.13 Effective Address Calculation (1)
No
1
Offset
1
2
4
r
op
31 0
31 23
2
3 Register indirect with displacement
@(d:16,ERn) or @(d:32,ERn)
4
r
op disp
r
op
rm
op rn
31 0
31 0
r
op
Don't care
31 2331 0
Don't care
31 0
disp
31 0
31 0
31 2331 0
Don't care
31 2331 0
Don't care
24
24
24
24
Addressing Mode and Instruction Format Effective Address Calculation Effective Address (EA)
Register direct(Rn)
General register contents
General register contents
General register contents
General register contents
Sign extension
Register indirect(@ERn)
Register indirect with post-increment or
pre-decrement
•Register indirect with post-increment @ERn+
•Register indirect with pre-decrement @-ERn
1, 2, or 4
1, 2, or 4
Operand Size
Byte
Word
Longword
Operand is general register contents.
Rev. 1.0, 02/02, page 43 of 502
Table 2.13 Effective Address Calculation (2)
No
5
op 31 23
31 0
Don't care
abs
@aa:8 7
H'FFFF
op 31 23
31 0
Don't care
@aa:16
op
@aa:24
@aa:32
abs 15
16
31 2331 0
Don't care
31 23
31 0
Don't care
abs
op
abs
6
op IMM
#xx:8/#xx:16/#xx:32
8
24
24
24
24
Addressing Mode and Instruction Format
Absolute address
Immediate
Effective Address Calculation Effective Address (EA)
Sign extension
Operand is immediate data.
31 23
7
Program-counter relative
@(d:8,PC) @(d:16,PC)
Memory indirect @@aa:8
• Normal mode*
• Advanced mode
31 0
Don't care
23 0
disp
0
31 2331 0
Don't care
disp
op
23
op
8
abs 31 0
abs
H'000000 78
015 31 2331 0
Don't care 15
H'0016
op abs 31 0
abs
H'000000 78
0
31
24
24
24
Note: * Normal mode is not available in this LSI.
PC contents
Sign
extension
Memory contents
Memory contents
Rev. 1.0, 02/02, page 44 of 502
2.8 P rocessin g S t at es
The H8S/2000 CPU has five ma in proce ssing states: the reset state, exception handling state,
program execution sta te, bus-re leased state, a nd power-down state. Figure 2.13 indi cates the sta te
transitions.
• Rese t State
In this state, the CPU and all on-chip peripheral modules are initialized and not operating.
Whe n the
5(6
input goes low, all current processing stops and the CPU enters t he reset state.
All interrupts are m asked in the reset state . Reset exception handl ing st a rts whe n the
5(6
signal changes from low to high . For details , refer to s ec tion 4 , Exception Handli ng.
The reset state can also be e ntered by a watchdog ti mer overfl ow.
• Exception-Handling State
The exception-ha ndling state is a transient state that occurs when the CPU al ters the normal
processing flow due to an exc eption source, such as a re set, trace, interrupt, or trap i nstruction.
The CPU fetches a start address (vector) from the e xception vector table and branches t o that
address. For further details, refer to section 4, E xception Handling.
• Progra m Execut ion State
In this state, the CPU e xecutes program inst ructions in se que nce.
• Bus-Release d State
The bus-re leased sta te occurs whe n the bus has be e n re leased in response to a bus request from
a bus master other than the CPU.
While the bus is released, the CPU halts operations.
• Program stop state
This is a power-down st ate in which t he CPU stops ope rating. The program stop state occurs
when a SLEEP instruc tion is executed or the CPU enters hardware sta ndby mode. For further
details, refer to section 19, Power-Down Modes.
Rev. 1.0, 02/02, page 45 of 502
Program execution state
Exception handling state
Program halt state
Bus-released state
Reset state
*
End of bus
request
Bus
request
Interrupt
request
SLEEP instruction
= High
= High,
= Low
Notes: From any state, a transition to hardware standby mode occurs when goes low.
*From any state except hardware standby mode, a transition to the reset state
occurs whenever goes low. A transition can also be made to the reset state
when the watchdog timer overflows.
Bus
request End of
bus request
Request for
exception
handling
End of
exception
handling
Figure 2.13 State Transitions
2.9 Usage Note
2. 9.1 Note o n Bit Manipulation Instruc tio ns
Bit manipulation instructions such as BSET, BCLR, BNOT, BST, and BIST read data in byte
units, perform bit manipulation, a nd write data in byte units. Thus, c are must be taken when these
bit manipulation instructions a re executed for a register or port including write-only bit s.
In addition, the BCLR instruction can be used to clear the flag of an internal I/O register. In this
case, if t he flag to be cleared has been set by a n interrupt processing routi ne, the flag nee d not be
read before execut ing the BCLR instruction .
Rev. 1.0, 02/02, page 46 of 502
Rev. 1.0, 02/02, page 47 of 502
Section 3 MCU Operating Modes
3.1 Operat in g Mod e Selection
This LSI supports onl y operati ng mode 7, that i s, the a dvanced single-chip mode. The ope rating
mode is determined by the setting of the mode pins (MD2 and MD0). Only m ode 7 can be used in
this LSI. Therefore, al l mode pins must be fixed hi gh, as shown in table 3.1. Do not change the
mode pin settings during ope ration.
Tabl e 3.1 M CU Operat i ng Mode Selection
MCU CPU External Data Bus
Operating
Mode MD2 MD0 Operating
Mode Description On-Chip
ROM Initial
Width Max.
Width
7 1 1 Advanced mode Singl e-chip mode Enabl ed — —
3.2 Register Descri pt i on s
The following registers are related to the operating mode.
• Mode control register (MDCR)
• System cont rol register (SYSCR)
3. 2.1 Mode Co ntrol Register (MDCR)
Bit Bit Name Initial Value R/ W Descriptions
7−1R/WReserved
Only 1 should be wr itten to this bit.
6 to
3−0−Reserved
These bits are always read as 0 and cannot be
modified.
2MDS2 −R This bit indicates the input level at pin MD2 (the current
operating m ode). This bit corresponds to MD2. MDS2
is read-only bit and this cannot be writ t en to. The MD2
input level is latched into this bit when MDCR is read.
This latch is canceled by a reset. This latch is canceled
by a reset.
1−1RReserved
This bit is always read as 1 and cannot be modified.
Rev. 1.0, 02/02, page 48 of 502
Bit Bit Name Initial Value R/ W Descriptions
0MDS0 −RThis bit indicates the input level at pin MD0 (the current
operating m ode). This bit corresponds to MD0. MDS0
is read-only bit and this cannot be writ t en to. The MD0
input level is latched into this bit when MDCR is read.
This latch is canceled by a reset. This latch is canceled
by a reset.
3. 2.2 Syste m Contr ol Regi st er( SYSCR)
SYSCR se lects the interrupt cont rol mode and the detected e dge for NMI, and enabl es or di sables
on-chip RAM.
Bit Bit Name Intial Value R/W Descriptions
7−0R/WReserved
Only 0 should be wr itten to this bit.
6−0−Reserved
This bit is always read as 0 and cannot be modified.
5
4INTM1
INTM0 0
0R/W
R/W These bits select the cont rol mode of the int errupt
controller. For details of the interrupt control modes,
see section 5.6, Interrupt Contr ol Modes and Interrupt
Operation.
00: Interrupt contr ol mode 0
01: Setting prohibited
10: Interrupt contr ol mode 2
11: Setting prohibited
3NMIEG0 R/W
NMI Ed ge Select
Selects the valid edge of the NMI interrupt input.
0: An interrupt is requested at the falling edge of NMI
input
1: An interrupt is requested at the rising edge of NMI
input
2
1−0−Reserved
These bits are always read as 0 and cannot be
modified.
0RAME 1 R/W
RAM Enable
Enables or disables on- chip RAM. This bit is initialized
when the reset status is released.
0: On -chip RAM is disabled
1: On-chip RAM is enabled
Rev. 1.0, 02/02, page 49 of 502
3.3 Pi n Fun ct ions in Each Operat in g Mode
The CPU can access a 16-Mbyte address spac e in advanced mode . The on-ch ip ROM is enabled ,
however external addresses c annot be accesse d.
All I/O port s are available for use as input-out put ports.
Rev. 1.0, 02/02, page 50 of 502
3.4 Add ress Map
Figure 3. 1 shows the a ddress m ap in each operating mode.
H'000000
H'01FFFF
H'FFE000
H'FFEFBF
H'FFF800
H'FFFFC0
H'FFFFFF
H'FFFF3F
H'FFFF60
H'FFFFBF
On-chip ROM
(F-ZTAT/MASK ROM*)
On-chip RAM
On-chip RAM
Internal I/O registers
Internal I/O registers
ROM: 128 kbytes
RAM: 4 kbytes
Mode 7
Advanced single-chip mode
H8S/2282
H'000000
H'01FFFF
H'00FFFF
H'FFE000
H'FFEFBF
H'FFF800
H'FFFFC0
H'FFFFFF
H'FFFF3F
H'FFFF60
H'FFFFBF
On-chip ROM
(MASK ROM*)
On-chip RAM
On-chip RAM
Internal I/O registers
Internal I/O registers
ROM: 64 kbytes
RAM: 4 kbytes
Mode 7
Advanced single-chip mode
H8S/2281
Fi g ure 3. 1 Address Map
Rev. 1.0, 02/02, page 51 of 502
Section 4 Exception Handling
4.1 Exception Handling Types and P riority
As table 4.1 indicates, exception handling may be caused by a reset, trace, trap instruction, or
interrupt. Exception handling is prioritized as shown in table 4.1. If t wo or more excepti ons occur
simultaneously, they are accepte d and proce ssed in order of priority. Exception sources, the stack
structure, a nd operation of the CPU vary depending on the i nterrupt control mode. For details on
the interrupt control mode, refer to section 5, Interrupt Controller.
Table 4.1 Exception Typ es an d Priori ty
Priority Exception Type St art of Exception Handl i ng
High Reset Starts immediat ely after a low-to-high transition at the
5(6
pin, or when the watchdog timer overflows. The CPU enters
the reset state when the
5(6
pin is low.
Trace*1Starts when execut ion of the current instruction or except ion
handling ends, if the trace (T) bit in the EXR is set to 1
Direct transition Starts when a direction t r ansition occurs as the result of
SLEEP instr u ct ion exec ution.
Interrupt Starts when execution of the current instruction or exception
handling ends, if an inter r upt request has been issued*2
Low Trap instruction*3Started by execution of a trap instruction (TRAPA)
Notes: 1. Traces ar e enabled only in interrupt control mode 2. Trace except ion handling is not
executed after execut ion of an RTE instruction.
2. I nterrup t dete ct ion is not perfo rm e d on completion of ANDC, ORC, XORC, or LDC
instruction execution, or on completion of reset exception handling.
3. Trap instruction exception handling requests are accepted at all times in pr ogram
execution state.
4.2 Except i on S ou rces an d Excep t i on Vector Tabl e
Diff erent vector address es ar e assign ed to differen t excep tion so urces. Table 4.2 lis ts th e exceptio n
sources and their vector addresses. Since t he usable modes diffe r de pending on the produc t, for
details on each product, refer to section 3, MCU Operating Modes.
Rev. 1.0, 02/02, page 52 of 502
Table 4.2 Exc e ption H andling Vector Table
Vector Address*1
Exception Sour ce Vector Num ber Norm al Mode*2Advanced Mod e
Power-on rese t 0 H'0000 to H'0001 H'0000 to H'000 3
Manual reset *21 H '0002 to H'0003 H'0004 to H'000 7
Reserved for system use 2 H'0004 t o H'0005 H'0008 to H'000B
3 H'0006 to H'0007 H'000C to H'000F
4 H'0008 to H'001 9 H'0010 to H'001 3
Trace 5 H'000A to H'000B H'0014 to H'0017
Interrupt (direct transitions)*36 H'000C to H'000D H'0018 to H'001B
Int errupt (NMI) 7 H'000E to H'000F H'001C to H'001F
Trap in struc tion (#0 ) 8 H'0010 to H'001 1 H'0020 to H'0023
(#1) 9 H'0012 to H'0013 H'0024 to H'0027
(#2) 10 H'0014 to H'0015 H'0028 to H'002B
(#3) 11 H'0016 to H'0017 H'002C to H'002F
Reserved f or system use 12 H'0018 to H'0019 H'0030 to H'0033
13 H'001A to H'001B H'0034 t o H'0037
14 H'001C to H'001D H'0038 to H'003B
15 H'001E to H'001F H'003C to H'003F
External interrupt IRQ0 16 H'0020 to H'0021 H'0040 to H'0043
IRQ1 17 H'0022 to H'0023 H'0044 to H'0047
IRQ2 18 H'0024 to H'0025 H'0048 to H'004B
IRQ3 19 H'0026 to H'0027 H'004C to H'004F
IRQ4 20 H'0028 to H'0029 H'0050 to H'0053
IRQ5 21 H'002A to H'002B H'0054 to H'0057
Reserved for system use 22 H'002C to H'002D H'0058 t o H'005B
23 H'002E to H'002F H'005C to H'005F
Internal interrupt*424
127
H'0030 to H'0031
H'00FE to H'00FF
H'0060 to H'0063
H'01FC to H'01FF
Notes: 1. Lower 16 bits of the address .
2. Not available in this LSI.
3. For details on direct transitions, see section 19.10, Direct Transitions.
4. For details of internal interrupt vectors, see section 5.5, Interrupt Exception Handling
Vector Table.
Rev. 1.0, 02/02, page 53 of 502
4.3 Reset
A reset has the hig hest exception priori ty.
Whe n the
5(6
pin goes low, all processing halts and this LSI enters the reset. To ensure that this
LSI is reset, hold the
5(6
pin low for at least 20 m s at power-up. To re set the chip during
operation, hold the
5(6
pin low for at least 20 states. A reset initializes the internal state of the
CPU and the registe rs of on-chip peripheral modules.
The chip can also be reset by overflow of the watchdog timer. For details see section 9, Watchdog
Timer.
The interrupt cont rol mode is 0 immediately after reset.
4.3.1 Reset Exception Handling
Whe n the
5(6
pin goes high after being held low for the necessary time, this LSI starts reset
exception handling as follows:
1. The internal state of the CPU and the registers of the on-chip peripheral modules are
initialized, the T bit is cleared to 0 in EXR, and the I bit is set to 1 in EXR and CCR.
2. The reset exception handling vector address is read and transferred to the PC, and program
execution starts from the address indicated by the PC.
Figures 4.1 and 4.2 show examples of the reset se quence.
Rev. 1.0, 02/02, page 54 of 502
High
Vector fetch Internal
processing Prefetch of first
program instruction
(1)(3) Reset exception handling vector address(when reset, (1)=H'000000, (3)=H'000002)
(2)(4) Start address (contents of reset exception handling vector address)
(5) Start address ((5)=(2)(4))
(6) First program instruction
φ
Internal
address bus
Internal read
signal
Internal write
signal
Internal data
bus
(1)
(2) (4) (6)
(3) (5)
Fi g ure 4. 1 Re se t Seque nce (Adva nce d Mode wi th On-chi p ROM Enable d)
Rev. 1.0, 02/02, page 55 of 502
D15 D0
High
* * *
Address bus
Vector fetch Internal
processing Prefetch of first
program instruction
(1)
(2) (4) (6)
(3) (5)
(1)(3) Reset exception handling vector address(when reset, (1)=H'000000, (3)=H'000002)
(2)(4) Start address (contents of reset exception handling vector address)
(5) Start address ((5)=(2)(4))
(6) First program instruction
Note: * Three program wait states are inserted.
Fi g ure 4. 2 Re se t Seque nce (Adva nce d Mode wi th On-chi p ROM Disable d: Cannot be Used
in this LSI)
4.3.2 Interrupts afte r Reset
If an i nterrupt i s accepted after a reset and before the st ack pointer (SP) is initialized, the PC and
CCR will not be saved correc tly , leading to a program crash . To preven t this , all interrup t requests,
including NMI, are disabl e d imme diately a fter a reset. Since the fi rst instruction of a program is
always executed immediately after the reset state ends, make sure that this instruction initializes
the stack pointer (example: MOV.L #xx: 32, SP).
4.3.3 State of On-Chip Periphera l Modul es after Reset Rel ease
After reset release, MSTPCRA to MSTPCRD* are initialized to H'3F, H'FF, H'FF, and
B'11****** re spective l y, and all module s enter m odule stop mode. Conse quently, on-chip
peripheral module registers cannot be read or written to. Register reading and writing is enabled
when the module stop mode is exited.
Note: * The initial values of bits 5 to 0 in MSTPCRD are undefined.
Rev. 1.0, 02/02, page 56 of 502
4.4 Traces
Traces are enable d in interrupt c ontrol m ode 2. T race mode i s not activated in i nterrupt control
mode 0, irrespective of the state of the T bit. For details of interrupt control modes, see section 5,
Interrupt Controller.
If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on
completion of each instruction. Trace mode is not affected by interrupt masking. Table 4.3 shows
the state of CCR and EXR after execution of trace exception handling. Trace mode is canceled by
clearing the T bit in EXR to 0. The T bit saved on the stack retains its value of 1, and when control
is returned from the trace exception handling routine by the RTE instruction, trace mode resumes.
Trace exception handling i s not carried out after execution of the RTE instruc tion.
Interrupts are accepted even within the trace exception handling routine.
Table 4.3 Status of CCR and EXR after Trace Exception Handling
CCR EXR
Int errupt Control Mode I UI I2 to I0 T
0 Trace except ion handling cannot be used.
21——0
Legend
1: Set to 1
0: Cleared to 0
—: Retain s value pr ior to exec utio n
4.5 Interrupts
Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt
control mode s and can assign interrupts other than NMI to eight priorit y/mask levels t o enable
multiplexed interrupt cont rol. The source to start interrupt e xception handling and the ve ctor
address differ depending on the product. For de tails, refer to section 5, Interrupt Controller.
Interrupt exception handlin g is condu ct ed as follows :
1. The values in the program counter (PC), condition code register (CCR), a nd extended cont rol
register (EXR) are saved to the stack.
2. The interrupt mask bit is updated and the T bit is c leared to 0.
3. A vector addre ss corre sponding to the interrupt source is ge nerated, t he start address is loaded
from the vector table t o the PC, a nd program e xecution begi ns from that addre ss.
Rev. 1.0, 02/02, page 57 of 502
4.6 Trap In st ru ct i o n
Tr a p instr uction exce ption hand lin g star t s when a TRAPA in stru ct i on is execu te d . Tra p inst ruction
exception handling can be exe c uted at all times in the program executi on state.
Trap instruction exception handling is conducted as follows:
1. The values in the program counter (PC), condition code register (CCR), a nd extended cont rol
register (EXR) are saved to the stack.
2. The interrupt mask bit is updated and the T bit is c leared.
3. A vector address c orresponding to the interrupt source is generated, the start a ddress is l oaded
from the vector table t o the PC, a nd program e xecution starts from that address.
The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector
number from 0 to 3, as specified in the instruction code.
Table 4.4 shows the status of CCR and EXR after execution of trap instruction exception handling.
Tabl e 4.4 Sta tus o f CCR and EXR after Trap Instruction Except ion Handl i ng
CCR EXR
Int errupt Control Mode I UI I2 to I0 T
01———
21——0
Legend
1: Set to 1
0: Cleared to 0
—: Retain s value pr ior to exec utio n
Rev. 1.0, 02/02, page 58 of 502
4.7 Sta ck Stat us after Except i on Handl ing
Figures 4.3 shows the sta ck after com pletion of trap instruc tion exception handling a nd interrupt
exception handling.
CCR
CCR*
1
PC (16 bits)
SP
EXR
Reserved*
1
CCR
CCR*
1
PC (16 bits)
SP
CCR
PC (24 bits)
SP
EXR
Reserved*
1
CCR
PC (24 bits)
SP
(a) Normal Modes
*
2
(b) Advanced Modes
Interrupt control mode 0 Interrupt control mode 2
Interrupt control mode 0 Interrupt control mode 2
Note: 1.
2. Ignored on return.
Normal modes are not available in this LSI.
Figure 4.3 Stack Status after Exception Handling
Rev. 1.0, 02/02, page 59 of 502
4.8 Usage Note
When accessing word data or longword da ta, this LSI assumes that the l owest address bit i s 0. The
stack should always be ac cessed by word transfer instruction or longword transfer instruction, and
the value of the stack poi nter (SP, ER7) should al ways be kept even. Use the following
instructions to save regi sters:
PUSH.W Rn (or MOV.W Rn, @-SP)
PUSH.L ERn (or MOV.L ERn, @-SP)
Use the following instructions to resto re regist ers:
POP.W Rn (or MOV.W @SP+, Rn)
POP.L ERn (or MOV.L @SP+, ERn)
Setting SP to an odd value may l ead to a ma lfunction. Figure 4.4 shows an example of what
happens when the SP value is odd.
SP
CCR
PC
R1L
SP
: Condition code register
: Program counter
: General register R1L
: Stack pointer
CCR
SP SP R1L H'FFFEFA
H'FFFEFB
H'FFFEFC
H'FFFEFD
H'FFFEFE
H'FFFEFF
PC PC
TRAPA instruction executedSP set to H'FFFEFF
Data saved above SP
MOV.B R1L, @-ER7 executed
Contents of CCR lost
Address
Legend
Note: This diagram illustrates an example in which the interrupt control mode is 0, in advanced mode.
Fi g ure 4. 4 O pera t ion whe n SP Value Is Odd
Rev. 1.0, 02/02, page 60 of 502
Rev. 1.0, 02/02, page 61 of 502
Section 5 Interrupt Controller
5.1 Features
• Two interrup t con trol modes
Any of two interrupt control modes ca n be set by means of t he INTM1 and INTM0 bi ts in
the system control register (SYSCR).
• Priorities settable with IPR
An interrupt priority register (IPR) i s provided for setting interrupt priorities. Eight pri ority
levels can be set for each module for all interrupts except NMI. NMI is assigned the
highest priority level of 8, and can be accepted at all times.
• Independent vec t or a ddresses
All interrupt sources are assigned independent ve c tor addresses, making it unnecessary for
the source to be identified in the i nterrupt handling routi ne.
• Seven ext ernal i nterrupts
NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling
edge can be selected for NMI. Falling e dge, rising edge, or both edge detection, or l evel
sensing, can be selected for IRQ5 to IRQ0.
Rev. 1.0, 02/02, page 62 of 502
A block diagram of the interrupt c ontroller is shown in figure 5.1.
SYSCR
NMI input
IRQ input
Internal interrupt
request
WOVI0 to RM0
NMIEG
INTM1, INTM0
NMI input unit
IRQ input unit
ISR
ISCR IER
IPR
Interrupt controller
Priority
determination
Interrupt
request
Vector number
I
I2 to I0 CCR
EXR
CPU
ISCR
IER
ISR
IPR
SYSCR
: IRQ sense control register
: IRQ enable register
: IRQ status register
: Interrupt priority register
: System control register
Legend
Fi g ure 5. 1 Bl ock Diagram of Interr upt Controller
Rev. 1.0, 02/02, page 63 of 502
5.2 Input/Output Pins
Table 5.1 sum marizes the pins of the i nterrupt controller.
Table 5.1 P i n Configuration
Name I/O Function
NMI Input Nonmaskable external interrupt
Rising or falling edge can be selected
,54
,54
,54
,54
,54
,54
Input
Input
Input
Input
Input
Input
Maskable ext ernal interrupts
Rising, falling, or both edges, or level sensing, can be selected
5.3 Register Descri pt i on s
The interrupt controller has t he following regi sters. For details system c ontrol register(SYSCR),
refer to section 3.2.2, System Control Register(SYSCR).
• System cont rol register (SYSCR)
• IRQ sense control registe r H (ISCRH)
• IRQ sense control registe r L (ISCRL)
• IRQ enable register (IER)
• IRQ sta tus register (ISR)
• Interrupt priority registe r A (IPRA)
• Interrupt priority registe r B (IPRB)
• Interrupt priority registe r C (IPRC)
• Interrupt priority registe r D (IPRD)
• Interrupt priori ty register E (IPRE)
• Interrupt priority registe r F (IPRF)
• Interrupt priority registe r G (IPRG)
• Interrupt priority registe r J (IPRJ)
• Interrupt priority registe r K (IPRK)
• Interrupt priority registe r M (IPRM)
Rev. 1.0, 02/02, page 64 of 502
5. 3.1 Inte r rupt Prior i ty Regi ste r s A to G, J, K , M (I P RA to IPRG, IPRJ, IPRK, IPRM )
The IPR re gisters set pri orities (levels 7 to 0) for interrupts othe r than NMI. There a re ten IPR
registers. The corresponde nce be tween interrupt sourc e s and IPR settings is shown in table 5.2.
Setting a value in the range from H'0 to H'7 in the 3-bi t groups of bits 0 to 2 and 4 to 6 sets t he
priority of the corresponding interru pt.
Bit Bit Name Initial Value R/W Description
7−0−Reserved
These bits are always read as 0.
6
5
4
IPR6
IPR5
IPR4
1
1
1
R/W
R/W
R/W
Sets the priority of the cor r esponding interrupt
source.
000: Priority level 0 (Lowest )
001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priorit y level 7 (Highest)
3−0−Reserved
These bits are always read as 0.
2
1
0
IPR2
IPR1
IPR0
1
1
1
R/W
R/W
R/W
Sets the priority of the cor r esponding interrupt
source.
000: Priority level 0 (Lowest )
001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priorit y level 7 (Highest)
Rev. 1.0, 02/02, page 65 of 502
5.3.2 IRQ Enable Register (IER)
IER cont rol s the ena bling and disabling of int errupt requests IRQ5 to IRQ0.
Bit Bit Name Initial Value R/W Description
7
6−
−0
0R/W
R/W Reserved
Only 0 should be wr itten to these bit s.
5 IRQ5E 0 R/W IRQ5 Enable
The IRQ5 interr upt request is enabled when t his
bit is 1.
4 IRQ4E 0 R/W IRQ4 Enable
The IRQ4 interr upt request is enabled when t his
bit is 1.
3 IRQ3E 0 R/W IRQ3 Enable
The IRQ3 interr upt request is enabled when t his
bit is 1.
2 IRQ2E 0 R/W IRQ2 Enable
The IRQ2 interr upt request is enabled when this
bit is 1.
1 IRQ1E 0 R/W IRQ1 Enable
The IRQ1 interr upt request is enabled when t his
bit is 1.
0 IRQ0E 0 R/W IRQ0 Enable
The IRQ0 interr upt request is enabled when t his
bit is 1.
Rev. 1.0, 02/02, page 66 of 502
5. 3.3 IRQ Se nse Contro l Re gister s H and L (ISCRH, ISCRL)
The ISCR registers select the source that generates an interrupt request at pins
,54
to
,54
.
Bit Bit Name Initial Value R/W Description
15
14
13
12
−
−
−
−
0
0
0
0
R/W
R/W
R/W
R/W
Reserved
Only 0 should be wr itten to these bit s.
11
10 IRQ5SCB
IRQ5SCA 0
0R/W
R/W I RQ 5 Sense Control B
IRQ5 Sense Control A
00: Interrupt request generat ed at
,54
input
level lo w
01: In terrup t request genera ted at falling edge
of
,54
input
10: Interrupt request generat ed at r ising edge of
,54
input
11: Interrupt req ues t g enerated at b oth f a llin g
and rising edges of
,54
input
9
8IRQ4SCB
IRQ4SCA 0
0R/W
R/W I RQ 4 Sense Control B
IRQ4 Sense Control A
00: Interrupt request generat ed at
,54
input
level lo w
01: In terrup t request genera ted at falling edge
of
,54
input
10: Interrupt request generat ed at r ising edge of
,54
input
11: Interrupt req ues t g enerated at b oth f a llin g
and rising edges of
,54
input
7
6IRQ3SCB
IRQ3SCA 0
0R/W
R/W I RQ 3 Sense Control B
IRQ3 Sense Control A
00: Interrupt request generat ed at
,54
input
level lo w
01: In terrup t request genera ted at falling edge
of
,54
input
10: Interrupt request generat ed at r ising edge of
,54
input
11: Interrupt req ues t g enerated at b oth f a llin g
and rising edges of
,54
input
Rev. 1.0, 02/02, page 67 of 502
Bit Bit Name Initial Value R/W Description
5
4IRQ2SCB
IRQ2SCA 0
0R/W
R/W IRQ2 Sense Control B
IRQ2 Sense Control A
00: Interrupt request generat ed at
,54
input
level lo w
01: In terrup t request genera ted at falling edge
of
,54
input
10: Interrupt request generat ed at r ising edge of
,54
input
11: Interrupt req ues t g enerated at b oth f a llin g
and rising edges of
,54
input
3
2IRQ1SCB
IRQ1SCA 0
0R/W
R/W I RQ 1 Sense Control B
IRQ1 Sense Control A
00: Interrupt request generat ed at
,54
input
level lo w
01: In terrup t request genera ted at falling edge
of
,54
input
10: Interrupt request generat ed at r ising edge of
,54
input
11: Interrupt req ues t g enerated at b oth f a llin g
and rising edges of
,54
input
1
0IRQ0SCB
IRQ0SCA 0
0R/W
R/W I RQ 0 Sense Control B
IRQ0 Sense Control A
00: Interrupt request generat ed at
,54
input
level lo w
01: In terrup t request genera ted at falling edge
of
,54
input
10: Interrupt request generat ed at r ising edge of
,54
input
11: Interrupt req ues t g enerated at b oth f a llin g
and rising edges of
,54
input
Rev. 1.0, 02/02, page 68 of 502
5. 3.4 IRQ Sta t us Regi ster (ISR)
ISR indicates t he status of IRQ5 t o IRQ0 interrupt reque sts.
Bit Bit Name Initial Value R/W Description
7
6−
−0
0R/W
R/W Reserved
Only 0 should be wr itten to these bit s.
5
4
3
2
1
0
IRQ5F
IRQ4F
IRQ3F
IRQ2F
IRQ1F
IRQ0F
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
[Setting condition]
When the interrupt source selected by the ISCR
registers occurs
[Clearing condit ions]
•Cleared by reading I RQnF flag when IRQnF
= 1, then writing 0 to IRQnF flag
•When interrupt exception handling is
executed when low-level detection is set and
,54Q
input is high
•When IRQ n interrupt exception handling is
executed when falling, rising, or both-edge
detection is set (n=5 to 0)
Rev. 1.0, 02/02, page 69 of 502
5.4 Interru p t So urces
5.4.1 External Interrupts
There are seven ext ernal i nterrupts: NMI and IRQ5 t o IRQ0. These i nterrupts c an be used t o
restore this LSI from soft ware standby m ode.
NMI Inter rupt: NMI i s the highest-priority interrupt, and i s always accepted by the CPU
regardless of the i nterrupt control mode or the status of the CPU interrupt mask bits. The NMIEG
bit in SYSCR can be used to select whether an interrupt is requested at a rising edge or a falling
edge on the NMI pin.
IRQ5 t o IRQ0 Interrupts: Interrupts IRQ5 t o IRQ0 a re reque sted by an i nput signal at pins
,54
to
,54
Interrupts IRQ5 t o IRQ0 have the following features:
• Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling
edge, rising edg e, or both edges , at pins
,54
to
,54
.
• Enabling or disabling of i nterrupt requests IRQ5 to IRQ0 c a n be selected wi t h IER.
• The interrupt priority level can be set with IPR.
• The sta tus of i nterrupt requests IRQ5 to IRQ0 is i ndicated i n ISR. ISR flags can be cleared t o 0
by softwa re.
The detection of IRQ5 to IRQ0 int errupts does not de pend on whether the relevant pin has been
set for i nput or output . However, whe n a pin i s used as an external interrupt i nput pin, do not clear
the corresponding DDR to 0; and use the pin as an I/O pin for another function.
A block diagram of interrupts IRQ5 to IRQ0 i s shown in figure 5.2.
IRQn interrupt
request
IRQnE
IRQnF
S
R
Q
Clear signal
Edge / level
detection circuit
IRQnSCA, IRQnSCB
input
Note: n= 5 to 0
Fi g ure 5. 2 Bl ock Diagram of Interr upt s IRQ5 to IRQ0
Rev. 1.0, 02/02, page 70 of 502
5. 4.2 Internal Inter r upt s
The sourc es for i nternal int errupts from on-chip pe ripheral modul es have t he following features:
• For each on-chip peripheral module there are flags that indicate the interrupt request status,
and ena ble bits that se lect ena bling or di sabling of these interrupts. If both of these are set to 1
for a particular inte rrupt sourc e, an int errupt reque st is issue d to the interrupt controller.
• The interrupt priority level can be set by means of IPR.
5.5 Interru p t Except i on Hand li ng Vector Tabl e
Table 5.2 shows interrupt exception ha ndling source s, vector addre sses, a nd interrupt priorities.
For de fault priorities, the lo w er th e v ector nu mber, th e h igher th e p r iority . Priorities among
modules c an be set by me a ns of the IPR. Modules se t at the sam e priority will conform t o their
default priorities. Priorities within a module are fixed.
Rev. 1.0, 02/02, page 71 of 502
Tabl e 5.2 Inte rrupt Sourc e s, Vec tor Addre sse s, a nd Interr upt Priorities
Vector
Address*
Interrupt
Source Origin of
Interrupt Source Vector
Number Advanced
Mode IPR Priority
External NMI 7 H'001C High
pin IRQ0 16 H'0040 IPRA6 to IPRA4
IRQ1 17 H'0044 IPRA2 to IPRA0
IRQ2 18 H'0048 IPRB6 to IPRB4
IRQ3 19 H'004C IPRB6 to IPRB4
IRQ4 20 H'0050 IPRB2 to IPRB0
IRQ5 21 H'0054
Reserved — 22 H'0058
for system
use — 23 H'005C
Watchdog
timer 0 WOVI0 25 H'0064 IPRD6 to IPRD4
A/D ADI 28 H'0070 IPRE2 to IPRE0
Watchdog
timer 1 WOVI1 29 H'0074 IPRE2 to IPRE0
TPU TGI0A 32 H'0080 IPRF6 to IPRF4
channel 0 TGI0B 33 H'0084
TGI0C 34 H'0088
TGI0D 35 H'008C
TCI0V 36 H'0090
TPU TGI1A 40 H'00A0 IPRF2 to IPRF0
channel 1 TGI1B 41 H'00A4
TCI1V 42 H'00A8
TCI1U 43 H'00AC
TPU TGI2A 44 H'00B 0 IPRG6 to IPRG4
channel 2 TGI2B 45 H'00B4
TCI2V 46 H'00B8
TCI2U 47 H'00BC Low
Rev. 1.0, 02/02, page 72 of 502
Vector
Address*
Interrupt
Source Origin of
Interrupt Source Vector
Number Advanced
Mode IPR Priority
SCI ERI0 80 H '0140 IPRJ2 to IPR J0 High
channel 0 RXI0 81 H'0144
TXI0 82 H'0148
TEI0 83 H'014C
SCI ERI1 84 H '0150 IPRK6 to IPRK4
channel 1 RXI1 85 H'0154
TXI1 86 H'0158
TEI1 87 H'015C
PWM CMI1 104 H'01A0 IPRM6 to IPR M4
CMI2 105 H'01A4
Reserved — 106 H'01A8
for system
use — 107 H'01AC
HCAN ERS0/ OVR0, RM0,
RM1, SL E0 108 H'01B0 IPRM2 to IPRM0
(mailbox 0
reception) 109 H'01B4
Reserved
for system
use
— 111 H'01BC Low
Note: * Lower 16 bits of the start addr ess.
Rev. 1.0, 02/02, page 73 of 502
5.6 Interrupt Control Modes and Interrupt Operation
The interrupt cont roller has two mode s: interrupt cont rol mode 0 and int e rrupt cont rol mode 2.
Interrupt operations differ depe nding on the int e rrupt control mode. The interrupt c ontrol mode is
selected by SYSCR. Table 5.3 shows the diffe rences between interrupt c ontrol mode 0 and
interrupt control mode 2.
Table 5.3 Interrupt Control Modes
Interrupt Priority Setting Interrupt
Control Mode Registers Mask Bits Descript ion
0 Default I The priorities of interrupt sources are fixed at
the defa ult settings .
Interrupt sources, except for NMI, ar e masked
by the I bit.
2 IPR I2 to I0 8 priority levels other than NMI can be set with
IPR.
8-level int errupt mask control is performed by
bits I2 to I0.
5. 6.1 Interr upt Contr ol Mode 0
In interrupt control mode 0, interrupt reque sts other than for NMI a re masked by the I bit of the
CCR in the CPU. Figure 5.3 shows a flowchart of t he interrupt a cceptance operation in thi s case.
1 If an interrupt source occurs when the corresponding i nterrupt enable bit is set to 1, an
interrupt re quest is sent t o the interrupt control ler.
2 If the I bit is set to 1, only an NMI int e rrupt is accepted, and othe r interrupt reque sts are hel d
pending. If the I bit is cleared, an interrupt requ est is accept ed.
3 Interrupt requests are sent to the interrupt c ontroller, the highe st-ranked interrupt according to
the priorit y system is accepted, a nd other i nterrupt requests are hel d pending.
4 When the CPU accepts an interrupt request, it starts interrupt exception handling after
execution of the current instruction has been completed.
5 The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on
the stack shows the address of the first instruction to be executed after returning from the
interrupt handling routine.
6 Next, the I bit in CCR is se t to 1. This masks all interrupt s except NMI.
7 The CPU generates a vector address for the accepted interrupt and starts execution of the
interrupt handling routine at the address i ndicated by the contents of the vector address in the
vector table.
Rev. 1.0, 02/02, page 74 of 502
Program execution status
Interrupt generated?
NMI
IRQ0
IRQ1
RM0
I = 0
Save PC and CCR
I ← 1
Read vector address
Branch to interrupt handling routine
Yes
No
Yes
Yes
Yes No
No
No
Yes
Yes
No
Hold
pending
Figure 5.3 Flowchart of Procedure up to Interrupt Acceptance
in Interrupt Control Mode 0
Rev. 1.0, 02/02, page 75 of 502
5. 6.2 Interr upt Contr ol Mode 2
In interrupt control mode 2, mask control is appli ed to e ight levels for i nterrupt requests othe r than
NMI by comparing the EXR int errupt m ask level (I2 to I0 bits) in the CPU and the IPR setting.
Figure 5. 4 shows a flowchart of t he interrupt a cceptance operati on in this c ase.
1 If an interrupt source occurs when the correspondin g inter rupt enable bit is s e t t o 1, an i nterrupt
request i s sent to the interrupt c ontroller.
2 When interrupt requests are sent t o the i nterrupt controller, the inte rrupt with the highest
priority ac cording to the interrupt priority level s set in IPR is selected, and lower-priority
interrupt re quests a re held pending. If a number of interrupt requests with t he same priority are
generated at t he same time, the i nterrupt request with the highe st priority according to the
priority system shown in table 5.3 is selected.
3 Next, the priority of t he selected interrupt request is compared with t he inte rrupt mask level set
in EXR. An interrupt request with a priority no higher than the mask level set at that time is
held pe ndi ng, and only an interrupt request with a priority higher tha n the i nterrupt m a sk le vel
is acce pte d.
4 When the CPU accepts an interrupt request, it starts interrupt exception handling after
execution of the current instruction has been completed.
5 The PC, CCR, and E XR are saved to the stack area by interrupt exception handling. T he PC
saved on the stack shows the addre ss of the first i nstruction to be executed a fter returning from
the interrupt handling routine.
6 The T bit in EXR is cleared to 0. The interrupt mask level is rewritten with the priority level of
the accepted interrupt.
If the accepted interrupt i s NMI, the interrupt mask level is set to H'7.
7 The CPU generates a vector address for the accepted interrupt and starts execution of the
interrupt handling routine at the address i ndicated by the contents of the vector address in the
vector table.
Rev. 1.0, 02/02, page 76 of 502
Yes
Program execution status
Interrupt generated?
NMI
Level 6 interrupt?
Mask level 5
or below?
Level 7 interrupt?
Mask level 6
or below?
Save PC, CCR, and EXR
Clear T bit to 0
Update mask level
Read vector address
Branch to interrupt handling routine
Hold
pending
Level 1 interrupt?
Mask level 0?
Yes
Yes
No Yes
Yes
Yes
No
Yes
Yes
No
No
No
No
No
No
Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance in Control Mode 2
5. 6.3 Interr upt Except ion Handl ing Seque nce
Figure 5. 5 shows the i nterrupt exception ha ndling seque nce. The example shown is for t he case
where interrupt control mode 0 is set in adva nced mode, and the program area and stack a rea are
in on-chi p memory.
Rev. 1.0, 02/02, page 77 of 502
(14)(12)(10)(6)(4)(2)
(1) (5) (7) (9) (11) (13)
Interrupt service
routine instruction
prefetch
Internal
operation
Vector fetch
Stack
Instruction
prefetch Internal
operation
Interrupt
acceptance
Interrupt level determination
Wait for end of instruction
Interrupt
request signal
Internal
address bus
Internal
read signal
Internal
write signal
Internal
data bus
φ
(3)
(1)
(2) (4)
(3)
(5)
(7)
Instruction prefetch address (Not executed.
This is the contents of the saved PC, the return address.)
Instruction code (Not executed.)
Instruction prefetch address (Not executed.)
SP-2
SP-4
Saved PC and saved CCR
Vector address
Interrupt handling routine start address (Vector address contents)
Interrupt handling routine start address ((13) = (10)(12))
First instruction of interrupt handling routine
(6) (8)
(9) (11)
(10) (12)
(13)
(14)
(8)
Figure 5.5 Interrupt Exception Handling
Rev. 1.0, 02/02, page 78 of 502
5. 6.4 Interr upt Response Times
Table 5.4 shows interrupt response times - the interval between generation of an interrupt re quest
and exe c ution of the first instruction i n the interrupt handling routine. The execution status
symbols used in table 5.4 are explained in table 5.5.
This LSI i s capable of fast word transfer t o on-chip memory, has the program are a in on-chip
ROM and the stack area in on-chip RAM, ena bling high-speed proce ssing.
Tabl e 5.4 Inte rrupt Re sponse Times
No rmal Mode*5Advanced Mode
No. Execution Status
Interrupt
control
mode 0
Interrupt
control
mode 2
Interrupt
control
mode 0
Interrupt
control
mode 2
1 Interrupt priority determination*133 33
2 Number of wait states unt il executing
instruction ends*21 to 19 +2·SI1 to 19+2· SI1 t o 19+2·SI1 to 19+2·SI
3 PC, CCR, EXR stack save 2 ·SK3·SK2·SK3·SK
4 Ve c tor fe tc h SISI2·SI2·SI
5 Instruction fetch*32·SI2·SI2·SI2·SI
6 Internal processing*422 22
Total (using on-chip mem ory) 11 to 31 12 to 32 12 to 32 13 to 33
Notes: 1. Two states in case of internal interrupt .
2. Refers t o MULXS and DIVXS instructions.
3. Prefetch after interrupt acceptance and interrupt handling routine prefetch.
4. Internal pr ocessing after interrupt acceptance and internal processing after vector fetch.
5. Not available in this LSI.
Rev. 1.0, 02/02, page 79 of 502
Table 5.5 Number of State s in Interrupt Handling Routine Execution Status
Object of Access
External Device *
8 Bit Bus 16 Bit Bus
Symbol Internal
Memory 2-State
Access 3-State
Access 2-State
Access 3-State
Access
Instruction fetch SI 1 4 6+2m 2 3+m
Branch address read SJ
Stack manipulation SK
Legend
m: Number of wai t states in an externa l de vice a ccess.
Note: *Cannot be used in t his LSI.
5.7 Usage Notes
5. 7.1 Conte nt i o n betwee n Interrupt Ge nera tio n a nd Disabling
When an interrupt e nable bit is cleared to 0 to disable interrupts, the disa bling becomes e ffective
after execution of the instruction.
When an interrupt e nable bit is cleared to 0 by an instruction such as BCLR or MOV, and if a n
interrupt is generated during exe cution of t he instruction, the interrupt concerned will still be
enabled on completion of the instruct i on, and so interrupt exception handling for that i nterrupt wil l
be execut ed on completion of the instruc tion. However, if the re is an interrupt reque st of higher
priority than that int errupt, interrupt exc e ption handling wil l be executed for the hi gher-priority
interrupt, and the lower-priority interrupt will be ignored.
The sa me also applies whe n an int errupt source fla g is cle ared to 0.
Figure 5. 6 shows an example in which the TGIEA bit in the TP'U's TIER_0 register is cleared to
0.
The above contention will not occur if an enable bit or interrupt source flag is cl eared to 0 while
the interrupt is masked.
Rev. 1.0, 02/02, page 80 of 502
Internal
address bus
Internal
write signal
φ
TCIEV
TCFV
TCIV
interrupt signal
TIER_0 write cycle by CPU TCIVexception handling
TIER_0 address
Fi g ure 5. 6 Contention between Interr upt Ge nera tio n and Disabli ng
5. 7.2 Instructi o ns t hat Disable Inter r upt s
The i n stru ctions that disable i nterrupt s are LDC, ANDC, ORC, and XORC. After any of these
instructions are executed, all interrupts including NMI are disabled and the next instruction is
always executed. When the I bit is set by one of these instructions, the new value becomes valid
two states after execution of the instruction ends.
5. 7.3 When Int er r upt s Are Disa bled
There are times when interrupt acceptance is di sabled by the interrupt cont roller.
The interrupt cont roller disable s interrupt acceptance for a 3-state period a fter the CPU has
updated the m a sk level with an LDC, ANDC, ORC, or XORC i nstruction.
Rev. 1.0, 02/02, page 81 of 502
5. 7.4 Interr upts duri ng Exec ution o f EEPMOV Instruc tio n
Int errupt o perat ion diff ers bet w een t he EE PMOV.B instructi o n and the EEPMOV.W i n st ruct i o n.
With the EEPMOV.B instruction, a n interrupt reque st (including NMI) issued during the transfer
is not accepted until the move is completed.
With the EEPMOV.W i n struction, if an interrupt request is issued during t he transfer, interrupt
exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this
case is the address of the next instruction.
Therefore, if an interrupt is generated during execution of an EEPMOV.W in struction, the
following c oding should be used.
L1: EEPMOV.W
MOV.W R4,R4
BNE L1
5. 7.5 IRQ Inter rupts
Whe n the clo c k is operating,
,54
inputs are accepted in sync hronization wit h the clock input. In
software standb y mod e,
,54
inputs are accepted async hronously. For details on the
,54
input
conditions, re fer to section 21.3.2, Control Signa l Timing.
Rev. 1.0, 02/02, page 82 of 502
Rev. 1.0, 02/02, page 83 of 502
Section 6 Bus Controller
The H8S/2600 CPU is driven by a syste m clock, denoted by the symbol ø.
The bus c ontroller controls a me m ory cycle and a bus cycle. Different methods are used to access
on-chip memory and on-c hip periph eral mod ul es. The bus contr oll er also has a bus arbitration
function, a nd control s the operation of t he int ernal bus master.
6.1 Basic Tim ing
The period from one rising edge of ø to the ne xt is refe rred to a s a "state." The memory cycle or
bus cycle consists of one, two, three, or four states. Different methods are use d to ac cess on-chip
memory, on-chip peripheral modules, and the external address space.
6. 1.1 On-Chip Memor y Access Timing (ROM, RAM)
On-chip memory is accessed in one state. The data bus is 16 bits wide, permitting both byte and
word transfer instruction. Fi gure 6.1 shows the on-chip m emory access cycle.
T1
φ
Internal address bus
Bus cycle
Address
Read data
Write data
Internal read signal
Internal data bus
Internal write signal
Internal data bus
Read
access
Write
access
Fi g ure 6. 1 O n-Chip Memory Access Cycl e
BSCS209A_000020020200
Rev. 1.0, 02/02, page 84 of 502
6.1.2 On-Chip Peripheral Module Access Timing
The on-chip pe ripheral modules, except for HCAN, PW M, LCD, Ports H and J, are accessed in
two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O
register bei ng accessed. For details, refer to section 20, L i st of Registers. Figure 6.2 shows a ccess
timing for t he on-chip periphe ral modules.
T1 T2
φ
Internal address bus
Bus cycle
Address
Read data
Write data
Internal read signal
Internal data bus
Internal write signal
Internal data bus
Read
access
Write
access
Figure 6.2 On-C h ip Periphera l Mo d ule Access Cycle
Rev. 1.0, 02/02, page 85 of 502
6.1.3 On-Chip HCAN Module Access Timing
On-chip HCAN module access is performed in four states. The data bus widt h is 16 bits. Wait
states c a n be inserted by means of a wait request from the HCAN. On-chi p HCAN module access
timing is shown in fi gures 6. 3.
T1 T3
T2 Tw Tw T4
φ
Internal address bus
Bus cycle
Address
Read data
Write data
HCAN read signal
Internal data bus
HCAN write signal
Internal data bus
Read
access
Write
access
Fi g ure 6. 3 O n-Chip HCAN Module Access Cycl e (Wait Sta tes Inse rte d)
6.1.4 On-Chi p PWM, LCD, Por t s H and J Module Access Timing
On-chip PWM, LCD, Ports H and J module a ccess timing i s performed i n four states. The data bus
width is 16 bits. PWM, LCD, Ports H and J m odule access timing is shown in figure 6.4.
T1 T3
T2 T4
φ
Internal address bus
Bus cycle
Address
Read data
Write data
PWM, LCD, ports H
and J read signal
Internal data bus
PWM, LCD, ports H
and J write signal
Internal data bus
Read
access
Write
access
Figure 6.4 On-Chip PWM, LCD, Ports H and J Module Access Cycle
Rev. 1.0, 02/02, page 86 of 502
Rev. 1.0, 02/02, page 87 of 502
Section 7 I/O Ports
Table 7.1 sum marizes the port functions. T he pins of each port also have other functions such as
input/output or external interrupt input pi ns of on-c hip peripheral modules. Each I/O port includes
a dat a direction register (DD R) that con trols input /outp ut , a dat a reg iste r (DR) tha t stores output
data, and a port registe r (PORT) used to rea d the pi n sta tes. The input-only port s do not have a DR
or DDR register.
Ports 3 a nd A t o C includes an open-drain control register (ODR) that controls the on/off state of
the output buffer PMOS.
All of th e I/O ports can dr ive a single TTL load an d 30 pF capacit iv e load.
Rev. 1.0, 02/02, page 88 of 502
Table 7.1 P or t Func tions (1)
Port Description Port and
Ot her Functi ons Name Input/Output and
Output Type
P17/TIOCB2/TCLKD
P16/TIOCA2/
,54
P15/TIOCB1/TCLKC
P14/TIOCA1/
,54
P13/TIOCD0/TCLKB
P12/TIOCC0/TCLKA
P11/TIOCB0
Port 1 General I/O port also
functioning as TPU_0,
TPU_1,and TPU_2 I/O
pins and int er rupt inp ut
pins
P10/TIOCA0
P35/SCK1/
,54
P34/RxD1
P33/TxD1
P32/SCK0/
,54
P31/RxD0
Port 3 General I/O port also
func t io ni ng as SCI _0
and SCI_1 I/O pins and
interrupt input pins
P30/TxD0
Push-pull or open-drain output
type select able
P47/AN7
P46/AN6
P45/AN5
P44/AN4
P43/AN3
P42/AN2
P41/AN1
Port 4 General input po rt also
func t io ni ng as A/D
conv er t er an al og in put
pins
P40/AN0
PA7/SEG28
PA6/SEG27
PA5/SEG26
PA4/SEG25
PA3/COM4
PA2/COM3
PA1/COM2
Port A General I/O port also
func t io ni ng as se gm en t
and common output pins
of LCD
PA0/COM1
Push-pull or open-drain output
type select able
Rev. 1.0, 02/02, page 89 of 502
Table 7.1 P or t Func tions (2)
Port Description Port and
Ot her Functi ons Name Input/Output and
Output Type
PB7/SEG20
PB6/SEG19
PB5/SEG18
PB4/SEG17
PB3/SEG16
PB2/SEG15
PB1/SEG14
Port B General I/O port also
func t io ni ng as se gm en t
out pu t pins of LCD
PB0/SEG13
Push-pull or open-drain output
type select able
PC7/SEG12
PC6/SEG11
PC5/SEG10
PC4/SEG9
PC3/SEG8
PC2/SEG7
PC1/SEG6
Port C General I/O port also
func t io ni ng as se gm en t
out pu t pins of LCD
PC0/SEG5
Push-pull or open-drain output
type select able
PD7/SEG4
PD6/SEG3
PD5/SEG2
Port D General I/O port also
func t io ni ng as se gm en t
out pu t pins of LCD
PD4/SEG1
PF7/φ
PF6/SEG24
PF5/SEG23
PF4/SEG22
PF3/
$'75*
/
,54
Port F General I/O port also
func t io ni ng as interr u pt
input pin, A/D converter
start trigger input pin,
segm ent outpu t pins of
LCD, and a system clock
output pin PF2/SEG21
Rev. 1.0, 02/02, page 90 of 502
Table 7.1 P or t Func tions (3)
Port Description Port and
Ot her Functi ons Name Input/Output and
Output Type
PH7/PWM1H
PH6/PWM1G
PH5/PWM1F
PH4/PWM1E
PH3/PWM1D
PH2/PWM1C
PH1/PWM1B
Port H General I/O port also
func t io ni ng as PW M _1
output pins
PH0/PWM1A
PJ7/PWM2H
PJ6/PWM2G
PJ5/PWM2F
PJ4/PWM2E
PJ3/PWM2D
PJ2/PWM2C
PJ1/PWM2B
Port J General I/O port also
func t io ni ng as PW M _2
output pins
PJ0/PWM2A
Rev. 1.0, 02/02, page 91 of 502
7.1 Port 1
Port 1 is an 8-bit I/O port. Port 1 has the following registers.
• Port 1 data direction register (P1DDR)
• Port 1 data registe r (P1DR)
• Port 1 register (PORT1)
7. 1.1 Port 1 Data Direct i o n Register (P1 DDR)
The indivi dual bits of P1DDR specify input or output for the pins of port 1.
Bit Bit Name Initial Value R/W Descr i ption
7 P17DDR 0 W
6 P16DDR 0 W
5 P15DDR 0 W
4 P14DDR 0 W
3 P13DDR 0 W
2 P12DDR 0 W
1 P11DDR 0 W
0 P10DDR 0 W
When a pin function is specified to a general I/O port,
setting this bit to 1 makes t he corresponding port 1
pin an output pin, while clearing this bit to 0 makes
the pin an input pin.
7.1.2 Port 1 Data Register (P 1DR)
P1DR store s output data for the port 1 pins.
Bit Bit Name Initial Value R/W Descr i ption
7 P17DR 0 R/W
6 P16DR 0 R/W
5 P15DR 0 R/W
4 P14DR 0 R/W
3 P13DR 0 R/W
2 P12DR 0 R/W
1 P11DR 0 R/W
0 P10DR 0 R/W
Output data for a pin is stored when the pin f unction
is specif ied to a general I/O port.
Rev. 1.0, 02/02, page 92 of 502
7.1.3 Port 1 Register (PORT1)
PORT1 shows port 1 pin states. PORT1 ca nnot be modified.
Bit Bit Name Initial Value R/W Descr i ption
7 P17 Undefined*R
6 P16 Undefined*R
5 P15 Undefined*R
4 P14 Undefined*R
3 P13 Undefined*R
2 P12 Undefined*R
1 P11 Undefined*R
0 P10 Undefined*R
If a port 1 r ead is performed while P1DDR bits ar e
set to 1, the P1DR values are read. I f a port 1 r ead is
perform e d while P1 DDR bits are cleared t o 0, the pin
states are read.
Note: * Determined by t he states of pins P17 to P10.
7.1.4 Pin Functions
Port 1 pins also function as I/O pins of T PU_0, T PU_1, and TPU_2, and i nterrupt i nput pins. The
correspondence be t ween the registe r specification and the pi n functions is shown below.
Rev. 1.0, 02/02, page 93 of 502
• P17/TIOCB2/TCLKD
The pin function is switched as shown below according to the combination of the TPU channel
2 settings (by bits MD3 to MD0 in TMDR_2, bits IOB3 to IOB0 in TIOR_2, and bits CCL R1
and CCLR0 in TCR_2), bits TPSC2 t o TPSC0 in TCR_0, and bi t P17DDR.
TPU channel 2
settings (1) in table below (2) in table below
P17DDR — 0 1
Pin function P17 input P17 outputTIOCB2 output
TIO CB2 input*1
TCLKD input*2
TPU channel 2
settings (2) (1) (2) (2) (1) (2)
MD3 to MD0 B'0000, B'01xx B'0010 B'0011
IOB 3 to IOB0 B'0000
B'0100
B'1xxx
B'0001 to B'00 11
B'0101 to B'01 11 — B'xx00 Other than B'xx00
CCLR1, CCL R0 — — — — O th er
than
B'10
B'10
Output function — Output compare
output ——
PWM
mode 2
output
—
Legend
x: Don’t care
Notes: 1. TIOCB2 input when M D3 to MD0 = B'0000 or B'01xx while IOB3 = 1.
2. TCLKD input when TPSC2 to TPSC0 = B'111 in TCR_0.
TCLKD input when phase counting mode is set to channel 2.
Rev. 1.0, 02/02, page 94 of 502
• P16/TIOCA2/
,54
The pin function is switched as shown below according to the combination of the TPU channel
2 settings (by bits MD3 to MD0 in TMDR_2, bits IOA3 to IOA0 in TIOR_2, and bits CCLR1
and CCLR0 in TCR_2) and bit P16DDR.
TPU channel 2
settings (1) in table below (2) in table below
P16DDR — 0 1
Pin function P16 input P16 outputTIOCA2 output
TIO CA2 input*1
,54
input
TPU channel 2
settings (2) (1) (2) (1) (1) (2)
MD3 to MD0 B'0000, B'01xx B'001x B'0010 B'0011
IOA 3 to IOA0 B'0000
B'0100
B'1xxx
B'0001 to B'00 11
B'0101 to B'01 11 B'xx00 Other than B'xx00
CCLR1, CCL R0 — — — — O th er
than
B'01
B'01
Output function — Output compare
output —PWM
mode 1
output*2
PWM
mode 2
output
—
Legend
x: Don’t care
Notes: 1. TIOCA2 input when MD3 to M D0 = B'0000 or B'01xx while IO A3 = 1.
2. TIOCB2 out put disabled.
Rev. 1.0, 02/02, page 95 of 502
• P15/TIOCB1/TCLKC
The pin function is switched as shown below according to the combination of the TPU channel
1 settings (by bits MD3 to MD0 in TMDR_1, bits IOB3 to IOB0 in TIOR_1, and bits CCL R1
and CCLR0 in TCR_1), bits TPSC2 t o TPSC0 in TCR_0 to TCR_2, and bi t P15DDR.
TPU channel 1
settings (1) in table below (2) in table below
P15DDR — 0 1
Pin function P15 input P15 outputTIOCB1 output
TIO CB1 input*1
TCLKC input*2
TPU channel 1
settings (2) (1) (2) (2) (1) (2)
MD3 to MD0 B'0000, B'01xx B'0010 B'0011
IOB 3 to IOB0 B'0000
B'0100
B'1xxx
B'0001 to B'00 11
B'0101 to B'01 11 — B'xx00 Other than B'xx00
CCLR1, CCL R0 — — — — O th er
than
B'10
B'10
Output function — Output compare
output ——
PWM
mode 2
output
—
Legend
x: Don’t care
Notes: 1. TIOCB1 input when M D3 to MD0 = B'0000 or B'01xx while IOB3 to IOB0 = B'10xx.
2. TCLKC input when TPSC2 to TPSC0 = B'110 f or any am ong TCR_0 to TCR_2.
TCLKC input when phase counting mode is set for channel 2.
Rev. 1.0, 02/02, page 96 of 502
• P14/TIOCA1/
,54
The pin function is switched as shown below according to the combination of the TPU channel
1 settings (by bits MD3 to MD0 in TMDR_1, bits IOA3 to IOA0 in TIOR_1, and bits CCLR1
and CCLR0 in TCR_1) and bit P14DDR.
TPU channel 1
settings (1) in table below (2) in table below
P14DDR — 0 1
Pin function P14 input P14 outputTIOCA1 output
TIO CA1 input*1
,54
input
TPU channel 1
settings (2) (1) (2) (1) (1) (2)
MD3 to MD0 B'0000, B'01xx B'001x B'0010 B'0011
IOA 3 to IOA0 B'0000
B'0100
B'1xxx
B'0001 to B'00 11
B'0101 to B'01 11 B'xx00 Other
than
B'xx00
Other than B'xx00
CCLR1, CCL R0 — — — — O th er
than
B'01
B'01
Output function — Output compare
output —PWM
mode 1
output*2
PWM
mode 2
output
—
Legend
x: Don’t care
Notes: 1. TIOCA1 input when MD3 to M D0 = B'0000 or B'01xx while IO A3 to IOA0 = B'10xx.
2. TIOCB1 out put disabled.
Rev. 1.0, 02/02, page 97 of 502
• P13/TIOCD0/TCLKB
The pin function is switched as shown below according to the combination of the TPU channel
0 settings (by bits MD3 to MD0 in TMDR_0, bits IOD3 to IOD0 in TIORL_0, and bits
CCLR2 to CCLR0 in TCR_0), bits TPSC2 to T PSC0 in TCR_0 to TCR_2, a nd bit P13DDR.
TPU channel 0
settings (1) in table below (2) in table below
P13DDR — 0 1
Pin function P13 input P13 outputTIOCD0 output
TIO CD0 input*1
TCLKB input*2
TPU channel 0
settings (2) (1) (2) (2) (1) (2)
MD3 to MD0 B'0000 B'0010 B'0011
IOD3 to IOD0 B' 0000
B'0100
B'1xxx
B'0001 to B'00 11
B'0101 to B'01 11 — B'xx00 Other than B'xx00
CCLR2 t o
CCLR0 — — — — Other
than
B'110
B'110
Output function — Output compare
output ——
PWM
mode 2
output
—
Legend
x: Don’t care
Notes: 1. TIOCD0 input when M D3 to MD0 = B'0000 while IOD3 to IOD0 = B'10xx.
2. TCLKB input when TPSC2 to TPSC0 = B'101 for any among TCR_0 to TCR_2.
TCLKB input when phase counting mode is set for channel 1.
Rev. 1.0, 02/02, page 98 of 502
• P12/TIOCC0/TCLKA
The pin function is switched as shown below according to the combination of the TPU channel
0 settings (by bits MD3 to MD0 in TMDR_0, bits IOC3 to IOC0 in TIORL_0, and bit s CCL R2
to CCLR0 in TCR_0), bit s TPSC2 to TPSC0 i n TCR_0 to TCR_2, a nd bit P12DDR.
TPU channel 0
settings (1) in table below (2) in table below
P12DDR — 0 1
Pin function P12 input P12 outputTIOCC0 output
TIO CC0 input*1
TCLKA input*2
TPU channel 0
settings (2) (1) (2) (1) (1) (2)
MD3 to MD0 B'0000 B'001x B'0010 B'0011
IOC3 to IOC0 B' 0000
B'0100
B'1xxx
B'0001 to B'00 11
B'0101 to B'01 11 B'xx00 Other
than
B'xx00
Other than B'xx00
CCLR2 t o
CCLR0 — — — — Other
than
B'101
B'101
Output function — Output compare
output —PWM
mode 1
output*3
PWM
mode 2
output
—
Legend
x: Don’t care
Notes: 1. TIOCC0 input when M D3 to MD0 = B'0000 while IOC3 to IOC0 = B'10xx.
2. TCLKA input when TPSC2 to TPSC0 = B'100 for any among TCR_0 to TCR_2.
TCLKA input when phase counting mode is set for channel 1.
3. TIOCC0 output disabled. Output disabled and settings (2) effective when BFA = 1 or
BFB = 1 in TM DR_ 0.
Rev. 1.0, 02/02, page 99 of 502
• P11/TIOCB0
The pin function is switched as shown below according to the combination of the TPU channel
0 settings (by bits MD3 to MD0 in TMDR_0, bits IOB3 to IOB0 in TIORH_0, and bits
CCLR2 to CCLR0 in TCR_0) and bit P11DDR.
TPU channel 0
settings (1) in table below (2) in table below
P11DDR — 0 1
Pin function P11 input P11 outputTIOCB0 output
TIO CB0 input
TPU channel 0
settings (2) (1) (2) (2) (1) (2)
MD3 to MD0 B'0000 B'0010 B'0011
IOB 3 to IOB0 B'0000
B'0100
B'1xxx
B'0001 to B'00 11
B'0101 to B'01 11 — B'xx00 Other than B'xx00
CCLR2 t o
CCLR0 —— ——
Other
than
B'010
B'010
Output function — Output compare
output ——
PWM
mode 2
output
—
Legend
x: Don’t care
Note: TIOCB0 input when MD3 to M D0 = B'0000 while IOB3 to IOB0 = B'10xx.
Rev. 1.0, 02/02, page 100 of 502
• P10/TIOCA0
The pin function is switched as shown below according to the combination of the TPU channel
0 settings (by bits MD3 to MD0 in TMDR_0, bits IOA3 to IOA0 in TIORH_0, and bits
CCLR2 to CCLR0 in TCR_0) and bit P10DDR.
TPU channel 0
settings (1) in table below (2) in table below
P10DDR — 0 1
Pin function P10 input P10 outputTIOCA0 output
TIO CA0 input*
TPU channel 0
settings (2) (1) (2) (1) (1) (2)
MD3 to MD0 B'0000 B'001x B'0010 B'0011
IOA 3 to IOA0 B'0000
B'0100
B'1xxx
B'0001 to B'00 11
B'0101 to B'01 11 B'xx00 Other
than
B'xx00
Other than B'xx00
CCLR2 t o
CCLR0 —— ——
Other
than
B'001
B'001
Output function — Output compare
output —PWM
mode 1
output*2
PWM
mode 2
output
—
Legend
x: Don’t care
Notes: 1. TIOCA0 input when MD3 to M D0 = B'0000 while IOA3 to IOA0 = B'10xx.
2. TIOCA0 out put disabled.
Rev. 1.0, 02/02, page 101 of 502
7.2 Port 3
Port 3 is a 6-bit I/O port that also has other functions. Port 3 has the following re gisters.
• Port 3 data direction register (P3DDR)
• Port 3 data registe r (P3DR)
• Port 3 register (PORT3)
• Port 3 open-drain control regi ster (P3ODR)
7.2.1 Por t 3 Data Directi o n Register (P3DDR)
The indivi dual bits of P3DDR specify input or output for the pins of port 3.
Bit Bit Name Initial Value R/W Descr i ption
7
6−Undefined −Reserved
These bits will return undef ined values if read.
5 P35DDR 0 W
4 P34DDR 0 W
3 P33DDR 0 W
2 P32DDR 0 W
1 P31DDR 0 W
0 P30DDR 0 W
When a pin function is specified to a general I/O port,
setting this bit to 1 makes t he corresponding port 1
pin an output pin, while clearing this bit to 0 makes
the pin an input pin.
7.2.2 Port 3 Data Register (P 3DR)
P3DR store s output data for the port 3 pins.
Bit Bit Name Initial Value R/W Descr i ption
7
6−Undefined −Reserved
These bits will return undef ined values if read.
5 P35DR 0 R/W
4 P34DR 0 R/W
3 P33DR 0 R/W
2 P32DR 0 R/W
1 P31DR 0 R/W
0 P30DR 0 R/W
Output data for a pin is stored when the pin f unction
is specif ied to a general I/O port.
Rev. 1.0, 02/02, page 102 of 502
7.2.3 Port 3 Register (PORT3)
PORT3 shows port 3 pin states. PORT3 ca nnot be modified.
Bit Bit Name Initial Value R/W Descr i ption
7
6−Undefined −Reserved
These bits will return undef ined values if read.
5 P35 Undefined*R
4 P34 Undefined*R
3 P33 Undefined*R
2 P32 Undefined*R
1 P31 Undefined*R
0 P30 Undefined*R
If a port 3 r ead is performed while P3DDR bits ar e
set to 1, the P3DR values are read. I f a port 3 r ead is
perform e d while P3 DDR bits are cleared t o 0, the pin
states are read.
Note: * Determined by t he states of pins P35 to P30.
7. 2.4 Port 3 Open-Drain Contro l Regist er (P3ODR)
P3ODR se lects the output type of port 3.
Bit Bit Name Initial Value R/W Descr i ption
7
6−Undefined −Reserved
These bits will return undef ined values if read.
5 P35ODR 0 R/W
4 P34ODR 0 R/W
3 P33ODR 0 R/W
2 P32ODR 0 R/W
1 P31ODR 0 R/W
0 P30ODR 0 R/W
Setting this bit to 1 turns off the PMOS of the
corresponding pin, and if t he pin function is specified
to output, makes it an open- drain output pin, while
clearing this bit to 0 makes it a push-pull output pin.
Rev. 1.0, 02/02, page 103 of 502
7.2.5 Pin Functions
Port 3 pins also function as I/O pins for SCI_0 and SCI_1, and interrupt input pins. The
correspondence be t ween the registe r specification and the pi n functions is shown below.
• P35/SCK1/
,54
The pin function is switched as shown below according to the combination of bit C/
$
in SM R an d
bits CKE0 and CKE1 in SCR of SCI_1, and bit P35DDR.
CKE1 0 1
C/
$
01−
CKE0 0 1 −−
P35DDR 0 1 −−−
P35 input P35 output SCK1 output SCK1 output SCK1 inputPin function
,54
input
• P34/RxD1
The pin function is switched as shown below according to the combination of bit RE in SCR of
SCI_1 a nd bit P34DDR.
RE 0 1
P34DDR 0 1 −
Pin function P34 input P34 output RxD1 input
• P33/TxD1
The pin function is switched as shown below according to the combination of bit TE in SCR of
SCI_1 a nd bit P33DDR.
TE 0 1
P33DDR 0 1 −
Pin function P33 input P33 output TxD1 output
Rev. 1.0, 02/02, page 104 of 502
• P32/SCK0/
,54
The pin function is switched as shown below according to the combination of bit C/
$
in SM R an d
bits CKE0 and CKE1 in SCR of SCI_0, and bit P32DDR.
CKE1 0 1
C/
$
01−
CKE0 0 1 −−
P32DDR 0 1 −−−
P32 input P32 output SCK0 output SCK0 output SCK0 inputPin function
,54
input
• P31/RxD0
The pin function is switched as shown below according to the combination of bit RE in SCR of
SCI_0 a nd bit P31DDR.
RE 0 1
P31DDR 0 1 −
Pin function P31 input P31 output RxD0 input
• P30/TxD0
The pin function is switched as shown below according to the combination of bit TE in SCR of
SCI_0 a nd bit P30DDR.
TE 0 1
P30DDR 0 1 −
Pin function P30 input P30 output TxD0 input
Rev. 1.0, 02/02, page 105 of 502
7.3 Port 4
Port 4 is an 8-bit I/O port that also functions a s an A/D c onverter analog input port. Port 4 has the
following re gister.
• Port 4 register (PORT4)
7.3.1 Port 4 Register (PORT4)
PORT4 shows port 4 pin states. PORT4 ca nnot be modified.
Bit Bit Name Initial Value R/W Descr i ption
7 P47 Undefined*R
6 P46 Undefined*R
5 P45 Undefined*R
4 P44 Undefined*R
3 P43 Undefined*R
2 P42 Undefined*R
1 P41 Undefined*R
0 P40 Undefined*R
The pin states are always read when a port 4 read is
performed.
Note: * Determined by t he states of pins P47 to P40.
Rev. 1.0, 02/02, page 106 of 502
7.4 Port A
Port A i s an 8-bit I/O port that a lso has other functions. Port A has the following registers.
• Port A data direc t ion regist e r (PADDR )
• Port A data regi ste r (PADR)
• Port A re gister (PORT A)
• Port A open-dra i n control register (PAODR)
7.4.1 P or t A Data Di re c tion Register (PADDR)
The i ndi vid ual bit s of PADDR specify inp ut or outp ut for the pins of port A.
Bit Bit Name Initial Value R/W Descr i ption
7 PA7DDR 0 W
6 PA6DDR 0 W
5 PA5DDR 0 W
4 PA4DDR 0 W
3 PA3DDR 0 W
2 PA2DDR 0 W
1 PA1DDR 0 W
0 PA0DDR 0 W
When a pin function is specified to a general I/O port,
setting this bit to 1 makes t he corresponding port A
pin an output pin, while clearing this bit to 0 makes
the pin an input pin.
7.4.2 P or t A Data Re gi ster (PADR)
PADR sto r e s output data f or the port A pins.
Bit Bit Name Initial Value R/W Descr i ption
7 PA7DR 0 R/W
6 PA6DR 0 R/W
5 PA5DR 0 R/W
4 PA4DR 0 R/W
3 PA3DR 0 R/W
2 PA2DR 0 R/W
1 PA1DR 0 R/W
0 PA0DR 0 R/W
Output data for a pin is stored when the pin f unction
is specif ied to a general I/O port.
Rev. 1.0, 02/02, page 107 of 502
7.4.3 Port A Regi ster (PO RTA)
PORTA shows port A pin states. PORTA cannot be modified.
Bit Bit Name Initial Value R/W Descr i ption
7 PA7 Undefined*R
6 PA6 Undefined*R
5 PA5 Undefined*R
4 PA4 Undefined*R
3 PA3 Undefined*R
2 PA2 Undefined*R
1 PA1 Undefined*R
0 PA0 Undefined*R
If a port A re ad is perfo rm e d while PADDR bits ar e
s et to 1, the PAD R va lu es are read. If a port A read
is performed while PADDR bits are cleared t o 0, the
pin states are read.
Note: * Determined by t he states of pins PA7 to PA0.
7. 4.4 Port A Ope n Drain Contro l Regist er (PAODR)
PAODR selects the output type of port A.
Bit Bit Name Initial Value R/W Descr i ption
7 PA7ODR 0 R/W
6 PA6ODR 0 R/W
5 PA5ODR 0 R/W
4 PA4ODR 0 R/W
3 PA3ODR 0 R/W
2 PA2ODR 0 R/W
1 PA1ODR 0 R/W
0 PA0ODR 0 R/W
Setting this bit to 1 turns off the PMOS of the
corresponding pin, and if t he pin function is specified
to output, makes it an open- drain output pin, while
clearing this bit to 0 makes it a push-pull output pin.
7.4.5 Pin Functions
Port A pi ns also funct ion as segment output pins and common output pins of the LCD. The
correspondence be t ween the registe r specification and the pi n functions is shown below.
• PA7/SEG28, PA6/SEG27, PA5/SEG26, PA4/SEG25
The p in function is switched as shown belo w acco rdin g to the combinat i on of bits SGS3 to
SGS0 in LPC R of the LCD and bit PAnDDR.
Rev. 1.0, 02/02, page 108 of 502
SGS3 to SGS0 0000 Other than 0000
PAnDDR 0 1 −
Pin function PA7 to PA4 input PA7 to PA4 output SEG28 to SEG25 output
n = 7 to 4
• PA3/C OM4, PA2 /COM3, PA1/ C OM2, PA0/C OM1
The p in function is switched as shown belo w acco rdin g to the combinat i on of bits SGS3 to
SGS0 in LPC R of the LCD and bit PAnDDR.
SGS3 to SGS0 0000 Other than 0000
PAnDDR 0 1 −
Pin function PA3 to PA0 input PA3 to PA0 output COM4 to COM1 out put
n = 3 to 0
7.5 Port B
Port B is an 8-bit I/O port that also has other functions. Port B has the following registers.
• Port B data direction registe r (PBDDR)
• Port B data register (PBDR)
• Port B register (PORTB)
• Port B open-drain control regi ster (PBODR)
7. 5.1 Port B Data Direct i o n Register (PB DDR)
The indivi dual bits of PBDDR specify input or output for the pins of port B.
Bit Bit Name Initial Value R/W Descr i ption
7 PB7DDR 0 W
6 PB6DDR 0 W
5 PB5DDR 0 W
4 PB4DDR 0 W
3 PB3DDR 0 W
2 PB2DDR 0 W
1 PB1DDR 0 W
0 PB0DDR 0 W
When a pin function is specified to an general I /O
port, set t ing this bit to 1 makes t he corresponding
port 1 pin an output pin, while clear ing this bit to 0
makes t he pin an input pin.
Rev. 1.0, 02/02, page 109 of 502
7.5.2 Port B Data Register (P BDR)
PBDR store s output data for the port B pins.
Bit Bit Name Initial Value R/W Descr i ption
7 PB7DR 0 R/W
6 PB6DR 0 R/W
5 PB5DR 0 R/W
4 PB4DR 0 R/W
3 PB3DR 0 R/W
2 PB2DR 0 R/W
1 PB1DR 0 R/W
0 PB0DR 0 R/W
Output data for a pin is stored when the pin f unction
is specif ied to a general I/O port.
7.5.3 Port B Register (PORTB)
PORTB shows port B pin states. PORTB ca nnot be modified.
Bit Bit Name Initial Value R/W Descr i ption
7 PB7 Undefined*R
6 PB6 Undefined*R
5 PB5 Undefined*R
4 PB4 Undefined*R
3 PB3 Undefined*R
2 PB2 Undefined*R
1 PB1 Undefined*R
0 PB0 Undefined*R
If a port B re ad is perfo rm e d while PBDDR bits ar e
s et to 1, the PBD R va lu es are read. If a port B read
is performed while PBDDR bits are cleared t o 0, the
pin states are read.
Note: * Determined by t he states of pins PB7 to PB0.
7.5.4 Port B Open Dr ai n Control Regi ster (PBO DR)
PBODR se lects the output type of port B.
Rev. 1.0, 02/02, page 110 of 502
Bit Bit Name Initial Value R/W Descr i ption
7 PB7ODR 0 R/W
6 PB6ODR 0 R/W
5 PB5ODR 0 R/W
4 PB4ODR 0 R/W
3 PB3ODR 0 R/W
2 PB2ODR 0 R/W
1 PB1ODR 0 R/W
0 PB0ODR 0 R/W
Setting this bit to 1 turns off the PMOS of the
corresponding pin, and if t he pin function is specified
to output, makes it an open- drain output pin, while
clearing this bit to 0 makes it a push-pull output pin.
7.5.5 Pin Functions
Port B pins also function as segme nt output pins of the LCD. The corre spondence between the
register specification and the pin functions is shown below.
• PB7/SEG20, PB6/ SE G19, PB5/SE G1 8, PB4/ SE G17
The p in function is switched as shown belo w acco rdin g to the combinat i on of bits SGS3 to
SGS0 in LPC R of the LCD and bit PBnDDR.
SGS3 to SGS0 0000 or 0001 Other than 0000 or 0001
PBnDDR 0 1 −
Pin function PB7 to PB4 input PB7 to PB4 output SEG20 to SEG17 output
n = 7 to 4
• PB3/SEG16, PB2/ SE G15, PB1/SE G1 4, PB0/ SE G13
The p in function is switched as shown belo w acco rdin g to the combinat i on of bits SGS3 to
SGS0 in LPC R of the LCD and bit PBnDDR.
SGS3 to SGS0 0000 to 0010 Other than 0000 to 0010
PBnDDR 0 1 −
Pin function PB3 to PB0 input PB3 to PB0 output SEG16 to SEG13 output
n = 3 to 0
7.6 Port C
Port C is an 8-bit I/O port that also has other functions. Port C has the following registers.
• Port C data direction registe r (PCDDR)
• Port C data register (PCDR)
Rev. 1.0, 02/02, page 111 of 502
• Port C register (PORTC)
• Port C open-drain control regi ster (PCODR)
7.6.1 P or t C Data Di re c tion Register (PCDDR)
The indivi dual bits of PCDDR specify input or output for the pins of port C.
Bit Bit Name Initial Value R/W Descr i ption
7 PC7DDR 0 W
6 PC6DDR 0 W
5 PC5DDR 0 W
4 PC4DDR 0 W
3 PC3DDR 0 W
2 PC2DDR 0 W
1 PC1DDR 0 W
0 PC0DDR 0 W
When a pin function is specified to a general I/O port,
setting this bit to 1 makes t he corresponding port 1
pin an output pin, while clearing this bit to 0 makes
the pin an input pin.
7.6.2 P or t C Data Re gi ster (PCDR)
PCDR store s output data for the port C pins.
Bit Bit Name Initial Value R/W Descr i ption
7 PC7DR 0 R/W
6 PC6DR 0 R/W
5 PC5DR 0 R/W
4 PC4DR 0 R/W
3 PC3DR 0 R/W
2 PC2DR 0 R/W
1 PC1DR 0 R/W
0 PC0DR 0 R/W
Output data for a pin is stored when the pin f unction
is specif ied to a general I/O port.
7.6.3 Port C Regi ster (PO RTC)
PORTC shows port C pin states. PORTC ca nnot be modified.
Rev. 1.0, 02/02, page 112 of 502
Bit Bit Name Initial Value R/W Descr i ption
7 PC7 Undefined*R
6 PC6 Undefined*R
5 PC5 Undefined*R
4 PC4 Undefined*R
3 PC3 Undefined*R
2 PC2 Undefined*R
1 PC1 Undefined*R
0 PC0 Undefined*R
If a port C read is performed while PCDDR bit s are
set to 1, the PCDR values are read. If a port C read
is perform ed while PCDDR bit s are clear e d to 0, the
pin states are read.
Note: * Determined by t he states of pins PC7 to PC0.
7. 6.4 Port C Ope n Drain Contro l Regist er (PCODR)
PCODR se lects the output type of port C.
Bit Bit Name Initial Value R/W Descr i ption
7 PC7ODR 0 R/W
6 PC6ODR 0 R/W
5 PC5ODR 0 R/W
4 PC4ODR 0 R/W
3 PC3ODR 0 R/W
2 PC2ODR 0 R/W
1 PC1ODR 0 R/W
0 PC0ODR 0 R/W
Setting this bit to 1 turns off the PMOS of the
corresponding pin, and if t he pin function is specified
to output, makes it an open- drain output pin, while
clearing this bit to 0 makes it a push-pull output pin.
7.6.5 Pin Funct ions
Port C pins also function as segme nt output pins of the LCD. The corre spondence between the
register specification and the pin functions is shown below.
• PC7/SEG12, PC6/ SE G11, PC5/SE G1 0, PC4/ SE G9
The p in function is switched as shown belo w acco rdin g to the combinat i on of bits SGS3 to
SGS0 in LPC R of the LCD and bit PCnDDR.
Rev. 1.0, 02/02, page 113 of 502
SGS3 to SGS0 0000 to 0011 Other than 0000 to 0011
PCnDDR 0 1
Pin function PC7 to PC4 input PC7 to PC4 output SEG12 to SEG9 output
n = 7 to 4
• PC3/ SE G8, PC2/ SE G7, PC1/SEG6, PC0 / SEG5
The p in function is switched as shown belo w acco rdin g to the combinat i on of bits SGS3 to
SGS0 in LPC R of the LCD and bit PCnDDR.
SGS3 to SGS0 0000 to 0100 Other than 0000 to 0100
PCnDDR 0 1 −
Pin function PC3 to PC0 input PC3 to PC0 output SEG8 to SEG5 output
n = 3 to 0
7.7 Port D
Port D i s a 4-bit I/O port tha t also ha s other funct ions. Port D has the following regi sters.
• Port D data direc t ion regist e r (PDDDR )
• Port D data regi ste r (PDDR)
• Port D re gister (PORT D)
7.7.1 P or t D Data Di re c tion Register (PDDDR)
The i ndi vid ual bit s of PDDDR specify inp ut or outp ut for the pins of port D.
Bit Bit Name Initial Value R/W Descr i ption
7 PD7DDR 0 W
6 PD6DDR 0 W
5 PD5DDR 0 W
4 PD4DDR 0 W
When a pin function is specified to a general I/O port,
setting this bit to 1 makes t he corresponding port 1
pin an output pin, while clearing this bit to 0 makes
the pin an input pin.
3
to
0
−Undefined −Reserved
These bits will return undef ined values if read.
7.7.2 P or t D Data Re gi ster (PDDR)
PDDR sto r e s output data f or the port D pins.
Rev. 1.0, 02/02, page 114 of 502
Bit Bit Name Initial Value R/W Descr i ption
7 PD7DR 0 R/W
6 PD6DR 0 R/W
5 PD5DR 0 R/W
4 PD4DR 0 R/W
Output data for a pin is stored when the pin f unction
is specif ied to a general I/O port.
3
to
0
−Undefined −Reserved
These bits will return undef ined values if read.
Rev. 1.0, 02/02, page 115 of 502
7.7.3 Port D Regi ster (PO RTD)
PORTD shows port D pin states. PORTD cannot be modified.
Bit Bit Name Initial Value R/W Descr i ption
7 PD7 Undefined*R
6 PD6 Undefined*R
5 PD5 Undefined*R
4 PD4 Undefined*R
If a port D read is performed while PDDDR bit s are
set to 1, the PDDR values are read. If a port D read
is perform ed while PDDDR bit s are clear e d to 0, the
pin states are read.
3
to
0
−Undefined −Reserved
These bits will return undef ined values if read.
Note: * Determined by the states of pins PD7 t o PD4.
7.7.4 Pin Funct ions
Port D pi ns also funct ion as segment output pins of the LCD. The c orrespondence between the
register specification and the pin functions is shown below.
• PD7/SEG4, PD6/SEG3, PD5/SEG2, PD4/SEG1
The p in function is switched as shown belo w acco rdin g to the combinat i on of bits SGS3 to
SGS0 in LPC R of the LCD and bit PDnDDR.
SGS3 to SGS0 Other than 0110 0110
PDnDDR 0 1 −
Pin function PD7 to PD4 input PD7 to PD4 output SEG4 to SEG1 output
n = 7 to 4
Rev. 1.0, 02/02, page 116 of 502
7.8 Port F
Port F i s an 8-bit I/ O port that also has other funct ions. Port F has the foll owing re gisters.
• Port F data di rect i on reg i ste r (PFDDR)
• Port F data regi ste r (PFDR)
• Port F re gister (PORTF)
7. 8.1 Port F Data Direction Regi st er (PFDDR)
The i ndi vid ual bit s of PFDDR specify inp ut or outp ut for the pins of port F.
Bit Bi t Name Initi al Value R/W Description
7 PF7DDR 0 W When the pin function is specif ied to a gener al I/O
port, set t ing this bit to 1 makes t he PF7 pin the φ
output pin, while clearing this bit to 0 makes the pin
an input pin.
6 PF6DDR 0 W
5 PF5DDR 0 W
4 PF4DDR 0 W
3 PF3DDR 0 W
2 PF2DDR 0 W
When a pin function is specified to a general I/O
port, set t ing this bit to 1 makes t he corresponding
port F pin an output pin, while clearing this bit to 0
makes t he pin an input pin.
1
0−Undefined −Reserved
These bits will return undef ined values if read.
Rev. 1.0, 02/02, page 117 of 502
7.8.2 Por t F Data Register (PF DR)
PFDR st or es output dat a fo r the port F pin s.
Bit Bi t Name Initi al Value R/W Description
7−0R/W
Reserved
Only 0 should be wr itten to this bit.
6PF6DR 0 R/W
5PF5DR 0 R/W
4PF4DR 0 R/W
3PF3DR 0 R/W
2PF2DR 0 R/W
Output data for a pin is stored when the pin f unction
is specif ied to a general I/O port.
1
0−Undefined −Reserved
These bits will return undef ined values if read.
7.8.3 P or t F Register (PORTF )
PORTF shows port F pin states. PORTF ca nnot be m odified.
Bit Bit Name Initi al Value R/W Description
7 PF7 Undefined*R
6 PF6 Undefined*R
5 PF5 Undefined*R
4 PF4 Undefined*R
3 PF3 Undefined*R
2 PF2 Undefined*R
If a port F r ead is performed while PFDDR bits are
set to 1, the PFDR values ar e read. If a port F r ead is
per fo rm e d while PFDDR bits ar e cleare d to 0, the pin
states are read.
1
0−Undefined −Reserved
These bits will return undef ined values if read.
Note: * Determined by the states of pins PF7 to PF2.
Rev. 1.0, 02/02, page 118 of 502
7.8.4 Pin Functions
Port F pi ns also funct ion as an e xternal interrupt i nput pin, an A/D conve rter sta rt trigger input pin,
segment output pins of the LCD, and a syste m clock output pin. The correspondence between the
register specification and the pin functions is shown below.
• PF7/φ
The pin function is switched as shown below according to bit PF7DDR.
PF7DDR 0 1
Pin function PF7 input φ output
• PF6/SEG24
The p in function is switched as shown belo w acco rdin g to the combinat i on of bits SGS3 to
SGS0 in LPC R of the LCD and bit PF6DDR.
SGS3 to SGS0 0000 Other than 0000
PF6DDR 0 1 −
Pin function PF6 input PF6 output SEG24 output
• PF5/SEG23
The p in function is switched as shown belo w acco rdin g to the combinat i on of bits SGS3 to
SGS0 in LPC R of the LCD and bit PF5DDR.
SGS3 to SGS0 0000 Other than 0000
PF5DDR 0 1 −
Pin function PF5 input PF5 out put SEG23 out put
• PF4/SEG22
The p in function is switched as shown belo w acco rdin g to the combinat i on of bits SGS3 to
SGS0 in LPC R of the LCD and bit PF4DDR.
SGS3 to SGS0 0000 Other than 0000
PF4DDR 0 1 −
Pin function PF4 input PF4 out put SEG22 out put
Rev. 1.0, 02/02, page 119 of 502
• PF3/
$'75*
/
,54
The pin function is switched as shown below according to the combination of bits TRGS1 and
TR GS0 in ADCR of the A/D conve rter and bit PF3DDR.
PF3DDR 0 1
PF3 input PF3 output
$'75*
input*
Pin function
,54
input
Note: When TRGS1 = 1 and TRGS0 = 1, it becomes
$'75*
input.
• PF2/SEG21
The p in function is switched as shown belo w acco rdin g to the combinat i on of bits SGS3 to
SGS0 in LPC R of the LCD and bit PF2DDR.
SGS3 to SGS0 0000 Other than 0000
PF2DDR 0 1 −
Pin function PF2 input PF2 out put SEG21 out put
Rev. 1.0, 02/02, page 120 of 502
7.9 Port H
Port H i s an 8-bit I/O port that a lso has other functions. Port H has the following registers.
• Port H data direc t ion regist e r (PHDDR )
• Port H data regi ste r (PHDR)
• Port H re gister (PORT H)
7. 9.1 Port H Dat a Direct ion Regi ster (PH DDR)
The i ndi vid ual bit s of PHDDR specify inp ut or outp ut for the pins of port H.
Bit Bit Name I nitial Value R/W Description
7 PH7DDR 0 W
6 PH6DDR 0 W
5 PH5DDR 0 W
4 PH4DDR 0 W
3 PH3DDR 0 W
2 PH2DDR 0 W
1 PH1DDR 0 W
0 PH0DDR 0 W
When a pin function is specified to a general I/O port,
setting this bit to 1 makes t he corresponding port 1
pin an output pin, while clearing this bit to 0 makes
the pin an input pin.
7.9.2 Port H Data Re gi ster (PH DR)
PHDR sto r e s output data f or the port H pins.
Bit Bit Name I nitial Value R/W Description
7 PH7DR 0 R/W
6 PH6DR 0 R/W
5 PH5DR 0 R/W
4 PH4DR 0 R/W
3 PH3DR 0 R/W
2 PH2DR 0 R/W
1 PH1DR 0 R/W
0 PH0DR 0 R/W
Output data for a pin is stored when the pin f unction
is specif ied to a general I/O port.
Rev. 1.0, 02/02, page 121 of 502
7.9.3 Port H Register (PO RTH)
PORTH shows port H pin states. PORTH cannot be modified.
Bit Bit Name I nitial Value R/W Description
7 PH7 Undefined*R
6 PH6 Undefined*R
5 PH5 Undefined*R
4 PH4 Undefined*R
3 PH3 Undefined*R
2 PH2 Undefined*R
1 PH1 Undefined*R
0 PH0 Undefined*R
If a port H read is performed while PHDDR bit s are
set to 1, the PHDR values are read. If a port H read
is perform ed while PHDDR bit s are clear e d to 0, the
pin states are read.
Note: * Determined by t he states of pins PH7 to PH0.
7.9.4 Pin Funct ions
Port H pi ns also funct ion as the PWM_1 output pi ns. The c orrespondence bet ween the register
specification a nd t he pin functions is shown below.
• PH7/PWM1H
The pin function is switched as shown below according to the combination of bit OE1H in
PWOCR_1 of PWM_1 and bit PH7DDR.
OE1H 0 1
PH7DDR 0 1 −
Pin function PH7 input PH7 output PWM1H output
• PH6/PWM1G
The pin function is switched as shown below according to the combination of bit OE1G in
PWOCR_1 of PWM_1 and bit PH6DDR.
OE1G 0 1
PH6DDR 0 1 −
Pin function PH6 input PH6 output PWM1G output
Rev. 1.0, 02/02, page 122 of 502
• PH5/PWM1F
The pin function is switched as shown below according to the combination of bit OE1F in
PWOCR_1 of PWM_1 and bit PH5DDR.
OE1F 0 1
PH5DDR 0 1 −
Pin function PH5 input PH5 output PWM1F output
• PH4/PWM1E
The pin function is switched as shown below according to the combination of bit OE1E in
PWOCR_1 of PWM_1 and bit PH4DDR.
OE1E 0 1
PH4DDR 0 1 −
Pin function PH4 input PH4 output PWM1E out put
• PH3/PWM1D
The pin function is switched as shown below according to the combination of bit OE1D in
PWOCR_1 of PWM_1 and bit PH3DDR.
OE1D 0 1
PH3DDR 0 1 −
Pin function PH3 input PH3 output PWM1D output
• PH2/PWM1C
The pin function is switched as shown below according to the combination of bit OE1C in
PWOCR_1 of PWM_1 and bit PH2DDR.
OE1C 0 1
PH2DDR 0 1 −
Pin function PH2 input PH2 output PWM1C out put
Rev. 1.0, 02/02, page 123 of 502
• PH1/PWM1B
The pin function is switched as shown below according to the combination of bit OE1B in
PWOCR_1 of PWM_1 and bit PH1DDR.
OE1B 0 1
PH1DDR 0 1 −
Pin function PH1 input PH1 output PWM1B output
• PH0/PWM1A
The pin function is switched as shown below according to the combination of bit OE1A in
PWOCR_1 of PWM_1 and bit PH0DDR.
OE1A 0 1
PH0DDR 0 1 −
Pin function PH0 input PH0 output PWM1A output
Rev. 1.0, 02/02, page 124 of 502
7.10 Port J
Port J i s an 8-bit I/O port that also has other funct ions. Port J has the followi ng registers.
• Port J data di rect i on reg i ste r (PJDDR)
• Port J data regi ste r (PJDR )
• Port J re gister (PORTJ)
7. 10. 1 Por t J Data Directi o n Register (PJDDR)
The i ndi vid ual bit s of PJDDR speci fy input o r output f or the pins of port J.
Bit Bit Name I nitial Value R/W Description
7 PJ7DDR 0 W
6 PJ6DDR 0 W
5 PJ5DDR 0 W
4 PJ4DDR 0 W
3 PJ3DDR 0 W
2 PJ2DDR 0 W
1 PJ1DDR 0 W
0 PJ0DDR 0 W
When a pin function is specified to a general I/O port,
setting this bit to 1 makes t he corresponding port 1
pin an output pin, while clearing this bit to 0 makes
the pin an input pin.
7.10.2 Port J Data Register (P JDR)
PJDR sto r e s output dat a fo r the port J pins.
Bit Bit Name Initial Value R/W Description
7PJ7DR 0 R/W
6PJ6DR 0 R/W
5PJ5DR 0 R/W
4PJ4DR 0 R/W
3PJ3DR 0 R/W
2PJ2DR 0 R/W
1PJ1DR 0 R/W
0PJ0DR 0 R/W
Output data for a pin is stored when the pin f unction
is specif ied to a general I/O port.
Rev. 1.0, 02/02, page 125 of 502
7.10.3 Port J Register (PORTJ)
PORTJ shows port J pin states. PORTJ ca nnot be modified.
Bit Bit Name Initi al Value R/W Description
7 PJ7 Undefined*R
6 PJ6 Undefined*R
5 PJ5 Undefined*R
4 PJ4 Undefined*R
3 PJ3 Undefined*R
2 PJ2 Undefined*R
1 PJ1 Undefined*R
0 PJ0 Undefined*R
If a port J r ead is performed while PJDDR bits ar e set
to 1, the PJDR values are read. If a port J r ead is
performed while PJDDR bits are cleared to 0, the pin
states are read.
Note: * Determined by t he states of pins PJ7 to PJ0.
7.10.4 Pin Functions
Port J pi ns also funct ion as the PW M_2 output pins. The c orrespondence between the regist er
specification a nd t he pin functions is shown below.
• PJ7/PWM2H
The pin function is switched as shown below according to the combination of bit OE2H in
PWOCR_2 of PWM_2 and bit PJ7DDR.
OE2H 0 1
PJ7DDR 0 1 −
Pin function PJ7 input PJ7 output PWM2H output
• PJ6/PWM2G
The pin function is switched as shown below according to the combination of bit OE2G in
PWOCR_2 of PWM_2 and bit PJ6DDR.
OE2G 0 1
PJ6DDR 0 1 −
Pin function PJ6 input PJ6 output PWM2G output
Rev. 1.0, 02/02, page 126 of 502
• PJ5/PWM2F
The pin function is switched as shown below according to the combination of bit OE2F in
PWOCR_2 of PWM_2 and bit PJ5DDR.
OE2F 0 1
PJ5DDR 0 1 −
Pin function PJ5 input PJ5 output PWM2F out put
• PJ4/PWM2E
The pin function is switched as shown below according to the combination of bit OE2E in
PWOCR_2 of PWM_2 and bit PJ4DDR.
OE2E 0 1
PJ4DDR 0 1 −
Pin function PJ4 input PJ4 output PWM2E out put
• PJ3/PWM2D
The pin function is switched as shown below according to the combination of bit OE2D in
PWOCR_2 of PWM_2 and bit PJ3DDR.
OE2D 0 1
PJ3DDR 0 1 −
Pin function PJ3 input PJ3 output PWM2D output
• PJ2/PWM2C
The pin function is switched as shown below according to the combination of bit OE2C in
PWOCR_2 of PWM_2 and bit PJ2DDR.
OE2C 0 1
PJ2DDR 0 1 −
Pin function PJ2 input PJ2 output PWM2C output
Rev. 1.0, 02/02, page 127 of 502
• PJ1/PWM2B
The pin function is switched as shown below according to the combination of bit OE2B in
PWOCR_2 of PWM_2 and bit PJ1DDR.
OE2B 0 1
PJ1DDR 0 1 −
Pin function PJ1 input PJ1 output PWM2B output
• PJ0/PWM2A
The pin function is switched as shown below according to the combination of bit OE2A in
PWOCR_2 of PWM_2 and bit PJ0DDR.
OE2A 0 1
PJ0DDR 0 1 −
Pin function PJ0 input PJ0 output PWM2A output
Rev. 1.0, 02/02, page 128 of 502
7.11 Pin Switc h Func tion
The upper or lower 4 bits of port H and port J are switched according to t he combi nation of the
TRPB an d TR P A b its in TR P RT.
7. 11. 1 Transpo r t Regist er (TRP RT )
TRPRT spec ifies the switch of pin functions in port H a nd port J by the combination of the TRPB
and TRPA bits.
Bit Bit Name Initial Value R/W Description
7
to
2
Undefined Reserved
These bits will return undef ined values if read.
1 TRPB 0 R/W
0 TRPA 0 R/W The pin functions in ports H and J are switched as
shown below according to the combination of the
TRPB and TRPA bits.
00: Initial v a lu e
01: The pi n functi ons of PH 3 t o PH 0 are swi tched t o
those of PJ3 to PJ0.
10: The pi n functi ons of PH 7 t o PH 4 are swi tched t o
those of PJ7 to PJ4.
11: The pin functions of PH7 t o PH4 and PH3 to PH0
are sw itched to th ose of PJ 7 to PJ 4 and P J3 t o
PJ0, respect ively.
7.11.2 Reading of Port Regi sters by Switc hing the Pin
In r eading PO R TH and PO RTJ, the pi ns to be re ad will differ by the TRPB an d T RPA bits in
TRPRT. Table 7.2 lists t he pins of regi sters t o be rea d by switching t he pins.
For the status of the pins to be read in PORTH and PORTJ, refer to section 7.9.3, Port H Re gister
(PORTH), and section 7.10.3, Port J Register (PORTJ). Set TRPRT before writing t o data
dir ec ti on regist ers ( PHDDR and PJDDR) and data regi ste r s (PHDR and PJDR).
Rev. 1.0, 02/02, page 129 of 502
Table 7.2 Pins of Registers to be Read and PWM Output by Switching Pins
TRPB
7
Bit
Read
Data
6543210
PH7 input/
PWM1H/
PHDR7
PH6 input/
PWM1G/
PHDR6
PH5 input/
PWM1F/
PHDR5
PH4 input/
PWM1E/
PHDR4
PH3 input/
PWM1D/
PHDR3
PH2 input/
PWM1C/
PHDR2
PH1 input/
PWM1B/
PHDR1
PH0 input/
PWM1A/
PHDR0
01
10
11
TRPA Port H Port J
46
Pin No.
Pin
State
45 44 43 40 39 38 37
PH7 input/
PWM1H/
PHDR7
PH6 input/
PWM1G/
PHDR6
PH5 input/
PWM1F/
PHDR5
PH4 input/
PWM1E/
PHDR4
PH3 input/
PWM1D/
PHDR3
PH2 input/
PWM1C/
PHDR2
PH1 input/
PWM1B/
PHDR1
PH0 input/
PWM1A/
PHDR0
PJ7 input/
PWM2H/
PJDR7
PJ6 input/
PWM2G/
PJDR6
PJ5 input/
PWM2F/
PJDR5
PJ4 input/
PWM2E/
PJDR4
PJ3 input/
PWM2D/
PJDR3
PJ2 input/
PWM2C/
PJDR2
PJ1 input/
PWM2B/
PJDR1
PJ0 input/
PWM2A/
PJDR0
56 55 54 53 50 49 48 47
PJ7 input/
PWM2H/
PJDR7
PJ6 input/
PWM2G/
PJDR6
PJ5 input/
PWM2F/
PJDR5
PJ4 input/
PWM2E/
PJDR4
PJ3 input/
PWM2D/
PJDR3
PJ2 input/
PWM2C/
PJDR2
PJ1 input/
PWM2B/
PJDR1
PJ0 input/
PWM2A/
PJDR0
PJ7 input/
PWM2H/
PJDR7
PJ6 input/
PWM2G/
PJDR6
PJ5 input/
PWM2F/
PJDR5
PJ4 input/
PWM2E/
PJDR4
PH3 input/
PWM2D/
PJDR3
PH2 input/
PWM2C/
PJDR2
PH1 input/
PWM2B/
PJDR1
PH0 input/
PWM2A/
PJDR0
PJ7 input/
PWM2H/
PJDR7
PJ6 input/
PWM2G/
PJDR6
PJ5 input/
PWM2F/
PJDR5
PJ4 input/
PWM2E/
PJDR4
PJ3 input/
PWM1D/
PHDR3
PJ2 input/
PWM1C/
PHDR2
PJ1 input/
PWM1B/
PHDR1
PJ0 input/
PWM1A/
PHDR0
PH7 input/
PWM2H/
PJDR7
PH6 input/
PWM2G/
PJDR6
PH5 input/
PWM2F/
PJDR5
PH4 input/
PWM2E/
PJDR4
PJ3 input/
PWM2D/
PJDR3
PJ2 input/
PWM2C/
PJDR2
PJ1 input/
PWM2B/
PJDR1
PJ0 input/
PWM2A/
PJDR0
PJ7 input/
PWM1H/
PHDR7
PJ6 input/
PWM1G/
PHDR6
PJ5 input/
PWM1F/
PHDR5
PJ4 input/
PWM1E/
PHDR4
PJ3 input/
PWM2D/
PJDR3
PJ2 input/
PWM2C/
PJDR2
PJ1 input/
PWM2B/
PJDR1
PJ0 input/
PWM2A/
PJDR0
PH7 input/
PWM2H/
PJDR7
PH6 input/
PWM2G/
PJDR6
PH5 input/
PWM2F/
PJDR5
PH4 input/
PWM2E/
PJDR4
PH3 input/
PWM2D/
PJDR3
PH2 input/
PWM2C/
PJDR2
PH1 input/
PWM2B/
PJDR1
PH0 input/
PWM2A/
PJDR0
PJ7 input/
PWM1H/
PHDR7
PJ6 input/
PWM1G/
PHDR6
PJ5 input/
PWM1F/
PHDR5
PJ4 input/
PWM1E/
PHDR4
PJ3 input/
PWM1D/
PHDR3
PJ2 input/
PWM1C/
PHDR2
PJ1 input/
PWM1B/
PHDR1
PJ0 input/
PWM1A/
PHDR0
PH7 input/
PWM1H/
PHDR7
PH6 input/
PWM1G/
PHDR6
PH5 input/
PWM1F/
PHDR5
PH4 input/
PWM1E/
PHDR4
PJ3 input/
PWM1D/
PHDR3
PJ2 input/
PWM1C/
PHDR2
PJ1 input/
PWM1B/
PHDR1
PJ0 input/
PWM1A/
PHDR0
PH7 input/
PWM1H/
PHDR7
PH6 input/
PWM1G/
PHDR6
PH5 input/
PWM1F/
PHDR5
PH4 input/
PWM1E/
PHDR4
PH3 input/
PWM2D/
PJDR3
PH2 input/
PWM2C/
PJDR2
PH1 input/
PWM2B/
PJDR1
PH0 input/
PWM2A/
PJDR0
PJ7 input/
PWM1H/
PHDR7
PJ6 input/
PWM1G/
PHDR6
PJ5 input/
PWM1F/
PHDR5
PJ4 input/
PWM1E/
PHDR4
PH3 input/
PWM1D/
PHDR3
PH2 input/
PWM1C/
PHDR2
PH1 input/
PWM1B/
PHDR1
PH0 input/
PWM1A/
PHDR0
PH7 input/
PWM2H/
PJDR7
PH6 input/
PWM2G/
PJDR6
PH5 input/
PWM2F/
PJDR5
PH4 input/
PWM2E/
PJDR4
PH3 input/
PWM1D/
PHDR3
PH2 input/
PWM1C/
PHDR2
PH1 input/
PWM1B/
PHDR1
PH0 input/
PWM1A/
PHDR0
PJ7 input/
PWM1H/
PHDR7
PJ6 input/
PWM1G/
PHDR6
PJ5 input/
PWM1F/
PHDR5
PJ4 input/
PWM1E/
PHDR4
PJ3 input/
PWM1D/
PHDR3
PJ2 input/
PWM1C/
PHDR2
PJ1 input/
PWM1B/
PHDR1
PJ0 input/
PWM1A/
PHDR0
PH7 input/
PWM2H/
PJDR7
PH6 input/
PWM2G/
PJDR6
PH5 input/
PWM2F/
PJDR5
PH4 input/
PWM2E/
PJDR4
PH3 input/
PWM2D/
PJDR3
PH2 input/
PWM2C/
PJDR2
PH1 input/
PWM2B/
PJDR1
PH0 input/
PWM2A/
PJDR0
7
Bit
Read
Data
6543210
Pin No.
Pin
State
7
Bit
Read
Data
6543210
46
Pin No.
Pin
State
45 44 43 40 39 38 37 56 55 54 53 50 49 48 47
7
Bit
Read
Data
6543210
Pin No.
Pin
State
7
Bit
Read
Data
6543210
46
Pin No.
Pin
State
45 44 43 40 39 38 37 56 55 54 53 50 49 48 47
7
Bit
Read
Data
6543210
Pin No.
Pin
State
7
Bit
Read
Data
6543210
46
Pin No.
Pin
State
45 44 43 40 39 38 37 56 55 54 53 50 49 48 47
7
Bit
Read
Data
6543210
Pin No.
Pin
State
00
Rev. 1.0, 02/02, page 130 of 502
Rev. 1.0, 02/02, page 131 of 502
Section 8 16-Bit Timer Pulse Unit (TPU)
This LSI ha s an on-chip 16-bit timer pulse unit (T PU) compri sed of three 16-bit timer c hannels.
The function list of the 16-bit timer unit and its block diagram are shown i n table 8.1 and figure
8.1, respec tively.
8.1 Features
• Maximum 8-pulse input/output
• Selection of 8 counter input clocks for each channel
• The fol lowing operations can be set for ea c h c ha nnel:
Wav ef orm output at co mpare match
Input capture function
Counter clear opera tio n
Synchronous operation:
Multiple timer counters (TCNT) can be written to simultaneously
Simultaneo u s c learing by co mpare match an d inp ut captu re is poss ible
Register simultaneous i nput/output is possible by synchronous c ounter ope ration
A maxim um 7-phase PWM out put is possible i n combination wi th synchronous opera tion
• Buffer opera tio n settabl e for channe l 0
• Phase counting mode settable independently for each of channels 1 and 2
• Fast access vi a internal 16-bit bus
• 13 interrupt sources
• A/D converter conve rsion sta rt trigger can be ge nerated
• Module stop mode can be set
TIMTPU4A_000020020200
Rev. 1.0, 02/02, page 132 of 502
Table 8.1 TP U Functi ons (1)
It em Channel 0 Channel 1 Channel 2
Count clock ø/1
ø/4
ø/16
ø/64
TCLKA
TCLKB
TCLKC
TCLKD
ø/1
ø/4
ø/16
ø/64
ø/256
TCLKA
TCLKB
ø/1
ø/4
ø/16
ø/64
ø/1024
TCLKA
TCLKB
TCLKC
General registers TGRA_0
TGRB_0 TGRA_1
TGRB_1 TGRA_2
TGRB_2
General registers/ buff er
registers TGRC_0
TGRD_0 ——
I/O pins TIOCA0
TIOCB0
TIOCC0
TIOCD0
TIOCA1
TIOCB1 TIOCA2
TIOCB2
Counter clear
function TGR compare match or
input capture TGR compare match or
input capture TGR compare match or
input capture
Compare 0 out put
match 1 output
output Toggle
output
Input capture
function
Synchronous
operation
PWM mode
Phase coun ting
mode —
Buffer operation ——
Rev. 1.0, 02/02, page 133 of 502
Table 8.1 TP U Functi ons (2)
It em Channel 0 Channel 1 Channel 2
A/D c onverter trigger TGRA _0 compare
match or input capture TGRA_1 compare
match or input capture TGRA_2 compare
match or input capture
Interrupt sources 5 sources
• Compare
match or
input capture 0A
• Compare
match or
input
capture 0B
• Compare
match or
input
capture 0C
• Compare
match or
input
capture 0D
• Overflow
4 sources
• Compare
match or input
capture 1A
• Compare
match or
input
capture 1B
• Overflow
• Underflow
4 sources
• Compare
match or
input
capture 2A
• Compare
match or
input
capture 2B
• Overflow
• Underflow
Legend
: Possible
— : Not possible
Rev. 1.0, 02/02, page 134 of 502
Channel 2
TMDR
TSR
TCR
TIOR
TIER
TGRA
TCNT
TGRB
TGRC
Channel 1
TMDR
TSR
TCR
TIOR
TIER
TGRA
TCNT
TGRB
Channel 0
Control logic for channel 0 to 2
TGRA
TCNT
TGRB
TGRD
Bus
interface
Common
TSYR
Control logic
TSTR
φ/1
φ/4
φ/16
φ/64
φ/256
φ/1024
TCLKA
TCLKB
TCLKC
TCLKD
Legend
TSTR:
TSYR:
TCR:
TMDR:
Timer start register
Timer synchro register
Timer control register
Timer mode register
Timer I/O control registers (H, L)
Timer interrupt enable register
Timer status register
TImer general registers (A, B, C, D)
TIOCA0
TIOCB0
TIOCC0
TIOCD0
TIOCA1
TIOCB1
TIOCA2
TIOCB2
Interrupt request signals
Channel 0:
Channel 1:
Channel 2:
Internal data bus
A/D converter convertion start signal
Module data bus
TGI0A
TGI0B
TGI0C
TGI0D
TCI0V
TGI1A
TGI1B
TCI1V
TCI1U
TGI2A
TGI2B
TCI2V
TCI2U
TMDR
TSR
TCR
TIORH
TIER TIORL
Input/output pins
Channel 0:
Channel 1:
Channel 2:
Clock input
Internal clock:
External clock:
TIOR(H, L)
TIER:
TSR:
TGR(A, B, C, D):
F igu r e 8.1 Bl ock D iagr am of TPU
Rev. 1.0, 02/02, page 135 of 502
8.2 Input/Output Pins
Table 8.2 P i n Configuration
Channel Symbol I/O Function
All TCLKA Input External clock A input pin
(Channel 1 phase counting m ode A phase input)
TCLKB Input External clock B input pin
(Channel 1 phase counting m ode B phase input)
TCLKC Input External clock C input pin
(Channel 2 phase counting m ode A phase input)
TCLKD Input External clock D input pin
(Channel 2 phase counting m ode B phase input)
0 TIO CA0 I/O TGRA_0 input capture input/output compare output/PWM output pin
TIO CB0 I/O TGRB_0 input capture input/ output compar e output/PWM output pin
TIO CC0 I /O TGRC_0 input capture input/ output compar e output/PWM output pin
TIO CD0 I /O TGRD_0 input capture input/ output compar e output/PWM output pin
1 TIO CA1 I/O TGRA_1 input capture input/output compare output/PWM output pin
TIO CB1 I/O TGRB_1 input capture input/ output compar e output/PWM output pin
2 TIO CA2 I/O TGRA_2 input capture input/output compare output/PWM output pin
TIO CB2 I/O TGRB_2 input capture input/ output compar e output/PWM output pin
Rev. 1.0, 02/02, page 136 of 502
8.3 Register Descri pt i on s
The TPU ha s the following registers. To distinguish registers i n each channe l, an underscore and
the channe l number are added as a suffix to the re gister name; TCR for channel 0 is expressed as
TCR_0.
• Timer control register_0 (TCR_0)
• Timer mode register_0 (TMDR_0)
• Timer I/O control re gister H_0 (TIORH_0)
• Timer I/O control re gister L_0 (TIORL_0)
• Timer int errupt ena ble register_0 (TIER_0)
• Timer status reg ister_0 (TSR_0)
• Timer counter_0 (TCNT_0)
• Timer gene ral register A_0 (TGRA_0)
• Timer gene ral register B_0 (TGRB_0)
• Timer gene ral register C_0 (TGRC_0)
• Timer gene ral register D_0 (TGRD_0)
• Timer control register_1 (TCR_1)
• Timer mode register_1 (TMDR_1)
• Timer I/O control re gister _1 (TIOR_1)
• Timer int errupt ena ble register_1 (TIER_1)
• Timer status reg ister_1 (TSR_1)
• Timer counter_1 (TCNT_1)
• Timer gene ral register A_1 (TGRA_1)
• Timer gene ral register B_1 (TGRB_1)
• Timer control register_2 (TCR_2)
• Timer mode register_2 (TMDR_2)
• Timer I/O control re gister_2 (TIOR_2)
• Timer int errupt ena ble register_2 (TIER_2)
• Timer status reg ister_2 (TSR_2)
• Timer counter_2 (TCNT_2)
• Timer gene ral register A_2 (TGRA_2)
• Timer gene ral register B_2 (TGRB_2)
Common Registers
• Timer start register (TSTR)
• Timer synchro register (T SYR)
Rev. 1.0, 02/02, page 137 of 502
8. 3.1 Tim er Control Registe r (TCR)
The TCR registers control the TCNT operation for each channel. The TPU has a total of three
TCR regi sters, one for each channel. TCR register settings shoul d be conduc ted only whe n TCNT
operation i s stopped.
Bit Bit Name I nitial value R/W Description
7
6
5
CCLR2
CCLR1
CCLR0
0
0
0
R/W
R/W
R/W
Counter Clear 0 to 2
These bits select the TCNT counter clear ing source.
See tables 8.3 and 8.4 f or details.
4
3CKEG1
CKEG0 0
0R/W
R/W Clock Edge 0 and 1
These bits select the input clock edge. When the
input clock is counted using both edges, the input
clock per iod is halved (e.g. ø/4 bot h edges = ø/2
rising edge). If phase counting mode is used on
channels 1 and 2, t his setting is ignored and the
phase coun ting mode setting has priority. Internal
clock edge selection is valid when the input clock is
ø/4 or slower. This setting is ignored if the input clock
is ø/1, or when overflow/underflow of anot her
channel is selected.
00: Count at rising edge
01: Count at falling edge
1X: Count at both edges
2
1
0
TPSC2
TPSC1
TPSC0
0
0
0
R/W
R/W
R/W
Time Prescaler 0 t o 2
These bits select the TCNT counter clock. The clock
source can be selected independently for each
channel. See tables 8. 5 to 8. 7 for details.
Legend
X: Don’t care
Rev. 1.0, 02/02, page 138 of 502
Tabl e 8.3 CCLR0 to CCLR2 ( Cha nnel 0)
Channel Bit 7
CCLR2 Bit 6
CCLR1 Bit 5
CCLR0 Description
0 0 0 0 TCNT clearing disabled
1TCNT cleared by TGRA compare m atch/input
capture
10TCNT cleared by TGRB compare m atch/input
capture
1 TCNT cleared by count er clearing for another
channel performing synchronous clearing/
synchronous oper ation*1
1 0 0 TCNT clearing disabled
1 TCNT cleared by TGRC compare match/input
capture*2
10TCNT cleared by TGRD compare m atch/input
capture*2
1 TCNT cleared by count er clearing for another
channel performing synchronous clearing/
synchronous oper ation*1
Notes: 1. Synchronous operation is set by setting the SYNC bit in TSYR t o 1.
2. When TGRC or TGRD is used as a buffer register , TCNT is not cleared because t he
buffer register setting has priority, and compare match/input captur e does not occur.
Tabl e 8.4 CCLR0 to CCLR2 ( Cha nnels 1 and 2)
Channel Bit 7
Reserved*2Bit 6
CCLR1 Bit 5
CCLR0 Description
1, 2 0 0 0 TCNT clearing disabled
1 TCNT cleared by TGRA compare match/input
capture
10TCNT cleared by TGRB compare m atch/input
capture
1 TCNT cleared by count er clearing for another
channel performing synchronous clearing/
synchronous oper ation*1
Notes: 1. Synchronous operation is selected by setting the SYNC bit in TSYR to 1.
2. Bit 7 is r eserved in channels 1 and 2. It is always r ead as 0 and cannot be modified.
Rev. 1.0, 02/02, page 139 of 502
Tabl e 8.5 TP SC0 to TPSC2 (Channe l 0)
Channel Bit 2
TPSC2 Bit 1
TPSC1 Bit 0
TPSC0 Description
0 0 0 0 Int ernal clock: count s on ø/1
1 Internal clock: count s on ø/4
1 0 Internal clock: count s on ø/16
1 Internal clock: count s on ø/64
1 0 0 External clock: counts on TCLKA pin input
1 External clock: counts on TCLKB pin input
1 0 Ext ernal clock: counts on TCLKC pin input
1 External clock: counts on TCLKD pin input
Tabl e 8.6 TP SC0 to TPSC2 (Channe l 1)
Channel Bit 2
TPSC2 Bit 1
TPSC1 Bit 0
TPSC0 Description
1 0 0 0 Int ernal clock: count s on ø/1
1 Internal clock: count s on ø/4
1 0 Internal clock: count s on ø/16
1 Internal clock: count s on ø/64
1 0 0 External clock: counts on TCLKA pin input
1 External clock: counts on TCLKB pin input
1 0 Internal clock: count s on ø/256
1 Setting pr ohibited
Note: This set t ing is ignored when channel 1 is in phase counting mode.
Rev. 1.0, 02/02, page 140 of 502
Tabl e 8.7 TP SC0 to TPSC2 (Channe l 2)
Channel Bit 2
TPSC2 Bit 1
TPSC1 Bit 0
TPSC0 Description
2 0 0 0 Int ernal clock: count s on ø/1
1 Internal clock: count s on ø/4
1 0 Internal clock: count s on ø/16
1 Internal clock: count s on ø/64
1 0 0 External clock: counts on TCLKA pin input
1 External clock: counts on TCLKB pin input
1 0 Ext ernal clock: counts on TCLKC pin input
1 Internal clock: count s on ø/1024
Note: This set t ing is ignored when channel 2 is in phase counting mode.
8.3.2 Timer Mode Register (TMDR)
The TMDR registers are used to set the operating mode of each channel. The TPU has three
TMDR registers, one for each channel. TMDR register settings should be changed only when
TCNT operation is stopped.
Bit Bit Name Initi al value R/W Description
7
6–
–1
1–
–Reserved
These bits are always read as 1 and cannot be
modified.
5 BFB 0 R/W Buffer Operation B
Specifies whether TG RB is to oper ate in the normal
way, or TGRB and TGRD are t o be used together
for buffer operation. When TGRD is used as a buf fer
register, TGRD input capture/output compar e is not
generated.
In channels 1 and 2, which have no TG RD, bit 5 is
reserved. It is always read as 0 and cannot be
modified.
0: TGRB operates normally
1: TGRB and TGRD used toget her for buffer
operation
Rev. 1.0, 02/02, page 141 of 502
Bit Bit Name Initi al value R/W Description
4 BFA 0 R/W Buffer Operation A
Specifies whether TG RA is to oper ate in the normal
way, or TGRA and TGRC are t o be used together
for buffer operation. When TGRC is used as a buf fer
register, TGRC input capture/output compar e is not
generated.
In channels 1, and 2, which have no TG RC, bit 4 is
reserved. It is always read as 0 and cannot be
modified.
0: TGRA operates normally
1: TGRA and TGRC used toget her for buffer
operation
3
2
1
0
MD3
MD2
MD1
MD0
0
0
0
0
R/W
R/W
R/W
R/W
Modes 0 to 3
These bits are used t o set the timer operating mode.
MD3 is a reserved bit. In a write, it should always be
written with 0. See t able 8.8 for details.
Table 8.8 M D0 to M D3
Bit 3
MD3*1Bit 2
MD2*2Bit 1
MD1 Bit 0
MD0 Description
0 0 0 0 Normal operation
1 Reserved
10PWM mode 1
1 PWM mode 2
1 0 0 Phase count ing mode 1
1 Phase counting mode 2
1 0 Phase counting m ode 3
1 Phase counting mode 4
1XXX—
Legend
X: Don’t care
Not e s: 1. MD3 is a reserved bit. In a write, it s hould a lwa y s be writt e n with 0.
2. Phase counting mode cannot be set for channel 0. In this case, 0 should always be
written to MD 2.
Rev. 1.0, 02/02, page 142 of 502
8. 3.3 Tim er I/O Cont rol Re gister (TIO R)
The TIOR registers control the TGR registers. The TPU has four TIOR registers, two for channel
0, and one each for channels 1 and 2.
Care is required as TIOR is affected by the TMDR setting. The initial output specified by TIOR is
valid when the counter is stopped (the CST bit in TSTR is cleared to 0). Note also that, in PWM
mode 2, the output at the point at which the counter is cleared to 0 is specified.
When TGRC or TGRD is designat e d for buffer ope ration, thi s setting is invalid and the re gister
operates as a buffer regi ster.
TIORH_0, TIOR_1, TIOR_2
Bit Bit Name Initial
value R/W Description
7
6
5
4
IOB3
IOB2
IOB1
IOB0
0
0
0
0
R/W
R/W
R/W
R/W
I/O Co n trol B0 to B3
Specify the function of TG RB.
3
2
1
0
IOA3
IOA2
IOA1
IOA0
0
0
0
0
R/W
R/W
R/W
R/W
I/O Co n trol A0 to A3
Specify the function of TG RA.
TIORL_0
Bit Bit Name Initial
value R/W Description
7
6
5
4
IOD3
IOD2
IOD1
IOD0
0
0
0
0
R/W
R/W
R/W
R/W
I/O Co n tr o l D0 to D3
Specify the function of TG RD.
3
2
1
0
IOC3
IOC2
IOC1
IOC0
0
0
0
0
R/W
R/W
R/W
R/W
I/O Co n tr o l C0 to C3
Specify the function of TG RC.
Rev. 1.0, 02/02, page 143 of 502
Table 8.9 TIORH_0
Description
Bit 7
IOB3 Bit 6
IOB2 Bit 5
IOB1 Bit 4
IOB0 TGRB_0
Function TIOCB0 Pi n Function
0 0 0 0 O utput Output disabled
1 compare
register Initial outp ut is 0
0 output at compare mat ch
1 0 Init ia l o utp ut is 0
1 output at compare mat ch
1 Initial output is 0
Toggle output at com pare match
1 0 0 Output disabled
1 Initial output is 1
0 output at compare mat ch
1 0 Init ia l o utp ut is 1
1 output at compare mat ch
1 Initial output is 1
Toggle output at com pare match
1 0 0 0 I nput Input captur e at r ising edge
1 capt ure Input captur e at f alling edge
1 X register Input capture at both edges
1 X X Capture input source is channel 1/ count clock
Input capture at TCNT_1 count- up/ count-down*
Legend
X: Don’t care
Note: * When bits TPSC0 to TPSC2 in TCR_1 are set to B'000 and ø/1 is used as t he TCNT_1
count clock, this set t ing is invalid and input capture is not generated.
Rev. 1.0, 02/02, page 144 of 502
Table 8.10 TIORL_0
Description
Bit 7
IOD3 Bit 6
IOD2 Bit 5
IOD1 Bit 4
IOD0 TGRD_0
Function TIOCD0 Pi n Function
0 0 0 0 Output Output disabled
1 Compare
register*2Init ia l out put is 0
0 output at compare mat ch
1 0 Init ia l out put is 0
1 output at compare mat ch
1 Initial output is 0
Toggle output at com pare match
1 0 0 Output disabled
1 Initial output is 1
0 output at compare mat ch
1 0 Init ia l out put is 1
1 output at compare mat ch
1 Initial output is 1
Toggle output at com pare match
1 0 0 0 Input Capture input sour ce is TIOCD0 pin
Input capture at rising edge
1 capture Capture input sour ce is TIOCD0 pin
Input capture at falling edge
1 X register*2Capture input sour ce is TIOCD0 pin
Input capture at both edges
1 X X Capture input source is channel 1/count clock
Input capture at TCNT_1 count-up/ count-down*1
Legend
X: Don’t care
Notes: 1. When bits TPSC0 to TPSC2 in TCR_1 are set to B'000 and ø/1 is used as the TCNT_1
count clock, this set t ing is invalid and input capture is not generated.
2. When the BFB bit in TMDR_0 is set to 1 and TGRD_0 is used as a buffer register, this
setting is invalid and input capture/ output compar e is not gener ated.
Rev. 1.0, 02/02, page 145 of 502
Table 8.11 TIOR_1
Description
Bit 7
IOB3 Bit 6
IOB2 Bit 5
IOB1 Bit 4
IOB0 TGRB_1
Function TIOCB1 Pi n Function
0 0 0 0 Output O utput disabled
1 compare
register Initial outp ut is 0
0 output at compare mat ch
1 0 In itial out put is 0
1 output at compare mat ch
1 Initial output is 0
Toggle output at com pare match
1 0 0 Output disabled
1 Initial output is 1
0 output at compare mat ch
1 0 In itial out put is 1
1 output at compare mat ch
1 Initial output is 1
Toggle output at com pare match
1 0 0 0 I nput Capture input source is TIO CB1 pin
Input capture at rising edge
1 c apt ure Capture input source is TIOCB1 pin
Input capture at falling edge
1 X regist er Capture input source is TIOCB1 pin
Input capture at both edges
1 X X T GRC_0 compare match/ in put capture
Input capture at generation of TGRC_0 compare
ma t ch/input capture
Legend
X: Don’t care
Rev. 1.0, 02/02, page 146 of 502
Table 8.12 TIOR_2
Description
Bit 7
IOB3 Bit 6
IOB2 Bit 5
IOB1 Bit 4
IOB0 TGRB_2
Function TIOCB2 Pi n Function
0 0 0 0 Output O utput disabled
1 compare
register Initial outp ut is 0
0 output at compare mat ch
1 0 Initial out put is 0
1 output at compare mat ch
1 Initial output is 0
Toggle output at com pare match
1 0 0 O utput disabled
1 Initial output is 1
0 output at compare mat ch
1 0 Initial out put is 1
1 output at compare mat ch
1 Initial output is 1
Toggle output at com pare match
1 X 0 0 Input Capt ure input sour ce is TIO CB2 pin
Input capture at rising edge
1 capt ure Capture input source is TIOCB2 pin
Input capture at falling edge
1 X register Capture input source is TIOCB2 pin
Input capture at both edges
Legend
X: Don’t care
Rev. 1.0, 02/02, page 147 of 502
Table 8.13 TIORH_0
Description
Bit 3
IOA3 Bit 2
IOA2 Bit 1
IOA1 Bit 0
IOA0 TGRA_0
Function TIOCA0 Pi n Function
0 0 0 0 Output O utput disabled
1 compare
register Initial outp ut is 0
0 output at compare mat ch
1 0 Initial out put is 0
1 output at compare mat ch
1 Initial output is 0
Toggle output at com pare match
1 0 0 O utput disabled
1 Initial output is 1
0 output at compare mat ch
1 0 Initial out put is 1
1 output at compare mat ch
1 Initial output is 1
Toggle output at com pare match
1 0 0 0 Input Capture input source is TIOCA0 pin
Input capture at rising edge
1 capt ure Capture input source is TIOCA0 pin
Input capture at falling edge
1 X register Capture input source is TIOCA0 pin
Input capture at both edges
1 X X Capture input source is channel 1/count clock
Input capture at TCNT_1 count-up/ count-down
Legend
X: Don’t care
Rev. 1.0, 02/02, page 148 of 502
Table 8.14 TIORL_0
Description
Bit 3
IOC3 Bit 2
IOC2 Bit 1
IOC1 Bit 0
IOC0 TGRC_0
Function TIOCC0 Pi n Function
0 0 0 0 Output O utput disabled
1 compare
register*I nitial o utp ut is 0
0 output at compare mat ch
1 0 Initial out put is 0
1 output at compare mat ch
1 Initial output is 0
Toggle output at com pare match
1 0 0 Output disabled
1 Initial output is 1
0 output at compare mat ch
1 0 Initial out put is 1
1 output at compare mat ch
1 Initial output is 1
Toggle output at com pare match
1 0 0 0 Input Capture input source is TIOCC0 pin
Input capture at rising edge
1 capt ure Capt ure input source is TIOCC0 pin
Input capture at falling edge
1 X register*Capture input source is TIOCC0 pin
Input capture at both edges
1 X X Capture input source is channel 1/count clock
Input capture at TCNT_1 count-up/ count-down
Legend
X: Don’t care
Note:*When the BFA bit in TM DR_0 is set to 1 and TGRC_0 is used as a buffer register, this
setting is invalid and input capture/ output compar e is not gener ated.
Rev. 1.0, 02/02, page 149 of 502
Table 8.15 TIOR_1
Description
Bit 3
IOA3 Bit 2
IOA2 Bit 1
IOA1 Bit 0
IOA0 TGRA_1
Function TIOCA1 Pi n Function
0 0 0 0 Output O utput disabled
1 compare
register Initial outp ut is 0
0 output at compare mat ch
1 0 Initial out put is 0
1 output at compare mat ch
1 Initial output is 0
Toggle output at com pare match
1 0 0 O utput disabled
1 Initial output is 1
0 output at compare mat ch
1 0 Initial out put is 1
1 output at compare mat ch
1 Initial output is 1
Toggle output at com pare match
1 0 0 0 Input Capture input source is TIOCA1 pin
Input capture at rising edge
1 capt ure Capt ure input source is TIOCA1 pin
Input capture at falling edge
1 X register Capture input source is TIOCA1 pin
Input capture at both edges
1XX Capture input source is TGRA_0 compare
ma t ch/input capture
Input capture at generation of channel
0/TGRA_0 compare match/input captu re
Legend
X: Don’t care
Rev. 1.0, 02/02, page 150 of 502
Table 8.16 TIOR_2
Description
Bit 3
IOA3 Bit 2
IOA2 Bit 1
IOA1 Bit 0
IOA0 TGRA_2
Function TIOCA2 Pi n Function
0 0 0 0 Output O utput disabled
1 compare
register Initial outp ut is 0
0 output at compare mat ch
1 0 Init ia l o utp ut is 0
1 output at compare mat ch
1 Initial output is 0
Toggle output at com pare match
1 0 0 Output disabled
1 Initial output is 1
0 output at compare mat ch
1 0 Init ia l o utp ut is 1
1 output at compare mat ch
1 Initial output is 1
Toggle output at com pare match
1 X 0 0 Input Capture input sour ce is TIO CA2 pin
Input capture at rising edge
1 capt ure Capt ure input source is TIOCA2 pin
Input capture at falling edge
1 X register Capt ure input sour ce is TIOCA2 pin
Input capture at both edges
Legend
X: Don’t care
8. 3.4 Tim er Inte rr upt E na ble Register (TIER)
The TIER registers control enabling or disabling of interrupt requests for each channel. The TPU
has three TIER registers, one for each channe l.
Rev. 1.0, 02/02, page 151 of 502
Bit Bit Name I nitial value R/W Description
7 TTGE 0 R/W A/ D Conversion Start Request Enable
Enables or disables generation of A/D conversion
start requests by TGRA input capture/ compare
match.
0: A/D conversion start request gener ation disabled
1: A/D conversion start request gener ation enabled
6–1–Reserved
This bit is always read as 1 and cannot be modified.
5 TCIEU 0 R/W Underflow Interrupt Enable
Enables or disables in terrup t requ ests (TCIU) by the
TCFU flag when the TCFU flag in TSR is set to 1 in
channels 1 and 2.
In channel 0, bit 5 is reser ved. It is always read as 0
and cannot be modified.
0: In terrup t requests (TCIU) by TCFU disabled
1: In terrup t requests (TCIU) by TCFU enabled
4 TCIEV 0 R/W O v erflow Interrupt Enable
Enables or disables in terrup t requ ests (TCIV) by the
TCFV flag when the TCFV flag in TSR is set to 1.
0: In terrup t requests (TCIV) by TCFV disabled
1: In terrup t requests (TCIV) by TCFV enabled
3 TGI ED 0 R/W TGR Interrupt Enable D
Enables or disables in terrup t requ est s (T GID) by the
TGFD bit when the TG FD bit in TSR is set to 1 in
channel 0.
In channels 1 and 2, bit 3 is reserved. It is always
read as 0 and cannot be modified.
0: Interrupt requests (TGID) by TGFD bit disabled
1: Interrupt requests (TGID) by TGFD bit enabled
2 TGI EC 0 R/W TGR Interrupt Enable C
Enables or disables in terrup t requ est s (T GIC) by the
TGFC bit when the TG FC bit in TSR is set to 1 in
channel 0.
In channels 1 and 2, bit 2 is reserved. It is always
read as 0 and cannot be modified.
0: Interrupt requests (TGIC) by TGFC bit disabled
1: Interrupt requests (TGIC) by TGFC bit enabled
Rev. 1.0, 02/02, page 152 of 502
Bit Bit Name I nitial value R/W Description
1 TGI EB 0 R/W TGR Interrupt Enable B
Enables or disables in terrup t requ est s (T GIB) by the
TGFB bit when the TGFB bit in TSR is set to 1.
0: Interrupt requests (TGIB) by TGFB bit disabled
1: Interrupt requests (TGIB) by TGFB bit enabled
0 TGI EA 0 R/W TGR Interrupt Enable A
Enables or disables in terrup t requ est s (T GIA) by the
TGFA bit when the TGFA bit in TSR is set to 1.
0: Interrupt requests (TGIA) by TGFA bit disabled
1: Interrupt requests (TGIA) by TGFA bit enabled
Rev. 1.0, 02/02, page 153 of 502
8. 3.5 Tim er Stat us Regi st er (TSR)
The TSR reg is ters indicate the st atu s o f each chan nel. The TPU h as th ree TSR registe r s , one fo r
each ch annel.
Bit Bit Name I nitial value R/W Descr i ption
7 TCFD 1 R Count Direction Flag
Status flag that shows the direction in which TCNT
counts in channels 1 and 2.
In channel 0, bit 7 is reser ved. It is always read as 1
and cannot be modified.
0: TCNT counts down
1: TCNT counts up
6–1–Reserved
This bit is always read as 1 and cannot be modified.
5 TCFU 0 R/(W)*Underflow Flag
Status flag that indicates that TCNT underflow has
occurred when channels 1 and 2 are set to phase
counting mode . Only 0 can be w rit ten , for flag
clearing.
In channel 0, bit 5 is reser ved. It is always read as 0
and cannot be modified.
[Setting condition]
When the TCNT value underflows (changes from
H'0000 to H'FFFF )
[Clearing condition]
When 0 is written to TCFU after reading TCFU = 1
4 TCFV 0 R/(W)*Overflow Flag
Status flag that indicates that TCNT overflow has
occurred. Only 0 can be wr itten, for flag clearing.
[Setting condition]
When the TCNT value overflows (changes from
H'FFFF to H'0000 )
[Clearing condition]
When 0 is written to TCFV after reading TCFV = 1
Rev. 1.0, 02/02, page 154 of 502
Bit Bit Name I nitial value R/W Descr i ption
3TGFD 0 R/(W)*Input Capture/Output Compare Flag D
Status flag that indicates the occur rence of TGRD
input capture or compare match in channel 0. In
channels 1 and 2, bit 3 is reserved. It is always read
as 0 and cannot be modified.
[Setting condition s]
• When TCNT = TGRD and TGRD is functioning as
output co mpare regist er
• When TCNT value is transferred to TG RD by
input capture signal and TGRD is func t ioning as
input capture registe r
[Clearing condition]
• When 0 is written t o TGFD after reading TG FD =
1
2TGFC 0 R/(W)*Input Capture/Output Compare Flag C
Status flag that indicates the occur rence of TGRC
input capture or compare match in channel 0. In
channels 1 and 2, bit 2 is reserved. It is always read
as 0 and cannot be modified.
[Setting condition s]
• When TCNT = TGRC and TGRC is functioning as
output co mpare regist er
• When TCNT value is transferred to TG RC by
input capture signal and TGRC is func t ioning as
input capture registe r
[Clearing condition]
• When 0 is written t o TGFC after reading TG FC =
1
Rev. 1.0, 02/02, page 155 of 502
Bit Bit Name I nitial value R/W Descr i ption
1TGFB 0 R/(W)*Input Capture/Output Compare Flag B
Status flag that indicates the occur rence of TGRB
input capture or compare match.
[Setting condition s]
• When TCNT = TGRB and TGRB is functioning as
output co mpare regist er
• When TCNT value is transferred t o TGRB by
input capture signal and TGRB is functioning as
input capture registe r
[Clearing condition]
• When 0 is written to TGFB aft er reading TGFB =
1
0TGFA 0 R/(W)*Input Capture/Output Compare Flag A
Status flag that indicates the occur rence of TGRA
input capture or compare match.
[Setting condition s]
• When TCNT = TGRA and TGRA is functioning as
output co mpare regist er
• When TCNT value is transferred t o TGRA by
input capture signal and TGRA is functioning as
input capture registe r
[Clearing condition]
• When 0 is written to TGFA aft er reading TGFA =
1
Note: * O nly 0 can be writ ten, for flag clear ing.
8. 3.6 Tim er Counter (TCNT)
The TCNT regi sters are 16-bi t readable/writable c ounters. The T PU has three TCNT counters, one
for each channel.
The TCNT counters are initialized to H'0000 by a reset, and in hardware standby mode.
The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit
unit.
Rev. 1.0, 02/02, page 156 of 502
8.3. 7 Tim er Genera l Regi ster (T GR)
The TGR registers a re dual functi on 16-bit re a dable/writable re gi sters, functioning a s ei t her output
compare or input capture regi sters. The TPU has eight TGR registers, four for channel 0 and two
each for channels 1 and 2. TGRC and TGRD for c hannel 0 can a lso be designated for operation a s
buffer registers. The T GR re gisters cannot be accessed in 8-bit units; they must a lways be
accessed as a 16-bit uni t. TGR buffer register combinations a re TGRA—TGRC and TGRB—
TGRD.
8.3.8 Timer Start Register (TSTR)
TSTR selects operation/stoppage for channels 0 to 2. When setting the operating mode in TMDR
or setting the count clock in TCR, first stop the TCNT counter.
Bit Bit Name I nitial value R/W Description
7 to
3–0–Reserved
Only 0 should be wr itten to these bit s.
2
1
0
CST2
CST1
CST0
0 R/W Counter St art 2 to 0
These bits select operation or stoppage for TCNT.
If 0 is written to the CST bit during operation with the
TIO C pin designated for output, the counter stops but
the TIOC pin output com pare output level is retained.
If TIOR is written to when the CST bit is cleared to 0,
the pin output level will be changed t o the set initial
output value.
0: TCNT_2 to TCNT_0 count operation is stopped
1: TCNT_2 to TCNT_0 performs count operation
Rev. 1.0, 02/02, page 157 of 502
8. 3.9 Tim er Sync hr o Regist er (TSYR)
TSYR selects indepe ndent operation or synchronous operation for the channel 0 t o 2 TCNT
counters. A channel performs synchronous operation whe n the c orresponding bit in T SYR is set t o
1.
Bit Bit Name I nitial value R/W Description
7 to
3–0R/WReserved
Only 0 should be wr itten to these bit s.
2
1
0
SYNC2
SYNC1
SYNC0
0 R/W Timer Synchro 2 to 0
These bits are used t o select whether operation is
independent of or synchronized with other channels.
When synchronous operat ion is selected, the TCNT
synchronous pr esetting of multiple channels, and
synchronous clearing by counter clear ing on anot her
channel, are possible.
To set synchrono us oper ation , the SYNC bi ts for at
least two channel s mus t be set to 1. To set
synchronous clearing, in addition t o the SYNC bit ,
the TCNT clearing sour ce mu st also be set by mean s
of bits CCLR0 to CCLR2 in TCR.
0: TCNT_2 to TCNT_0 operates independently
(TCNT pr esetting /clearing is unrelated to ot her
channels)
1: TCNT_2 to TCNT_0 performs synchronous
operation
TCNT synchronous presetting/synchronous clearing
is possible
Rev. 1.0, 02/02, page 158 of 502
8.4 Operation
8.4.1 Basic Functi ons
Each channel has a TCN T and TGR register . TCNT perfor ms up-co unting, and is also capabl e of
free-running operation, synchronous counting, and external e vent counting.
Each TGR can be used as an input capture register or output com pare regi ster.
Counter Operat io n : W hen one of bits CST0 to CST2 is set to 1 in TSTR, t he TCNT counter for
the corresponding channe l begins counting. TCNT can operate as a free-runni ng counter, pe riodic
counter, for example.
1. Example of count operation setting procedure
Figure 8. 2 shows an example of the count operation se tting proc e dure.
Operation selection
Select counter clock
Periodic counter
Select counter clearing source
Select output compare register
Set period
Free-running counter
Start count operation
<Free-running counter><Periodic counter>
Start count operation
Select the counter
clock with bits
TPSC2 to TPSC0 in
TCR. At the same
time, select the
input clock edge
with bits CKEG1
and CKEG0 in TCR.
For periodic counter
operation, select the
TGR to be used as
the TCNT clearing
source with bits
CCLR2 to CCLR0 in
TCR.
Designate the TGR
selected in [2] as an
output compare
register by means of
TIOR.
Set the periodic
counter cycle in the
TGR selected in [2].
Set the CST bit in
TSTR to 1 to start
the counter
operation.
[1]
[1]
[2]
[2]
[3][3]
[4]
[4]
[5]
[5]
Figure 8.2 Example of Counter Ope r ation Setting Procedure
Rev. 1.0, 02/02, page 159 of 502
2. Free-running count operation and peri odic count ope ration
Immediately after a re set, the TPU’s TCNT count e rs are all designa ted as free-running
counters. When the relevant bit in TSTR is set to 1 t he correspondi ng TCNT counter starts up-
count operation as a free-running counte r. When TCNT ove rfl ows (from H'FFFF to H'0000),
the TCFV bit in TSR is set to 1. If the value of the corresponding TCIEV bit in TIER is 1 at
this point , the TPU requests an interrupt. After overflow, TCNT starts c ounting up again from
H'0000.
Figure 8. 3 illustrates fre e -running counter ope ration.
TCNT value
H'FFFF
H'0000
CST bit
TCFV
Time
Fi g ure 8.3 Fre e - Runni ng Counter Oper a tio n
When compare match is selected as the TCNT cl earing sourc e, the TCNT counte r for the
relevant channel performs periodic count operation. The TGR register for setting the period is
desig nated as an output co mpare reg is ter, and co unter clearin g by compar e match is se lected
by means of b its C CLR0 to C C LR2 in TC R . Af ter the se ttings h ave b e en made, TCNT st ar ts
up-count ope ration as a pe riodic counte r when t he corre sponding bit i n TSTR is set to 1. When
the count value matches the value in TGR, the TGF bit in TSR is set to 1 and TCNT is cleared
to H'0000.
If the value of the corresponding T GIE bi t in T IER is 1 at this point, the TPU requests an
interrupt. After a compare match, TCNT starts coun ting up aga in from H'0000 .
Figure 8. 4 illustrates pe ri odic counter operat ion.
Rev. 1.0, 02/02, page 160 of 502
TCNT value
TGR
H'0000
CST bit
TGF
Time
Counter cleared by TGR
compare match
Flag cleared by software
Figure 8.4 Periodic Cou n t er Opera t ion
Waveform Output by Compare M atch: T he TPU can pe rform 0, 1, or t oggle output from the
correspondin g outpu t pin using comp ar e match .
1. Example of setting procedure for waveform output by compare match
Figure 8. 5 shows an example of the setting procedure for wa veform out put by compare match
Output selection
Select waveform output mode
Set output timing
Start count operation
<Waveform output>
Select initial value 0 output or 1 output, and
compare match output value 0 output, 1 output,
or toggle output, by means of TIOR. The set
initial value is output at the TIOC pin unit the
first compare match occurs.
Set the timing for compare match generation in
TGR.
Set the CST bit in TSTR to 1 to start the count
operation.
[1]
[1] [2]
[2]
[3]
[3]
Figure 8.5 Example of Setting Proc e dure for Wavefor m Output by Compare M atch
Rev. 1.0, 02/02, page 161 of 502
2. Examples of waveform output operation
Figure 8. 6 shows an example of 0 output/1 output.
In this example TCNT has bee n designat ed as a fre e-running counter, and settings ha ve been
made such that 1 is output by compare match A, and 0 is output by compare match B. When
the set level and the pin level coincide, the pin level does not change.
TCNT value
H'FFFF
H'0000
TIOCA
TIOCB
Time
TGRA
TGRB
No change No change
No change No change
1 output
0 output
Figure 8.6 Example of 0 Output/1 O utput Operati on
Figure 8. 7 shows an example of toggle out put.
In this example, TCNT ha s been designa ted as a periodic c ounter (with counte r clearing on
compare match B), and settings have been made such that the output is toggled by both
compare match A and compare match B.
TCNT value
H'FFFF
H'0000
TIOCB
TIOCA
Time
TGRB
TGRA
Toggle output
Toggle output
Counter cleared by TGRB compare match
Figure 8.7 Example of Toggle O utput O peration
Rev. 1.0, 02/02, page 162 of 502
Input Capture Func tio n: The TCNT value can be transferred to TGR on detection of the TIOC
pin input edge.
Rising edge, falling edge, or both edge s can be selected as the detected edge . For channe l s 0 and 1,
it is also possible to specify another channel's counter input clock or compare match signal as the
input capt ure sourc e.
Note: When another channe l's count e r input clock is used as the input capture input for channel
0, ø/1 should not be selected as the counter input clock used for input capture i nput. Input
capture will not be generated if ø/1 is selected.
1. Example of input capture oper at ion setting procedure
Figure 8. 8 shows an example of the input ca pture operation setting proce dure.
Input selection
Select input capture input
Start count
<Input capture operation>
Designate TGR as an input capture register by
means of TIOR, and select rising edge, falling
edge, or both edges as the input capture source
and input signal edge.
Set the CST bit in TSTR to 1 to start the count
operation.
[1]
[2]
[1]
[2]
Fig ure 8.8 Example of Input Captur e Operation Setting Procedur e
Rev. 1.0, 02/02, page 163 of 502
2. Exa mp le of input captu re o p eration
Figure 8.9 shows an example of inpu t captur e oper ation.
In this example both rising and falling e dges ha ve been selected as the TIOCA pi n input
capture input edge, the fa lling edge has been sel ected as the TIOCB pin input capture input
edge, and counter cl earing by T GRB i nput capture ha s been designa ted for T CNT.
TCNT value
H'0180
H'0000
TIOCA
TGRA
H'0010
H'0005
Counter cleared by TIOCB
input (falling edge)
H'0160
H'0005 H'0160 H'0010
TGRB H'0180
TIOCB
Time
Fig ure 8.9 Example of Input Captur e Operation
Rev. 1.0, 02/02, page 164 of 502
8.4.2 Synchronous Ope ration
In sync hronous ope ration, the values i n a number of TCNT counte rs can be rewritten
simultaneously (synchronous presetting). Al so, a num ber of TCNT counters c an be cleared
simultaneously by making the appropriate setting in TCR (synchronous clearing).
Synchronous operation e nables TGR to be i ncremented wi th respect to a single time base.
Channels 0 to 2 c an all be de signated for synchronous operation.
Example of Synchronous O peration Setting Procedure: Figure 8.10 shows an example of the
synchronous operation set ting proce dure.
No
Yes
Synchronous operation
selection
Set synchronous
operation
Synchronous presetting
Set TCNT
<Synchronous presetting> <Counter clearing> <Synchronous clearing>
Synchronous clearing
Clearing
source generation
channel?
Select counter
clearing source
Start count
Set synchronous
counter clearing
Start count
Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous
operation.
When the TCNT counter of any of the channels designated for synchronous operation is
written to, the same value is simultaneously written to the other TCNT counters.
Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare,
etc.
Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing
source.
Set to 1 the CST bits in TSTR for the relevant channels, to start the count operation.
[1]
[2]
[3]
[4]
[5]
[1]
[3]
[4]
[4]
[5]
[2]
Figure 8.10 Example of Synchronous O peration Setting Procedure
Rev. 1.0, 02/02, page 165 of 502
Example of Synchronous O peration: Fi gure 8. 11 shows an example of synchronous operation.
In this example, sync hronous ope ration and PWM mode 1 have been de signated for channels 0 to
2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and
synchronous clearing has been se t for the channel 1 and 2 count er clearing source.
Three-phase PWM wave forms a re output from pi ns TIOC0A, TIOC1A, and TIOC2A. At this
time, sync hronous pre setting, and synchronous clearing by TGRB_0 compare match, are
performed for channel 0 to 2 TCNT counte rs, and the data set in TGRB_0 is used as the PWM
cycle.
For details of PWM modes, see section 8.4.4, PWM Modes.
TCNT0 to TCNT2 values
H'0000
TIOCA0
TIOCA1
TGRB_0
Synchronous clearing by TGRB_0 compare match
TGRA_2
TGRA_1
TGRB_2
TGRA_0
TGRB_1
TIOCA2
Time
Figure 8.11 Example of Synchronous O peration
8.4.3 Buffer Ope ration
Buffer ope ration, provided for channel 0, enables T GRC and TGRD to be used as buffer re gisters.
Buffer ope ration di ffers depending on whethe r TGR has been designat ed as an input capture
register or as a compare match register.
Table 8.17 shows the regi ster combinations use d in buffer operation.
Rev. 1.0, 02/02, page 166 of 502
Table 8.17 Register Combinations i n Buffer Operation
Channel Timer General Register Buffer Register
0 TGRA_0 TGRC_0
TGRB_0 TGRD_0
• When TGR is an ou tput comp are reg is ter
When a compare m atch occurs, the va l ue in t he buffer re gister for t he correspondi ng channel is
trans ferre d to the timer gen eral reg ister.
This operation is illustrated in fi gure 8.12.
Buffer register Timer general
register TCNTComparator
Compare match signal
Figure 8.12 Compare Match Buffer Operation
• When TGR is an inp ut captu re r egister
When input c apture occurs, t he value in T CNT is transferred to T GR and the value previously
held in the timer ge neral re gister is t ransferred to the buffer re gister.
This operation is illustrated in fi gure 8.13.
Buffer register Timer general
register TCNT
Input capture
signal
Fi g ure 8. 13 Input Captur e Buf fer Oper ati on
Example of Buffer Operation Setting P rocedure: Figure 8.14 shows an e xample of the buffer
operation set ting proce dure.
Rev. 1.0, 02/02, page 167 of 502
Buffer operation
Select TGR function
Set buffer operation
Start count
<Buffer operation>
[1]
[2]
[3]
[1]
[2]
[3]
Designate TGR as an input capture register or
output compare register by means of TIOR.
Designate TGR for buffer operation with bits
BFA and BFB in TMDR.
Set the CST bit in TSTR to 1 start the count
operation.
Figure 8.14 Example of Buffer Oper ation Setting Pr ocedure
Examples of Buffer Operation
1. Whe n TG R is an ou tput comp are reg is ter
Figure 8. 15 shows an operation example in which PWM mode 1 has been de signated for
channel 0, and buffer operation has been designated for TGRA and T GRC. The settings used
in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0
output at compare match B.
As buffer operation has been set, when c ompare match A occ urs the output changes and the
value in buffer regi ster TGRC is simultaneously tra nsferred to timer gene ral register T GRA.
This operation is repeated each time that compare match A occurs.
For details of PWM modes, see section 8.4.4, PWM Modes.
TCNT value
TGRB_0
H'0000
TGRC_0
TGRA_0
H'0200 H'0520
TIOCA
H'0200
H'0450 H'0520
H'0450
TGRA_0 H'0450H'0200
Transfer
Time
Figure 8.15 Example of Buffer Operat ion (1)
Rev. 1.0, 02/02, page 168 of 502
2. Whe n TG R is an inp ut cap ture r egister
Figure 8. 16 shows an operation example in which T GRA has been designated as an i nput
capture re gister, and buffer operation ha s bee n designated for TGRA and TGRC.
Counter c learing by TGRA input capture has been set for TCNT, and both rising and falling
edges have bee n selected as t he TIOCA pin i nput capture i nput edge.
As buffer operation has been set, when t he TCNT value is stored in TGRA upon the
occurrence of input capture A, the value previously stored in TGRA is simultaneously
trans ferre d to TG R C.
TCNT value
H'09FB
H'0000
TGRC
Time
H'0532
TIOCA
TGRA H'0F07H'0532
H'0F07
H'0532
H'0F07
H'09FB
Figure 8.16 Example of Buffer Operat ion (2)
Rev. 1.0, 02/02, page 169 of 502
8.4.4 PWM Modes
In PWM mode, PWM waveform s are output from t he output pins. The output le vel ca n be selected
as 0, 1, or toggle out put in re sponse to a com pa re match of each TGR.
TGR regist ers settings can be used to output a PWM wave form in t he range of 0% to 100% duty.
Designating TGR compare match a s the counter cl earing sourc e enables the period t o be set i n that
register. All channels can be designat ed for PWM mode independentl y. Synchronous operation is
also possible.
There are two PWM modes, as described below.
• PWM mode 1
PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and
TGRC with TGRD. The output specified by bits IOA0 to IOA3 and IOC0 to IOC3 in TIOR is
output from the TIOCA a nd T IOCC pins at compare matches A and C, and the output
specified by bits IOB0 to IOB3 and IOD0 to IOD3 in TIOR is output at compare matches B
and D. The initial output value is the value set in TGRA or TGRC. If the set values of paired
TGRs are identical, the output value does not change when a compare match occurs.
In PWM mode 1, a maximum 4-pha se PW M output is possible.
• PWM mode 2
PWM output is generated using one TGR as the cycle register and the others as duty registers.
The output spec i fied in TIOR is performed by means of compare ma tches. Upon counter
clearing by a synchronization register compare match, the output value of each pin is the initial
value set in TIOR. If the set values of the cycle and duty registers are identical, the output
value does not change when a compare match occurs.
In PWM mode 2, a maximum 7-pha se PW M output is possible in combination use with
synchronous operation.
The correspondence be tween PWM output pins and registers is shown in table 8.18.
Rev. 1.0, 02/02, page 170 of 502
Table 8.18 PWM Output Registers and Output Pins
Output Pins
Channel Registers PWM Mode 1 PWM Mode 2
0 TGRA_0 TIOCA0 TIOCA0
TGRB_0 TIOCB0
TGRC_0 TIOCC0 TIOCC0
TGRD_0 TIOCD0
1 TGRA_1 TIOCA1 TIOCA1
TGRB_1 TIOCB1
2 TGRA_2 TIOCA2 TIOCA2
TGRB_2 TIOCB2
Note: In PWM mode 2, PWM output is not possible for the TG R register in which the period is set.
Rev. 1.0, 02/02, page 171 of 502
Example of PWM M ode Setti ng Procedure: Figure 8.17 shows a n exampl e of the PWM m ode
setting procedur e .
PWM mode
Select counter clock
Select counter clearing source
Select waveform output level
Set TGR
Set PWM mode
Start count
<PWM mode>
Select the counter clock with bits TPSC2 to
TPSC0 in TCR. At the same time, select the
input clock edge with bits CKEG1 and CKEG0
in TCR.
Use bits CCLR2 to CCLR0 in TCR to select the
TGR to be used as the TCNT clearing source.
Use TIOR to designate the TGR as an output
compare register, and select the initial value and
output value.
Set the cycle in the TGR selected in [2], and set
the duty in the other the TGR.
Select the PWM mode with bits MD3 to MD0 in
TMDR.
Set the CST bit in TSTR to 1 start the count
operation.
[1]
[2]
[3]
[4]
[5]
[6]
[1]
[2]
[3]
[4]
[5]
[6]
Figure 8.17 Example of P WM Mode Setting Procedure
Examples of PWM Mode Operation: Figure 8.18 shows an exam ple of PWM mode 1 operation.
In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA
init ial output valu e an d ou tp ut valu e, and 1 is set as th e TG R B output va lue.
In this case, the v alue set in TG R A is us ed as th e per iod, an d the v alues set in the TGRB reg isters
are used as the duty levels.
TCNT value
TGRA
H'0000
TIOCA
Time
TGRB
Counter cleared by
TGRA compare match
Figure 8.18 Example of P WM Mode Operati on (1)
Rev. 1.0, 02/02, page 172 of 502
Figure 8. 19 shows an example of PWM mode 2 operation.
In this example, sync hronous ope ration is designated for c hannels 0 a nd 1, TGRB_1 compare
match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the
output va l ue of the other TGR regist ers (TGRA_0 to TGRD_0, TGRA_1), outputting a 5-phase
PWM waveform.
In this ca se, the val ue set in TGRB_1 is used a s the cycle, and t he values set in t he othe r TGRs are
used as th e du ty levels .
TCNT value
TGRB_1
H'0000
TIOCA0
Counter cleared by
TGRB_1 compare match
Time
TGRA_1
TGRD_0
TGRC_0
TGRB_0
TGRA_0
TIOCB0
TIOCC0
TIOCD0
TIOCA1
Figure 8.19 Example of P WM Mode Operati on (2)
Rev. 1.0, 02/02, page 173 of 502
Figure 8. 20 shows exam ples of PWM waveform output with 0% duty and 100% duty in PWM
mode.
TCNT value
TGRA
H'0000
TIOCA
Time
TGRB
0% duty
TGRB rewritten
TGRB
rewritten
TGRB rewritten
TCNT value
TGRA
H'0000
TIOCA
Time
TGRB
100% duty
TGRB rewritten
TGRB rewritten
TGRB rewritten
Output does not change when cycle register and duty register
compare matches occur simultaneously
TCNT value
TGRA
H'0000
TIOCA
Time
TGRB
100% duty
TGRB rewritten
TGRB rewritten
TGRB rewritten
Output does not change when cycle register and duty
register compare matches occur simultaneously
0% duty
Figure 8.20 Example of P WM Mode Operati on (3)
Rev. 1.0, 02/02, page 174 of 502
8. 4.5 Phase Counting Mode
In phase counting mode, the phase difference between two external clock inputs is detected and
TCNT is incremented/decrem e nted accordingly. This mode can be set for channels 1 a nd 2.
When phase counting mode is set, an external clock is selected as the counter input clock and
TCNT operate s as an up/down-counter rega rdless of the setting of bits TPSC0 to TPSC2 and bit s
CKEG0 a nd CKEG1 in TCR. Howeve r, the functions of bits CCLR0 and CCLR1 in TCR, a nd of
TIOR, T IER, and TGR, a re val id, and input capture/compa re match and interrupt func tions can be
used.
This can be used for two-phase encoder pulse input.
If overflow occurs when TCNT is counting up, the TCFV flag in T SR is set; if underflow oc curs
when TCNT is counti ng down, the TCFU flag is set.
The TCFD bit in TSR is the count direction flag. Reading the TCFD flag reveals whether TCNT is
counting up or down.
Table 8.19 shows the corre spondenc e between external cl ock pins and channe ls.
Tabl e 8.1 9 Pha se Counti ng Mode Clock Input Pins
Exter nal Clock Pi ns
Channels A-Phase B-Phase
When channel 1 is set to phase counting mode TCLKA TCLKB
When channel 2 is set to phase counting mode TCLKC TCLKD
Example of Phase Counting Mode Setting Proc edure: Figure 8. 21 shows an example of the
phase counting m ode setting procedure.
Phase counting mode
Select phase counting mode
Start count
<Phase counting mode>
Select phase counting mode with bits MD3 to
MD0 in TMDR.
Set the CST bit in TSTR to 1 to start the count
operation.
[1]
[2]
[1]
[2]
Figure 8.21 Example of P hase Counting Mode Setting P rocedure
Rev. 1.0, 02/02, page 175 of 502
Examples of Phase Counti ng Mode Operation: In phase counting mode, TCNT counts up or
down a ccording to the phase difference betwee n two e xternal cl ocks. The re are four modes,
according to the coun t cond itions.
1. Phase coun ting mode 1
Figure 8. 22 shows an example of pha se c ounting m ode 1 operation, and table 8.20 sum marizes
the TCNT up/down-count conditions.
TCNT value
Time
Down-count
Up-count
TCLKA (channel 1)
TCLKC (channel 2)
TCLKB (channel 1)
TCLKD (channel 2)
Figure 8.22 Example of P hase Counting Mode 1 Operation
Tabl e 8.2 0 Up/Do wn- Count Co ndi t ions i n Phase Count i ng Mode 1
TCLKA (Channel 1)
TCLKC (Channel 2) TCLKB (Channel 1)
TCLKD (Channel 2) Operation
High lev e l Up-count
Low level Low level
High lev e l
High lev e l Down- c o u nt
Low level High leve l
Low level
Legend
: Rising edge
: Falling edge
Rev. 1.0, 02/02, page 176 of 502
2. Phase coun ting mode 2
Figure 8. 23 shows an example of pha se c ounting m ode 2 operation, and table 8.21 sum marizes
the TCNT up/down-count conditions.
Time
Down-countUp-count
TCNT value
TCLKA (channel 1)
TCLKC (channel 2)
TCLKB (channel 1)
TCLKD (channel 2)
Figure 8.23 Example of P hase Counting Mode 2 Operation
Tabl e 8.2 1 Up/Do wn- Count Co ndi t ions i n Phase Count i ng Mode 2
TCLKA (Channel 1)
TCLKC (Channel 2) TCLKB (Channel 1)
TCLKD (Channel 2) Operation
High lev e l Don’t care
Low level Don’t care
Low level Don’t car e
High level Up-count
High lev e l Don’t care
Low level Don’t care
High level Don’t care
Low level Down-count
Legend
: Rising edge
: Falling edge
Rev. 1.0, 02/02, page 177 of 502
3. Phase coun ting mode 3
Figure 8. 24 shows an example of pha se c ounting m ode 3 operation, and table 8.22 sum marizes
the TCNT up/down-count conditions.
Time
Up-count Down-count
TCNT value
TCLKA (channel 1)
TCLKC (channel 2)
TCLKB (channel 1)
TCLKD (channel 2)
Figure 8.24 Example of P hase Counting Mode 3 Operation
Tabl e 8.2 2 Up/Do wn- Count Co ndi t ions i n Phase Count i ng Mode 3
TCLKA (Channel 1)
TCLKC (Channel 2) TCLKB (Channel 1)
TCLKD (Channel 2) Operation
High lev e l Don’t care
Low level Don’t care
Low level Don’t car e
High level Up-count
High lev e l Down- c o u nt
Low level Don’t care
High level Don’t care
Low level Don’t car e
Legend
: Rising edge
: Falling edge
Rev. 1.0, 02/02, page 178 of 502
4. Phase coun ting mode 4
Figure 8. 25 shows an example of pha se c ounting m ode 4 operation, and table 8.23 sum marizes
the TCNT up/down-count conditions.
Time
Up-count Down-count
TCNT value
TCLKA (channel 1)
TCLKC (channel 2)
TCLKB (channel 1)
TCLKD (channel 2)
Figure 8.25 Example of P hase Counting Mode 4 Operation
Tabl e 8.2 3 Up/Do wn- Count Co ndi t ions i n Phase Count i ng Mode 4
TCLKA (Channel 1)
TCLKC (Channel 2) TCLKB (Channel 1)
TCLKD (Channel 2) Operation
High lev e l Up-count
Low level
Low level Don’t car e
High lev e l
High lev e l Down- c o u nt
Low level
High level Don’t care
Low level
Legend
: Rising edge
: Falling edge
Rev. 1.0, 02/02, page 179 of 502
Phase Counting Mode Applic a tion Example: Figure 8.26 shows a n exam ple in which channel 1
is in phase counting mode , and c hannel 1 is coupled with c ha nnel 0 to input servo motor 2-phase
encoder pulses in order to detect position or speed.
Channel 1 is set to phase counting mode 1, and the encode r pulse A-phase and B-phase are input
to TCLK A and TCLKB.
Channel 0 operates with TCNT counter clearing by TGRC_0 compare match; TGRA_0 and
TGRC_0 are used for the com pare match function and are set with the spee d control pe ri od and
position control period . TGRB_0 is used for inpu t captur e, with TGRB _0 and TGRD_ 0 oper at ing
in buffer mode. The channel 1 counter input clock i s designated as the TGRB_0 input capture
source, and the pulse wi dths of 2-phase encoder 4-m ultiplication pulses are detecte d.
TGRA_1 a nd TGRB_1 for channel 1 are de signated for input capture, and cha nnel 0 TGRA_0 and
TGRC_0 compare matches are selected as the input capture source and store the up/down-counter
values for the control periods.
This procedure e nables t he accurat e detection of position and speed.
Rev. 1.0, 02/02, page 180 of 502
TCNT_1
TCNT_0
Channel 1
TGRA_1
(speed period capture)
TGRA_0
(speed control period)
TGRB_1
(speed period capture)
TGRC_0
(position control period)
TGRB_0 (pulse width capture)
TGRD_0 (buffer operation)
Channel 0
TCLKA
TCLKB
Edge
detection
circuit
+
-
+
-
Figure 8.26 Phase Counting Mode Application Example
Rev. 1.0, 02/02, page 181 of 502
8.5 Interrupts
There are three kinds of TPU interrupt source; TGR inpu t capture/comp ar e match, TCN T
overflow, and TCNT underfl ow. Each interrupt source has it s own status fl a g and enable/disabled
bit, allowing the generation of interrupt request signals to be enabled or di sabled i ndividual l y.
When an interrupt re quest is generated, the c orresponding status fl ag in T SR is set to 1. If the
correspondin g ena bl e/d isable bit in TIER is set to 1 at this time, an interrupt is request ed. The
interrupt re quest is cleared by clearing the status flag to 0.
Relative cha nnel priorities can be changed by the i nterrupt c ontroller, however the priori t y orde r
within a channel is fi xed. For details, see section 5, Int e rrupt Controller.
Table 8.24 lists the TPU interrupt sources.
Table 8.24 TPU Interrupts
Channel Name Interrupt Source Interrupt Flag
0 TGI0A TGRA_0 input capt ure/compare match TG FA0
TGI0B TGRB_0 input capt ure/compare match TG FB0
TGI0C TG RC_0 input capture/com pare match TGFC0
TGI0D TG RD_0 input capture/com pare match TGFD0
TCI0V TCNT_0 overflow TCFV0
1 TGI1A TGRA_1 input capt ure/compare match TG FA1
TGI1B TGRB_1 input capt ure/compare match TG FB1
TCI1V TCNT_1 overflow TCFV1
TCI1U TCNT_1 underflow TCFU1
2 TGI2A TGRA_2 input capt ure/compare match TG FA2
TGI2B TGRB_2 input capt ure/compare match TG FB2
TCI2V TCNT_2 overflow TCFV2
TCI2U TCNT_2 underflow TCFU2
Note: This table shows the initial state immediately aft er a reset. The relative channel priorities
can be changed by the int errupt controller.
Rev. 1.0, 02/02, page 182 of 502
Input Capture/Co mpare Match Int errupt: An interrupt is requested if the TGIE bit in TIER is
set to 1 when the TGF fla g in TSR is set to 1 by the occ urrence of a TGR input capture/compare
match on a particul ar channel. The interrupt re quest is cleared by cle aring t he TGF flag to 0. The
TPU ha s eight i nput capture/compa re match interrupts, four for channe l 0, and two each for
channels 1 and 2.
Over f l o w Interr upt: An interrupt is requested if the TCIEV bit in TIER is set to 1 when the
TCFV flag in TSR is set t o 1 by the oc c urrence of TCNT ove rflow on a channel. The interrupt
request is cleared b y clearin g the TCFV f lag to 0 . The TPU h as th r ee over flo w interrupts, on e for
each ch annel.
Under f l o w Interr upt: An interrupt i s reque sted if t he TCIEU bit in TIER i s set to 1 when the
TCFU flag in TSR is set t o 1 by the oc c urrence of TCNT underflow on a channe l. The interrupt
request is cleared b y clearin g the TCFU f lag to 0 . The TPU h as two u nd erflow in ter rupts, on e
each for channels 1 and 2.
8.6 A/D Convert er Act ivat i on
The A/D c onverter can be activated by the T GRA input capture/ c ompare match for a channe l.
If the TTGE bit in TIER is set to 1 when t he TGFA flag in TSR is set t o 1 by the occ urrence of a
TGRA input capture/compare match on a particular channel, a request to begin A/D conversion is
sent to the A/D converter. If the TPU conversion start trigger has been selected on the A/D
converter side at this time, A/D conversion is begun.
In the TPU, a total of three TGRA input ca pture/compa re match i nterrupts can be used as A/D
converter conversion sta rt sourc e s, one for each channe l.
Rev. 1.0, 02/02, page 183 of 502
8.7 Operation Timing
8. 7.1 Input/Output Timing
TCNT Count Timing : Figure 8.27 shows TCNT count timing in internal clock operation, and
figure 8.28 shows TCNT count timing i n external c lock operation.
TCNT
TCNT
input clock
Internal clock
φ
N-1 N N+1 N+2
Falling edge Rising edge
Figure 8.27 Count Timing in Internal Clock Operation
TCNT
TCNT
input clock
External clock
φ
N-1 N N+1 N+2
Falling edge Rising edge Falling edge
Figure 8.28 Count Timing in External Clock Operation
Rev. 1.0, 02/02, page 184 of 502
Output Co mpare Output Timing: A compare match signal is generated in the final state in
which TCNT and TGR match (the point at which the count value matched by TCNT is updated).
When a compare match signal is generated, the output value set in TIOR is output at the output
compare output pin. After a match between TCNT and TGR, the compare match signal is not
generated until the TCNT input clock is generated.
Figure 8. 29 shows output c om pare out put timing.
TGR
TCNT
TCNT
input clock
N
N N+1
Compare
match signal
TIOC pin
φ
Figure 8.29 Output Compare Output Timing
Input Capture Sig nal Timing: Figure 8.30 shows input capture signal timi ng.
TCNT
Input capture
input
N N+1 N+2
NN+2
TGR
Input capture
signal
φ
Fi g ure 8. 30 Input Captur e Input Si g nal Timing
Rev. 1.0, 02/02, page 185 of 502
Tim i ng for Counte r Cleari ng by Compare Matc h/Input Ca pture : Figure 8.31 shows t he
timing when counter clearing on compare match is specified, and figure 8.32 shows the timing
when co unter clearin g o n inp ut captu re is sp ecified .
TCNT
Counter
clear signal
Compare
match signal
TGR N
N H'0000
φ
Fi g ure 8. 31 Co unter Clear Timi ng (Com pare Match)
TCNT
Counter clear
signal
Input capture
signal
TGR
N H'0000
N
φ
Fi g ure 8. 32 Co unter Clear Timi ng (Input Ca pt ure)
Rev. 1.0, 02/02, page 186 of 502
Buffer Ope ration Timing: Figures 8.33 and 8.3 4 show the timing in buffe r oper ation.
TGRA,
TGRB
Compare
match signal
TCNT
TGRC,
TGRD
nN
N
n n+1
φ
Figure 8.33 Buffer O peration Timing (Compare Matc h)
TGRA,
TGRB
TCNT
Input capture
signal
TGRC,
TGRD
N
n
n N+1
N
N N+1
φ
Fi g ure 8.34 Buf f er Opera tio n Tim i ng (Input Ca pt ure )
Rev. 1.0, 02/02, page 187 of 502
8. 7.2 Interr upt Signal Tim i ng
TGF Flag Setting Timing in Case of Compare M atch: Figure 8. 35 shows the timing for setting
of the TGF flag in TSR on comp are match, and TG I in ter rupt request sig n al timing.
TGR
TCNT
TCNT input
clock
N
N N+1
Compare
match signal
TGF flag
TGI interrupt
φ
Fi g ure 8.35 TG I Inte rr upt Ti ming (Compa re Match)
TGF Fla g Set ting Timing in Case of Input Capt ure : Figure 8. 36 shows the t iming for setting of
the TGF flag in TSR on input capture, and TGI i nterrupt request signal t iming.
TGR
TCNT
Input capture
signal
N
N
TGF flag
TGI interrupt
φ
Fi g ure 8. 36 T G I Interr upt Timing ( Input Ca pt ure)
Rev. 1.0, 02/02, page 188 of 502
TCFV Flag/T CFU Fla g Setting Tim in g : Figure 8.37 shows the timing for setting of the TCFV
flag in TSR on ove rflow, and TCIV interrupt request signal timing.
Figure 8. 38 shows the t iming for se tting of the T CFU fla g in TSR on underflow, and TCIU
interrupt re quest si gnal timing.
Overflow
signal
TCNT
(overflow)
TCNT input
clock
H'FFFF H'0000
TCFV flag
TCIV interrupt
φ
Fi g ure 8. 37 T CIV Inter r upt Set ting Tim i ng
Underflow
signal
TCNT
(underflow)
TCNT
input clock
H'0000 H'FFFF
TCFU flag
TCIU interrupt
φ
Fi g ure 8. 38 T CIU Inter r upt Set ting Tim i ng
Rev. 1.0, 02/02, page 189 of 502
Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing
0 to it . Figure 8.39 shows the timing for st a tus flag clearing by the CPU.
Status flag
Write signal
Address TSR address
Interrupt
request
signal
TSR write cycle
T1 T2
φ
Figure 8.39 Timing for Status Flag Clearing by CPU
Rev. 1.0, 02/02, page 190 of 502
8.8 Usage Notes
8.8.1 Module Stop Mode Setti ng
TPU ope ration can be disabl e d or e nabled using the module stop control re gi ster. T he initial
setting is for TPU operation to be halted. Register access is enabled by clearing module stop
mode. For deta ils, refer t o sec tion 19, Power-Down Modes.
8. 8.2 Input Clo c k Restri ctions
The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at
least 2.5 states in the case of both-edge detection. The TPU will not operate properly at narrower
pulse widt hs.
In phase c ounting mode, the phase diffe rence and overl ap betwe e n the two i nput clocks must be at
least 1.5 states, and the pulse width must be at least 2.5 states. Figure 8.40 shows the input clock
conditions in phase counting mode.
Overlap
Phase
differ-
ence
Phase
differ-
ence
Overlap
TCLKA
(TCLKC)
TCLKB
(TCLKD)
Pulse width Pulse width
Pulse width Pulse width
Notes: Phase difference and overlap
Pulse width : 1.5 states or more
: 2.5 states or more
Figure 8.4 0 Phase Diff erenc e, Ov erlap , a n d Pulse Widt h in Phase Cou nting Mod e
Rev. 1.0, 02/02, page 191 of 502
8.8.3 Caution on Period Setti ng
When counter clearing on compare match is set, TCNT is cleared in the final state in which it
matches the TGR value (t he point at which the count va lue matched by TCNT is updat ed).
Consequentl y, the ac tual counter frequenc y is given by the following formula:
f = ø
(N + 1)
Where f : Counter frequency
ø : Operating frequency
N : TGR set value
8.8.4 Contention between TCN T Write and Clear Oper ations
If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing
takes precedence and the TCNT write i s not performe d.
Figure 8. 41 shows the t iming in thi s case.
Counter clear
signal
Write signal
Address
ø
TCNT address
TCNT
TCNT write cycle
T1 T2
N H'0000
Figure 8.41 Contention between TCNT Write and Clear Operations
Rev. 1.0, 02/02, page 192 of 502
8. 8.5 Conte nt i o n betwee n TCNT Write and Increme nt Oper a tions
If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence
and TCNT is not incremented.
Figure 8. 42 shows the t iming in thi s case.
TCNT input
clock
Write signal
Address
ø
TCNT address
TCNT
TCNT write cycle
T1 T2
N M
TCNT write data
Figure 8.42 Contention betwee n TCNT Write and Increment O perations
Rev. 1.0, 02/02, page 193 of 502
8.8.6 Contention between TGR Write and Compare Match
If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence
and the compare match signal is inhibited. A compare match does not occur even if the previous
value is written.
Figure 8. 43 shows the t iming in thi s case.
Compare
match signal
Write signal
Address
ø
TGR address
TCNT
TGR write cycle
T1 T2
N M
TGR write data
TGR
N N+1
Inhibited
Figure 8.43 Contention betwee n TG R Write and Compare Matc h
Rev. 1.0, 02/02, page 194 of 502
8.8.7 Contention between Buffer Registe r Write and Compare Match
If a compare match occurs in the T2 state of a TGR write cycle, the data that is transferred to TGR
by the buffer operation will be that in the buffer prior to the write.
Figure 8. 44 shows the t iming in thi s case.
Compare
match signal
Write signal
Address
ø
Buffer register
address
Buffer
register
TGR write cycle
T1 T2
N
TGR
N M
Buffer register write data
Figure 8.44 Contention betwee n Buffer Register Write and Compare Match
Rev. 1.0, 02/02, page 195 of 502
8. 8.8 Conte nt i o n betwee n TGR Read and Input Capture
If an i nput capture signa l is generated in the T1 state of a TGR rea d cycle, the da ta that i s read will
be that in th e buffer aft er inpu t captur e transf er .
Figure 8. 45 shows the t iming in thi s case.
Input capture
signal
Read signal
Address
ø
TGR address
TGR
TGR read cycle
T1 T2
M
Internal
data bus
X M
Fi g ure 8. 45 Co ntention be t wee n TGR Read and Input Capture
Rev. 1.0, 02/02, page 196 of 502
8. 8.9 Conte nt i o n betwee n TGR Wri te a nd Input Captur e
If an i nput capture signa l is generated in the T2 state of a TGR write cycle, the input capture
operation t akes precedence and t he write to TGR i s not performed.
Figure 8. 46 shows the t iming in thi s case.
Input capture
signal
Write signal
Address
ø
TCNT
TGR write cycle
T1 T2
M
TGR
M
TGR address
Fi g ure 8. 46 Co ntention be t wee n TGR Wri te and Input Capt ure
Rev. 1.0, 02/02, page 197 of 502
8. 8.1 0 Co nt e nt i o n between Buffer Register Write a nd Input Capture
If an i nput capture signa l is generated in the T2 state of a buffer re gister write cycle, the buffer
operation t akes precedence and t he write to the buffer register is not pe rformed.
Figure 8. 47 shows the t iming in thi s case.
Input capture
signal
Write signal
Address
ø
TCNT
Buffer register write cycle
T1 T2
N
TGR
N
M
M
Buffer
register
Buffer register
address
Fi g ure 8. 47 Co ntention be t wee n Buffer Register Write and Input Ca pture
Rev. 1.0, 02/02, page 198 of 502
8. 8.1 1 Co nt e nt i o n between Over flo w/ Under f low and Counte r Cl eari ng
If ov er flow/un derf lo w an d co u nter clearing oc cu r si mu ltaneo usly, th e TC F V /TCFU f la g in TS R is
not set and TCNT clearing takes precedence.
Figure 8. 48 shows the operation ti ming when a TGR compare match i s specified as the clearing
source, and when H'FFFF i s set in TGR.
Counter
clear signal
TCNT input
clock
ø
TCNT
TGF
Disabled
TCFV
H'FFFF H'0000
Fi g ure 8. 48 Co ntention be t wee n Overflo w and Counter Cleari ng
Rev. 1.0, 02/02, page 199 of 502
8.8.12 Contention between TCNT Write and Overflow/Underflow
If there is an up-count or down-count in the T2 state of a TCNT write cycle, and
overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is
not set.
Figure 8. 49 shows the operation ti ming when there is conte nt ion bet ween TCNT write and
overflow.
Write signal
Address
ø
TCNT address
TCNT
TCNT write cycle
T1 T2
H'FFFF M
TCNT write data
TCFV flag
Figure 8.49 Contention between TCNT Write and Overflow
8.8.13 Multiplexing of I/O Pins
In this LSI, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the TCLKB input pin
with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and the TCLKD input
pin with t he TIOCB2 I/O pi n. Whe n an ext ernal clock is input, com pare match output should not
be performed from a m ultiplexed pin.
8.8.14 Interrupts in Module Stop Mode
If module stop mode is entered when a n interrupt has been reque ste d, it will not be possible to
clear the CPU interrupt source. Inte rrupts shoul d therefore be disabled before ente ri ng m odule
stop mode.
8.8.15 Interrupts in Subactive Mode/Watch Mode
If subactive m ode/watch mode is ent ered when an interrupt ha s been reque sted, it will not be
possible to clear the CPU inte rrupt sourc e. Interrupts should therefore be disabled before entering
sub active mo de/w atch mod e.
Rev. 1.0, 02/02, page 200 of 502
Rev. 1.0, 02/02, page 201 of 502
Section 9 Watchdog Timer
The watchdog timer (WDT_0, WDT_1) is an 8-bit timer that can generate an internal reset signal
for this LSI if a system cra sh prevents the CPU from writing t o the time r counter, thus allowing i t
to overflow.
When this watchdog function is not needed, the WDT can be used as an interval timer. In interval
timer operation, an interval timer interrupt is generated each time the counter overflows.
The block diagram of the WDT_0 is shown in figure 9.1. The block diagram of the WDT_1 is
shown in figure 9.2.
9.1 Features
• Selectable from eight counter input clocks.
• Sw itchable be tw ee n w atchdog timer mode and inte rva l timer mode
In watchdog timer mode
• If the counter overflows, it is possible to select whether this LSI is internally reset or the WDT
generates a n internal NMI interrupt.
In interval timer mode
• If the counter overflows, the WDT generates an interval timer interrupt (WOVI).
WDT0105A_000120020200
Rev. 1.0, 02/02, page 202 of 502
Overflow
Interrupt
control
WOVI
(interrupt request
signal)
Internal reset signal*Reset
control
RSTCSR TCNT TCSR
ø/2
ø/64
ø/128
ø/512
ø/2048
ø/8192
ø/32768
ø/131072
Clock Clock
select
Internal clock
sources
Bus
interface
Module bus
TCSR
TCNT
RSTCSR
Note: * An internal reset signal can be generated by setting the register.
: Timer control/status register
: Timer counter
: Reset control/status register
WDT
Legend
Internal bus
F igu r e 9.1 Bl ock D iagr am of WDT_0
Overflow
Interrupt
control
WOVI
(interrupt request
signal)
Internal NMI
Internal reset signal
Internal reset signal*
Reset
control
TCNT TSCR
ø/2
ø/64
ø/128
ø/512
ø/2048
ø/8192
ø/32768
ø/131072
øSUB/2
øSUB/4
øSUB/8
øSUB/16
øSUB/32
øSUB/64
øSUB/128
øSUB/256
Clock Clock
select
Internal clock
Bus
interface
Module bus
TCSR
TCNT
Note: * An internal reset signal can be generated by setting the register.
The generated reset is a power-on reset.
: Timer control/status register
: Timer counter
WDT
Legend
Internal bus
F igu r e 9.2 Bl ock D iagr am of WDT_1
Rev. 1.0, 02/02, page 203 of 502
9.2 Register Descri pt i on s
The WDT has the following three registers. To prevent accidental overwriting, TCSR, TCNT, and
RSTCSR ha ve to be written to by a different method to normal registers. For details, refer t o
section 9.5.1, Notes on Register Access.
• Timer control/status register (TCSR)
• Timer counter (TCNT)
• Reset control/status register (RSTCSR)
9.2.1 Timer Counter 0 and 1 (TCNT_0 and TCNT_1)
TCNT is an 8-bit readable/writable up-counter. TCNT is initialized to H'00 by a reset, when the
TME bit in TCSR is cleared to 0.
9.2.2 Ti mer Control/Status Register 0 and 1 (TCSR_0 and TCSR_1)
TCSR selects the clock source to be input to TCNT, and selecting the timer mode.
• TCSR_0
Bit Bit Name Initial Value R/W Descri ption
7OVF 0 R/(W)
*Overflow Flag
Indicates that TCNT has overflowed. Only a write
of 0 is permitted, to clear the flag.
[Setting condition]
When TCNT overflows (changes from H'FF t o
H'00)
When internal reset request generat ion is select ed
in watchdog timer mode, OVF is cleared
automatically by the internal reset.
[Clearing condition]
Cleared by reading TCSR when OVF = 1, then
writing 0 to OVF
6WT/
,7
0 R/W Timer Mode Select
Selects whether the WDT is used as a watchdog
timer or interval timer.
0: In terval time r mode
1: Watchdog timer mod e
Rev. 1.0, 02/02, page 204 of 502
Bit Bit Name Initial Value R/W Descri ption
5 TME 0 R/W Timer Enable
When this bit is set to 1, TCNT starts counting.
When this bit is cleared, TCNT st ops counting and
is initializ ed to H'00.
4
3—
—1
1—
—Reserved
These bits are always read as 1 and cannot be
modified.
2
1
0
CKS2
CKS1
CKS0
0
0
0
R/W
R/W
R/W
Clock Se le ct 0 to 2
Selects the clock source to be input to TCNT. The
overflow f r equency for ø = 20 M Hz is enclosed in
parentheses.
000: Clock ø/2 (frequency: 25.6 µs)
001: Clock ø/64 (frequen cy: 819.2 µs)
010: Clock ø/128 (frequency: 1.6 ms)
011: Clock ø/512 (frequency: 6.6 ms)
100: Clock ø/2048 (frequ ency : 26.2 ms )
101: Clock ø/8192 (frequ ency : 104.9 ms )
110: Clock ø/32768 ( frequency : 419.4 ms)
111: Clock ø/131072 (fr equency: 1.68 s)
Note: *O nly 0 can be written, for flag clearing.
• TCSR_1
Bit Bit Name Initial Value R/W Descri ption
7OVF 0 R/(W)*Overflow Flag
Indicates that TCNT has overflowed from H’FF to
H’00. Only a write of 0 is permitted, to clear the
flag.
[Setting condition]
When TCNT overflows (changes from H'FF t o
H'00)
When internal reset request generat ion is select ed
in watchdog timer mode, OVF is cleared
automatically by the internal reset.
[Clearing condition]
Cleared by reading TCSR when OVF = 1, then
writing 0 to OVF
Rev. 1.0, 02/02, page 205 of 502
Bit Bit Name Initial Value R/W Descri ption
6WT/
,7
0 R/W Timer Mode Select
Selects whether the WDT is used as a watchdog
timer or interval timer.
0: In terval time r mode
1: Watchdog timer mod e
5 TME 0 R/W Timer Enable
When this bit is set to 1, TCNT starts counting.
When this bit is cleared, TCNT st ops counting and
is initializ ed to H'00.
4 PSS 0 R/W Pr es c a ler Sele ct
Selects the clock source to be input to TCNT.
0: Counts the divided clock of φ–based prescaler
(PSM)
1: Counts the divided clock of φSUB–based
prescaler (PSS)
3 RST/NMI 0 R/W Reset or NMI
Selects whether an internal reset request or an
NMI interrupt request when the TCNT overflows
during the watchdog timer mode.
0: NMI interrupt request
1: In ternal reset reques t
2
1
0
CKS2
CKS1
CKS0
0
0
0
R/W
R/W
R/W
Clock Se le ct 2 to 0
Selects the clock source to be input to TCNT. The
overflow cycle for ø = 20 MHz (5-MHz input to this
LSI multiplied by four, and øSUB = 3 9.1 kHz) is
enclosed in parentheses. The overflow cycle is the
period from which TCNT starts counting and unt il
it overflows.
When PSS = 0:
000: ø/2 (cycle: 25.6 µs)
001: ø/6 4 (cycle : 819.2 ms )
010: ø/128 ( cycle: 1.6 ms)
011: ø/512 ( cycle: 6.6 ms)
100: ø/2048 ( cycle: 26. 2 ms)
101: ø/8192 (cycle: 104. 9 ms)
110: ø/32768 (cycle: 419. 4 ms)
111: ø/131072 (cycle: 1.68s)
When PSS = 1:
000: øSUB/2 (cycle: 13.1 ms)
Rev. 1.0, 02/02, page 206 of 502
Bit Bit Name Initial Value R/W Descri ption
001: øSUB/4 (cycle: 26.2 ms)
010: øSUB/8 (cycle: 52.4 ms)
011: øSUB/16 ( cycle: 104.9 ms)
100: øSUB/32 ( cycle: 209.7 ms)
101: øSUB/64 ( cycle: 419.4 ms)
110: øSUB/128 (cycle: 838 .9 ms)
111: øSUB/256 (cycl e: 1.6777 s)
Note: *O nly a 0 can be written, for flag clearing.
Rev. 1.0, 02/02, page 207 of 502
9. 2.3 Rese t Contr ol/ St a tus Register (RSTCSR)
RSTCSR controls the generation of the internal reset signal when TCNT overflows, and selects
the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the
5(6
pi n,
and not by the WDT internal reset signal c aused by overfl ows.
Bit Bit Name Initial Value R/W Descri ption
7WOVF 0 R/(W)
*Watchdog Ove rflow Flag
This bit is set when TCNT overflows in wat chdog
timer mode. This bit cannot be set in interval timer
mode, and only 0 can be wr itten.
[Setting condition]
Set when TCNT overflows (c hanged from H'FF to
H'00) in watchdog timer mode
[Clearing condition]
Cleared by reading RSTCSR when WOVF = 1,
and then wr iting 0 t o WOVF
6 RSTE 0 R/W Reset Enable
Specifies whether or not a r eset signal is
generated in the chip if TCNT overflows during
watchdog timer oper ation .
0: Reset signal is not generated even if TCNT
overflows
(Though t his LSI is not reset, TCNT and TCSR in
W DT are reset)
1: Reset signal is generated if TCNT overflows
5 RSTS 0 R/ W Reset Select
Selects the inter nal reset t y pe to be generated if
TCNT over f lows dur ing watchdog timer operation.
0: Power- on reset
1: Setting prohibited
4 to
0— 1 — Reserved
These bits are always read as 1 and cannot be
modified.
Note: *O nly 0 can be written, for flag clearing.
Rev. 1.0, 02/02, page 208 of 502
9.3 Operation
9.3.1 Watchdog Timer Mode
To use the WDT as a watchdog timer, set the WT/
,7
bit in TC S R a n d th e T ME bi t to 1.
When the WDT is used as a watchdog timer, and if TCNT overflows without be ing rewrit ten
beca u se of a system mal f uncti o n or other error, a WDTOVF sign al is output.
TCNT does not overflow while the system is operating normally. Software must prevent TCNT
overflows by rewriting t he TCNT va lue (norm ally be writing H'00) before overflows occurs.
In watchdog t imer mode, the W DT can internally reset this L SI with a WDTOVF signal.
When the RSTE bit of the RSTCSR is set to 1, and if the TCNT overflows, an internal reset signal
for this LSI is i ssue d at the same time as a WDTOVF signal. In th is case, select power-on reset by
setting the RSTS bit of the RSTCSR to 0.
If a reset caused by a signa l input to the
5(6
pin occurs at the same time as a reset caused by a
WDT overfl ow, the
5(6
pin reset ha s priorit y and the WOVF bit in RSTCSR i s clea re d to 0.
The W DTOVF signal is outp ut for 132 state s when the RSTE bit = 1 of RSTC SR, and for 130
states when the RSTE bit = 0.
Wh en the TCNT ov erf l o ws in watch dog tim e r mode, t he WOVF bit of the RSTC SR is set to 1.
If the RSTE bit of the RSTCSR has been set to 1, an internal reset signal for the entire LSI is
generated at T CNT overflow.
Rev. 1.0, 02/02, page 209 of 502
TCNT value
H'00 Time
H'FF
WT/ = 1
TME = 1 Write H'00
to TCNT WT/ = 1
TME = 1 Write H'00
to TCNT
518 states
Internal reset signal*
WT/
TME
Notes: 1.
2. After the WOVF bit becomes 1, it is cleared to 0 by an internal reset.
The internal reset signal is generated only if the RSTE bit is set to 1.
Overflow
Internal reset is
generated
WOVF = 1*
: Timer mode select bit
: Timer enable bit
Legend
2
1
Figure 9.3 (a) WDT_0 Operation in Watchdog Timer Mode
TCNT value
H'00 Time
H'FF
WT/IT = 1
TME = 1 Write H'00
to TCNT WT/IT = 1
TME = 1 Write H'00
to TCNT
515/516 states
WT/IT
TME
Legend
Overflow
Internal reset
is generated
WOVF = 1*
: Timer mode select bit
: Timer enable bit
1
Internal reset signal*
2
Notes: 1.
2. After the WOVF bit becomes 1, it is cleared to 0 by an internal reset.
The internal reset signal is generated only if the RSTE bit is set to 1.
Figure 9.3 (b) WDT_1 O peration in Watchdog Timer M ode
Rev. 1.0, 02/02, page 210 of 502
9.3.2 I n terval Timer Mode
When the WDT is used as an interval timer, an interval timer interrupt (WOVI) is generated each
time the TCNT overflows. Therefore, a n interrupt ca n be gene rated at intervals.
When the TCNT overflows in interval timer mode, an interval timer interrupt (WOVI) is requested
at the time the OVF bit of the TCSR is set to 1.
TCNT value
H'00 Time
H'FF
WT/ =0
TME=1 WOVI
Overflow Overflow Overflow Overflow
Legend
WOVI: Interval timer interrupt request generation
WOVI WOVI WOVI
Figure 9.4 Operation in Interval Ti mer Mode
Rev. 1.0, 02/02, page 211 of 502
9.4 Interrupts
During inte rval timer mode operation, an overfl ow generates an i nterval timer i nterrupt (W OVI).
The inte rval timer interrupt is re quested whenever the OVF flag is set t o 1 in T C SR. OVF must be
cleared to 0 in the interrupt hand ling routine.
If an NMI interrupt request ha s been chosen in watchdog timer m ode, an NMI interrupt reque st i s
generated when the T CNT overflows.
Tabl e 9.1 WDT Inter r upt Source
Name Interrupt Source Interrupt Flag
WOVI TCNT overflow (interval timer mode) OVF
NMI TCNT overf low (wat chdog timer mode) O VF
9.5 Usage Notes
9. 5.1 Note s o n Register Access
The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being
more difficult t o write t o. The procedures for writing to and reading these registers a re give n
below.
Wr i ting to TCNT, TCSR, a nd RST CSR
These registers m ust be written to by a word transfer instruc t ion. They cannot be written to by a
byte tran s f er instructio n.
TCNT and TCSR both have the same write address. Therefore, the relative condi tion shown in
figure 9.5 needs to be satisfied in order to write to TCNT or TCSR. The transfer instruction writes
the lower byte data to TCNT or TCSR according to the satisfied condition.
To write to RSTCSR, execute a word transfer instruction for address H'FF76. A byte transfer
instruction cannot write to RST CSR.
Th e met hod of writin g 0 to the WOVF bit diffe r s from that o f writing to the R STE and RSTS bit s.
To wri te 0 to the WOVF bit , sat i sf y the conditi o n shown in figure 9.5 . If sati sfie d , the tran sf e r
instruct ion clea r s the WOVF bit to 0, but has no effect on the R STE and RSTS bits. To write to
the RSTE and RSTS bits, satisfy the condition shown in figure 9.5. If satisfied, the transfer
instruction writes the values in bits 5 and 6 of the lower byte into the RSTE and RSTS bits,
respectively, but has no effect on the WOVF bit.
Rev. 1.0, 02/02, page 212 of 502
TCNT write
Writing to RSTE and RSTS bits
TCSR write
Writing 0 to WOVF bit
Address:
Address:
15 8 7 0
H'5A
H'FF74
H'FF76 Write data
15 8 7 0
H'5A
H'FF74
H'FF76 Write data or H'00
Fig ure 9.5 Writing to TCNT, TCSR, and RSTCSR (example for WDT0)
Rea di ng TCNT, TCSR, a nd RST CSR (WDT0)
These registers are read in the same way as other registers. The read addresses are H'FF74 for
TC SR, H'FF75 for TCNT, and H'FF7 7 for RSTCSR .
9. 5.2 Co nt e nt i o n betwee n Timer Counter (TCNT) Write and Increm e nt
If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write
takes priority and the timer counter is not incremented. Figure 9.6 shows this operation.
Address
ø
Internal write signal
TCNT input clock
TCNT NM
T1T2
TCNT write cycle
Counter write data
Fi g ure 9. 6 Contention between TCNT Write and Increm e nt
Rev. 1.0, 02/02, page 213 of 502
9. 5.3 Changi ng Value of CKS2 to CKS0
If bits CKS0 to CKS2 in TCSR are writ ten to while the WDT is opera ting, errors could occur in
the incrementation. Software must be used t o stop t he watchdog timer (by clearing t he TME bi t to
0) before changing the value of bit s CKS0 to CKS2.
9. 5.4 Switchi ng betwee n Watchdog Timer Mode and Inter va l Timer Mo de
If the mode i s switched from watchdog timer to i nterval timer while the W DT i s operating, errors
could oc c ur in the incrementation. Soft ware must be used to stop the watchdog timer (by clearing
the TME bit to 0) before switching the mode.
9.5.5 Internal Rese t in Watchdog Timer Mode
This LSI i s not re set int ernally if TCNT overflows while the RSTE bit is cleared to 0 during
watchdog timer opera tion, howe ver TCNT and TCSR of the WDT are reset.
TCNT, TCSR , or RSTCR cannot be written to for 132 states following an overf low. During this
period, any at tempt to rea d the WOVF flag i s not acknowledged. Accordingly, wait 132 states
af ter ove r flo w to write 0 to the WOVF fla g for clea rin g.
9.5.6 OVF Fl ag Clearing i n Interval Timer Mode
Wh en set ti ng of the OVF flag is in conte ntion with read i n g of the OVF flag in inte rval time r
mo de, t he OVF flag may not be clea red eve n when 0 is writt en to it after the OVF flag has be en
read as 1. When there is a possibility of contention between the setting and reading of the OVF
flag when t he OVF flag is polled while t he interval t ime r interrupt i s disabled, 0 should be only
written to the OVF a fter rea ding the OVF at least t wice in its ‘1’ state t o ensure clearing of the
flag.
Rev. 1.0, 02/02, page 214 of 502
Rev. 1.0, 02/02, page 215 of 502
Section 10 Serial Communication Interface (SCI)
This LSI has two independent serial communication interface (SCI) channels. The SCI can handle
both asynchronous and clocked synchronous serial comm uni cation. Serial data com munication
can be ca rried out using standard asynchronous communication chi ps such a s a Universal
Asynchronous Receiver/Transmitter (UART) or an Asynchronous Communication Interface
Adapter (ACIA). A function is also provided for serial communication betwee n processors
(multiprocessor c ommunication funct i on). The SCI also supports an IC card (Smart Card)
interface conforming to ISO/IE C 7816-3 (Identification Card) as a serial communication interface
extension function.
Figure 10. 1 shows a bloc k diagram of the SCI.
10.1 Features
• Choice of asynchronous or clocked synchronous serial communication mode
• Full-duple x com mun ic ation capability
The transmitter and receiver are mutually independent, enabling transmission and reception to
be executed si mu ltaneo usly.
Double-buffe ring is used in both the transmit ter and the receiver, ena bling continuous
transmission and continuous reception of serial data.
• On-chip baud rate genera t or allows any bit ra t e to be selected
External clock can be selected as a transfer clock source (except for in Smart Card interface
mode).
• Choice of LSB-first or MSB-first transfer (e xcept in the case of asynchronous mode 7-bit data)
• Four interrupt sourc e s
Transmit-end, transmit-data-empty, receive-da t a-full, and receive e rror — that can issue
requests.
• Module stop mode can be set
Asynchrono us mode
• Data length: 7 or 8 bits
• Stop bit length: 1 or 2 bits
• Parity: Even, odd, or none
• Receive e rror de tection: Pa rity, overrun, and framing errors
• Break detection: Break can be detected by reading the RxD pin level directly in the case of a
framing error
SCI0024A_000020020200
Rev. 1.0, 02/02, page 216 of 502
Clocked Synchronous mode
• Data length: 8 bits
• Receive e rror de tection: Ove rrun errors detected
Smart Ca rd Interfa ce
• Automatic transmission of error signal (parity error) i n receive m ode
• Error signal detection and automati c data retransmissio n in transmi t mod e
• Direct convent ion and i nverse convention bot h support e d
RxD
TxD
SCK
Clock
External clock
ø
ø/4
ø/16
ø/64
TEI
TXI
RXI
ERI
RSR
RDR
TSR
TDR
SMR
SCR
SSR
SCMR
BRR
: Receive shift register
: Receive data register
: Transmit shift register
: Transmit data register
: Serial mode register
: Serial control register
: Serial status register
: Smart card mode register
: Bit rate register
SCMR
SSR
SCR
SMR
Transmission/
reception control
Baud rate
generator
BRR
Module data bus
Bus interface
RDR
TSRRSR
Parity generation
Parity check
Legend
TDR
Internal
data bus
Figure 10.1 Block Diagram of SCI
Rev. 1.0, 02/02, page 217 of 502
10.2 Input/Output Pins
Table 10.1 shows the serial pins for each SCI channel.
Table 10. 1 Pin Configuration
Channel Pin Name*I/O Function
SCK0 I/O SCI0 clock input/output
RxD0 Input SCI0 receive dat a input
0
TxD0 Output SCI0 transmit data out put
SCK1 I/O SCI1 clock input/output
RxD1 Input SCI1 receive dat a input
1
TxD1 Output SCI1 transmit data out put
Note: *Pin names SCK, RxD, and TxD are used in the text for all channels, omitting the channel
designation.
10.3 Register Descrip t i on s
The SCI has the following registers for each channel. The serial mode register (SMR), serial status
register (SSR), and serial control register (SCR) are desc ri bed separately for normal seri al
communication interface mode and Smart Card interface mode because their bit functions differ in
part.
• Receive shift register (RSR)
• Receive data register (RDR)
• Transmit data register (TDR)
• Transmit shift register (TSR)
• Serial mode register (SMR)
• Serial control registe r (SCR)
• Serial st atus registe r (SSR)
• Smart c ard mode register (SCMR)
• Bit rate register (BRR)
Rev. 1.0, 02/02, page 218 of 502
10. 3. 1 Rec ei ve Shi f t Regist er (RSR)
RSR is a shift register that is used to receive serial dat a input to the RxD pin a nd convert it into
parallel data. When one byte of data has been received, it is transferred to RDR automatically.
RSR cannot be directly accesse d by the CPU.
10. 3. 2 Rec eive Da t a Reg i ster (RDR)
RDR is an 8-bit register that stores received data. When the SCI has received one byte of serial
data, it transfers the received serial data from RSR to RDR, where it is stored. After this, RSR is
receive-enabl ed. As RSR a nd RDR function as a doubl e buffer i n this wa y, continuous receive
operations are possible. After c onfirming that the RDRF bit in SSR is set t o 1, rea d RDR only
once. RDR cannot be written to by the CPU.
10. 3. 3 T r a nsm i t Data Regist er (TDR)
TDR is an 8-bit register that stores data for transmission. When the SCI detects that TSR is empty,
it transfers the transm it data written in TDR to T SR and starts tra nsmission. T he double-buffered
structure of TDR and TSR ena bles continuous serial transmission. If t he next transmit da ta has
already been written to TDR during serial transmission, the SCI transfers the written data to TSR
to continue transmission. Although TDR can be read or written to by the CPU at all times, to
achieve reliable serial transmission, write transmit data to TDR only once after confirming that the
TDRE bit in SSR is set to 1.
10. 3. 4 T r a nsm i t Shif t Regist er (TSR)
TSR is a shift regi ster that transmits serial data. To pe rform serial data transmi ssion, the SCI first
transfers transmit data from TDR to TSR, then sends the data to the TxD pin. TSR cannot be
directly accesse d b y th e CPU .
Rev. 1.0, 02/02, page 219 of 502
10.3.5 Serial Mode Register (SMR)
SMR is used to set t he SCI’s serial transfer format and sel ect the baud rate gene rator clock source.
Some bit functions of SMR differ between normal serial communication interface mode and Smart
Card interface mode.
Normal Se rial Com m unication Int erface Mode (When SMIF in SCMR is 0)
Bit Bit Name I nitial Value R/W Description
7C/
$
0 R/W Com munication Mode
0: Asynchronous mode
1: Cloc ked synchron ous mo de
6 CHR 0 R/W Character Length (enabled only in asynchronous
mode)
0: Selects 8 bits as the data length.
1: Selects 7 bits as the data length.
The MSB (bit 7)of TDR is not transm itted in
transmission.
In clocked synchronous mode, a fixed data length
of 8 bits is used.
5 PE 0 R/W Parity Enable ( enabled only in asynchronous
mode)
When this bit is set to 1, the parity bit is added to
transmit data before transmission, and the parity
bit is checked in recept ion. For a m ultiprocessor
format, par it y bit addition and checking are not
performed regardless of the PE bit setting.
4O/
(
0 R/W Parity M ode (enabled only when the PE bit is 1 in
asynch ronou s mode )
0: Selects even parity.
1: Selects odd parity.
3STOP 0 R/WStop Bit Length ( enabled only in asynchr onous
mode)
Selects the st op bit length in tr ansmission.
0: 1 stop bit
1: 2 stop bits
In reception, only the first stop bit is checked. If
the second stop bit is 0, it is treated as the start bit
of the next transmit char acter.
Rev. 1.0, 02/02, page 220 of 502
Bit Bit Name I nitial Value R/W Description
2MP 0 R/WMult iprocessor Mode (enabled only in
asynch ronou s mode )
When this bit is set to 1, the multiprocessor
communication function is enabled. The PE bit
and O/
(
bit settin g s ar e inva lid in m u ltiproces s or
mode.
1 CKS1 0 R/W
0 CKS0 0 R/W Clo c k Sele ct 0 and 1
These bits select the clock source for the baud
rate generator.
00: ø clock (n = 0)
01: ø/4 clock (n = 1)
10: ø/16 clock (n = 2)
11: ø/64 clock (n = 3)
For the relationship bet ween the bit rate register
setting and the baud r ate, see section 10.3.9, Bit
Rat e Register (BRR). n is the decimal
re presentation of the val ue of n in BR R (see
section 10.3.9, Bit Rate Regist er (BRR)).
Rev. 1.0, 02/02, page 221 of 502
Smart Ca rd Interfa ce Mode (When SMIF in SCMR is 1)
Bit Bit Name I nitial Value R/W Description
7 GM 0 R/W GSM Mode
When this bit is set to 1, the SCI operates in GSM
mode. In GSM mode, the timing of the TEND
setting is advanced by 11. 0 etu (Elementary Tim e
Unit: the time for transfer of one bit), and clock
output contr ol mode addition is performed. For
details, refer to section 10.7.8, Clock Output
Control.
6BLK 0 R/WWhen this bit is set to 1, the SCI operates in block
transfer mode. For details on block transfer mode,
refer to section 10.7.3, Block Transfer Mode.
5PE 0 R/WParity Enable (enabled only in asynchronous
mode)
When this bit is set to 1, the parity bit is added to
transmit data in transmission, and the parity bit is
chec k e d in recept io n. In Smart Card int erface
mode, this bit must be set to 1.
4O/
(
0 R/W Parity M ode (enabled only when the PE bit is 1 in
asynch ronou s mode )
0: Selects even parity.
1: Selects odd parity.
For det a ils on setting th is bit in Smar t Card
interface mode, refer to section 10.7.2, Data
Format (Except for Block Transfer Mode) .
3 BCP1 0 R/W
2 BCP0 0 R/W
Basic Clock Pulse 1 and 0
These bits specify the num ber of basic clock
periods in a 1-bit tr ansfer interval on the Smart
Car d int erface.
00: 32 clock (S = 32)
01: 64 clock (S = 64)
10: 372 clock (S = 372)
11: 256 clock (S = 256)
For det a ils, refe r t o sect io n 10.7 .4 , Rec e iv e Data
Sampling Tim ing and Reception Margin in Smart
Card Int erface Mode. S stands f or the value of S
in BRR (see section 10.3.9, Bit Rate Register
(BRR)).
Rev. 1.0, 02/02, page 222 of 502
Bit Bit Name I nitial Value R/W Description
1 CKS1 0 R/W
0 CKS0 0 R/W
Clock Se le ct 0 and 1
These bits select the clock source for the baud
rate generator.
00: ø clock (n = 0)
01: ø/4 clock (n = 1)
10: ø/16 clock (n = 2)
11: ø/64 clock (n = 3)
For the relationship bet ween the bit rate register
setting and the baud r ate, see section 10.3.9, Bit
Rat e Register (BRR). n is the decimal
re presentation of the val ue of n in BR R (see
section 10.3.9, Bit Rate Regist er (BRR)).
Rev. 1.0, 02/02, page 223 of 502
10.3.6 Serial Control Register (SCR)
SCR is a register t hat ena bles or disables SCI transfe r operati ons and interrupt requests, a nd is also
used to selection of t he transfer clock source. For details on i nterrupt requests, refer t o section
10.8, Interrupts. Some bit functions of SCR differ between norma l serial com munication i nterface
mode and S ma rt Card interfa ce mode .
Normal Se rial Com m unication Int erface Mode (When SMIF in SCMR is 0)
Bit Bit Name I nitial Value R/W Description
7 TI E 0 R/W Transmit Interrupt Enable
When this bit is set to 1, the TXI interrupt request
is enabled.
6 RIE 0 R/W Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt
requests are enabled.
5 TE 0 R/W Transmit Enable
When this bit s set t o 1, transmission is enabled.
4 RE 0 R/W Receive Enable
When this bit is set to 1, recept ion is enabled.
3MPIE 0 R/WMultiprocessor Interrupt Enable (enabled only
when the MP bit in SMR is 1 in asynchronous
mode)
When this bit is set to 1, receive data in which the
multiprocess or bit is 0 is skipped, and set t ing of
th e RDRF, FER, and ORER statu s f lag s in SSR is
prohibited. On r eceiving dat a in which the
mu ltiproc e sso r bit is 1, th is bit is aut omat ic a lly
cleared and normal recept ion is r esumed. For
details, refer to sect ion 10.5, Multiprocessor
Communicat ion Function.
2 TEI E 0 R/W Transmit End Int errupt Enable
This bit is set to 1, TEI interrupt request is
enabled.
Rev. 1.0, 02/02, page 224 of 502
Bit Bit Name I nitial Value R/W Description
1 CKE1 0 R/W
0 CKE0 0 R/W
Clock Enable 0 and 1
Selects the clock source and SCK pin function.
Asynch ronous mode
00: Internal clock
SCK pin functions as I/O port
01: Internal clock
Outputs a clock of the same frequency as the bit
rate from the SCK pin.
1X: Exter nal clock
Inputs a clock with a frequency 16 times the bit
rate from the SCK pin.
Clocked synchronous mode
0X: Internal clock (SCK pin functions as clock
output)
1X: Exter nal clock ( SCK pin functions as clock
input)
Legend
X: Don’t care
Smart Ca rd Interfa ce Mode (When SMIF in SCMR is 1)
Bit Bit Name I nitial Value R/W Description
7 TI E 0 R/W Transmit Interrupt Enable
When this bit is set to 1, TXI inter rupt request is
enabled.
6 RIE 0 R/W Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt
requests are enabled.
5 TE 0 R/W Transmit Enable
When this bit is set to 1, transm ission is enabled.
4 RE 0 R/W Receive Enable
When this bit is set to 1, recept ion is enabled.
3MPIE 0 R/WMultiprocessor Interrupt Enable (enabled only
when the MP bit in SMR is 1 in asynchronous
mode)
Write 0 to this bit in Smart Card interface m ode.
2 TEI E 0 R/W Transmit End Int errupt Enable
Write 0 to this bit in Smart Card interface m ode.
Rev. 1.0, 02/02, page 225 of 502
Bit Bit Name I nitial Value R/W Description
1
0CKE1
CKE0 0
0R/W Clock Enable 0 and 1
Enables or disables clock output from the SCK
pin. The clock output can be dynam ically switched
in GSM mode. For details, refer to section 10.7.8,
Clock Output Control.
When the GM bit in SMR is 0:
00: Output disabled (SCK pin can be used as an
I/O port pin)
01: Clock output
1X: Reserved
When the GM bit in SMR is 1:
00: Output fixed low
01: Clock output
10: Output fixed high
11: Clock output
Legend
X: Don’t care
Rev. 1.0, 02/02, page 226 of 502
10.3.7 Serial Status Register (SSR)
SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. 1 cannot
be written to flags TDRE, RDRF, ORER, PER, and FER; they can only be cleared. Some bit
functions of SSR differ bet ween normal serial communication interface mode and Smart Card
interface mode.
Normal Se rial Com m unication Int erface Mode (When SMIF in SCMR is 0)
Bit Bit Name I nitial Value R/W Description
7 TDRE 1 R/(W)*Transmit Data Register Empty
Displays whether TDR cont ains transmit dat a.
[Setting condition s]
• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR
[Clearing condition]
• When 0 is written t o TDRE aft er reading TDRE
= 1
6 RDRF 0 R/(W)*Rece iv e Data Regis ter Full
In dic at es t h at the rece iv ed data is stored in RDR.
[Setting condition]
• When serial reception ends normally and
re c eiv e data is tr ansferr ed from RSR to RDR
[Clearing condition]
• When 0 is writte n to RDRF after reading RDRF
= 1
The RDRF flag is not affe ct e d and retain s it s valu e
when the RE bit in SCR is cleared to 0.
5 ORER 0 R/(W)*Overrun Error
[Setting condition]
• When the next ser ial recept ion is completed
while RDRF = 1
[Clearing condition]
• When 0 is written t o ORER after reading
ORER = 1
Note: Only 0 for clearing the flag can be written.
Rev. 1.0, 02/02, page 227 of 502
Bit Bit Name I nitial Value R/W Description
4FER 0 R/(W)*Framing Error
[Setting condition]
• When the stop bit is 0
[Clearing condition]
• When 0 is written to FER after reading FER =
1
In 2-stop- bit mode, only the first stop bit is
checked.
3 PER 0 R/(W)*Pa r ity Error
[Setting condition]
• When a parity error is detected during
reception
[Clearing condition]
• When 0 is written t o PER aft er reading PER =
1
2 TEND 1 R Transmit End
[Setting condition s]
• When the TE bit in SCR is 0
• When TDRE = 1 at tr ansmission of the last bit
of a 1-by te serial trans mit charac ter
[Clearing condition]
• When 0 is written t o TDRE aft er reading TDRE
= 1
1 MPB 0 R Mult ipro c essor Bit
MPB stores the multiprocessor bit in the receive
data. When the RE bit in SCR is cleared to 0 its
state is retained.
0 MPBT 0 R/W Mu ltiprocessor Bit Tr ansfer
MPBT stores the mul tiproce ssor bit to be added to
the transmit data.
Note: Only 0 for clearing the flag can be written.
Rev. 1.0, 02/02, page 228 of 502
Smart Ca rd Interfa ce Mode (When SMIF in SCMR is 1)
Bit Bit Name I nitial Value R/W Description
7 TDRE 1 R/(W)*Tr ansmit Data Register Empty
Displays whether TDR cont ains transmit dat a.
[Setting condition s]
• When the TE bit in SCR is 0
• When data is transferred from TDR to TSR
and data can be written to TDR
[Clearing condition]
• When 0 is written t o TDRE aft er reading TDRE
= 1
6 RDRF 0 R/(W)*Receiv e Data Regis ter Full
In dic at es t h at the rece iv ed data is stored in RDR.
[Setting condition]
• When serial reception ends normally and
re c eiv e data is tr ansferr ed from RSR to RDR
[Clearing condition]
• When 0 is writte n to RDRF after reading RDRF
= 1
The RDRF flag is not affe ct e d and retain s it s valu e
when the RE bit in SCR is cleared to 0.
5 ORER 0 R/(W)*Overrun Error
[Setting condition]
• When the next ser ial recept ion is completed
while RDRF = 1
[Clearing condition]
• When 0 is written t o ORER after reading
ORER = 1
4ERS 0 R/(W)
*Error Signal Status
[Setting condition]
• When the low level of the error signal is
sampled
[Clearing condition]
• When 0 is written t o ERS after r eading ERS =
1
Note: Only 0 for clearing the flag can be written.
Rev. 1.0, 02/02, page 229 of 502
Bit Bit Name I nitial Value R/W Description
3 PER 0 R/(W)*Pa r ity Error
[Setting condition]
• When a parity error is detected during
reception
[Clearing condition]
• When 0 is written t o PER aft er reading PER =
1
2 TEND 1 R Transmit End
This bit is set to 1 when no error signal has been
sent back from the receiving end and the next
transmit data is ready to be transferred to TDR.
[Setting condition s]
• When the TE bit in SCR is 0 and the ERS bit is
also 0
• When the ESR bit is 0 and the TDRE bit is 1
af ter the specif ied int erv a l follo win g
transmission of 1-byte dat a.
The timing of bit setting differ s according to the
register setting as follows:
When GM = 0 and BLK = 0, 2.5 etu af ter
transmission starts
When GM = 0 and BLK = 1, 1.5 etu af ter
transmission starts
When GM = 1 and BLK = 0, 1.0 etu af ter
transmission starts
When GM = 1 and BLK = 1, 1.0 etu af ter
transmission starts
[Clearing condition]
• When 0 is written t o TDRE aft er reading TDRE
= 1
1 MPB 0 R Mult ipro c essor Bit
This bit is not used in Sm art Car d interface mode.
0 MPBT 0 R/W Mu ltiprocessor Bit Tr ansfer
Write 0 to this bit in Smart Card interface m ode.
Note: Only 0 for clearing the flag can be written.
Rev. 1.0, 02/02, page 230 of 502
10.3.8 Smart Card Mode Register (SCMR)
SCMR is a register that selects Smart Card interface mode and its format.
Bit Bit Name I nitial Value R/W Description
7
6
5
4
—
—
—
—
1
1
1
1
—
—
—
—
Reserved
These bits are always read as 1.
3 SDIR 0 R/W Sm a rt Card Data Tran sf er Direc tion
Selects the ser ial/parallel conversion format.
0: LSB-first in transfer
1: MSB-first in transfer
The bit setting is valid only when the transfer data
format is 8 bits. For 7-bit data, LSB-first is fixed.
2 SINV 0 R/W Smart Card Data Invert
Specifies inversio n of the data logic lev el. Th e
SINV bit does not af f ect the logic level of the parity
bit. To invert the parity bit, invert the O/
(
bit in
SMR.
0: TDR content s are transmitt ed as they are.
Receiv e d ata is store d as it is in RDR
1: TDR content s are inver ted before being
transmitted. Receive data is st ored in inver ted
fo rm in RDR
1— 1 — Reserved
This bit is always read as 1.
0 SMIF 0 R/W Smart Card Interface Mode Select
This b it is set to 1 to mak e the SCI op era te in
Smart Card interface mode.
0: Norm al asynchr onous mode or clocked
synch ronous mode
1: Smart card interface mode
Rev. 1.0, 02/02, page 231 of 502
10. 3. 9 Bit Rate Regist er (BRR)
BRR is an 8-bit re gister tha t adjusts t he bit rate. As the SCI performs baud rate generator control
independently for each channel, different bit rates can be set for each channel. Table 10.2 shows
the relationships bet ween the N se t ting in BRR and bit rate B for normal a synchronous m ode,
clocked synchronous m ode, and Smart Card int erface mode. The initial va lue of BRR is H'FF, and
it can be read or written to by the CPU at all times.
Tabl e 10. 2 The Rel atio nshi ps betwee n The N Sett i ng in BRR and Bit Rate B
Mode Bit Rat e Error
Asynchronous
Mode
B = 64 2
2n-1
(N + 1)
ø 10
6
Error (%) = { B 64 2
2n-1
(N + 1) -1 } 100
ø 10
6
Clocked
Synchronous
Mode
B = 8 2
2n-1
(N + 1)
ø 10
6
—
Smart Card
Interface Mode
B = S 2
2n-1
(N + 1)
ø 10
6
Error (%) = { B S 2
2n-1
(N + 1) -1 } 100
ø 10
6
Note: B: Bit rate (bit/s)
N: BRR setting for baud r ate generator (0 ≤ N ≤ 255)
ø: O perating f r equency (M Hz)
n and S: Determined by the SMR settings shown in t he following tables.
SMR Setti ng SMR Setti ng
CKS1 CKS0 n BCP1 BCP0 S
000 0032
011 0164
102 10372
113 11256
Table 10. 3 shows sample N settings in BRR in normal asynchronous mode. Table 10.4 shows the
maximum bit rate for each freque ncy in norm al asynchronous mode. Table 10.6 shows sa m ple N
settings i n BRR in clocked sync hronous mode. Table 10.8 shows sample N settings in BRR in
Smart Card interface mode. In Smart Card interface mode, S (the number of basic clock periods in
a 1-bit transfer interval) can be selected. For details, refer to section 10.7.4, Receive Data
Sampling Timing and Reception Margin. Tables 10.5 and 10.7 show the maximum bit rates with
external clock input.
Rev. 1.0, 02/02, page 232 of 502
Table 10. 3 BRR Setti ngs for Various Bit Rate s (Async hronous M ode) (1)
Operating Frequency ø (MHz)
4 4.9152 5 6
Bit Rate
(bit/s) n N Error
(%) n N Error
(%) n N Error
(%) n N Error
(%)
110 2 70 0.03 2 86 0.31 2 88 –0.25 2 106 –0.44
150 1 207 0.16 1 255 0.00 2 64 0.16 2 77 0.16
300 1 103 0.16 1 127 0.00 1 129 0.16 1 155 0.16
600 0 207 0.16 0 255 0.00 1 64 0.16 1 77 0.16
1200 0 103 0.16 0 127 0.00 0 129 0.16 0 155 0.16
2400 0 51 0.16 0 63 0.00 0 64 0.16 0 77 0.16
4800 0 25 0.16 0 31 0.00 0 32 –1.36 0 38 0.16
9600 0 12 0.16 0 15 0.00 0 15 1.73 0 19 –2.34
19200 — — — 0 7 0.00 0 7 1.73 0 9 –2.34
31250 0 3 0.00 0 4 –1.70 0 4 0.00 0 5 0.00
38400 — — — 0 3 0.00 0 3 1.73 0 4 –2.34
Operating Frequency ø (MHz)
6.144 7.3728 8 9.8304
Bit Rate
(bit/s) n N Error
(%) n N Error
(%) n N Error
(%) n N Error
(%)
110 2 108 0.08 2 130 –0.07 2 141 0.03 2 174 –0.26
150 2 79 0.00 2 95 0.00 2 103 0.16 2 127 0.00
300 1 159 0.00 1 191 0.00 1 207 0.16 1 255 0.00
600 1 79 0.00 1 95 0.00 1 103 0.16 1 127 0.00
1200 0 159 0.00 0 191 0.00 0 207 0.16 0 255 0.00
2400 0 79 0.00 0 95 0.00 0 103 0.16 0 127 0.00
4800 0 39 0.00 0 47 0.00 0 51 0.16 0 63 0.00
9600 0 19 0.00 0 23 0.00 0 25 0.16 0 31 0.00
19200 0 9 0.00 0 11 0.00 0 12 0.16 0 15 0.00
31250 0 5 2.40 — — — 0 7 0.00 0 9 –1.70
38400 0 4 0.00 0 5 0.00 — — — 0 7 0.00
Rev. 1.0, 02/02, page 233 of 502
Table 10. 3 BRR Setti ngs for Various Bit Rate s (Async hronous M ode) (2)
Operating Frequency ø (MHz)
10 12 12.288 14
Bit Rate
(bit/s) n N Error
(%) n N Error
(%) n N Error
(%) n N Error
(%)
110 2 177 –0.25 2 212 0.03 2 217 0.08 2 248 –0.17
150 2 129 0.16 2 155 0.16 2 159 0.00 2 181 0.13
300 2 64 0.16 2 77 0.16 2 79 0.00 2 90 0.13
600 1 129 0.16 1 155 0.16 1 159 0.00 1 181 0.13
1200 1 64 0.16 1 77 0.16 1 79 0.00 1 90 0.13
2400 0 129 0.16 0 155 0.16 0 159 0.00 0 181 0.13
4800 0 64 0.16 0 77 0.16 0 79 0.00 0 90 0.13
9600 0 32 –1.36 0 38 0.16 0 39 0.00 0 45 –0.93
19200 0 15 1.73 0 19 –2.34 0 19 0.00 0 22 –0.93
31250 0 9 0.00 0 11 0.00 0 11 2.40 0 13 0.00
38400 0 7 1.73 0 9 –2.34 0 9 0.00 — — —
Operating Frequency ø (MHz)
14.7456 16 17.2032 18
Bit Rate
(bit/s) n N Error
(%) n N Error
(%) n N Error
(%) n N Error
(%)
110 3 64 0.70 3 70 0.03 3 75 0.48 3 79 –0.12
150 2 191 0.00 2 207 0.13 2 223 0.00 2 233 0.16
300 2 95 0.00 2 103 0.13 2 111 0.00 2 116 0.16
600 1 191 0.00 1 207 0.13 1 223 0.00 1 233 0.16
1200 1 95 0.00 1 103 0.13 1 111 0.00 1 116 0.16
2400 0 191 0.00 0 207 0.13 0 223 0.00 0 233 0.16
4800 0 95 0.00 0 103 0.13 0 111 0.00 0 116 0.16
9600 0 47 0.00 0 51 0.13 0 55 0.00 0 58 –0.69
19200 0 23 0.00 0 25 0.13 0 27 0.00 0 28 1.02
31250 0 14 –1.70 0 15 0.00 0 13 1.20 0 17 0.00
38400 0 11 0.00 0 12 0.13 0 13 0.00 0 14 –2.34
Rev. 1.0, 02/02, page 234 of 502
Table 10. 3 BRR Setti ngs for Various Bit Rate s (Async hronous M ode) (3)
Operating Frequency ø (MHz)
19.6608 20
Bit Rate
(bit/s) n N Error
(%) n N Error
(%)
110 3 86 0.31 3 88 –0.25
150 2 255 0.00 3 64 0.16
300 2 127 0.00 2 129 0.16
600 1 255 0.00 2 64 0.16
1200 1 127 0.00 1 129 0.16
2400 0 255 0.00 1 64 0.16
4800 0 127 0.00 0 129 0.16
9600 0 63 0.00 0 64 0.16
19200 0 31 0.00 0 32 –1.36
31250 0 19 –1.70 0 19 0.00
38400 0 15 0.00 0 15 1.73
Rev. 1.0, 02/02, page 235 of 502
Table 10. 4 Maximum Bi t Rate for Each Fr equency (Asynchronous Mode)
ø (MHz) Maxi mum Bit
Rate (bit/s) n N ø (MHz) Maximum Bit
Ra te (bit/s ) n N
4 125000 0 0 12 375000 0 0
4.9152 153600 0 0 12.288 384000 0 0
5 156250 0 0 14 437500 0 0
6 187500 0 0 14.7456 460800 0 0
6.144 192000 0 16 500000 0 0
7.3728 230400 0 0 17.2032 537600 0 0
8 250000 0 0 18 562500 0 0
9.8304 307200 0 0 19.6608 614400 0 0
10 312500 0 0 20 625000 0 0
Tabl e 10. 5 Ma x imum Bit Rate with Exter nal Cl ock Input (Asy nc hrono us Mode )
ø (MHz) Exte r nal Input
Clock (MHz) Maximum Bit
Rate (bit/s) ø (MHz) Exter nal Input
Clock (MHz) Maximum Bit
Ra te (bit/s )
4 1.0000 62500 12 3.0000 187500
4.9152 1.2288 76800 12.288 3.0720 192000
5 1.2500 78125 14 3.5000 218750
6 1.5000 93750 14.7456 3.6864 230400
6.144 1.5360 96000 16 4.0000 250000
7.3728 1.8432 115200 17.2032 4.3008 268800
8 2.0000 125000 18 4.5000 281250
9.8304 2.4576 153600 19.6608 4.9152 307200
10 2.5000 156250 20 5.0000 312500
Rev. 1.0, 02/02, page 236 of 502
Table 10. 6 BRR Setti ngs for Various Bit Rate s (Clocke d Sync hronous Mode)
Operating Frequency ø (MHz)
4 8 10 16 20
Bit Rate
(bit/s) nN nN nN nN nN
110 — —
250 2 249 3 124 — — 3 249
500 2 124 2 249 — — 3 124 — —
1k 1 249 2 124 — — 2 249 — —
2.5k 1 99 1 199 1 249 2 99 2 124
5k 0 199 1 99 1 124 1 199 1 249
10k 0 99 0 199 0 249 1 99 1 124
25k 0 39 0 79 0 99 0 159 0 199
50k 0 19 0 39 0 49 0 79 0 99
100k 0 9 0 19 0 24 0 39 0 49
250k 0 3 0 7 0 9 0 15 0 19
500k 0 1 0 3 0 4 0 7 0 9
1M 0 0*01 03 04
2.5M 0 0*01
5M 00*
Legend
Blank : Cannot be set.
— : Can be set, but there will be a degree of err or.
: Continuous transfer is not possible.
Note: * M ake the settings so t hat the error does not exceed 1%.
Tabl e 10. 7 Ma x imum Bit Rate with Exter nal Cl ock Input (Clocked Synchrono us Mode )
ø (MHz) Exte r nal Input
Clock (MHz) Maximum Bit
Rate (bit/s) ø (MHz) Exter nal Input
Clock (MHz) Maximum Bit
Ra te (bit/s )
4 0.6667 666666.7 14 2.3333 2333333.3
6 1.0000 1.000000.0 16 2.6667 2666666.7
8 1.3333 1333333.3 18 3.0000 3000000.0
10 1.6667 1666666.7 20 3.3333 3333333.3
12 2.0000 2000000.0
Rev. 1.0, 02/02, page 237 of 502
Table 10. 8 Examples of Bit Rate for Various BRR Settings (Smart Card Interface Mode)
(When n = 0 and S = 372)
Operating Frequency ø (MHz)
7.1424 10.00 10.7136 13.00
Bit Rate
(bit/s) n N Error
(%) n N Error
(%) n N Error
(%) n N Error
(%)
9600 0 0 0.00 0 1 30 0 1 25 0 1 8.99
Operating Frequency ø (MHz)
14.2848 16.00 18.00 20.00
Bit Rate
(bit/s) n N Error
(%) n N Error
(%) n N Error
(%) n N Error
(%)
9600 0 1 0.00 0 1 12.01 0 2 15.99 0 2 6.60
Table 10.9 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode)
(when S = 372)
ø (MHz) Maxi mum Bit
Rate (bit/s) n N ø (MHz) Maximum Bit
Ra te (bit/s ) n N
7.1424 9600 0 0 14.2848 19200 0 0
10.00 13441 0 0 16.00 21505 0 0
10.7136 14400 0 0 18.00 24194 0 0
13.00 17473 0 0 20.00 26882 0 0
Rev. 1.0, 02/02, page 238 of 502
10.4 Operation in Asynchron ou s Mode
Figure 10. 2 shows the ge neral format for asynchronous serial comm unication. One frame consi sts
of a sta rt bit (l ow level), fol lowed by data (in L SB-first order), a parity bi t (high or low level), and
finally stop bits (high level). In asynchronous serial communication, the transmi ssion line i s
usually held in the mark state (high level). The SCI monitors the transmission line. When the
transmission line goes to the space state (l ow le vel), the SCI recognizes a start bit and starts serial
communication. In asynchronous se rial communication, the communication line is usuall y he l d in
the mark state (high level). The SCI monitors the communication line, and when it goes to the
space state (low level), recognizes a start bit and starts serial communication. Inside the SCI, the
transmitter and receiver are independent units, enabling full-duplex. The transmitter and receiver
both have a double -buffered structure, so dat a can be re ad or written during transmi ssion or
rec ep tion, en abling co ntinuo u s d ata transfer .
LSB
Start
bit
MSB
Idle state
(mark state)
Stop bit
0
Transmit/receive data
D0 D1 D2 D3 D4 D5 D6 D7 0/1 1 1
1 1
Serial
data Parity
bit
1 bit 1 or
2 bits
7 or 8 bits 1 bit,
or none
One unit of transfer data (character or frame)
Figure 10.2 Data Format i n Asynchronous Communic ation (Example with 8-Bit Data,
Parity, Two Stop Bits)
10.4.1 Data Tr ansfer Format
Table 10. 10 shows the data transfe r formats that can be used in asynchronous mode. Any of 12
transfer formats can be se lected a ccording to the SMR setting. For details on t he multiprocessor
bit, refer to section 10.5, Mul tiprocessor Communication Function.
Rev. 1.0, 02/02, page 239 of 502
Table 10. 10 Serial Transfer Formats (Asynchronous Mode )
PE
0
0
1
1
0
0
1
1
—
—
—
—
S 8-bit data
STOP
S 7-bit data
STOP
S 8-bit data
STOP STOP
S 8-bit data
P
STOP
S 7-bit data
STOP
P
S 8-bit data
MPB STOP
S 8-bit data
MPB STOPSTOP
S 7-bit data
STOPMPB
S 7-bit data
STOPMPB STOP
S 7-bit data
STOPSTOP
CHR
0
0
0
0
1
1
1
1
0
0
1
1
MP
0
0
0
0
0
0
0
0
1
1
1
1
STOP
0
1
0
1
0
1
0
1
0
1
0
1
SMR Settings
123456789101112
Serial Transfer Format and Frame Length
STOP
S 8-bit data
P
STOP
S 7-bit data
STOP
P
STOP
Legend
S : St art bit
STOP : Stop bit
P : Parity bit
MPB : Mul ti proce ssor bi t
Rev. 1.0, 02/02, page 240 of 502
10.4.2 Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times t he transfe r
rate. In reception, the SCI samples the falling edge of the start bit using the basic clock, and
performs i nternal synchroniz ation. Rec eive data is latched internally at the rising edge of the 8th
pulse of t he basic clock as shown in figure 10.3. T hus, the reception margin in async hronous mode
is given by formula (1) below.
M = (0.5 – ) – – (L – 0.5) F 100 [%]
1
2N D – 0.5
N
... Formula (1)
Where M : Reception margin (%)
N : Rat io of bit rate to c lock (N = 16)
D : Clock duty (D = 0.5 to 1.0)
L : Frame length (L = 9 to 12)
F : Absolute value of clock rate deviation
Assum i n g valu e s of F (absol ute value of clock rate deviation) = 0 and D (cl ock dut y) = 0.5 in
formula (1), the reception margin can be given by the form ul a.
M = {0.5 – 1/(2 × 16)} × 100 [%] = 46.875%
However, t hi s is only the comput ed value, a nd a ma rgin of 20% to 30% should be allowed for in
system desig n.
Internal basic
clock
16 clocks
8 clocks
Receive data
(RxD)
Synchronization
sampling timing
Start bit D0 D1
Data sampling
timing
15 0 7 15 007
Figure 10.3 Re ceive Data Sampli ng Ti mi ng in Asynchronous Mode
Rev. 1.0, 02/02, page 241 of 502
10.4.3 Clock
Either an inte rnal clock generated by the on-c hip baud rate genera tor or an external clock input a t
the SCK pin can be selected as the SCI’s serial clock, according to the setting of the C/
$
bi t in
SMR and the CKE0 and CKE1 bits in SCR. When an external clock is input at the SCK pin, the
clock frequency should be 16 times the bit rate used.
When the SCI is operate d on an int e rnal cl ock, the clock can be output from t he SCK pin. The
frequency of the clock output in this case is equal to the bit rate, and the phase is such that the
rising edge of the clock is in the m i ddle of the transmit dat a, as shown in Figure 10.4.
0
1 frame
D0 D1 D2 D3 D4 D5 D6 D7 0/1 11
SCK
TxD
Fi g ure 10.4 Rel ati onship between Output Cloc k and Transfer Data Phase
(Asynchronous Mode)
Rev. 1.0, 02/02, page 242 of 502
10. 4. 4 SCI Initiali z ati on (Async hr o no us Mode)
Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then
initialize the SCI as described below. When the operating mode, or transfer format, is changed for
example, the TE and RE bits must be cleared to 0 before making the change using the following
procedure. W hen the TE bit is cleared to 0, the TDRE flag i s set to 1. Note tha t clearing the RE bit
to 0 does not initialize the contents of the RDRF, PER, FER, and ORER flags, or the contents of
RDR. Whe n the e xternal clock is used in asynchronous mode, t he clock must be supplied even
during ini tialization.
Wait
<Initialization completion>
Start initialization
Set data transfer format in
SMR and SCMR
[1]
Set CKE1 and CKE0 bits in SCR
(TE and RE bits are 0)
No
Yes
Set value in BRR
Clear TE and RE bits in SCR to 0
[2]
[3]
Set TE and RE bits in
SCR to 1, and set RIE, TIE, TEIE,
and MPIE bits to 1 [4]
1-bit interval elapsed?
[1] Set the clock selection in SCR.
Be sure to clear bits RIE, TIE,
TEIE, MPIE, TE, and RE to 0.
When the clock is selected in
asynchronous mode, it is output
immediately after SCR settings are
made.
[2] Set the data transfer format in SMR
and SCMR.
[3] Write a value corresponding to the
bit rate to BRR. Not necessary if
an external clock is used.
[4] Wait at least one bit interval, then
set the TE bit or RE bit in SCR to 1.
Also set the RIE, TIE, TEIE, and
MPIE bits to 1.
Setting the TE and RE bits enables
the TxD and RxD pins to be used.
Fi g ure 10.5 Sample SCI Initiali z ati o n Flowchart
Rev. 1.0, 02/02, page 243 of 502
10.4.5 Data Transmission (Asynchronous Mode)
Figure 10. 6 shows an example of ope ration for transmission in asynchronous m ode. In
transmission, the SCI operates as described below.
1. The SCI monitors the TDRE flag in SSR. If the flag is cleared to 0, the SCI recognizes that
data has been written to TDR, and transfers the data from TDR to TSR.
2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
transmission. If the TIE bit is set to 1 at this time, a t ransmit data em pty inte rrupt reque st (TXI)
is generated. Cont inuous t ransmission is possible because the TXI interrupt routi ne writes ne xt
transmit data to TDR before transmission of the current transmit data has been completed.
3. Data is sent from the TxD pin in the following order: start bit, t ransmit data, parity bit or
multiprocessor bit (may be omitted de pending on the form at), and stop bit.
4. The SCI checks the TDRE flag at the timing for sending the stop bit.
5. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then
serial transmissi on of the next fram e is started.
6. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the “mark
state” is entered, in which 1 is output. If the TEIE bit in SCR is set to 1 at this time, a TEI
interrupt re quest is gene rated.
Figure 10. 7 shows a sample fl owchart for transmi ssion in a synchronous m ode.
TDRE
TEND
0
1 frame
D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 1
1 1
DataStart
bit Parity
bit Stop
bit Start
bit Data Parity
bit Stop
bit
TXI interrupt
request generated Data written to TDR and
TDRE flag cleared to 0 in
TXI interrupt service routine TEI interrupt
request generated
Idle state
(mark state)
TXI interrupt
request generated
Figure 10.6 Example of O peration in Transmission in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit)
Rev. 1.0, 02/02, page 244 of 502
No
<End>
[1]
Yes
Initialization
Start transmission
Read TDRE flag in SSR [2]
Write transmit data to TDR
and clear TDRE flag in SSR to 0
No
Yes
No
Yes
Read TEND flag in SSR
[3]
No
Yes
[4]
Clear DR to 0 and
set DDR to 1
Clear TE bit in SCR to 0
TDRE = 1
All data transmitted?
TEND = 1
Break output?
[1] SCI initialization:
The TxD pin is automatically
designated as the transmit data
output pin.
After the TE bit is set to 1, a frame
of 1s is output, and transmission is
enabled.
[2] SCI status check and transmit data
write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR and clear the
TDRE flag to 0.
[3] Serial transmission continuation
procedure:
To continue serial transmission,
read 1 from the TDRE flag to
confirm that writing is possible,
then write data to TDR, and then
clear the TDRE flag to 0.
[4] Break output at the end of serial
transmission:
To output a break in serial
transmission, set DDR for the port
corresponding to the TxD pin to 1,
clear DR to 0, then clear the TE bit
in SCR to 0.
Fi g ure 10.7 Sample Serial Tra nsmission Flo wchart
Rev. 1.0, 02/02, page 245 of 502
10.4.6 Serial Data Reception (Asynchronous Mode)
Figure 10. 8 shows an example of ope ration for reception in asynchronous m ode. In se rial
reception, the SCI operates as described be l ow.
1. The SCI moni tors the communication line. If a start bit is de tected, the SCI performs int ernal
synchronization, re ceives re ceive dat a in RSR, and che cks the pa rity bi t and stop bit.
2. If an overrun error occ urs (when reception of the ne xt data is com pleted while the RDRF flag
is still set to 1), the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time, an
ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag
remains to be set to 1.
3. If a parity error i s detected, the PER bit in SSR is set to 1 and rec eive data is transferred t o
RDR. If the RIE bit in SCR is set t o 1 a t this time, an ERI int errupt re que st i s generated.
4. If a framing error is detected (when the stop bit is 0), the FER bit in SSR is set to 1 and receive
data is transferred to RDR. If the RIE bit in SCR is set to 1 at this ti me, an ERI interrup t
request is generated.
5. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is
transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is
generated. Conti nuous reception is possible because the RXI interrupt routine reads t he receive
data transferred to RDR before reception of the next receive data has been completed.
RDRF
FER
0
1 frame
D0 D1 D7 0/1 1 0 D0 D1 D7 0/1 0
1 1
DataStart
bit Parity
bit Stop
bit Start
bit Data Parity
bit Stop
bit
ERI interrupt request
generated by framing
error
Idle state
(mark state)
RDR data read and RDRF
flag cleared to 0 in RXI
interrupt service routine
RXI interrupt
request
generated
Figure 10.8 Example of SCI O peration in Reception
(Example with 8-Bit Data, Parity, One Stop Bit)
Rev. 1.0, 02/02, page 246 of 502
Table 10.11 shows the states of the SSR status flags and receive data handling when a receive
error is detected. If a receive error i s det ected, the RDRF flag reta i ns its state before receiving
data. Reception c annot be resumed while a rec eive error fla g is se t to 1. Accordingly, clear the
ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 10. 9 shows a sample
flow chart for serial da t a reception.
Table 10.11 SSR Status Flags and Rec ei ve Data Handling
SSR Status Flag
RDRF*ORER FER PER Receive Data Receive Error Type
1 1 0 0 Lost Overrun error
0 0 1 0 Transferred to RDR Framing error
0 0 0 1 Transferred to RDR Parity error
1 1 1 0 Lost Overrun error + framing error
1 1 0 1 Lost Overrun error + parity error
0 0 1 1 Transferred to RDR Framing error + parity error
1111Lost Overrun error + framing error +
parity error
Note: *Th e RDRF flag reta in s the state it had before data rece ption.
Rev. 1.0, 02/02, page 247 of 502
Yes
<End>
[1]
No
Initialization
Start reception
[2]
No
Yes
Read RDRF flag in SSR [4]
[5]
Clear RE bit in SCR to 0
Read ORER, PER, and
FER flags in SSR
Error processing
(Continued on next page)
[3]
Read receive data in RDR, and
clear RDRF flag in SSR to 0
No
Yes
PER FER ORER = 1
RDRF = 1
All data received?
[1] SCI initialization:
The RxD pin is automatically
designated as the receive data input
pin.
[2] [3] Receive error processing and break
detection:
If a receive error occurs, read the
ORER, PER, and FER flags in SSR to
identify the error. After performing the
appropriate error processing, ensure
that the ORER, PER, and FER flags are
all cleared to 0. Reception cannot be
resumed if any of these flags are set to
1. In the case of a framing error, a
break can be detected by reading the
value of the input port corresponding to
the RxD pin.
[4] SCI status check and receive data read:
Read SSR and check that RDRF = 1,
then read the receive data in RDR and
clear the RDRF flag to 0. Transition of
the RDRF flag from 0 to 1 can also be
identified by an RXI interrupt.
[5] Serial reception continuation procedure:
To continue serial reception, before the
stop bit for the current frame is
received, read the RDRF flag, read
RDR, and clear the RDRF flag to 0.
Figure 10.9 Sample Serial Reception Data Flowchart (1)
Rev. 1.0, 02/02, page 248 of 502
<End>
[3]
Error processing
Parity error processing
Yes
No
Clear ORER, PER, and
FER flags in SSR to 0
No
Yes
No
Yes
Framing error processing
No
Yes
Overrun error processing
ORER = 1
FER = 1
Break?
PER = 1
Clear RE bit in SCR to 0
Figure 10.9 Sample Serial Reception Data Flowchart (2)
Rev. 1.0, 02/02, page 249 of 502
10.5 Multiprocessor Communication Function
Use of th e multiprocessor co mmu nic ation function en ables dat a transf er between a number of
processors sharing communication li nes by asynchronous seria l communication using the
multiprocessor format, in which a multiprocessor bit is added to the transfer data. When
multiprocessor communication i s performed, ea c h re ceiving station is addressed by a unique ID
code. The serial communication cycle consists of two component cycles; an ID transmission cycle
that specifies the receiving station, and a data transmission cycle. The multiprocessor bit is used to
differentiate between the ID transmission cycle and the data transmission cycle. If the
multiprocessor bit is 1, the cycle is an ID transmission cycle; if the multiprocessor bit is 0, the
cycle is a data transmission cycle. Figure 10.10 shows an example of inter-processor
communication using the multiproce ssor forma t. The transm i tting station first sends the ID code
of the receiving station with which it want s to perform se rial communication a s data wit h a 1
multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added.
When data with a 1 multiprocessor bit is received, the receiving station compares that data with its
own ID. The station whose ID matches then receives the data sent next. Stations whose IDs do not
match continue to skip data until data with a 1 multiprocessor bit is again received.
The SCI uses the MPIE bit in SCR to implement this function. When the MPIE bit is set to 1,
transfer of receive data from RSR to RDR, error flag de tection, and setting the SSR status flags,
RDRF, FE R, and ORER to 1, are inhibited until data with a 1 mul tiprocessor bi t is receive d. On
reception of a receive character with a 1 multiprocessor bit, the MPB bit in SSR is set to 1 and the
MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCR is set to
1 at this time, an RXI interrupt is generated.
When the multiprocessor format is selected, the parity bit setting is rendered invalid. All other bit
settings a re the same as those i n normal async hronous m ode. The clock used for mult iprocessor
communication is the same as t hat in normal asynchronous mode.
Rev. 1.0, 02/02, page 250 of 502
Transmitting
station
Receiving
station A Receiving
station B Receiving
station C Receiving
station D
(ID = 01) (ID = 02) (ID = 03) (ID = 04)
Serial transmission line
Serial
data
ID transmission cycle =
receiving station
specification
Data transmission cycle =
Data transmission to
receiving station specified by ID
(MPB = 1) (MPB = 0)
H'01 H'AA
Legend
MPB: Multiprocessor bit
Figure 10.10 Example of Communicati on Using Multiprocessor For mat
(Transmission of Data H'AA to Re ceiving Stati on A)
Rev. 1.0, 02/02, page 251 of 502
10. 5. 1 Mul t i proce ssor Ser i al Da ta Transmission
Figure 10. 11 shows a sampl e flowcha rt for mul tiprocessor serial data transmission. For an ID
transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission
cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI operations are the same
as those i n async hronous m ode.
No
<End>
[1]
Yes
Initialization
Start transmission
Read TDRE flag in SSR [2]
Write transmit data to TDR and
set MPBT bit in SSR
No
Yes
No
Yes
Read TEND flag in SSR
[3]
No
Yes
[4]
Clear DR to 0 and set DDR to 1
Clear TE bit in SCR to 0
TDRE = 1
All data transmitted?
TEND = 1
Break output?
Clear TDRE flag to 0
[1] SCI initialization:
The TxD pin is automatically
designated as the transmit data
output pin.
After the TE bit is set to 1, a
frame of 1s is output, and
transmission is enabled.
[2] SCI status check and transmit
data write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR. Set the
MPBT bit in SSR to 0 or 1.
Finally, clear the TDRE flag to 0.
[3] Serial transmission continuation
procedure:
To continue serial transmission,
be sure to read 1 from the TDRE
flag to confirm that writing is
possible, then write data to TDR,
and then clear the TDRE flag to
0.
[4] Break output at the end of serial
transmission:
To output a break in serial
transmission, set the port DDR to
1, clear DR to 0, then clear the
TE bit in SCR to 0.
Figure 10. 11 Sam p le Mult ip rocess o r Se rial Transmis s io n Flo wchart
Rev. 1.0, 02/02, page 252 of 502
10. 5. 2 Mul tiprocesso r Seri al Da ta Recepti o n
Figure 10. 13 shows a sampl e flowcha rt for mul tiprocessor serial data reception. If t he MPIE bit in
SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data
with a 1 multiproce ssor bit, the receive data is tra nsferred to RDR. An RXI interrupt reque st i s
generated at t hi s time. All ot he r SCI operations are t he same a s in asynchronous mode. Figure
10.12 shows an example of SCI operation for multiprocessor format reception.
MPIE
RDR
value
0D0 D1 D7 1 1 0 D0 D1 D7 0 1
11
Data (ID1)Start
bit MPB Stop
bit Start
bit Data (Data1) MPB Stop
bit
Data (ID2)Start
bit Stop
bit Start
bit Data (Data2) Stop
bit
RXI interrupt
request
(multiprocessor
interrupt)
generated
Idle state
(mark state)
RDRF
RDR data read
and RDRF flag
cleared to 0 in
RXI interrupt
service routine
If not this station’s ID,
MPIE bit is set to 1
again
RXI interrupt request is
not generated, and RDR
retains its state
ID1
(a) Data does not match station’s ID
MPIE
RDR
value
0D0 D1 D7 1 1 0 D0 D1 D7 0 1
11
MPB MPB
RXI interrupt
request
(multiprocessor
interrupt)
generated
Idle state
(mark state)
RDRF
RDR data read and
RDRF flag cleared
to 0 in RXI interrupt
service routine
Matches this station’s ID,
so reception continues, and
data is received in RXI
interrupt service routine
MPIE bit set to 1
again
ID2
(b) Data matches station’s ID
Data2ID1
MPIE = 0
MPIE = 0
Figure 10.12 Exampl e of SCI Ope r ation in Receptio n(Example wi th 8-Bit Data,
Multiprocessor Bit, One Stop Bit)
Rev. 1.0, 02/02, page 253 of 502
Yes
<End>
[1]
No
Initialization
Start reception
No
Yes
[4]
Clear RE bit in SCR to 0
Error processing
(Continued on
next page)
[5]
No
Yes
FER ORER = 1
RDRF = 1
All data received?
Read MPIE bit in SCR [2]
Read ORER and FER flags in SSR
Read RDRF flag in SSR [3]
Read receive data in RDR
No
Yes
This station’s ID?
Read ORER and FER flags in SSR
Yes
No
Read RDRF flag in SSR
No
Yes
FER ORER = 1
Read receive data in RDR
RDRF = 1
[1] SCI initialization:
The RxD pin is automatically designated
as the receive data input pin.
[2] ID reception cycle:
Set the MPIE bit in SCR to 1.
[3] SCI status check, ID reception and
comparison:
Read SSR and check that the RDRF
flag is set to 1, then read the receive
data in RDR and compare it with this
station’s ID.
If the data is not this station’s ID, set the
MPIE bit to 1 again, and clear the RDRF
flag to 0.
If the data is this station’s ID, clear the
RDRF flag to 0.
[4] SCI status check and data reception:
Read SSR and check that the RDRF
flag is set to 1, then read the data in
RDR.
[5] Receive error processing and break
detection:
If a receive error occurs, read the ORER
and FER flags in SSR to identify the
error. After performing the appropriate
error processing, ensure that the ORER
and FER flags are all cleared to 0.
Reception cannot be resumed if either
of these flags is set to 1.
In the case of a framing error, a break
can be detected by reading the RxD pin
value.
Figure 10.13 Sample Multiprocessor Serial Reception Flowchart (1)
Rev. 1.0, 02/02, page 254 of 502
<End>
Error processing
Yes
No
Clear ORER, and
FER flags in SSR to 0
No
Yes
No
Yes
Framing error processing
Overrun error processing
ORER = 1
FER = 1
Break?
Clear RE bit in SCR to 0
[5]
Figure 10.13 Sample Multiprocessor Serial Reception Flowchart (2)
Rev. 1.0, 02/02, page 255 of 502
10.6 Operation in Clocked Synchronous Mode
Figure 10. 14 shows the genera l format for cl ocked synchronous c ommunication. In clocked
synchronous mode, dat a is tra nsmitted or received synchronous with clock pulses. In clocked
synchronous serial com munication, data on the transm ission line is output from one falling edge of
the serial clock to the next. In clocked synchronous mode, the SCI receives dat a in synchronous
with the rising edge of the serial cl oc k. After 8-bit data i s output, the t ransmission line holds the
MSB state. In cl ocked synchronous mode, no parity or multiprocessor bit is a dded. Insi de the SCI,
the transmi tter and receiver are independent uni ts, ena bling full-duplex communication through
the use of a com mon clock. The transmi tt er and the receiver both hav e a double-bu ffered structure,
so data can be read or written duri ng transmi ssion or reception, enabl i ng continuous data transfer.
Don’t
care
Don’t
care
One unit of transfer data (character or frame)
Bit 0
Serial data
Synchronization
clock
Bit 1 Bit 3 Bit 4 Bit 5
LSB MSB
Bit 2 Bit 6 Bit 7
**
Note: * High except in continuous transfer
Figure 10.14 Data Format i n Synchronous Communication (for LSB-Fir st)
10.6.1 Clock
Either an inte rnal clock generated by the on-c hip baud rate genera tor or an external
synchronization clock input at t he SCK pi n can be selected, accordi ng to the setting of CKE0 and
CKE1 bits in SCR. When the SCI is operated on an internal clock, the serial clock is output from
the SCK pin. Eight serial clock pulses are output in the transfer of one character, and when no
transfer is performed the clock is fixe d high.
Rev. 1.0, 02/02, page 256 of 502
10. 6. 2 SCI Initiali z ati on (Clocked Synchro no us Mode)
Before transmitting and receiving data, the TE a nd RE bits i n SCR should be cleared to 0, then the
SCI should be initialized a s described i n a sample flowchart in Figure 10.15. When t he opera ting
mode, or transfer format, is changed for example, the TE and RE bits must be cleared to 0 before
making the change using the follow ing procedure. When the TE bit is cle ared to 0, the TDR E flag
is set to 1. Note that clearing the RE bit to 0 does not change the contents of the RDRF, PER,
FER, and ORER flags, or the contents of RDR.
Wait
<Transfer start>
Start initialization
Set data transfer format in
SMR and SCMR
No
Yes
Set value in BRR
Clear TE and RE bits in SCR to 0
[2]
[3]
Set TE and RE bits in SCR to 1, and
set RIE, TIE, TEIE, and MPIE bits [4]
1-bit interval elapsed?
Set CKE1 and CKE0 bits in SCR
(TE, RE bits 0) [1]
[1] Set the clock selection in SCR. Be sure
to clear bits RIE, TIE, TEIE, MPIE, TE,
and RE to 0.
[2] Set the data transfer format in SMR and
SCMR.
[3] Write a value corresponding to the bit
rate to BRR. Not necessary if an
external clock is used.
[4] Wait at least one bit interval, then set
the TE bit or RE bit in SCR to 1.
Also set the RIE, TIE TEIE, and MPIE
bits.
Setting the TE and RE bits enables the
TxD and RxD pins to be used.
Note: In simultaneous transmit and receive operations, the TE and RE bits should both be cleared
to 0 or set to 1 simultaneously.
Fi g ure 10.15 Sample SCI Initi alizati o n Flowc hart
Rev. 1.0, 02/02, page 257 of 502
10.6.3 Serial Data Transmission (Clocked Sync hronous Mode)
Figure 10. 16 shows an exa m ple of SCI operation for tra nsmission i n clocked synchronous mode.
In serial transmission, the SCI operates as described below.
1. The SCI monitors the TDRE flag in SSR, and if the flag is 0, the SCI recognizes that data has
been written to TDR, and transfers the data from TDR to TSR.
2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
transmission. If the TIE bit in SCR is set to 1 at this t ime, a t ransmit data em pty interrupt
(TXI) is generated . Continuous trans mission is possible because th e TXI interrup t rout ine
writes the next transmit data to TDR before transmission of the current transmit data has been
completed.
3. 8-bit data is sent from the TxD pin synchronized with the output cloc k when output clock
mode has been spec ified, and sync hronized with the input clock when use of an ext ernal c l ock
has been specified.
4. The SCI checks the TDRE flag at the timing for sending the MSB (bit 7).
5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission
of the next frame is started.
6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TDRE flag maintains the
output sta te of t he last bit. If the TEIE bit in SCR is set to 1 at this time, a TEI i nterrupt request
is generated. T he SCK pin is fixed high.
Figure 10. 17 shows a sampl e flow cha rt for serial data transmi ssion. Even i f the T DRE flag is
cleared to 0, transmi ssion wil l not start while a receive error flag (ORER, FER, or PER) is set to 1.
Make sure t hat the receive error flags are cleared to 0 before sta rting transmission. Note that
clearing the RE bit to 0 does not c lear t he receive error fla gs.
Rev. 1.0, 02/02, page 258 of 502
Transfer direction
Bit 0
Serial data
Synchronization
clock
1 frame
TDRE
TEND
Data written to TDR
and TDRE flag cleared
to 0 in TXI interrupt
service routine
TXI interrupt
request generated
Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
TXI interrupt
request generated TEI interrupt request
generated
Fi g ure 10.16 Sample SCI Tra nsmissi o n Opera tion in Clocked Synchr o no us Mode
Rev. 1.0, 02/02, page 259 of 502
No
<End>
[1]
Yes
Initialization
Start transmission
Read TDRE flag in SSR [2]
Write transmit data to TDR and
clear TDRE flag in SSR to 0
No
Yes
No
Yes
Read TEND flag in SSR
[3]
Clear TE bit in SCR to 0
TDRE = 1
All data transmitted?
TEND = 1
[1] SCI initialization:
The TxD pin is automatically
designated as the transmit data output
pin.
[2] SCI status check and transmit data
write:
Read SSR and check that the TDRE
flag is set to 1, then write transmit data
to TDR and clear the TDRE flag to 0.
[3] Serial transmission continuation
procedure:
To continue serial transmission, be
sure to read 1 from the TDRE flag to
confirm that writing is possible, then
write data to TDR, and then clear the
TDRE flag to 0.
Figure 10.17 Sample Serial Transmission Flowchar t
Rev. 1.0, 02/02, page 260 of 502
10.6.4 Serial Data Reception (Clocked Synchronous Mode)
Figure 10. 18 shows an exa m ple of SCI operation for rec eption i n clocked synchronous mode. In
serial reception, the SCI operates as described below.
1. The SCI perform s int e rnal initialization synchronous wit h a synchronous clock input or output,
starts receiving data, and stores the received data in RSR.
2. If an overrun error occ urs (when reception of the ne xt data is com pleted while the RDRF flag
in SSR is still set to 1), the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this
time, an ERI interrupt re quest is generated, receive data is not transfe rre d to RDR, and the
RDRF fla g remains to be set to 1.
3. If reception is completed successfully, the RDRF bit in SSR is set to 1, and receive data is
transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is
generated. Conti nuous reception is possible because the RXI interrupt routine reads t he receive
data transfe rred to RDR before rec eption of the next receive da ta has fi nished.
Bit 7
Serial data
Synchronization
clock
1 frame
RDRF
ORER
ERI interrupt request
generated by overrun
error
RXI interrupt
request generated
RDR data read and
RDRF flag cleared
to 0 in RXI interrupt
service routine
RXI interrupt
request
generated
Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
Figure 10.18 Exampl e of SCI Ope r ation in Receptio n
Reception cannot be resume d whil e a re ceive error flag is set to 1. Accordingl y, clear the ORER,
FER, PER, and RDRF bits to 0 before resumi ng reception. Figure 10.19 shows a sample flow
chart for serial data reception.
Rev. 1.0, 02/02, page 261 of 502
Yes
<End>
[1]
No
Initialization
Start reception
[2]
No
Yes
Read RDRF flag in SSR [4]
[5]
Clear RE bit in SCR to 0
Error processing
(Continued below)
[3]
Read receive data in RDR, and
clear RDRF flag in SSR to 0
No
Yes
ORER = 1
RDRF = 1
All data received?
Read ORER flag in SSR
<End>
Error processing
Overrun error processing
Clear ORER flag in SSR to 0
[3]
[1] SCI initialization:
The RxD pin is automatically
designated as the receive data input
pin.
[2] [3] Receive error processing:
If a receive error occurs, read the
ORER flag in SSR, and after
performing the appropriate error
processing, clear the ORER flag to 0.
Transfer cannot be resumed if the
ORER flag is set to 1.
[4] SCI status check and receive data
read:
Read SSR and check that the RDRF
flag is set to 1, then read the receive
data in RDR and clear the RDRF flag
to 0.
Transition of the RDRF flag from 0 to 1
can also be identified by an RXI
interrupt.
[5] Serial reception continuation
procedure:
To continue serial reception, before
the MSB (bit 7) of the current frame is
received, reading the RDRF flag,
reading RDR, and clearing the RDRF
flag to 0 should be finished.
Figure 10.19 Sample Serial Reception Flowchart
Rev. 1.0, 02/02, page 262 of 502
10. 6. 5 Simulta neous Serial Data Transm i ssion a nd Reception ( Cloc ked Synchronous
Mode)
Figure 10. 20 shows a sampl e flowcha rt for simultaneous se rial transmit and receive operations.
The following procedure shoul d be used for sim ultaneous serial data tra nsmit and receive
operation s . To sw itch from tran s mit mode to simultaneo u s tr ansmi t an d re ceive mod e, after
che ck ing tha t th e SCI has fi n is h ed transmission and th e TD R E and TEND f lag s are s et to 1 , cl ear
TE to 0. Then simultaneously set TE and RE to 1 with a single instruction. To switch from receive
mode to simultaneous transmit and receive mode, after checking that the SCI has finished
reception, clear RE to 0. Then aft er checking t hat the RDRF a nd receive error fla gs (ORER, FER,
and PER) are cleared to 0, simultaneously set TE and RE to 1 with a single instruction.
Rev. 1.0, 02/02, page 263 of 502
Yes
<End>
[1]
No
Initialization
Start transmission/reception
[5]
Error processing
[3]
Read receive data in RDR, and
clear RDRF flag in SSR to 0
No
Yes
ORER = 1
All data received?
[2]
Read TDRE flag in SSR
No
Yes
TDRE = 1
Write transmit data to TDR and
clear TDRE flag in SSR to 0
No
Yes
RDRF = 1
Read ORER flag in SSR
[4]
Read RDRF flag in SSR
Clear TE and RE bits in SCR to 0
[1] SCI initialization:
The TxD pin is designated as the
transmit data output pin, and the RxD
pin is designated as the receive data
input pin, enabling simultaneous
transmit and receive operations.
[2] SCI status check and transmit data
write:
Read SSR and check that the TDRE
flag is set to 1, then write transmit
data to TDR and clear the TDRE flag
to 0.
Transition of the TDRE flag from 0 to
1 can also be identified by a TXI
interrupt.
[3] Receive error processing:
If a receive error occurs, read the
ORER flag in SSR, and after
performing the appropriate error
processing, clear the ORER flag to 0.
Transmission/reception cannot be
resumed if the ORER flag is set to 1.
[4] SCI status check and receive data
read:
Read SSR and check that the RDRF
flag is set to 1, then read the receive
data in RDR and clear the RDRF flag
to 0. Transition of the RDRF flag from
0 to 1 can also be identified by an RXI
interrupt.
[5] Serial transmission/reception
continuation procedure:
To continue serial transmission/
reception, before the MSB (bit 7) of
the current frame is received, finish
reading the RDRF flag, reading RDR,
and clearing the RDRF flag to 0.
Also, before the MSB (bit 7) of the
current frame is transmitted, read 1
from the TDRE flag to confirm that
writing is possible. Then write data to
TDR and clear the TDRE flag to 0.
Note: When switching from transmit or receive operation to simultaneous
transmit and receive operations, first clear the TE bit and RE bit to 0,
then set both these bits to 1 simultaneously.
Figure 10.20 Sample Flowc hart of Simul taneous Serial Transmit and Receive O perations
Rev. 1.0, 02/02, page 264 of 502
10.7 Operation in Smart Card Interface
The SCI supports an IC ca rd (Sma rt Card) interface tha t conform s to ISO/IEC 7816-3
(Identification Card) as a serial com m unication i nterface e xtension function. Switching between
the normal serial communication interface and the Smart Card interface mode is carried out by
means of a register setting.
10.7.1 Pin Connec tion Example
Figure 10. 21 shows an exa m ple of c onnection with the Sma rt Card. In comm unication wit h an IC
card, as both transmission and reception are carried out on a single data transmission line, the TxD
pin and RxD pin should be connected to the LSI pin. The data transmission line should be pulled
up to the VCC power suppl y with a resistor. If an IC card is not connected, and the T E and RE bits
are both set to 1, closed transmission/reception is possible, enabling self-diagnosis to be carried
out. When the clock ge nerated on the Smart Card interface is used by an IC card, the SCK pin
output is input to the CLK pin of the IC card. This LSI port output is used as the reset signal.
TxD
RxD
This LSI
V
CC
I/O
Connected equipment
IC card
Data line
Clock line
Reset line
CLK
RST
SCK
Rx (port)
Figure 10.21 Schematic Diagr am of Smar t Car d Interface Pi n Connections
Rev. 1.0, 02/02, page 265 of 502
10.7.2 Data Format (Exc ept for Block Transfer Mode)
Figure 10. 22 shows the transfer data format in Sma rt Card interfa ce mode.
• One frame consists of 8-bit data plus a parity bit i n async hronous m ode.
• In transmission, a guard time of at least 2 etu (Elementary Time Unit: the time for transfer of
one bit) is left between the end of the parity bit and the start of the next frame.
• If a parity error is detected during reception, a low error signal level is output for one e tu
period, 10.5 etu after the start bit.
• If an error signal is sampled during t ransmission, the same data is ret ransmitted a ut omatically
after a delay of 2 etu or l onger.
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
When there is no parity error
Transmitting station output
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
When a parity error occurs
Transmitting station output
DE
Receiving station
output
: Start bit
: Data bits
: Parity bit
: Error signal
Legend
DS
D0 to D7
Dp
DE
Figure 10.22 Normal Smart Car d Interfac e Data Format
Data transfer with othe r types of IC c ards (di rect convent i on and inve rse convent ion) are
performed as described i n the following.
Ds
AZZAZZ ZZAA(Z) (Z) State
D0 D1 D2 D3 D4 D5 D6 D7 Dp
Fi g ure 10.23 Direct Co nvent i o n (SDIR = SINV = O/
(
(
= 0)
Rev. 1.0, 02/02, page 266 of 502
With the direction convention type IC and the above sample start character, the logic 1 level
corresponds to state Z and the logic 0 leve l to state A, and tra nsfer is performed in L SB-first order.
The start character data above is H'3B. For the direct convention type, clear the SDIR and SINV
bits in SCMR to 0. According to Smart Card regulations, clear the O/
(
bit in SMR to 0 to select
even parity mode.
Ds
AZZAAA ZAAA(Z) (Z) State
D7 D6 D5 D4 D3 D2 D1 D0 Dp
Fi g ure 10.24 Inver se Convent i o n (SDIR = SINV = O/
(
(
= 1)
With the inverse convention type, the logic 1 level corresponds t o state A a nd the l ogic 0 level to
state Z, and transfer is pe rformed i n MSB-first orde r. The start c haracter da ta for the above is
H'3F. For the inverse convention type, set the SDIR and SINV bits in SCMR to 1. According to
Smart Card regulations, even parity mode is the logic 0 level of the parity bit, and corresponds to
state Z. In this L SI, the SINV bit i nverts only data bits D0 to D7. Therefore, se t the O/
(
bit in
SMR to 1 to invert the parity bit for both transmission and reception.
10.7.3 Block Transfer Mode
Operation in block t ransfer mode is the same as that in SCI asynchronous m ode, e xcept for the
following points.
• In reception, though the pa rity check i s performed, no error signal i s output eve n if an e rror i s
detected. However, the PER bit in SSR is set to 1 and must be cleared before receiving the
parity bit of the next frame.
• In transmission, a guard time of at least 1 etu is left between the end of the parity bit and the
start of the next frame.
• In transmi ssion, because retransmission is not performed, the TEND flag is set to 1, 11.5 et u
after transmission start.
• As with the norma l Smart Card int erface, t he ERS fla g indica tes the error signal status, but
since error signal tra nsfer is not performed, thi s flag is al ways cl eared to 0.
Rev. 1.0, 02/02, page 267 of 502
10.7.4 Receive Data Sampling Timing and Reception Margin in Smart Card Interface
Mode
In Smart Card interface m ode, the SCI operates on a basic clock wit h a frequency of 32, 64, 372,
or 256 times the tra nsfer ra te (fixed at 16 times in normal asynchronous m ode) as determined by
bits BCP1 and BCP0. In reception, the SCI samples the falling edge of the start bit using the basic
clock, and performs internal synchronization. As shown in Figure 10.25, by sa m pling re ceive data
at the ri sing-edge of t he 16th, 32nd, 186t h, or 128th pulse of the basic clock, data ca n be latched at
the middle of the bit. The reception ma rgin is give n by the following form ula.
M = | (0.5 – ) – (L – 0.5) F – (1 + F) | 100%
1
2N | D – 0.5 |
N
Where M: Reception margin (%)
N: Ratio of bit rat e to cl ock (N = 32, 64, 372, and 256)
D: Clock duty (D = 0 t o 1.0)
L: Frame length (L = 10)
F: Absolute value of clock frequency deviation
Assum i n g valu e s of F = 0, D = 0.5 an d N = 372 in the above formula , the rec epti on margi n
formula is as follows.
M = (0.5 – 1/2 × 372) × 100%
= 49.866%
Internal
basic clock
372 clocks
186 clocks
Receive data
(RxD)
Synchronization
sampling timing
D0 D1
Data sampling
timing
185 371 0
371
185 0
0
Start bit
Figure 10.25 Receive Data Sampling Timing in Smart Card Mode
(Using Cl ock of 372 Times t he Transfer Rate )
Rev. 1.0, 02/02, page 268 of 502
10.7.5 Initialization
Before transmitting and receiving data, initialize the SCI as described below. Initialization is also
necessary when switching from transmit mode to receive mode, or vice versa.
1. Clear the TE and RE bits in SCR to 0.
2. Clear the e rror flags ERS, PER, and ORE R in SSR t o 0.
3. Se t the GM, BLK, O/
(
, BCP0, BCP1, CKS0, CKS1 bit s in SMR. Set the PE bit to 1.
4. Se t the SMIF, SDI R, and SINV bit s in SCMR.
When the SMIF bi t is set to 1, t he TxD and RxD pi ns are both switched from ports to SCI pi ns,
and are placed in the high-impedance sta te.
5. Set the value corr esponding to the bit rate in BRR.
6. Set the CKE0 and CKE1 bits in SCR. Clear the TIE, RIE, TE, RE, MPIE, and TEIE bits to 0.
If the CKE0 bit is set to 1, the clock is output from the SCK pin.
7. Wait at least one bit interval, then set the TIE, RIE, TE, and RE bits in SCR. Do not set the TE
bit and RE bit at the same time, except for self-diagnosis.
To switch from receive mode to transmit mode, after checking that the SCI has finished reception,
initialize the SCI, and set RE to 0 and TE to 1. Whether SCI has finished reception or not can be
checked with the RDRF, PER, or ORER flags. To switch from transmit mode to receive mode,
after checking that the SCI has finished transmission, initialize the SCI, and set TE to 0 and RE to
1. Whether SCI has finished transmission or not can be checked with the TEND flag.
10.7.6 Data Tr ansmission (Except for Block Transfer M ode)
As data transmission in Smart Card interface mode involves error signal sampling and
retransmission processing, the operations are different from those in normal serial communication
interface mode (except for block transfer mode). Figure 10.26 illustrates the retransfer operation
when the SCI is in transmit mode.
1. If an error signal is sent back from the receiving end after transmi ssion of one frame is
complete, the ERS bit in SSR is set to 1. If the RIE bit in SCR is enabled at this time, an ERI
interrupt re quest is gene rated. The ERS bi t in SSR should be kept c leared to 0 until the ne xt
parity bit i s sam pled.
2. The TEND bi t in SSR is not set for a frame i n whic h an error signal i ndicating a n abnormality
is received. Data is retransf err ed from TDR to TSR , and retransmi tted automatically.
3. If an error signal is not sent back from the receiving end, t he ERS bit in SSR is not set.
Transmission of one frame, including a retransfer, is judged to have been completed, and the
TEND bit in SSR is set to 1. If the TIE bit in SCR is enabled at this time, a TXI interrupt
request is g en erated. Writin g tr ansmit data to TDR tr ansfers the n ext transmit data.
Rev. 1.0, 02/02, page 269 of 502
Figure 10. 28 shows a flowcha rt for tra nsmission. In a transmit operation, the T DRE flag is set to 1
at the same time as the TEND flag in SSR is set, and a TXI interrupt will be generated if the TIE
bit in SCR has been set to 1. In the event of an error, the SCI retransmits the same data
automatically. During thi s period, the TEND flag re mains cleared to 0. Therefore, t he SCI and
DTC wi l l automatically transmi t the specified numbe r of bytes i n the event of a n error, including
retransmission. However, the ERS flag is not cleared automatically whe n an error occurs, and so
the RIE bit should be set to 1 beforeha nd so that an ERI re quest wi ll be generated in the event of
an error, and the ERS flag will be cleared.
D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (DE) Ds D0 D1 D2 D3 D4Ds
Transfer
frame n+1
Retransferred framenth transfer frame
TDRE
TEND
[1]
FER/ERS
Transfer to TSR from TDR Transfer to TSR from TDR Transfer to TSR
from TDR
[2] [3]
[3]
Fi g ure 10 .26 Retransf er Oper at i o n in SCI Transmi t Mode
Rev. 1.0, 02/02, page 270 of 502
The timing for setting the TEND flag depends on the value of the GM bit in SMR. The TEND
flag set timing is shown in Figure 10.27.
Ds D0 D1 D2 D3 D4 D5 D6 D7 DpI/O data
12.5 etu
TXI
(TEND interrupt)
11.0 etu
DE
Guard
time
When GM = 0
When GM = 1
: Start bit
: Data bits
: Parity bit
: Error signal
Legend
Ds
D0 to D7
Dp
DE
Figure 10.27 TEND Flag Gen eration Timing in Transm iss ion Ope ration
Rev. 1.0, 02/02, page 271 of 502
Initialization
No
Yes
Clear TE bit to 0
Start transmission
Start
No
No
No
Yes
Yes
Yes
Yes
No
End
Write data to TDR,
and clear TDRE flag
in SSR to 0
Error processing
Error processing
TEND = 1?
All data transmitted ?
TEND = 1?
ERS = 0?
ERS = 0?
Figure 10.28 Example of Transmission Processing F low
Rev. 1.0, 02/02, page 272 of 502
10.7.7 Serial Data Reception (Except for Block Transfer Mode)
Data reception i n Smart Card interface mode uses the same operation procedure as for normal
serial com munication i nterface mode. Figure 10.29 illust rates the retransfer operation when the
SCI is in receive mode.
1. If an error i s found when t he received pari ty bit i s checke d, the PER bit in SSR is
automatically set to 1. If the RIE bit in SCR is set at thi s time, an ERI interrupt request i s
generated. The PER bit in SSR should be kept cleared to 0 until the next parity bit is sampled.
2. The RDRF bit i n SSR is not set for a frame in which an error has occurred.
3. If no error is found when the received pa rity bit is checke d, the PER bi t in SSR is not set to 1,
the receive ope ration is judged to have been completed normally, and the RDRF flag in SSR is
automatically set to 1. If the RIE bit in SCR is enabled at this time, an RXI interrupt request is
generated.
Figure 10. 30 shows a flowcha rt for reception. In a re ceive opera tion, an RXI inte rrupt reque st is
generated when the RDRF fla g in SSR i s set to 1. If an e rror oc curs in receive mode a nd the
ORER or PER flag is set t o 1, a transfer error interrupt (ERI) request wil l be gene rated. Henc e, so
the error flag must be cleared to 0. Even when a parity error occurs in receive mode and the PER
flag is set to 1, the data that has been received is transferred to RDR and can be read from there.
Note: For details on receive operations in block transfer mode, refer to section 10.4, Operation in
Asynchronous Mode.
D0 D1 D2 D3 D4 D5 D6 D7 Dp DE Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp (DE)Ds D0 D1 D2 D3 D4Ds
Transfer
frame n+1
Retransferred framenth transfer frame
RDRF
[1]
PER
[2]
[3]
[3]
Fi g ure 10 .29 Retransf er Oper at i o n in SCI Receive Mode
Rev. 1.0, 02/02, page 273 of 502
Initialization
Read RDR and clear
RDRF flag in SSR to 0
Clear RE bit to 0
Start reception
Start
Error processing
No
No
No
Yes
Yes
ORER = 0 and
PER = 0
RDRF = 1?
All data received?
Yes
Figure 10.30 Example of Reception Pr ocessing Flow
10.7.8 Clock Ou t p ut Control
When the GM bit in SMR is set to 1, the clock output level can be fixed with bits CKE0 and
CKE1 in SCR. At this time, the minimum clock pulse width can be made the specified width.
Figure 10. 31 shows the timi ng for fixing the c lock output level. In this example, GM is set to 1,
CKE1 is cleared to 0, and the CKE0 bit is controlled.
Specified pulse width
SCK
CKE0
Specified pulse width
Figure 10.31 Timing for Fixing Clock Output Le vel
Rev. 1.0, 02/02, page 274 of 502
When turning on the pow er or switc hing between Smart Card interf ac e mod e and softw are
standby mode, the fol lowing proce dures should be followed in order to maintain the clock duty.
Powering On: To secure clock duty from power-on, the followi ng switching procedure shoul d be
followed.
1. The initial state is port input and high impedance. Use a pull-up resistor or pull-down resistor
to fix the potential.
2. Fix the SCK pin to the specified output level with the CKE1 bit in SCR.
3. Set SMR and SCMR, and switch to smart card mode operation.
4. Set the CKE0 bit in SCR to 1 to start clock output.
When Changing from Smart Card Interface Mode to Software Standby M ode :
1. Set the data register (DR) and data direction re gi ster (DDR) corresponding to the SCK pi n to
the value for the fixed output sta t e in software standby m ode.
2. Write 0 to t he TE bit and RE bit in the seri al control register (SCR) to hal t transmit/receive
operation. At the same time, set the CKE1 bit to the value for t he fixed output state in software
standby mode.
3. Write 0 to the CKE0 bit in SCR to halt the clock.
4. Wait for one serial clock peri od.
During this interval, clock output is fixed at the specified level, with the duty preserved.
5. Make the transition to the software standby state.
When Returni ng to Smart Card Interf ace Mode fr om Software Sta ndby Mode:
1. Exit the software standby state.
2. Write 1 to the CKE0 bit in SCR and output the clock. Signal generation is started with the
normal duty.
[1] [2] [3] [4] [5] [7]
Software
standby
Normal operation Normal operation
[6]
Figure 10.32 Clock Halt and Restart Procedure
Rev. 1.0, 02/02, page 275 of 502
10.8 Interrupts
10.8.1 Interrupts in Normal Serial Communication Inte rface Mode
Table 10.12 shows the interrupt sources in normal serial communication interface mode. A
different i nterrupt ve ctor is a ssigned to ea ch interrupt source, and indi vidual i nterrupt sources can
be enabled or disabled using the enable bits in SCR.
When the TDRE flag in SSR i s set to 1, a TXI interrupt request is generated. When the TEND flag
in SSR i s set to 1, a TEI interrupt re quest is gene rated.
When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER,
PER, or FER flag i n SSR is set to 1, an ERI interrupt request is generated.
A TEI interrupt is requested when the T END fla g is se t to 1 a nd the TEIE bi t is set to 1. If a TEI
interrupt and a TXI i nterrupt are requeste d simultaneously, the T XI interrupt has priori ty for
acceptance. However, if the TDRE and TEND flags are cleared simultaneously by the TXI
interrupt routine, the SCI cannot branch t o the TEI interrupt routine later.
Tabl e 10. 12 SCI Inter r upt Source s
Channel Name Interrupt Source I nt errupt Flag
ERI0 Receiv e Err or O RER, FER, PER
RXI0 Receiv e Data Full RDRF
TXI0 Tra nsm it Da ta Empty TDRE
0
TEI0 Tr ansmission End TEND
ERI1 Receiv e Err or O RER, FER, PER
RXI1 Receiv e Data Full RDRF
TXI1 Tra nsm it Da ta Empty TDRE
1
TEI1 Tr ansmission End TEND
Rev. 1.0, 02/02, page 276 of 502
10. 8. 2 Interr upts in Smart Car d Interfa ce Mode
Table 10. 13 shows the i nterrupt sourc e s in Smart Card interface m ode. The transmit end interrupt
(TEI) request c annot be used i n this mode.
Tabl e 10. 13 SCI Inter r upt Source s
Channel Name Int errupt Source Interrupt Flag
ERI0 Receiv e Err or , dete ct ion O RER, PER, ERS
RXI0 Receiv e Data Full RDRF
0
TXI0 Transmit Data Empty TEND
ERI1 Receiv e Err or , dete ct ion O RER, PER, ERS
RXI1 Receiv e Data Full RDRF
1
TXI1 Transmit Data Empty TEND
In transmit operations, the TDRE flag is also set to 1 at the same time as the TEND flag in SSR is
set, and a TXI interrupt i s gene rated. In t he event of an error, the SCI retransmits the same data
automatically. During this period, the TEND flag remains cleared to 0. The ERS flag is not cleared
automatically when an error occurs. He nce, the RIE bit shoul d be set to 1 beforehand so that an
ERI reque st will be gene rated i n the e vent of a n error, and the ERS fla g wil l be c leared.
In receive operations, a n RXI interrupt request is generated when t he RDRF flag in SSR is set to
1. If a n error occ urs, an error flag is set but t he RDRF fl a g is not. An E RI interrupt reque st is sent
to the CPU. Therefore, the error flag should be cleared.
10.9 Usage Notes
10.9.1 Module Stop Mode Setti ng
SCI operation can be disabled or enabled using the module stop control register. The initial setting
is for SCI operation to be halted. Register access is enabled by clearing module stop mode. For
details, refer to section 19, Power-Down Modes.
10.9.2 Break Detection and Processing
When framing error detection is performed, a break ca n be detected by reading the RxD pin value
directly. In a break, the input from the RxD pin becomes all 0s, setting the FER flag, and possibly
the PER flag. Note that as the SCI continues the receive operation after receiving a break, even if
the FER flag is cleared to 0, it will be set to 1 again.
Rev. 1.0, 02/02, page 277 of 502
10.9.3 Mark State and Bre ak Detection
When TE is 0, the TxD pin is used as an I/O port whose dire ction (i nput or output) and level are
determined by DR and DDR. This can be used to set the TxD pin to mark state (high level) or send
a break during serial data transmission. To maintain the communication line at mark state until TE
is set to 1, set both DDR and DR to 1. As TE is cleared to 0 at this point, the TxD pin becomes an
I/O port, and 1 is output from t he TxD pin. To send a break during serial tra nsmission, first set
DDR to 1 and DR to 0, and then clear TE to 0. When TE is cleared to 0, the transmitter is
initialized regardless of the current transmission state, the TxD pin becomes an I/O port, and 0 is
output from the TxD pin.
10.9.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)
Transmission cannot be started whe n a rec eive e rror flag (ORER, PER, or FER) is set to 1, even i f
the TDR E fl ag is clear ed to 0. Be sure to clear the receiv e error flags to 0 before starting
trans mis s ion. Note als o that rece ive error flags cannot be cleared to 0 even if the R E bit is cle ared
to 0.
Rev. 1.0, 02/02, page 278 of 502
Rev. 1.0, 02/02, page 279 of 502
Section 11 Hitachi Controller Area Network (HCAN)
The HCAN is a module for controlling a controller area network (CAN) for realtime
communication in vehicular and industrial equipment systems, etc. For details on CAN
specification, refer t o Bosch CAN Spec ification Version 2.0 1991, Robert Bosch GmbH.
The block diagram of the HCAN is shown in figure 11. 1.
11.1 Features
• CA N version: Bosch 2.0 B active compatible
Communication systems: NRZ (Non-Re t urn t o Zero) system (with bit-stuffi ng func tion)
Broadcast communication syst em
Transmission path: Bidirectional 2-wire serial communication
Communication spee d: Max. 1 Mbps
Data length: 0 to 8 bytes
• Number of channels: 1
• Data buffe rs: 16 (one receive-only buffer and 15 buffers settable for transmission/reception)
• Data transmission: Two methods
Mailb ox (buffer) number ord er (low-to-high)
Message priority (identifier) re verse-order (high-to-low)
• Data re ception: Two methods
Message ide ntifier match (t ransmit/receive-se tting buffe rs)
Reception with message identifier masked (receive-only)
• CPU int errupts: 12
Error interrupt
Reset proc e ssing i nterrupt
Message rec eption i nterrupt
Message tra nsmission i nterrupt
• HCAN operating mode s
• Support for various modes
Hardware reset
Soft wa re reset
Normal st atus (error-active, error-passive)
Bus off status
HCAN configuration mode
HCAN slee p mo de
HCAN hal t mode
IFCAN00B_000020020200
Rev. 1.0, 02/02, page 280 of 502
• Module stop mode can be set
Peripheral address bus
Peripheral data bus
HTxD
MBI
HRxD
CAN
Data Link Controller
MPI
(CDLC)
Tx buffer
Rx buffer
Message buffer
Message control
Message data
MC0–MC15, MD0–MD15 LAFM
Mailboxes
Microprocessor interface
CPU interface
Control register
Status register
HCAN
Bosch CAN 2.0B active
Figure 11.1 HCAN Block Diagram
• Message Buffer Interface (MBI)
The MBI, consisting of mailboxes and a local acceptance filter mask (LAFM) , st ore s CAN
transmit/received messages (identifiers, data, etc.) Transmit messages are written by the CPU.
For received messages, the data received by the CDLC is stored automatically.
• Microproce ssor Interface (MPI)
The MPI, consisting of a bus interface, control register, status register, etc., controls HCAN
internal data, status, and so forth.
• CAN Data Link Controller (CDLC)
The CDLC transmits and receives of messages conform ing to the Bosch CAN Ver. 2.0B active
standard (data frames, remote frames, error frames, overl oad fram es, inter-frame spac ing), as
well as CRC checking, bus arbitrati on, and other functions.
Rev. 1.0, 02/02, page 281 of 502
11.2 Input/Output Pins
Ta ble 11. 1 shows t he HCAN's pin s.
When using HCAN pins, settings m ust be ma de in the HCAN c onfiguration mode (during
initialization: MCR0 = 1 and GSR3 = 1).
Table 11. 1 Pin Configuration
Name Abbreviation Input/Output Function
HCAN transmit data pin HTxD O utput CAN bus transmission pin
HCAN receive dat a pin HRxD Input CAN bus reception pin
A bus driver is necessary for the interface between the pins and the CAN bus. A Philips
PCA82C250 compatible model is re commended.
11.3 Register Descrip t i on s
The HCAN has the following registers.
• Master cont rol register (MCR)
• Gene ral st at us registe r (GSR)
• Bit configuration regi ster (BCR)
• Mailbox configuration register (MBCR)
• Transmit wait register (TXPR)
• Transmit wait cancel register (TXCR)
• Transmit acknowledge register (TXACK)
• Abort acknowle dge regist er (ABACK)
• Receive complete register (RXPR)
• Remote reque st re gi ster (RFPR)
• Interrupt registe r (IRR)
• Mailbox interrupt mask register (MBIMR)
• Interrupt mask register (IMR)
• Receive error count er (REC)
• Transmi t error counter (T EC)
• Unread me ssa ge statu s reg i ste r (UMSR)
• Loca l accep ta nce filter mask H (LAFMH)
• Loca l accep ta nce filter mask L (LAFML)
• Message control (8-bit × 8 regi ster s × 16 sets) (MC0 to MC15)
• Message data (8-bit × 8 registers × 16 sets) (MD0 to MD15)
Rev. 1.0, 02/02, page 282 of 502
11.3.1 Master Control Register (MCR)
MCR controls the HCAN.
Bit Bit Name Initial Value R/W Descri ption
7 MCR7 0 R/W HCAN Sleep Mode Release
Whe n th is bit is set to 1, th e HCAN automat ic ally
exits HCAN sleep mode on detection of CAN bus
operation.
6— 0 R Reserved
This bit is always read as 0. Only 0 should be
written to this bit.
5 MCR5 0 R/W HCAN Sleep Mode
When this bit is set to 1, the HCAN transits to
HCAN sleep m ode. When this bit is cleared to 0,
HCAN sleep m ode is r eleased.
4
3— 0 R Reserved
These bits are always read as 0. Only 0 should be
written to these bits.
2 MCR2 0 R/W Message Transmission Method
0: Transmission order determined by message
identifier pr ior ity
1: Transmission order determined by mailbox
(buffer) number priority (TXPR1 > TXPR15)
1 MCR1 0 R/W Halt Request
When this bit is set to 1, the HCAN transits to
HCAN HALT m ode. When this bit is cleared to 0,
HCAN HALT mode is released.
Rev. 1.0, 02/02, page 283 of 502
Bit Bit Name Initial Value R/W Descri ption
0 MCR0 1 R/W Reset Request
When this bit is set to 1, the HCAN transits to reset
mode. For details, refer to section 11.4.1,
Har d ware Re set an d Soft ware Reset.
[Setting condition s]
• Po w e r-on reset
• Hardware st andby
• Software standby
• 1-wr ite ( softwar e rese t )
[Clearing condition]
• When 0 is written to this bit while the GSR3 bit
in G SR is 1
11.3.2 G e neral Status Register (G SR)
GSR indi cates the status of the CAN bus.
Bit Bit Name Initial Value R/W Descri ption
7 to
4— 0 R Reserved
These bits are always read as 0. Only 0 should be
written to these bits.
3 GSR3 1 R Reset Status Bit
Indicates whether the HCAN m odule is in the
normal oper ating state or the reset state. This bit
cannot be modified.
[Setting condition s]
• When ent er ing conf iguration mode after the
HCAN internal reset has finished
• Sleep mode
[Clearing condition]
• When ent er ing nor mal operation mode af t er the
MCR0 bit in MCR is cleared to 0 (Note that
there is a delay between clearing of the M CR0
bit and t he GSR3 bit.)
Rev. 1.0, 02/02, page 284 of 502
Bit Bit Name Initial Value R/W Descri ption
2 GSR2 1 R Message Tran smission S tatus Flag
Flag that indicates whether the m odule is current ly
in the messa ge transmission period. This bit canno t
be modified.
[Setting condition]
• Start of message transm ission (SO F)
[Clearing condition]
• Interval of three bits after EO F (End of Frame)
1 GSR1 0 R Transmit/Receive Warning Flag
This bit cannot be modified.
[Clearing condition]
• When TEC < 96 and REC < 96 or TEC ≥ 256
[Setting condition]
• When TEC ≥ 96 or REC ≥ 96
0 GSR0 0 R Bus Off Flag
This bit cannot be modified.
[Setting condition]
• When TEC ≥ 256 (bus off st ate)
[Clearing condition]
• Recovery fr om bus off state
Rev. 1.0, 02/02, page 285 of 502
11. 3. 3 Bit Co nfigurat i o n Register (BCR)
BCR that is used to set HCAN bit timing parameters and the baud rate prescaler. For details on
parameters, refer to section 11.4.2, Initialization after Hardware Reset.
Bit Bit Name Initial Value R/W Descri ption
15 BCR7 0 R/W
14 BCR6 0 R/W
Re-Synch ronization Jump Widt h (SJW )
Set the maximum bit synchronization width.
00: 1 t im e quantum
01: 2 t im e quanta
10: 3 t im e quanta
11: 4 t im e quanta
13 BCR5 0 R/W
12 BCR4 0 R/W
11 BCR3 0 R/W
10 BCR2 0 R/W
9 BCR1 0 R/W
8 BCR0 0 R/W
Baud Rat e Prescaler ( BRP)
Set the length of time quanta.
000000: 2 × system clock
000001: 4 × system clock
000010: 6 × system clock
:
111111: 128 × system clock
7 BCR15 0 R/W Bit Sample Po int (BSP)
Sets the point at which dat a is sampled.
0: Bit sampling at one point (end of time segm ent 1
(TSEG1))
1: Bit sampling at three point s (end of TSEG1 and
preceding and following time quanta)
6 BCR14 0 R/W
5 BCR13 0 R/W
4 BCR12 0 R/W
Time S egment 2 (TSEG2)
Set the TSEG2 width with in a range of 2 to 8 time
quanta.
000: Setting prohibited
001: 2 time quant a
010: 3 time quant a
011: 4 time quant a
100: 5 time quant a
101: 6 time quant a
110: 7 time quant a
111: 8 time quant a
Rev. 1.0, 02/02, page 286 of 502
Bit Bit Name Initial Value R/W Descri ption
3 BCR11 0 R/W
2 BCR10 0 R/W
1 BCR9 0 R/W
0 BCR8 0 R/W
Time S egment 1 (TSEG1)
Set the TSEG1 (PRSEG + PHSEG1) width to
between 4 and 16 t ime quanta.
0000: Setting prohibited
0001: Setting prohibited
0010: Setting prohibited
0011: 4 time quanta
0100: 5 time quanta
0101: 6 time quanta
0110: 7 time quanta
0111: 8 time quanta
1000: 9 time quanta
1001: 10 t ime quanta
1010: 11 t ime quanta
1011: 12 t ime quanta
1100: 13 t ime quanta
1101: 14 t ime quanta
1110: 15 t ime quanta
1111: 16 t ime quanta
Rev. 1.0, 02/02, page 287 of 502
11.3.4 M ailbox Configuration Register (MBCR)
MBCR i s used t o set the transfer di rection for each mailbox.
Bit Bit Name Initial Value R/W Descri ption
15 MBCR7 0 R/W
14 MBCR6 0 R/W
13 MBCR5 0 R/W
12 MBCR4 0 R/W
11 MBCR3 0 R/W
10 MBCR2 0 R/W
9 MBCR1 0 R/W
8— 1 R
7 MBCR15 0 R/W
6 MBCR14 0 R/W
5 MBCR13 0 R/W
4 MBCR12 0 R/W
3 MBCR11 0 R/W
2 MBCR10 0 R/W
1 MBCR9 0 R/W
0 MBCR8 0 R/W
These bits set the transfer direction for the
corresponding mailboxes from 1 to 15. MBCRn
determines the transfer direction for mailbox n (n
=1 to 15).
0: Corresponding mailbox is set for transm ission
1: Corresponding mailbox is set for reception
Bit 8 is reserved. This bit is always read as 1 and
th e write value should alwa y s be 1.
Rev. 1.0, 02/02, page 288 of 502
11.3.5 Tr ansmit Wai t Register (TXPR)
TXPR i s used t o set a t ransmit wait after a tra nsmit m essage is stored in a m ailbox (buffer) (CAN
bus arbitration wait).
Bit Bit Name Initial Value R/W Descri ption
15 TXPR7 0 R/W
14 TXPR6 0 R/W
13 TXPR5 0 R/W
12 TXPR4 0 R/W
11 TXPR3 0 R/W
10 TXPR2 0 R/W
9 TXPR1 0 R/W
8— 0 R
7 TXPR15 0 R/W
6 TXPR14 0 R/W
5 TXPR13 0 R/W
4 TXPR12 0 R/W
3 TXPR11 0 R/W
2 TXPR10 0 R/W
1 TXPR9 0 R/W
0 TXPR8 0 R/W
These bits set a transm it wait (CAN bus arbitration
wait) for the correspondi ng mailboxes 1 to 15.
When TXPRn (n = 1 to 15) is set to 1, the message
in mailbox n becomes the transmit wait state.
[Clearing condit ions]
• Completion of message tr ansmission
• Completion of transm ission cancellation
Bit 8 is reserved. This bit is always read as 1 and
th e write value should alwa y s be 1.
Rev. 1.0, 02/02, page 289 of 502
11. 3. 6 Tra nsm i t Wait Cancel Regist e r (T XCR)
TXCR control s the cancellation of transmi t wait messages in mailboxe s (buffers).
Bit Bit Name Initial Value R/W Descri ption
15 TXCR7 0 R/W
14 TXCR6 0 R/W
13 TXCR5 0 R/W
12 TXCR4 0 R/W
11 TXCR3 0 R/W
10 TXCR2 0 R/W
9 TXCR1 0 R/W
8— 0 R
7 TXCR15 0 R/W
6 TXCR14 0 R/W
5 TXCR13 0 R/W
4 TXCR12 0 R/W
3 TXCR11 0 R/W
2 TXCR10 0 R/W
1 TXCR9 0 R/W
0 TXCR8 0 R/W
These bits cancel the transm it wait message in the
corresponding mailboxes 1 to 15. When TXCRn (n
= 1 to 15) is set to 1, the transmit wait message in
mailbox n is canceled.
[Clearing condition]
• Comp le tion of TXPR clearing wh en transmit
message is canceled normally
Bit 8 is reserved. This bit is always read as 0 and
th e write value should alwa y s be 0.
Rev. 1.0, 02/02, page 290 of 502
11. 3. 7 Tra nsm i t Ackno wledge Register (TXACK)
TXACK contains status flags that indicate the normal transmission of mailbox (buffer) transmit
messages.
Bit Bit Name Initial Value R/W Descri ption
15 TXACK7 0 R/(W)*
14 TXACK6 0 R/(W)*
13 TXACK5 0 R/(W)*
12 TXACK4 0 R/(W)*
11 TXACK3 0 R/(W)*
10 TXACK2 0 R/(W)*
9 TXACK1 0 R/(W)*
8— 0 R
7 TXACK15 0 R/(W)*
6 TXACK14 0 R/(W)*
5 TXACK13 0 R/(W)*
4 TXACK12 0 R/(W)*
3 TXACK11 0 R/(W)*
2 TXACK10 0 R/(W)*
1 TXACK9 0 R/(W)*
0 TXACK 0 R/(W)*
These bits are status flags that indicat e error-free
transmission of the transmit message in the
corresponding mailboxes 1 to 15. When the
message in mailbox n (n = 1 t o 15) has been
transmitted error-free, TXACKn is set to 1.
[Setting condition]
• Completion of message tr ansmission for
corresponding mailbox
[Clearing condition]
• Wr iting 1
Bit 8 is reserved. This bit is always read as 0 and
th e write value should alwa y s be 0.
Note: Only 0 for clearing the flag can be written.
Rev. 1.0, 02/02, page 291 of 502
11.3.8 Abort Acknowl e dge Regi ster (ABACK )
ABACK contains status flags that indicate the normal cancellation (aborting) of mailbox (buffer)
transmit messag es .
Bit Bit Name Initial Value R/W Descri ption
15 ABACK7 0 R/(W)*
14 ABACK6 0 R/(W)*
13 ABACK5 0 R/(W)*
12 ABACK4 0 R/(W)*
11 ABACK3 0 R/(W)*
10 ABACK2 0 R/(W)*
9 ABACK1 0 R/(W)*
8— 0 R
7 ABACK15 0 R/(W)*
6 ABACK14 0 R/(W)*
5 ABACK13 0 R/(W)*
4 ABACK12 0 R/(W)*
3 ABACK11 0 R/(W)*
2 ABACK10 0 R/(W)*
1 ABACK9 0 R/(W)*
0 ABACK8 0 R/(W)*
These bits are status flags that indicat e error-free
cancellation ( abortion) of the transmit message in
the corresponding mailboxes 1 to 15. When the
message in mailbox n (n = 1 t o 15) has been
canc e led erro r- fr e e, ABACKn is set to 1.
[Setting condition]
• Completion of transm it message cancellation
for corresponding mailbox
[Clearing condition]
• Wr iting 1
Bit 8 is reserved. This bit is always read as 0. The
write value should always be 0.
Note: Only 0 for clearing the flag can be written.
Rev. 1.0, 02/02, page 292 of 502
11.3.9 Receive Complete Register (RXPR)
RXPR contains status fla gs tha t indicate the normal reception of messages i n mailboxes (buffers).
For reception of a remote frame, when a bit in this registe r is se t to 1, the c orresponding rem ote
request register (RFPR) bit is also set to 1 simultaneously.
Bit Bit Name Initial Value R/W Descri ption
15 RXPR7 0 R/(W)*
14 RXPR6 0 R/(W)*
13 RXPR5 0 R/(W)*
12 RXPR4 0 R/(W)*
11 RXPR3 0 R/(W)*
10 RXPR2 0 R/(W)*
9 RXPR1 0 R/(W)*
8 RXPR0 0 R/(W)*
7 RXPR15 0 R/(W)*
6 RXPR14 0 R/(W)*
5 RXPR13 0 R/(W)*
4 RXPR12 0 R/(W)*
3 RXPR11 0 R/(W)*
2 RXPR10 0 R/(W)*
1 RXPR9 0 R/(W)*
0 RXPR8 0 R/(W)*
When the message in mailbox n (n = 0 to 15) has
been received error-free, RXPRn is set to 1.
[Setting condition]
• Completion of message ( data fram e or remote
frame) reception in corresponding mailbox
[Clearing condition]
• Wr iting 1
Note: Only 0 for clearing the flag can be written.
Rev. 1.0, 02/02, page 293 of 502
11.3.10 Remote Re quest Re gi ster (RFPR)
RFPR cont ains status flags tha t indicate norma l reception of remote frames i n mailboxes (buffers).
When a bit in thi s register is set to 1, the corresponding receive compl ete registe r (RXPR) bit is
also set to 1 simultaneously.
Bit Bit Name Initial Value R/W Descri ption
15 RFPR7 0 R/(W)*
14 RFPR6 0 R/(W)*
13 RFPR5 0 R/(W)*
12 RFPR4 0 R/(W)*
11 RFPR3 0 R/(W)*
10 RFPR2 0 R/(W)*
9RFPR1 0 R/(W)
*
8RFPR0 0 R/(W)
*
7 RFPR15 0 R/(W)*
6 RFPR14 0 R/(W)*
5 RFPR13 0 R/(W)*
4 RFPR12 0 R/(W)*
3 RFPR11 0 R/(W)*
2 RFPR10 0 R/(W)*
1RFPR9 0 R/(W)
*
0RFPR8 0 R/(W)
*
When mailbox n (n = 0 to 15) has r eceived t he
remote frame error-free, ABACKn (n = 0 to 15) is
set to 1.
[Setting condition]
• Compl etion of r emot e f rame r ece ptio n i n
corresponding mailbox
[Clearing condition]
• Wr iting 1
Note: Only 0 for clearing the flag can be written.
Rev. 1.0, 02/02, page 294 of 502
11. 3. 11 Interrupt Register (IRR)
IRR is an interrupt status fl a g registe r.
Bit Bit Name Initial Value R/W Descri ption
15 IRR7 0 R/(W)*Overload Frame /Bus Off Re covery Interrup t Flag
[Setting condition s]
• When an overload frame is transmitted in
error active/passive state
• When 11 recessive bits are r eceived 128
time s (RE C ≥ 128) in bus off state
[Clearing condition]
• Wr iting 1
14 IRR6 0 R/(W)*Bus Off Interrupt Fla g
Status flag indicat ing the bus off stat e caused by
the transmit error counter.
[Setting condition]
• When TEC ≥ 256
[Clearing condition]
• Wr iting 1
13 IRR5 0 R/(W)*Error Passive Interrupt Flag
Status flag indicat ing the error passive stat e
caused by the transmit/receive err or count er.
[Setting condition]
When TEC ≥ 128 or REC ≥ 128
[Clearing condition]
• Wr iting 1
Note: Only 0 for clearing the flag can be written.
Rev. 1.0, 02/02, page 295 of 502
Bit Bit Name Initial Value R/W Descri ption
12 IRR4 0 R/(W)*Rece iv e Ov erloa d Warnin g Interr u pt Flag
Status flag indicating the error warning st ate
caused by the receive err or counter.
[Setting condition]
Whe n REC ≥ 96
[Clearing condition]
• Wr iting 1
11 IRR3 0 R/(W)*Transmit Overload Warning In terrupt Flag
Status flag indicating the error warning st ate
caused by the transmit error counter.
[Setting condition]
• When TEC ≥ 96
[Clearing condition]
• Wr iting 1
10 IRR2 0 R Remote Fram e Request Interrupt Flag
Status flag indicating that a remote frame has
been received in a mailbox (buffer).
[Setting condition]
• When remote frame reception is completed,
when corresponding MBIMR = 0
[Clearing condition]
• Clearing of all bits in RFPR (remote request
register)
9 IRR1 0 R Received message Int errupt Flag
Status flag indicating that a mailbox ( buffer)
received messa ge has been received normally .
[Setting condition]
• W hen d ata fra me or r emot e f rame r ecepti on i s
completed, when corresponding MBIMR = 0
[Clearing condition]
• Clearing of all bits in RXPR (receive complete
register)
Note: Only 0 for clearing the flag can be written.
Rev. 1.0, 02/02, page 296 of 502
Bit Bit Name Initial Value R/W Descri ption
8 IRR0 1 R/(W)*Reset Interrupt Flag
Status flag indicating that the HCAN module has
been reset . This bit cannot be masked by the
interrupt m ask register (I M R). If this bit is not
cleared to 0 after enter ing power- on reset or
returning from software standby mode, interrupt
pr o c essin g will st a rt immed ia tel y whe n the
interrupt controller enables interrupts.
[Setting condition]
• When the reset operation has finished after
entering power-on reset or software standby
mode
[Clearing condition]
• Wr iting 1
7 to
5— 0 — Reserved
These bits are always read as 0. Only 0 should
be written to t hese bits.
4 IRR12 0 R/(W)*Bus Operation Interrupt Flag
Status flag indicating detect ion of a dom inant bit
due to bus operation when the HCAN module is
in HCAN slee p mode.
[Setting condition]
• Bus oper ation (dom inant bit ) detection in
HCAN sleep m ode
[Clearing condition]
• Wr iting 1
3
2— 0 — Reserved
These bits are always read as 0. Only 0 should
be written to t hese bits.
Note: Only 0 for clearing the flag can be written.
Rev. 1.0, 02/02, page 297 of 502
Bit Bit Name Initial Value R/W Descri ption
1 IRR9 0 R Unread Interrupt Flag
Status flag indicating that a received message
has been overwritten before being read.
[Setting condition]
• When UMSR (unread mess age status
register) is set
[Clearing condition]
• Clearing of all bits in UM SR (unr ead message
status regist er)
0 IRR8 0 R/(W)*M ailbox Empty Interrupt Flag
Status flag indicat ing that the next transm it
message can be stored in the mailbox.
[Setting condition]
• When TXPR ( transmit wait register) is cleared
by completion of transmission or com pletion
of transmission abor t
[Clearing condition]
• Wr iting 1
Note: Only 0 for clearing the flag can be written.
Rev. 1.0, 02/02, page 298 of 502
11.3.12 Mailbox Interrupt Mask Register (MBIMR)
MBIMR controls the enabling or disabling of individual mailbox (buffer) interrupt requests.
Bit Bit Name Initial Value R/W Descri ption
15 MBIMR7 0 R/W
14 MBIMR6 0 R/W
13 MBIMR5 0 R/W
12 MBIMR4 0 R/W
11 MBIMR3 0 R/W
10 MBIMR2 0 R/W
9MBIMR1 0 R/W
8MBIMR0 0 R/W
7MBIMR150 R/W
6MBIMR140 R/W
5MBIMR130 R/W
4MBIMR120 R/W
3MBIMR110 R/W
2MBIMR100 R/W
1MBIMR9 0 R/W
0MBIMR8 0 R/W
Mai l b o x Inter ru pt Ma s k (MBI MR x)
When MBIMRn (n = 0 to 15) is cleared to 0, the
interrupt request in mailbox n is enabled. When set
to 1, the interrupt request is mask ed.
The interrupt source in a transmit mailbox is TXPR
clearing caused by tr ansmission end or
transmission cancellation. The int errupt source in a
receive mailbox is RXPR setting on reception end.
Rev. 1.0, 02/02, page 299 of 502
11. 3. 13 Inte r rupt Mask Register ( IMR)
IMR conta ins flags that enable or disable requests by i ndividual interrupt sources. T he interrupt
flag cannot be masked.
Bit Bit Name Initial Value R/W Descri ption
15 IMR7 1 R/W Overload Fra me /Bus Off Recovery Interrupt Mask
When this bit is cleared t o 0, OVR0 (interrupt
request by I RR7) is enabled. When set to 1, OVR0
is masked.
14 IMR6 1 R/W Bus Off Interrupt Mask
When this bit is cleared t o 0, ERS0 (interrupt
request by I RR6) is enabled. When set to 1, ERS0
is masked.
13 IMR5 1 R/W Error Passive Interrupt Mask
When this bit is cleared t o 0, ERS0 (interrupt
request by I RR5) is enabled. When set to 1, ERS0
is masked.
12 IMR4 1 R/W Receive Overload Warning Interrupt Mask
When this bit is cleared t o 0, OVR0 (interrupt
request by I RR4) is enabled. When set to 1, OVR0
is masked.
11 IMR3 1 R/W Transmit Overload Wa rning In terrup t Mask
When this bit is cleared t o 0, OVR0 (interrupt
request by I RR3) is enabled. When set to 1, OVR0
is masked.
10 I M R2 1 R/W Remote Fr ame Request I nterrupt M ask
When this bit is cleared t o 0, OVR0 (interrupt
request by I RR2) is enabled. When set to 1,
OVR0is masked.
9 IMR1 1 R/W Received m essage Interrupt Mask
When this bit is cleared t o 0, RM1 ( int errupt
request by I RR1) is enabled. When set to 1, RMI is
masked.
8— 0 R Reserved
This bit is always read as 0. Only 0 should be
written to this bit.
7— 1 R
6— 1 R
5— 1 R
Reserved
These bits are always read as 1. Only 1 should be
written to these bits.
Rev. 1.0, 02/02, page 300 of 502
Bit Bit Name Initial Value R/W Descri ption
4 IMR 12 1 R/W Bus O peratio n In terr upt M ask
When this bit is cleared t o 0, OVR0 (interrupt
request by I RR12) is enabled. When set to 1,
OVR0 is masked .
3— 1 R
2— 1 R Reserved
These bits are always read as 1. Only 1 should be
written to these bits.
1 IMR9 1 R/W Unread Interrupt Mask
When this bit is cleared t o 0, OVR0 (interrupt
request by I RR9) is enabled. When set to 1, OVR0
is masked.
0 IMR8 1 R/W Mailbox Em pty Interrupt Mask
When this bit is cleared t o 0, SLE0 (interrupt
request by I RR8) is enabled. When set to 1, SLE0
is masked.
11.3.14 Receive Error Counter (REC)
REC is an 8-bit read-onl y register that funct ions as a counter indicating the num ber of received
message e rrors on t he CAN bus. The count va lue is sti pulated in t he CAN protocol.
11.3.15 Transmit Er ror Counter (TEC)
TEC is a n 8-bit read-onl y register that functions as a counter indicating the num ber of transmit
message e rrors on t he CAN bus. The count va lue is sti pulated in t he CAN protocol.
Rev. 1.0, 02/02, page 301 of 502
11. 3. 16 Unread Message Sta t us Regi st er (UMSR)
UMSR c ont ain s sta tus f la g s that in dica te , f or individual mailboxes (buffers), that a rece ived
message ha s been overwri tten by a new re ceived message before be ing read. When ove rwritten by
a new message, data in the unread received message is lost.
Bit Bit Name Initial Value R/W Descri ption
15 UMSR7 0 R/W
14 UMSR6 0 R/W
13 UMSR5 0 R/W
12 UMSR4 0 R/W
11 UMSR3 0 R/W
10 UMSR2 0 R/W
9UMSR1 0 R/W
8UMSR0 0 R/W
7 UMSR15 0 R/W
6 UMSR14 0 R/W
5 UMSR13 0 R/W
4 UMSR12 0 R/W
3 UMSR11 0 R/W
2 UMSR10 0 R/W
1UMSR9 0 R/W
0UMSR8 0 R/W
[Setting condition]
• When a new message is received before RXPR
is cleared
[Clearing condition]
• Wr iting 1
Rev. 1.0, 02/02, page 302 of 502
11. 3. 17 Local Acce ptanc e Filter Masks ( LAFML, LAFMH)
LAFML and LAFMH individually set the identifier bits of th e message to be stored in mailbox 0
as Don't Care. For details, refer to section 11.4.4, Receive Mode. The relationship between the
identifier bits and mask bits are shown in the following.
• LAFML
Bit Bit Name Initial Value R/W Descri ption
15 LAFML7 0 R/W When this bit is set to 1, ID-7 of the received
message identifier is not compared.
14 LAFML6 0 R/W When this bit is set to 1, ID-6 of the received
message identifier is not compared.
13 LAFML5 0 R/W When this bit is set to 1, ID-5 of the received
message identifier is not compared.
12 LAFML4 0 R/W When this bit is set to 1, ID-4 of the received
message identifier is not compared.
11 LAFML3 0 R/W When this bit is set to 1, ID-3 of the received
message identifier is not compared.
10 LAFML2 0 R/W When this bit is set to 1, ID-2 of the received
message identifier is not compared.
9LAFML1 0 R/W
When this bit is set to 1, ID-1 of the received
message identifier is not compared.
8 LAFML0 0 R/W When this bit is set to 1, ID-0 of the received
message identifier is not compared.
7 LAFML15 0 R/W When this bit is set to 1, ID-15 of the received
message identifier is not compared.
6 LAFML14 0 R/W When this bit is set to 1, ID-14 of the received
message identifier is not compared.
5 LAFML13 0 R/W When this bit is set to 1, ID-13 of the received
message identifier is not compared.
4 LAFML12 0 R/W When this bit is set to 1, ID-12 of the received
message identifier is not compared.
3 LAFML11 0 R/W When this bit is set to 1, ID-11 of the received
message identifier is not compared.
2 LAFML10 0 R/W When this bit is set to 1, ID-10 of the received
message identifier is not compared.
1 LAFML9 0 R/W When this bit is set to 1, ID-9 of the received
message identifier is not compared.
0LAFML8 0 R/W
When this bit is set to 1, ID-8 of the received
message identifier is not compared.
Rev. 1.0, 02/02, page 303 of 502
• LAFMH
Bit Bit Name Initial Value R/W Descri ption
15 LAFM H7 0 R/W When this bit is set t o 1, ID-20 of the r eceived
message identifier is not compared.
14 LAFMH6 0 R/W When this bit is set to 1, ID-19 of the received
message identifier is not compared.
13 LAFMH5 0 R/W When this bit is set to 1, ID-18 of the received
message identifier is not compared.
12 — 0 R
11 — 0 R
10 — 0 R
Reserved
These bits are always read as 0. Only 0 should be
written to these bits.
9 LAFMH1 0 R/W When this bit is set to 1, ID-17 of the received
message identifier is not compared.
8LAFMH0 0 R/W
When this bit is set to 1, ID-16 of the received
message identifier is not compared.
7LAFMH150 R/W
When this bit is set to 1, ID-28 of the received
message identifier is not compared.
6 LAFMH14 0 R/W When this bit is set to 1, ID-27 of the received
message identifier is not compared.
5LAFMH130 R/W
When this bit is set to 1, ID-26 of the received
message identifier is not compared.
4 LAFMH12 0 R/W When this bit is set to 1, ID-25 of the received
message identifier is not compared.
3LAFMH110 R/W
When this bit is set to 1, ID-24 of the received
message identifier is not compared.
2 LAFMH10 0 R/W When this bit is set to 1, ID-23 of the received
message identifier is not compared.
1 LAFMH9 0 R/W When this bit is set to 1, ID-22 of the received
message identifier is not compared.
0LAFMH8 0 R/W
When this bit is set to 1, ID-21 of the received
message identifier is not compared.
Rev. 1.0, 02/02, page 304 of 502
11.3.18 Message Control (MC0 to MC15)
The message c ontrol register set s consi st of e i ght 8-bit registers for one mailbox. The HCAN has
16 sets of these registers. Because message control registers are in RAM, their initial values after
power-on are undefined. Be sure to initialize the m by writing 0 or 1. Figure 11. 2 shows the
register names for each mailbox.
MC0[1]
MC1[1]
MC2[1]
MC3[1]
MC15[1]
MC0[2]
MC1[2]
MC2[2]
MC3[2]
MC15[2]
MC0[3]
MC1[3]
MC2[3]
MC3[3]
MC15[3]
MC0[4]
MC1[4]
MC2[4]
MC3[4]
MC15[4]
MC0[5]
MC1[5]
MC2[5]
MC3[5]
MC15[5]
MC0[6]
MC1[6]
MC2[6]
MC3[6]
MC15[6]
MC0[7]
MC1[7]
MC2[7]
MC3[7]
MC15[7]
MC0[8]
MC1[8]
MC2[8]
MC3[8]
MC15[8]
Mail box 0
Mail box 1
Mail box 2
Mail box 3
Mail box 15
Fi g ure 11.2 Messag e Control Regi ster Configuratio n
The setting of message control regist e rs are shown in the fol l owing. Figures 11.3 a nd 11.4 show
the correspondence between the identifiers and register bit names.
SOF ID-28 ID-27 ID-18 RTR IDE R0
identifier
Figure 11.3 Standard For mat
SOF ID-28 ID-27 ID-18 SRR IDE ID-17 ID-16 ID-0 RTR R1
Standard identifier Extended identifier
Figure 11.4 Extended For mat
Rev. 1.0, 02/02, page 305 of 502
Register
Name Bi t Bit Name R/W Description
7 to 4 — R/W The initial value of these bits is undefined; they
mu st be initializ ed ( by writin g 0 or 1).
MCx[1]
3 to 0 DLC3 to
DLC0 R/W Data Length Code
Set the data length of a data frame or the data
length requested in a remote frame within the range
of 0 to 8 bits.
0000: 0 byte
0001: 1 byte
0010: 2 bytes
0011: 3 bytes
0100: 4 bytes
0101: 5 bytes
0110: 6 bytes
0111: 7 bytes
1000: 8 bytes
:
:
1111: 8 bytes
MCx[2] 7 t o 0 — R/W
MCx[3] 7 t o 0 — R/W
MCx[4] 7 t o 0 — R/W
The initial value of these bits is undefined; they
mu st be initializ ed ( by writin g 0 or 1).
7 to 5 ID-20 to I D- 18 R/W Sets ID-20 to ID- 18 in t he identifier.
4 RTR R/W Remote Transmission Request
Used to distinguish between data frames and
remote frames.
0: Data frame
1: Remote frame
3 IDE R/ W Identifier Extension
Used to distinguish between the st andard format
and extended format of data frames and remote
frames.
0: Standard format
1: Extended for mat
2— R/W
The initial value of this bit is undefined. It must be
init ializ e d b y writ in g 0 or 1.
MCx[5]
1 to 0 ID-17 to I D- 16 R/W Sets ID-17 and I D-16 in the ident ifier.
MCx[6] 7 t o 0 I D-28 to I D-21 R/ W Sets ID-28 to ID-21 in the identifier.
MCx[7] 7 to 0 ID-7 to ID-0 R/W Sets ID-7 to ID-0 in the identifier.
MCx[8] 7 to 0 ID-15 to ID-8 R/W Sets ID-15 to ID-8 in the identifier.
Note: x: Mailbox number
Rev. 1.0, 02/02, page 306 of 502
11.3.19 Message Data (M D0 to M D15)
The message da ta register set s consist of eight 8-bit regist ers for one mailbox. The HCAN has 16
sets of these registers. Because message data registers are in RAM, their initial values after power-
on are undefined. Be sure to initialize them by writing 0 or 1. Figure 11.5 shows the register
names for each mailbox.
MD0[1]
MD1[1]
MD2[1]
MD3[1]
MD15[1]
MD0[2]
MD1[2]
MD2[2]
MD3[2]
MD15[2]
MD0[3]
MD1[3]
MD2[3]
MD3[3]
MD15[3]
MD0[4]
MD1[4]
MD2[4]
MD3[4]
MD15[4]
MD0[5]
MD1[5]
MD2[5]
MD3[5]
MD15[5]
MD0[6]
MD1[6]
MD2[6]
MD3[6]
MD15[6]
MD0[7]
MD1[7]
MD2[7]
MD3[7]
MD15[7]
MD0[8]
MD1[8]
MD2[8]
MD3[8]
MD15[8]
Mail box 0
Mail box 1
Mail box 2
Mail box 3
Mail box 15
Figure 11.5 Message Data Configuration
Rev. 1.0, 02/02, page 307 of 502
11.4 Operation
11.4.1 Hardware and Software Resets
The HCAN can be reset by a hardware reset or software reset.
• Hardwar e Rese t
At powe r-on reset, or in hardware or softwa re standby mode, the HCAN is ini tialized by
automatically setting the MCR reset request bit (MCR0) in MCR and the reset state bit (GSR3)
in GSR. At the same time, all internal registers, except for message control and message data
registers, are initialized by a hardware reset.
• Software Reset
The HCAN can be reset by setting the MCR reset request bit (MCR0) in MCR via software. In
a software reset, the e rror counters (TEC and REC) are i nitialized, howe ve r other re gi sters a re
not. If the MCR0 bit i s set while the CAN control ler is pe rforming a communication operation
(transmission or reception), the initialization state is not entered until message transfer has
been completed. The reset status bit (GSR3) in GSR is set on completion of initialization.
11.4.2 Initialization after Hardw ar e Reset
After a hardware reset, the following initialization processing should be carried out:
1. Cleari ng of IRR0 bit in the interrupt register (IRR)
2. Bit rate setting
3. Mailbox transmi t/receive set tin gs
4. Mailbox (RAM) initial ization
5. Message transmission method setting
These i nitial settings must be made while the HCAN is in bi t configuration mode. Confi guration
mode is a state in which the GSR3 bit in GSR is set to 1 by a reset. Configuration mode i s exited
by clearing the MCR0 bit in MCR to 0; when the MCR0 bit is cleared to 0, the HCAN
automatically clears the GSR3 bit in GSR. There is a delay between clearing the MCR0 bit and
clearing the GSR3 bit because the HCAN needs time to be internally reset, there is a delay
between clearing of the MCR0 bit and GSR3 bit. After the HCAN exits configuration mode, the
power-up se quence begins, and communication with t he CAN bus is possible as soon as 11
consecutive recessive bits have been detected.
IRR0 Cleari ng: The reset interrupt flag (IRR0) is always set after a power-on reset or recovery
from software standby m ode. As an HCAN i nterrupt is initiated i mmediate l y when inte rrupts are
enabled, IRR0 should be cleared.
Rev. 1.0, 02/02, page 308 of 502
Hardware reset
MCR0 = 1 (automatic)
IRR0 = 1 (automatic)
GSR3 = 1 (automatic)
MCR0 = 0
GSR3 = 0?
Yes
No
GSR3 = 0 & 11
recessive bits received?
Can bus communication enabled
Yes
No
Bit configuration mode
Period in which BCR, MBCR, etc.,
are initialized
: Settings by user
: Processing by hardware
Initialization of HCAN module
Clear IRR0
BCR setting
MBCR setting
Mailbox initialization
Message transmission method initialization
IMR setting (interrupt mask setting)
MBIMR setting (interrupt mask setting)
MC[x] setting (receive identifier setting)
LAFM setting (receive identifier mask setting)
Figure 11.6 Hardware Reset Flowchart
Rev. 1.0, 02/02, page 309 of 502
MCR0 = 1
GSR3 = 1 (automatic)
Initialization of REC and TEC only
MCR0 = 0
GSR3 = 0?
CAN bus communication enabled
Bus idle?
Yes
Correction
Yes
Correction
: Settings by user
: Processing by hardware
No
No
No
No
No
BCR setting
MBCR setting
Mailbox (RAM) initialization
Message transmission method
initialization
OK?
IMR setting
MBIMR setting
MC[x] setting
LAFM setting
OK?
GSR3 = 0 & 11
recessive bits received?
Yes
Yes
Yes
Figure 11.7 Software Reset Flowchart
Bit Rate and Bit Ti ming Setti ngs: The bit rate and bit timing settings are made in the bit
configuration register (BCR). Settings shoul d be made such tha t all CAN c ontrollers connec t ed to
the CAN bus have the same baud rate and bit widt h. The 1-bit t ime consists of the tota l of the
settable time quantum (tq).
Rev. 1.0, 02/02, page 310 of 502
SYNC_SEG PRSEG PHSEG1 PHSEG2
Time segment 2
(TSEG2)
Time segment 1 (TSEG1)
1-bit time (8–25 time quanta)
2–16 time quanta 2–8 time quanta1 time quantum
Figure 11.8 Detailed Description of One Bit
SYNC_SE G is a segment for establishing the synchronization of nodes on the CAN bus. Norm al
bit edge t ransitions occur in this segme nt. PRSEG is a se gment for compensating for the physi cal
delay between networks. PHSEG1 is a buffer segment for correcting phase drift (positive). This
segment is extended when synchronization (resynchronization) is e stablished. PHSEG2 i s a buffer
segment for correcting phase drift (negative). This segment is shortened when synchronization
(resynchronization) is establishe d. Limits on the settable va l ue (TSEG1, TSEG2, BRP, sample
point, and SJW) are shown in ta ble 11.2.
Table 11. 2 Limits for the Settable Value
Name Abbreviation Min. Value Max. Value
Time segment 1 TSEG1 3*215
Time segment 2 TSEG2 1*37
Baud rate prescale r BRP 0 63
Bit sample point BSP 0 1
Re- s y nchr o n izat io n jum p width SJW*103
Not es: 1. SJW is stipulated in the CAN spec ificat ion s:
3 ≥ SJW ≥ 1
2. The minimum value of TSEG2 is stipulated in the CAN specifications:
TSEG2 ≥ 2+ SJW
3. The minimum value of TSEG1 is stipulated in the CAN specifications:
TSEG1 > TSEG2
Rev. 1.0, 02/02, page 311 of 502
Time Quanta (TQ) is an integer multiple of the number of system clocks, and is determined by the
baud rate pre scaler (BRP) a s follows. fCLK is the system clock frequency.
TQ = 2 × (BPR setting + 1)/fCLK
The following formula is used to calculate the 1-bit time and bit rate.
1-bit time = TQ × (3 + TSEG1 + TSEG2)
Bit rate = 1/Bit time
= fCLK/{2 × (BPR setting + 1) × (3 + TSEG1 + TSEG2)}
Note: fCLK = φ (system clock)
A BCR value is used for BRP, TSEG1, and TSEG2.
Example: With a system clock of 20 MHz, a BRP setting of B'000000, a TSEG1 setting of
B'0100, and a TSEG2 se tting of B'011:
Bit rate = 20/{2 × (0 + 1) × (3 + 4 + 3)} = 1 Mbps
Table 11. 3 Setting Range for TSEG1 and TSEG2 in BCR
TSEG2 (BCR[14:12])
001 010 011 100 101 110 111
TQ
Value2345678
TSEG1 0011 4 No Yes No No No No No
(BCR[11:8]) 0100 5 Yes*Yes Yes No No No No
0101 6 Yes*Yes Yes Yes No No No
0110 7 Yes*Yes Yes Yes Yes No No
0111 8 Yes*Yes Yes Yes Yes Yes No
1000 9 Yes*Yes Yes Yes Yes Yes Yes
1001 10 Yes*Yes Yes Yes Yes Yes Yes
1010 11 Yes*Yes Yes Yes Yes Yes Yes
1011 12 Yes*Yes Yes Yes Yes Yes Yes
1100 13 Yes*Yes Yes Yes Yes Yes Yes
1101 14 Yes*Yes Yes Yes Yes Yes Yes
1110 15 Yes*Yes Yes Yes Yes Yes Yes
1111 16 Yes*Yes Yes Yes Yes Yes Yes
Note: * Do not set a Baud Rate Prescaler (BRP) value of B’000000 (2 ×system clock).
Rev. 1.0, 02/02, page 312 of 502
Mai lb o x Tra n smit/Rec eive Settings: The HCAN has 16 mailboxes. Mailbox 0 is receive-only,
while mailboxes 1 to 15 can be set for transmission or reception. The Initial status of mailboxes 1
to 15 is for transmi ssion. Ma i lbox transmit/receive settings are not initialized by a softwa re reset.
Clearing a bit to 0 in the mailbox configuration register (MBCR) designates the corresponding
mailbox for transmission use, where as a setting of 1 in MBCR designates the corresponding
mailbox for reception use. When setting ma ilboxes for reception, in order to improve message
reception efficiency, hi gh-priority messages should be set i n low-to-high mailbox order.
Mailbox (Message Control/Data) Initial Settings: Message control/data are held in RAM, and
so their initial value s are undefined after power is supplied. Initial values must therefore be set in
all the mailboxes (by writing 0s or 1s).
Setting the Message Transmission Method: The following two kinds of message transmission
methods are avail abl e.
• Transmission order determined by message identifier priority
• Transmission order det ermined by mailbox number priority
Either of the message transmission methods can be selected with the message transmission method
bit (MCR2) in the maste r control register (MCR): Whe n messages are set to be transm i tted
according t o the message ide ntifier priori ty, if several me ssages are designat e d as waiting for
transmission (TXPR = 1), the message with the highest priority in the message identifier is stored
in the tra nsmit buffer. CAN bus a rbitration i s then carried out for the message stored i n the
transmit buffer, and the message is transmitted when the transmission right is acquired. When the
TXPR bi t is set, the highest-priority message is found and stored in t he transmit buffer.
When messages are set to be transmitted according to the mailbo x numb er prior ity, if several
messages are designated as waiting for transmission (TXPR = 1), messages are stored in the
transmit buffer in low-to-high mailbox order. CAN bus arbitration is then carried out for the
message stored in the transmit buffer, and the message is transmitted when the transmission right
is acquired.
Rev. 1.0, 02/02, page 313 of 502
11. 4. 3 Me ssa ge Transm i ssion
Messages are transmitted using mailboxes 1 to 15. The transmission procedure after initial settings
is describe d below, and a transmission flowc hart is shown in figure 11.9.
Initialization (after hardware reset only)
Clear IRR0
BCR setting
MBCR setting
Mailbox initialization
Message transmission method setting
Yes
No
Yes
Yes
: Settings by user
: Processing by hardware
No
No
Interrupt settings
Transmit data setting
Arbitration field setting
Control field setting
Data field setting
Message transmission
GSR2 = 0 (during transmission only)
TXACK = 1
IRR8 = 1
Clear TXACK
Clear IRR8
Message transmission wait
TXPR setting
Bus idle?
Transmission completed?
IMR8 = 1?
Interrupt to CPU
End of transmission
Figure 11.9 Transmiss ion Flow chart
Rev. 1.0, 02/02, page 314 of 502
CPU Inter rupt Source Set tings: The CPU interrupt source is set by the i nterrupt mask regi ster
(IMR) a nd mailbox int e rrupt ma sk regi ste r (MBIMR). Transmi ssion acknowledge and
transmission abort acknowle dge inte rrupts can be gene rated for individual mailboxes i n the
mailbox interrupt mask regi ster (MBIMR).
Arbi t r ati on Field Se tti ng : The a rbitration field is set by message control registers MCx[5]–
MCx[8] i n a tra nsmit mailbox. For a standard format, an 11-bit identifier (ID-28 to ID-18) and t he
RTR bit are set , and t he IDE bit is cleared to 0. For an e xtended format, a 29-bit i dentifier (ID-28
to ID-0) and the RTR bit are set, and the IDE bit is set to 1.
Contr o l Fiel d Setting: In the control field, the byte length of the data to be transmitted is set
within the range of zero to eight bytes. The register to be set is the message control register
MCx[1] i n a tra nsmit mailbox.
Data Field Setting: In the data field, the data to be transmitted is set within the range zero to
eight. The regi sters to be set are the message data registe rs MDx[1]–MDx[8]. The byte l e ngth of
the data to be transmitted is determined by the data length code in the control field. Even if data
exceeding the value set in the control field is set in the data field, up to the byte length set in the
control field will actually be transmitted.
Me ssa ge Transm i ssion: If the c orresponding ma ilbox transmit wait bit (TXPR1–TXPR15) in the
transmit wait register (TXPR) is set to 1 after message control and message data registers have
been set, the message enters tra nsmit wai t state. If t he message is tra nsmitted error-free, the
correspondin g ack nowledge bit (TXACK1 –TXA CK15) in the trans mit ackn ow ledge register
(TXACK) is set to 1, and t he corre sponding transmit wait bit (TXPR1–T XPR15) in the t ransmit
wait registe r (TXPR) is automatically cleared to 0. Also, if the corresponding bit (MBIMR1-
MBIMR15) i n the mailbox interrupt mask register (MBIMR) and the mailbox empty interrupt bit
(IRR8) in t he interrupt mask regist er (IMR) are both simul taneously se t to ena ble interrupts,
interrupts may be sent to the CPU.
If transmission of a t ransmit message i s aborted in the following cases, the m e ssage i s
retransmitted automatically:
• CA N bus ar bitration failure ( failur e to ac q u ire the bus )
• Error during transmi ssion (bit error, stuff error, CRC error, fram e error, or ACK error)
Me ssa ge Transm i ssion Ca nce ll atio n: Transmission cancellation can be specified for a message
stored in a mailbox as a transmit wait message. A transmit wait message is canceled by setting the
bit for the c orresponding ma ilbox (TXCR1–T XCR15) to 1 in the tra nsmit cancel register (T XCR).
Clearing the transmit wait register (TXPR) does not cancel transmission. When cancellation is
executed, the tra nsmit wait regi ster (TXPR) is aut omatically reset, and the correspondi ng bit is set
to 1 in the abort acknowledge regi ster (ABACK). An interrupt to t he CPU c a n be requested, and if
the mailbox em pty interrupt (IRR8) is enabled for the bi ts (MBIMR1-MBIMR15) corresponding
Rev. 1.0, 02/02, page 315 of 502
to the ma ilbox int errupt m ask register (MBIMR) a nd interrupt ma sk regi ster (IMR), interrupt s may
be sent t o the CPU.
However, a transmit wait message cannot be canceled at the following times:
• During internal arbitration or CAN bus arbitration
• During data frame or remote frame transmission
Figure 11. 10 shows a flowcha rt for tra nsmit m essage ca ncellation.
Message transmit wait TXPR setting
Yes
No
Yes
No
: Settings by user
: Processing by hardware
Set TXCR bit corresponding to
message to be canceled
Message not sent
Clear TXCR, TXPR
ABACK = 1
IRR8 = 1
Clear TXACK
Clear ABACK
Clear IRR8
Completion of message transmission
TXACK = 1
Clear TXCR, TXPR
IRR8 = 1
Cancellation possible?
IMR8 = 1?
End of transmission/transmission
cancellation
Interrupt to CPU
Figure 11.10 Transmit Me ssage Cancellation Flowchart
Rev. 1.0, 02/02, page 316 of 502
11. 4. 4 Me ssa ge Reception
The reception procedure after ini tial settings is described bel ow. A reception fl owchart i s shown in
figure 11.11.
RXPR
IRR1 = 1
No
IMR2 = 1?
Interrupt to CPU
Yes
No
Yes
Yes Yes
No
: Settings by user
: Processing by hardware
No
Yes
InitializationClear IRR0
BCR setting
MBCR setting
Mailbox (RAM) initialization
Receive data setting
Arbitration field setting
Local acceptance filter settings
Interrupt settings
Message reception
(Match of identifier
in mailbox?)
Same RXPR = 1?
IMR1 = 1?
Data frame?
Interrupt to CPU
Clear IRR1
End of reception
Clear IRR2, IRR1
Unread message
No
RXPR, RFPR = 1
IRR2 = 1, IRR1 = 1
Message control read
Message data read Message control read
Message data read
Transmission of data frame corresponding
to remote frame
Figure 11. 11 Re cep t ion Flowcha rt
Rev. 1.0, 02/02, page 317 of 502
CPU Inter rupt Source Set tings: CPU int errupt source settings are made in the interrupt mask
register (IMR) and mail box i nterrupt register (MBIMR). The message to be received is also
specified. Data frame and rem ote frame re ceive wait inte rrupt reque sts can be generated for
individual mailboxes in the MBIMR.
Arbi t r ati on Field Se tti ng : To receive a message, the message identifier must be set in advance in
the message control registers (MCx[1]–MCx[8]) for the receiving mailbox. When a message is
rec eived, all th e bits in th e received messag e identifi er ar e co mpared with those in each message
control regi ster identifier, a nd if a 100% match is found, the me ssage i s stored in the matching
mai l b o x. Mail bo x 0 has a local accep tan ce filt e r mask (L AFM) tha t all o ws Don't Care set ti n gs to
be made. The LAFM sett ing can be made only for mailbox 0. By making the Don' t Ca re sett i n g
for all the bits in the received m e ssage identifier, messages of multiple identifiers can be received.
Examples:
• When t he identifier of mailbox 1 is 010_1010_1010 (sta ndard format), only one ki nd of
message identifier can be received by mailbox 1:
Identifier 1: 010_1010_1010
• When t he identifier of mailbox 0 is 010_1010_1010 (standard format) and the LAFM setting is
000_0000_0011 (0: Care, 1: Don't Care ), a t otal of four kinds of message ide ntifiers can be
received by mailbox 0:
Identifier 1: 010_1010_1000
Identifier 2: 010_1010_1001
Identifier 3: 010_1010_1010
Identifier 4: 010_1010_1011
Me ssa ge Recept i o n: When a message is received, a CRC check is performed aut omatically. If the
result of the CRC check is normal, ACK is transmitted in the ACK field irrespective of whether
the message can be received or not.
• Data frame reception
If the received message i s confirmed to be error-free by the CRC check, the identifier in t he
mai l b o x (and also LAFM i n the case of mailb ox 0 onl y) and the identi fie r of the recei v e d
message, are compared. If a complete match is found, the message is stored in the mailbox.
The message identifier comparison is carried out on each mailbox in turn, starting with
mailbox 0 a nd e nding with m a ilbox 15. If a complete match is found, the comparison ends at
that point, the message i s store d in the matching mailbox, and the c orresponding rec eive
complete bit (RXPR0–RXPR15) is set in t he receive complete register (RXPR). However,
when a mailbox 0 LAFM comparison is carried out, even if the identifier matches, the mailbox
comparison sequence does not end at that point, but continues with mailbox 1 and then the
remaining mailboxes. It is therefore possible for a message matching mailbox 0 to be received
by another ma ilbox. Not e that the same message cannot be stored i n more t han one of
mailboxes 1 to 15. On re ceiving a message, a CPU interrupt re quest ma y be gene rated
Rev. 1.0, 02/02, page 318 of 502
depending on the ma ilbox int e rrupt ma sk regi ste r (MBIMR) and i nterrupt mask re gister (IMR)
settings.
• Remote frame reception
Two kinds of messages—data frames and remote frame s—can be stored in mailboxes. A
remote frame differs from a data frame in that the remote transmission request bit (RTR) in the
message control register and the data field are 0 bytes long. The data length to be returned in a
data fram e must be stored i n the data length c ode (DLC) in the control field.
When a remote frame (RTR = recessive) is received, the corresponding bit is set in the rem ote
request wait register (RFPR). If t he correspondi ng bit (MBIMR0–MBIMR15) i n the m ailbox
interrupt ma sk register (MBIMR) and the remot e frame request i nterrupt mask (IRR2) in the
interrupt ma sk register (IMR) a re set to the i nterrupt enable value at this time, an interrupt can
be sent t o the CPU.
Unread Message Overwrite: If the received message identifier matches the mailbox identifier,
the received message is stored in the mailbox regardless of whether the mailbox contains an
unread message or not. If a message ove rwrite occurs, the correspondi ng bit (UMSR0–UMSR15)
is set in the unread me ssage register ( UMSR ). In over writi ng an unread message, when a new
message i s received before the corresponding bit in the receive complete regi ster (RXPR) has be en
cleared, the unread me ssa ge register (UMSR) is set. If the unread interrupt flag (IRR9) in the
interrupt ma sk register (IMR) i s set to the interrupt e nable value at t hi s time, an interrupt ca n be
sent to t he CPU. Figure 11. 12 shows a flowchart for unrea d message ove rwriting.
Rev. 1.0, 02/02, page 319 of 502
No
: Settings by user
Unread message overwrite
Interrupt to CPU
End
IMR9 = 1?
UMSR = 1
IRR9 = 1
Clear IRR9
Message control/message data read
: Processing by hardware
Yes
Figure 11. 12 Un re a d Message Overw rite Flowcha rt
11. 4. 5 HCAN Sleep Mode
The HCAN is provided with an HCAN sleep mode that places the HCAN module in the sleep
state in order to re duce curre nt dissipation. Figure 11. 13 shows a flowchart of the HCAN sl eep
mode.
Rev. 1.0, 02/02, page 320 of 502
IRR12 = 1
Yes
MCR5 = 0
Yes
Yes
MCR5 = 0
Clear sleep mode?
Yes
No
No
No
Yes (manual)
No (automatic)
MCR5 = 1
Bus idle?
Initialize TEC and REC
Bus operation?
: Settings by user
: Processing by hardware
No
No
IMR12 = 1?
Sleep mode clearing method
MCR7 = 0?
11 recessive bits?
CAN bus communication possible
CPU interrupt
Figure 11.13 HCAN Sleep Mode Flowchart
Rev. 1.0, 02/02, page 321 of 502
HCAN sl eep mode is e ntered by setting the HCAN sleep mode bit (MCR5) to 1 in the master
control regi ster (MCR). If the CAN bus is operating, the t ra nsition to HCAN sleep mode i s
delayed until the bus becomes idle.
Either of t he following methods of clearing HCAN sleep mode can be selected:
• Clearing by software
• Clearing by CAN bus ope ration
Eleven recessive bits must be received after HCAN sleep mode is cleared before CAN bus
communication is re-enabled.
Clearing by Software: HCAN sleep mode is cleared by writing a 0 to MCR5 from the CPU.
Cle ari ng by CAN Bus Operati o n: The cancellation me thod is selected by the MCR7 bit set ting
in MCR. Clearing by CAN bus operation occurs automatically when the CAN bus performs a n
operation and this change is detected. In this case, the first message is not stored in a mailbox;
messages will be received normally from the second message onward. When a change is detected
on the CAN bus in HCAN sleep mode, the bus operation interrupt flag (IRR12) is se t in the
interrupt re gister (IRR). If the bus interrupt mask (IMR12) in the interrupt mask regi ster (IMR) is
set to the interrupt enabl e value at this time , an interrupt can be sent to the CPU.
Rev. 1.0, 02/02, page 322 of 502
11.4.6 HCAN Halt Mode
The HCAN halt mode is provided t o enabl e mailbox settings to be changed wit hout performing an
HCAN ha rdwa re o r software reset. Fi g u re 11.14 shows a flowc har t of the HCAN halt mode.
MCR1 = 1
Yes
: Settings by user
: Processing by hardware
No
Bus idle?
MBCR setting
MCR1 = 0
CAN bus communication possible
Figure 11. 14 HCA N Ha lt Mo de Flowchart
HCAN hal t mode i s entered by setting the halt reque st bit (MCR1) to 1 in the master c ontrol
register (MCR). If t he CAN bus is ope rating, the transition t o HCAN halt mode is del a yed until
the bus becomes idle.
HCAN hal t mode i s cleared by clearing MCR1 to 0.
Rev. 1.0, 02/02, page 323 of 502
11.5 Interrupts
Table 11. 4 lists the HCAN interrupt sourc e s. With the e xception of the reset processing vec tor
(IRR0), t he se source s can be masked. Masking is implemented using the m ailbox interrupt mask
register (MBIMR) and interrupt mask regi ster (IMR). For det ails on the interrupt vec tor of each
interrupt source, refer t o sec t ion 5, Interrupt Controller.
Tabl e 11. 4 HCAN Int er r upt Sour ce s
Name Descript ion Interrupt Flag
Error passive interrupt (TEC ≥ 128 or REC ≥ 128) I RR5
Bus off interrupt (TEC ≥ 256) IRR6
Reset process interr upt by power-on reset IRR0
Remote frame reception IRR2
Error warning interrupt (TEC ≥ 9 6) IRR3
Error warning interrupt (REC ≥ 96) IRR4
Overload frame tra ns missi on inter rup t/bus off recovery
interrupt ( 11 recessive bits × 128 times) IRR7
Unr ea d messa ge over writ e IRR9
ERS0/OVR0
Detection of CAN bus operation in HCAN sleep mode IRR12
RM0 Mailbox 0 message reception IRR1
RM1 Mailbox 1-15 mess age rec eption IRR1
SLE0 Message t rans mission/cancellation IRR8
Rev. 1.0, 02/02, page 324 of 502
11.6 CAN Bus Interf ace
A bus tra nsceiver IC is necessary to c onnect this LSI to a CAN bus. A Phil i ps PCA82C250
transceiver IC is recomme nded. Any other product must be compatible with the PCA82C250.
Figure 11. 15 shows a sampl e connection dia gram.
RS
RxD
TxD
Vref
Vcc
CANH
CANL
GND
HRxD
NC
Note: NC: No Connection
HTxD
This LSI
CAN bus
124
124
Vcc
PCA82C250
Figure 11.15 High-Speed Interface Usi ng PCA82C250
11.7 Usage Notes
11.7.1 Module Stop Mode Setti ng
HCAN opera tion ca n be disabled or e nabled using the m odule stop control register. T he initial
setting is for HCAN operation to be hal ted. Register ac cess is enabled by clearing module stop
mode. For deta ils, refer t o sec tion 19, Power-Down Modes.
11.7.2 Reset
The HCAN is reset by a power-on reset, in hardware sta ndby mode, and in software standby
mode. All the registers are initialized in a reset, however mailboxes (message control
(MCx[x])/message data (MDx[x])) are not. Aft er powe r-on, mailboxe s (message control
(MCx[x])/message data (MDx[x])) are not ini tialized, a nd their value s are undefi ned. T herefore,
mailbox initialization must always be carried out after a power-on reset, a transition to hardware
standby mode, or soft ware standby m ode. The re set int errupt fla g (IRR0) is always set after a
power-on reset or rec overy from software standby m ode. As thi s bit ca nnot be masked in the
interrupt ma sk register (IMR), if HCAN interrupt enabling is set in t he interrupt controller without
clearing the flag, an HCAN interrupt will be initiat ed imm ediat ely . IRR0 should therefore be
cleared during initialization.
Rev. 1.0, 02/02, page 325 of 502
11. 7. 3 HCAN Slee p Mode
The bus ope ration i nterrupt flag (IRR12) in the interrupt register (IRR) is set by CAN bus
operation i n HCAN sleep m ode. Therefore, t his flag i s not used by the HCAN to i ndicate sleep
mode release. Note that the reset status bit (GSR3) in the general status register (GSR) is set in
sleep mode .
11.7.4 Interrupts
When the mailbox inte rrupt ma sk register (MBIMR) is set, the int errupt re gister (IRR8, IRR2, or
IRR1) is not set by reception completion, transmission completion, or tra nsmission cancellation
for the set mailboxes.
11.7.5 Error Counters
In the case of error ac tive and error passive, REC and TEC normally count up and down. In the
bus-off sta te, 11-bit recessive sequences a re count ed (REC + 1) using REC. If REC reaches 96
during the count, IRR4 and GSR1 are se t, and if REC reaches 128, IRR7 is se t.
11 .7. 6 Reg ist er A cce s s
Byte or word access can be used on all HCAN re gisters. L ongword access cannot be used.
11.7.7 HCAN Medium-Speed Mode
In medi um -speed mode, neither rea d nor write is possible for t he HCAN registers.
11.7.8 R e g i st er Hol d in Sta ndby Mo des
All HCAN registers a re initialized in hardware sta ndby mode a nd soft ware st a ndby m ode.
11. 7. 9 Usa g e o f Bit Manipulat i o n Instruc ti ons
The HCAN status flags are cleared by writing 1, so do not use a bit manipulation instruction to
cl ea r a flag. When clearing a flag, use the MOV inst r ucti o n to write 1 to only the b it that i s to be
cleared.
Rev. 1.0, 02/02, page 326 of 502
Rev. 1.0, 02/02, page 327 of 502
Section 12 A/D Converter
This LSI i ncludes a successive approximation type 10-bit A/D c onverter that allows up to ei ght
analog input channels to be selected. The Block diagram of the A/D converter is shown in figure
12.1.
12.1 Features
• 10-bit re solution
• Eight input chann els
• Conversion time: 13.3 µs per channe l (at 20 MHz operation)
• Two operating modes
Single mode: Single-channel A/D conversion
Scan mode : Continuous A/D conversion on 1 to 4 channels
• Four da ta regist e rs
Conversion results are held in a 16-bit data re gister for each channel
• Sample and hold function
• Three methods conversion sta rt
Software
16-bit time r pulse unit (TPU) conversion start trigger
Ext er nal trig g er signal
• Interrupt request
An A/D conversion e nd interrupt reque st (ADI) ca n be gene rated
• Module stop mode can be set
ADCMS36A_000020020200
Rev. 1.0, 02/02, page 328 of 502
Module data bus
Control circuit
Internal data bus
10-bit D/A
Comparator
+
Sample-and-
hold circuit
ADI
interrupt
Bus interface
Successive approximations
register
Multiplexer
A
D
C
S
R
A
D
C
R
A
D
D
R
D
A
D
D
R
C
A
D
D
R
B
A
D
D
R
A
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Legend
ADCR : A/D control register
ADCSR : A/D control/status register
ADDRA : A/D data register A
ADDRB : A/D data register B
ADDRC : A/D data register C
ADDRD : A/D data register D
Conversion start
trigger from TPU
ø/2
ø/4
ø/8
ø/16
AV
CC
AV
SS
Figure 12.1 Block Diagr am of A/D Converter
Rev. 1.0, 02/02, page 329 of 502
12.2 Input/Output Pins
Table 12. 1 summarizes the input pins used by t he A/D converter. The eight analog input pins are
divided into four cha nnel sets and two groups; ana log input pins 0 to 3 (AN0 to AN3) comprising
group 0 and analog i nput pins 4 to 7 (AN4 t o AN7) com pri sing group 1. The AVcc a nd AVss pins
are the power supply pins for the analog block in the A/D converter.
Table 12. 1 Pin Configuration
Pin Name Sym bol I/O Function
Analog power supply pin AVCC Input Analog block power supply and reference
voltage
Analog gr ound pin AVSS Input Analog block ground and reference voltage
Analog input pin 0 AN0 I nput
Analog input pin 1 AN1 I nput
Analog input pin 2 AN2 I nput
Analog input pin 3 AN3 I nput
Group 0 analog input pins
Analog input pin 4 AN4 I nput
Analog input pin 5 AN5 I nput
Analog input pin 6 AN6 I nput
Analog input pin 7 AN7 I nput
Group 1 analog input pins
A/D external tr igger input
pin
$'75*
Input External tr igger input pin f or starting A/D
conversion
Rev. 1.0, 02/02, page 330 of 502
12.3 Register Descript i on s
The A/D converter has the following registers. The MSTPA1 bit in the module stop control
register (MSTPCRA) specifies the modes of this module as module stop mode. For details on
MSTPCRA, re fer to section 19.1.3, Module Stop Control Re gi sters A to D (MSTPCRA to
MSTPCRD).
• A/D data reg i ste r A (ADDRA)
• A/D data reg i ste r B (ADDRB)
• A/D data reg i ste r C (ADDRC)
• A/D data reg i ste r D (ADDRD)
• A/D cont r ol/ sta tus reg i ste r (ADCSR)
• A/D control re gister (ADCR)
12. 3. 1 A/D Dat a Register s A to D (ADDRA to ADDRD)
The re are four 16-bit rea d-only ADDR registers; ADDRA to ADDRD, used to store the results of
A/D conversion. The ADDR registers, which store a co nversion result for e ach channel, are
shown in table 12. 2.
The converted 10-bit data is stored in bits 6 to 15. The lower 6 bits are always read as 0.
The data bus between the CPU and the A/D converter is 8 bits wide. The upper byte can be read
directly from the CPU, however the lower byte should be read via a temporary register. The
temporary register contents are t ransferred from the ADDR whe n the upper by te data is read.
When reading t he ADDR, rea d the upper byt e before the lower byte, or read in word unit.
Tabl e 12. 2 Anal o g Input Cha nnels a nd Corre sponding ADDR Register s
Analog Input Channel
Gr oup 0 (CH2 = 0) Group 1 (CH2 = 1) A/D Data Register to Be Stored the Results
of A/D Conversion
AN0 AN4 ADDRA
AN1 AN5 ADDRB
AN2 AN6 ADDRC
AN3 AN7 ADDRD
Rev. 1.0, 02/02, page 331 of 502
12. 3. 2 A/D Cont rol / Status Register (ADCSR)
ADCSR controls A/D conversion operations.
Bit Bit Name Initial Value R/W Description
7ADF 0 R/(W)
*A/D End Flag
A status flag that indicates the end of A/D
conversion.
[Setting condition s]
• When A/D conversion ends
• When A/D conversion ends on all specified
channels
[Clearing condition]
• When 0 is written after reading ADF = 1
6 ADIE 0 R/W A/D Interrupt Enable
A/D conversion end interrupt (ADI) r equest enabled
when 1 is set
5 ADST 0 R/ W A/ D Start
Clearing t his bit to 0 st ops A/ D conver sion, and the
A/D converter enters the wait state.
Setting this bit to 1 starts A/D conversion. In single
mode, this bits is cleared to 0 automatically when
conversion on the specif ied channel is complet e. In
scan mode, conversion continues sequentially on
the specified channels until this bit is clear ed to 0
by software, a reset, or a transition to software
standby m ode, hardwar e standby m ode or module
stop mode.
4 SCAN 0 R/W Scan Mode
Selects single m ode or scan mode as the A/D
conversion operating mode.
0: Single mode
1: Scan m ode
3−0R/WReserved
The wri te value should al ways be 0.
Rev. 1.0, 02/02, page 332 of 502
Bit Bit Name Initial Value R/W Description
2 CH2 0 R/W
1 CH1 0 R/W
0 CH0 0 R/W
Channel Select 2 to 0
Select analog input channels.
When SCAN = 0 Wh e n SCAN = 1
000: AN0 000: AN0
001: AN1 001: AN0 and AN1
010: AN2 010: AN0 to AN2
011: AN3 011: AN0 to AN3
100: AN4 100: AN4
101: AN5 101: AN4 and AN5
110: AN6 110: AN4 to AN6
111: AN7 111: AN4 to AN7
Note: * Only 0 for clearing the flag can be written.
Rev. 1.0, 02/02, page 333 of 502
12. 3. 3 A/D Cont rol Re gister ( ADCR)
ADCR enables A/D conversion started by an external trigger signal.
Bit Bit Name Initial Value R/W Description
7TRGS1 0 R/W
6TRGS0 0 R/W
Timer Trigger Select 0 and 1
Enables t he start of A/D conversion by a trigger
signal. Only set bits TRGS0 and TRGS1 while
conversion is stopped (ADST = 0).
00: A/D conversion start by softwar e is enabled
01: A/D conversion start by TPU conversion start
trigger is enabled
10: Setting prohibited
11: A/D conversion start by external trigger pin
(
$'75*
) is enabled
5— 1 —
4— 1 — Reserved
These bits are always read as 1.
3 CKS1 0 R/W
2 CKS0 0 R/W Clock Se lect 0 and 1
These bits specify the A/D conver sion time. The
conversion tim e should be changed only when
ADST = 0. Specify a setting t hat gives a value
within the range shown in table 19. 7 in sect ion 19,
Electrical Characteristics.
00: Conversion time = 530 st ates (max.)
01: Conversion time = 266 st ates (max.)
10: Conversion time = 134 st ates (max.)
11: Conversion time = 68 st at es (max.)
1— 1 —
0— 1 —
Reserved
These bits are always read as 1.
Rev. 1.0, 02/02, page 334 of 502
12.4 Operation
The A/D c onverter operates by successive approxim ation wit h 10-bit resol ution. It has two
operating m odes; si ngle mode and scan mode. W hen changing t he operating m ode or analog input
channel, in order t o prevent incorrect operation, first clear the bit ADST to 0 in ADCSR. The
ADST b it can be set at th e same ti me as the ope rati ng mode or anal o g in put c han nel i s chan g ed.
12.4.1 Single Mode
In single mod e, A/D con version is to b e p erformed only on ce on th e specified single ch annel. The
operations are as foll ows.
1. A/ D conversion is st arte d when the ADST bit is set to 1, according t o software or external
trigger input.
2. When A/D conversion is completed, the resul t is tra nsferred to the corresponding A/D data
register to the channel.
3. On c omple ti o n of conver sion , the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at
this time, an ADI interrup t request is generated.
4. T he ADST bit rema ins set to 1 duri ng A/D conversion. When A/D conve rsion ends, t he ADST
bit is automatically cleared to 0 and the A/D converter enters the wait state.
12.4.2 Scan Mo d e
In scan mode, A/D conversion is to be performed sequentially on the specified channels (four
channels maximum). The operations are as follows.
1. W hen the ADST bit is set to 1 by software, TPU or external trigger i n put, A/D conversio n
starts on the first channe l in the group (AN0 when CH2 = 0 or AN4 when CH2 = 1).
2. When A/D conversion for each c ha nnel is completed, the result i s sequentially t ra nsferre d to
the A/D data registe r corresponding to ea ch channe l.
3. W hen conve rsion of all the sele ct e d chan nels is complete d , t he ADF flag is set to 1. If the
ADIE bit is set to 1 at this time, an ADI interrupt is requested after A/D conversion ends.
Conversion of the fi rst channel in t he group starts a gain.
4. St e p s [2] and [3] a re repeat ed as long as the ADST bit remains set to 1. When the ADST bit is
cleared to 0, A/D conversion stops and the A/D converter enters the wait state.
Rev. 1.0, 02/02, page 335 of 502
12. 4. 3 Input Sampli ng and A/D Conversion Time
The A/D c onverter has a built-in sample -and-hold c ircuit. T he A/D converter sam ples the analog
input when the A/D c onversi on start delay time (tD) has passed afte r the ADST bit is set to 1, then
starts conve rsion. Figure 12.2 shows the A/ D conve rsion timing. Table 12.3 shows the A/D
conversion time.
As indicated i n figure 12.2, the A/D conversion ti me (tCONV) includes tD and the input sampling time
(tSPL). The length of tD varies depending on the timing of the write access to ADCSR. The total
conversion time therefore varies within the ranges indicated in table 12.3.
In scan mode, the values given in table 12.3 apply to the first conversion time. The values given
in table 12.4 apply to the second and subsequent conversions. In both cases, set bits CKS1 and
CKS0 in ADCR to give an A/D conversion time within the range shown in tabl e 19.7 i n section
19, Electrical Characteristics.
(1)
(2)
t
D
t
SPL
t
CONV
ø
Address
Write signal
Input sampling
timing
ADF
Legend
(1) : ADCSR write cycle
(2) : ADCSR address
t
D
: A/D conversion start delay
t
SPL
: Input sampling time
t
CONV
: A/D conversion time
Fi g ure 12.2 A/D Conversion Timing
Rev. 1.0, 02/02, page 336 of 502
Table 12. 3 A/D Conver sion Time (Single Mode)
CKS1 = 0 CKS1 = 1
CKS0 = 0 CKS0 = 1 CKS0 = 0 CKS0 = 1
Item Symbol Min Typ Max Min Typ Max Min Typ Max Min Typ Max
A/D conversion
start delay tD18 — 33 10 — 17 6 — 9 4 — 5
Input sampling
time tSPL — 127 — — 63 — — 31 — — 15 —
A/D conversion
time tCONV 515 — 530 259 — 266 131 — 134 67 — 68
Note: All values represent the number of states.
Table 12. 4 A/D Conver sion Time (Scan Mode)
CKS1 CKS0 Conversion Time (State)
0 512 (Fixed)
0
1 256 (Fixed)
0 128 (Fixed)1
1 64 (Fixed)
Rev. 1.0, 02/02, page 337 of 502
12.4.4 External Trigger Input Timing
A/D conversion can be externally triggered . When the TRGS 0 and TRGS1 bits are set to 11 in
AD C R, extern al tr igger input is enabled at the
$'75*
pin. A falling edge at the
$'75*
pin sets
the ADST bit t o 1 in ADCSR, starting A/D conversion. Other operations, in both single and sc a n
mod e s, are the same as when the bit ADST has bee n set to 1 by softwa re. Figu re 12. 3 shows the
timing.
ø
Internal trigger signal
ADST A/D conversion
Fig ure 12.3 External Trigger Input Ti ming
12.5 Interrupts
The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion.
Setting the ADIE bit to 1 enables ADI interrupt requests whi l e the bit ADF i n ADCSR is se t to 1
after A/D conversion is completed.
Tabl e 12. 5 A/D Co nv erter Int e rr upt So urce
Name Interrupt Source Interrupt Source Flag
ADI A/D conversion completed ADF
Rev. 1.0, 02/02, page 338 of 502
12.6 A/D Conversio n P reci sion Def i nition s
This LSI' s A/D conversion prec ision definitions a re given below.
• Resolution
The number of A/D convert er digital output c odes
• Quantiz ation error
The devia tion inhe re nt in the A/D converter, given by 1/2 L SB (see figure 12.4).
• Offset error
The de viation o f th e analog input vol tage v alue from the id eal A/D con version characte r is tic
when the digital outpu t changes from the minimu m voltag e value B'000000 0000 (H'000) to
B'0000000001 (H'001) (see fi gure 12.5).
• Full-scal e error
The de viation o f th e analog input vol tage v alue from the id eal A/D con version characte r is tic
when the digital out put changes from B'1111111110 (H'3FE) to B'1111111111 (H' 3FF) (see
figure 12.5).
• Nonlinear ity error
The error with respect to the ide a l A/D conversion characteristic betwe en zero voltage and full-
scale volta ge. Doe s not i nclude offset error, full-scale error, or quantization error (see figure
12.5).
• Absolute precision
The devia tion betwe en the digital value and t he analog input value. Includes offset error, full-
scale error, quantizatio n error , and nonlin ear ity error.
Rev. 1.0, 02/02, page 339 of 502
111
110
101
100
011
010
001
000 1
1024 2
1024 1022
1024 1023
1024 FS
Quantization error
Digital output
Ideal A/D conversion
characteristic
Analog
input voltage
Figure 12.4 A/D Conversion Precision Definitions
FS
Digital output
Ideal A/D conversion
characteristic
Nonlinearity
error
Analog
input voltage
Offset error
Actual A/D conversion
characteristic
Full-scale error
Figure 12.5 A/D Conversion Precision Definitions
Rev. 1.0, 02/02, page 340 of 502
12.7 Usage Notes
12.7.1 Module Stop Mode Setti ng
Operation of the A/D converter can be disable d or enabled using the m odule stop control registe r.
The initial setting is for operation of the A/D converter to be halted. Register ac cess is enabl e d by
clearing module stop mode. For details, refer to section 19, Power-Down Mode s.
12. 7. 2 Perm i ssi ble Sig na l Sourc e Impe da nce
This LSI's analog input is designed such that conversion precision is guaranteed for an input signal
for whi c h the signal source impeda nce is 10 kΩ or less. This specification is provided to enable
the A/D c onverter's sample-and-hol d circuit input ca pacitance to be cha rged within the sampling
time; if the sensor output impe dance e xceeds 10 kΩ, charging ma y be insufficient and it may not
be possible to guarantee A/D conversion precision. However, for A/D conversion in single mode
with a large capacitance provided ext e rnally, the input load will essentially comprise only the
internal input resist anc e of 10 kΩ, and the signal source impedance is ignored. However, as a low-
pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a
large dif feren tial coef ficient (e.g., 5 mV /µs or great er) (see figure 12.6) . When conv ert ing a high-
speed ana l og signal, a low-impedance buffer should be insert e d.
12. 7. 3 Inf l uenc e s on Absol ute Preci si o n
Adding capacitance results in coupling with GND, and there fore noi se in GND ma y adversely
affect absolute precision. Be sure to make the connection to an electrically stable GND such as
AVss.
Care is also required to insure that filter circuits do not communicate with digital signals on the
mounting board (i.e. acting as antennas).
20 pF
10 k
C
in
=
15 pF
Sensor output
impedance
to 5 k
This LSI
Low-pass
filter
C to 0.1 F
Sensor input
A/D converter
equivalent circuit
Fig ure 12.6 Exampl e of Analog Input Circuit
Rev. 1.0, 02/02, page 341 of 502
12. 7. 4 Range o f Analog Power Supply and Other Pin Settings
If the conditions below are not met, the reliability of the device may be adversely affected.
• Analog input voltage range
The voltage appl ied to analog input pin ANn during A/D conversion should be i n the range
AVss ≤ ANn ≤ AVcc.
• Relationsh i p betwee n AVcc, AVss and Vcc, Vss
Set AVss = Vss as the relation ship between AVss and Vss. If the A/D converter is not use d, set
AVcc = Vcc as the rel ation ship betwe en AVcc and Vcc, and the AVcc and AVss pins must not
be left op en.
12.7.5 Notes on Board Design
In board design, digital circuitry and analog circuitry should be as mutually isolated as possible,
and layout i n whic h digital circuit signal lines and analog circuit signal lines cross or are in close
proximity should be avoi ded as far a s possi ble. Failure to do so may re sult in i ncorrect operation
of the analog circuitry due to inductance, adversely affecting A/D conversion values. Also, digital
circuitry must be isolated from the a nalog input signals (AN0 to AN7), and analog power suppl y
(AVcc) by the analog ground (AVss). Also, the anal og ground (AVss) shoul d be c onnected at one
point to a stable digital ground (Vss) on the board.
12. 7. 6 No t e s o n Noise Counter mea sure s
A protection c ircuit should be connected i n order to prevent dam age due t o abnormal voltage, such
as an excessive surge a t the analog i nput pins (AN0 to AN7), between AVc c and AVss, as shown
in figure 12.7. Also, the bypass capacitors connected to AVcc and the filter capacitor connected to
AN0 t o AN7 must be connect e d to AVss.
If a filter capacitor is connected, the input currents at the analog input pins (AN0 to AN7) are
averaged, and so an error ma y arise. Also, when A/D conversion is performed frequently, as in
scan mode, if the current cha rged and di scharged by the c apacitanc e of the sample-and-hold circuit
in the A/D convert e r exce eds the current input via the input impedance (Rin), an error will arise in
the an alog input p in v o ltage. Careful co n s ideration is th erefore requ ir ed when de ciding cir cuit
constants.
Rev. 1.0, 02/02, page 342 of 502
AVCC
*
1
AN0 to AN7
AVSS
R
in
*
2
100
0.1 F
0.01 F10 F
Notes: Values are reference values.
1.
2. R
in
: Input impedance
Fig ure 12.7 Exampl e of Analog Input Protection Ci rcui t
Table 12. 6 Analog Pin Specificati ons
Item Min Max Unit
Analog input capacitance — 20 pF
Permissible signal source impedance — 5 kΩ
20 pF
AN0 to AN7
Note: Values are reference values.
10 k To A/D converter
Fi g ure 12.8 Analog Input Pin Equivale nt Circui t
Rev. 1.0, 02/02, page 343 of 502
Section 13 Motor Control PWM Ti mer (PWM)
The H8S/2282 has an on-chip motor contr ol PWM (pulse widt h modu lator) with a maximum
capability of 16 pulse output s.
13.1 Features
• Maximum of 16 pulse out puts
Two 10-bit PWM channels, each wit h eight outputs.
Each channel i s provided with a 10-bit counter (PW CNT) and cycle register (PWCYR).
Duty and output pol arity can be set for e ach output .
• Buffered dut y re gi sters
Duty regist ers (PWDTR) are provided with buffer registers (PWBFR), with data
transferred automatically every cycle.
Channel 1 has four duty regist ers and four buffer registers.
Channel 2 has eight duty regi sters and four buffer registers.
• 0% to 100% duty
• Five opera ting cl ocks
There is a choice of five operating clocks (ø, ø/2, ø/4, ø/8, ø/16).
• On-chip output drive r
• High-speed ac cess is possible via a 16-bit bus interface
• Two interrup t sourc es
An interrupt can be requested independently for each channel by a cycle register compare
match.
• Module stop mode can be set
Figure 13. 1 shows a bloc k diagram of PWM channel 1 and fi gure 13.2 shows a bloc k diagram of
PWM channel 2.
MPWM000A_000020020200
Rev. 1.0, 02/02, page 344 of 502
PWCNT_1
PWCYR_1
PWDTR_1A
12 9 0
PWPR_1
P/N
P/N PWM1A
PWM1B
PWBFR_1A
12 9 0
PWDTR_1C P/N
P/N PWM1C
PWM1D
PWBFR_1C
PWDTR_1E P/N
P/N PWM1E
PWM1F
PWBFR_1E
PWDTR_1G P/N
P/N PWM1G
PWM1H
PWBFR_1G
PWCR_1 PWOCR_1
Compare
match
Interrupt
request
Internal
data bus
Bus interface
Port
control
Legend:
PWCR_1: PWM control register_1
PWOCR_1: PWM output control register_1
PWPR_1: PWM polarity register_1
PWCNT_1: PWM counter_1
PWCYR_1: PWM cycle register_1
PWDTR_1A, 1C, 1E, 1G: PWM duty register_1A, 1C, 1E, 1G
PWBFR_1A, 1C, 1E, 1G: PWM buffer register_1A, 1C, 1E, 1G
ø, ø/2, ø/4, ø/8, ø/16
Figure 13.1 Block Diagr am of PWM Channe l 1
Rev. 1.0, 02/02, page 345 of 502
PWBFR_2A
12 9 0
PWBFR_2B
PWBFR_2C
PWBFR_2D
PWCNT_2
PWCYR_2
PWOCR_2
PWPR_2
PWDTR_2A
PWDTR_2B
PWDTR_2C
PWDTR_2D
PWDTR_2E
PWDTR_2F
PWDTR_2G
PWDTR_2H
P/N
PWCR_2
P/N
P/N
P/N
P/N
P/N
P/N
P/N
PWM2A
PWM2B
PWM2C
PWM2D
PWM2E
PWM2F
PWM2G
PWM2H
90
Compare match
ø, ø/2, ø/4, ø/8, ø/16
Legend:
PWCR_2: PWM control register_2
PWOCR_2: PWM output control register_2
PWPR_2: PWM polarity register_2
PWCNT_2: PWM counter_2
PWCYR_2: PWM cycle register_2
PWDTR_2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H: PWM duty register_2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H
PWBFR_2A, 2B, 2C, 2D: PWM buffer register_2A, 2B, 2C, 2D
Internal
data bus
Interrupt
request
Bus interface
Port
control
Figure 13.2 Block Diagr am of PWM Channe l 2
Rev. 1.0, 02/02, page 346 of 502
13.2 Input/Output Pins
Table 13. 1 shows the PWM pin configuration.
Table 13. 1 Pin Configuration
Name Abbrev. I/O Function
PWM out put pin 1A PWM1A Output Channel 1A PWM output
PWM out put pin 1B PWM1B Output Channel 1B PWM output
PWM out put pin 1C PWM1C Output Channel 1C PWM output
PWM out put pin 1D PWM1D Output Channel 1D PWM output
PWM out put pin 1E PWM1E Output Channel 1E PWM output
PWM out put pin 1F PWM1F Output Channel 1F PWM out put
PWM out put pin 1G PWM1G Output Channel 1G PWM output
PWM out put pin 1H PWM1H Output Channel 1H PWM output
PWM out put pin 2A PWM2A Output Channel 2A PWM output
PWM out put pin 2B PWM2B Output Channel 2B PWM output
PWM out put pin 2C PWM2C Output Channel 2C PWM output
PWM out put pin 2D PWM2D Output Channel 2D PWM output
PWM out put pin 2E PWM2E Output Channel 2E PWM output
PWM out put pin 2F PWM2F Output Channel 2F PWM out put
PWM out put pin 2G PWM2G Output Channel 2G PWM output
PWM out put pin 2H PWM2H Output Channel 2H PWM output
13.3 Register Descrip t i on s
The PWM has the following registers. For details on module stop control registers, refer to section
19.1.3, Module Stop Control Regi sters A t o D (MSTPCRA to MSTPCRD).
• PWM c ontrol regi ster_1, 2 (PWCR_1, PWCR_2)
• PWM out put control regi ster_1, 2 (PWOCR_1, PWOCR_2)
• PWM polarity regist er_1 , 2 (PWPR_1 , PWPR_2)
• PWM counter_1, 2 (PWCN T_1 , PWCNT _2)
• PWM cycle register_1,2 (PWCYR _1, PWCY R_2)
• PWM dut y register_1A, 1C, 1E, 1G (PWDTR_1A, PWDT R_1C, PWDTR_1E, PWDTR_1G)
• PWM buffe r re gi ster_1A, 1C, 1E , 1G (PWBFR_1A, PWBFR_1C, PWBFR_1E, PWBFR_1G)
• PWM dut y register_2A to 2H (PWDTR_2A to PWDTRv2H)
• PWM buffe r re gi ster_2A t o 2D (PWBFR_2A to PWBFR_2D)
Rev. 1.0, 02/02, page 347 of 502
13. 3. 1 PWM Contro l Regist er _1, 2 (PWCR_1, PWCR_2)
PWCR perform s int e rrupt control, starting/stopping of the counter, and counte r clock selection. It
also co ntain s a f la g th at indicates a compare match wit h P WC Y R.
Bit Bi t Name Initial Value R/W Reserved
71
61Reserved
Bits 7 and 6 are reserved; they are always
read as 1 and cannot be modified.
5IE 0 R/W
Int errupt Enable
Bit 5 enables or disables an interrupt r equest
in the even t o f a c ompare match w i th PW CY R.
0: Interrupt disabled
1: In terrup t enabled
4CMF0 R/(W)
*Compare Match Flag
Bit 4 i ndi cates t he occurr enc e of a compare
ma tc h with PWCYR.
[Setting condition]
When PWCNT = PWCYR
[Clearing condition]
When 0 is written t o CMF aft er reading CMF =
1
3 CST 0 R/W Counter St art
Bit 3 selects starting or stopping of PWCNT.
0: PWCNT is stopped
1: PWCNT is started
2 CKS2 0 R/W
1 CKS1 0 R/W
0 CKS0 0 R/W
Clock Se le ct
Bits 2 to 0 select the operating clock for
PWCNT.
000: Count s on ø/1
001: Count s on ø/2
010: Count s on ø/4
011: Count s on ø/8
1xx: Count s on ø/16
Note: *O nly 0 can be written, to clear the f lag.
Legend
x: Don’t care
13.3.2 PWM Output Co ntrol Re gist er_ 1, 2 (PWOCR_1 , PWO CR_2)
PWOCR e nables or disables PWM output. PW OCR_1 controls outputs PW M1H to PWM1A, a nd
PWOCR_2 c ontrols outputs PW M2H to PWM2A.
Rev. 1.0, 02/02, page 348 of 502
PWOCR_1
Bit Bit Name Initial Value R/W Reserved
7OE1H 0 R/W
6OE1G 0 R/W
5OE1F 0 R/W
4OE1E 0 R/W
3OE1D 0 R/W
2OE1C 0 R/W
1OE1B 0 R/W
0OE1A 0 R/W
Output Enable
Each of these bits enables or disables the
corresponding PWM1H t o PWM1A output.
0: PWM output is disabled.
1: PWM output is enabled.
PWOCR_2
Bit Bit Name Initial Value R/W Reserved
7OE2H 0 R/W
6OE2G 0 R/W
5OE2F 0 R/W
4OE2E 0 R/W
3OE2D 0 R/W
2OE2C 0 R/W
1OE2B 0 R/W
0OE2A 0 R/W
Output Enable
Each of these bits enables or disables the
corresponding PWM2H to PWM2A out put.
0: PWM output is disabled.
1: PWM output is enabled.
Rev. 1.0, 02/02, page 349 of 502
13.3.3 PWM Polarity R egist er_ 1, 2 (PWPR_1 , PW PR_2)
PWPR selects the PWM output polarity. PWPR_1 controls output s PWM1H to PWM1A, and
PWPR_2 c ontrols output s PWM2H to PWM2A.
PWPR_1
Bit Bit Name Initial Value R/W Reserved
7 OPS1H 0 R/W
6 OPS1G 0 R/W
5 OPS1F 0 R/W
4 OPS1E 0 R/W
3 OPS1D 0 R/W
2 OPS1C 0 R/W
1 OPS1B 0 R/W
0 OPS1A 0 R/W
Polar ity Select
Each of these bits selects the output polarity to
PWM1H to PWM1A.
0: PWM direct output.
1: PWM inverse output.
PWPR_2
Bit Bit Name Initial Value R/W Reserved
7 OPS2H 0 R/W
6 OPS2G 0 R/W
5 OPS2F 0 R/W
4 OPS2E 0 R/W
3 OPS2D 0 R/W
2 OPS2C 0 R/W
1 OPS2B 0 R/W
0 OPS2A 0 R/W
Polar ity Select
Each of these bits selects the output polarity to
PWM2H to PWM2A.
0: PWM direct output.
1: PWM inverse output.
13.3.4 PWM Counter_1, 2 (PWCNT_1, PWCNT_2)
PWCNT is a 10-bit up-c ounter incremented by the input clock. T he input clock is selected by
clo ck s elect b its C K S2 to CK S 0 in P WC R.
PWCNT_1 is used as the channel 1 time base, and PWCNT_2 as the channel 2 time base.
PWCNT is initialized when the CST in PWCR is cleared t o 0, and also upon reset and i n standby
mode, watch mode, subactive mode, subsleep mode, and module stop mode. PWCNT is initialized
to H'FC00.
Rev. 1.0, 02/02, page 350 of 502
13. 3. 5 PWM Cycle Regi ster_1, 2 (PWCYR_1, PWCYR_2)
PWCYR i s a 16-bit read/ write register that sets the PWM conversion cycle. When a PWCYR
compare match occurs, PWCNT is cleared and data is transferred from the buffer register
(PWBFR) to the duty register (PWDTR). PWCYR_1 is used for the channel 1 conversion cycle
setting, and PWCYR_2 for the channel 2 conversion cycle setting.
PWCYR should be written to only while PWCNT is stopped. A value of H'FC00 must not be set.
PWCYR is initial ized to H'FFFF upon reset. Figure 13.3 shows t he compare match of the cycle
registers.
01 01
N
N–1
PWCNT
(lower 10 bits)
PWCYR
(lower 10 bits)
N–2
Compare matchCompare match
Figure 13.3 Cycle Register Compare Match
13.3.6 PWM Duty Register_1A, 1C, 1E, 1G (PWDTR_1A, PWDTR_1C, PWDTR_1E,
PWDTR_1G)
There are four PWDT R_1 reg iste rs . The PWM outpu t is deter min ed by the valu e of the OTS bit,
and PWDTR_1A is used for outputs PWM1A and PWM1B, PWDTR_1C for outputs PW M1C
and PWM1D, PWDTR_1E for output s PWM1E and PWM1F, and PWDTR_1G for outputs
PWM1G and PWM1H.
The PWDT R_1 re gi sters c annot be read from or written to directly. When a PWCYR_1 compare
match occurs, data i s transferred from buffer registe r 1 (PW BFR_1) to PWDTR_1.
The PWDT R_1 re gi sters a re initialized when the CST bit in PW CR_1 is cleared to 0, and al so
upon reset and in sta ndby mode and module st op mode.
Rev. 1.0, 02/02, page 351 of 502
Bit Bi t Name Initial Value R/W Reserved
15 to 13 1Reserved
These bits cannot be read from or writt en to.
12 OTS 0 O utput Terminal Select
Bit 12 indicates the value in bit 12 of
PWBFR_1 sent by a PWCYR_1 compar e
match, and selects t he pin used for PWM
output. Unselected pins output a low level (or a
high level when the corresponding bit in
PWPR_1 is set to 1).
PWDTR_1A register
0: PWM1A output selected
1: PWM1B output selected
PWDTR_1C
0: PWM 1C output selected
1: PWM 1D output selected
PWDTR_1E
0: PWM1E output selected
1: PWM 1F output selected
PWDTR_1G
0: PWM 1G output sel ected
1: PWM 1H output selected
11
10
1
1
Reserved
These bits are always read as 1 and cannot be
modified.
9DT90
8DT80
7DT70
6DT60
5DT50
4DT40
3DT30
2DT20
1DT10
0DT00
Duty
Bits 9 to 0 indicate the data in bits 9 to 0 of
PWBFR_1 sent by a PWCYR_1 compar e
match, and specify t he PWM out put dut y. A
high level (or a low level when the
corresponding bit in PWPR_1 is set to 1) is
output from the time PWCNT_1 is clear ed by a
PWCYR_1 compare m atch until a PWDTR_1
compare match occurs. When all of t he bits
are 0, ther e is no high- level (or low-level when
the corresponding bit in PWPR_1 is set to 1)
output period.
Rev. 1.0, 02/02, page 352 of 502
PWCNT_1
(lower 10 bits)
PWCYR_1
(lower 10 bits)
PWDTR_1
(lower 10 bits)
PWM output on
selected pin
PWM output on
unselected pin
Compare match
01
N
M
M–2 M–1 M N–1 0
Figure 13.4 Duty Register Compare Match (OPS = 0 in PWPR_1)
0 1 N–1 0
N
M
N–2
PWCNT_1
(lower 10 bits)
PWCYR_1
(lower 10 bits)
PWDTR_1
(lower 10 bits)
PWM output
(M = 0)
PWM output
(0 < M < N)
PWM output
(N ≤ M)
Figure 13.5 Differences in PWM Output According to Duty Register Set Value
(OPS = 0 in PWPR_1)
13.3.7 PWM Buffe r Register_1A, 1C, 1E, 1G (PWBF R_1A, PWBFR_1C, PWBFR_1E,
PWBFR_1G)
There are four PWBFR_1 registers. When a PWCYR_1 compare match occurs, data is transferred
from PWBFR_1A to PWDTR_1A, from PWBFR_1C t o PWDTR_1C, from PWBFR_1E to
PWDTR_1E, and from PWBFR_1G to PW DTR_1G.
Rev. 1.0, 02/02, page 353 of 502
Bit Bi t Name Initial Value R/W Reserved
15 to 13 1Reserved
These bits are always read as 1 and cannot be
modified.
12 OTS 0 R/W Output Terminal Select
Bit 12 is the data sent to bit 12 of PWDTR_1.
11
10
1
1
Reserved
These bits are always read as 1 and cannot be
modified.
9DT90 R/W
8DT80 R/W
7DT70 R/W
6DT60 R/W
5DT50 R/W
4DT40 R/W
3DT30 R/W
2DT20 R/W
1DT10 R/W
0DT00 R/W
Duty
Bits 9 to 0 comprise the data sent to bits 9 to 0
in PWDTR_1.
13.3.8 PWM Duty Register_2A to 2H (PWDTR_2A to PWDTR_2H)
There are eight PWDTR_2 registers. PWDTR_2A is used for output PWM2A, PW DTR_2B for
output PWM2B, PWDTR_2C for output PWM2C, PWDT R_2D for output PWM2D, PWDTR_2E
for output PWM2E, PWDTR_2F for output PWM2F, PW DTR_2G for output PWM2G, a nd
PWDTR_2H for output PWM2H.
The PWDT R_2 re gi sters c annot be read from or written to directly. When a PWCYR_2 compare
match occurs, data i s transferred from buffer registe r 2 (PW BFR_2) to PWDTR_2.
The PWDT R_2 re gi sters a re initialized when the CST bit in PW CR_2 is cleared to 0, and al so
upon reset and in sta ndby mode and module st op mode.
Rev. 1.0, 02/02, page 354 of 502
Bit Bi t Name Initial Value R/W Reserved
15 to 10 1Reserved
These bits cannot be read from or writt en to.
9DT90 R/W
8DT80 R/W
7DT70 R/W
6DT60 R/W
5DT50 R/W
4DT40 R/W
3DT30 R/W
2DT20 R/W
1DT10 R/W
0DT00 R/W
Duty
Bits 9 to 0 indicate the data in bits 9 to 0 of
PWBFR_2 sent by a PWCYR_2 compar e
match, and specify t he PWM out put dut y. A
high level (or a low level when the
corresponding bit in PWPR_2 is set to 1) is
output from the time PWCNT_2 is clear ed by a
PWCYR_2 compare m atch until a PWDTR_2
compare match occurs. When all the bits are
0, there is no high-level (or low-level when the
corresponding bit in PWPR_2 is set to 1)
output period.
PWCNT_2
(lower 10 bits)
PWCYR_2
(lower 10 bits)
PWDTR_2
(lower 10 bits)
PWM output
Compare match
01
N
M
M–2 M–1 M N–1 0
Figure 13.6 Duty Register Compare Match (OPS = 0 in PWPR_2)
Rev. 1.0, 02/02, page 355 of 502
0 1 N–1 0
N
M
N–2
PWCNT_2
(lower 10 bits)
PWCYR_2
(lower 10 bits)
PWDTR_2
(lower 10 bits)
PWM output
(M = 0)
PWM output
(0 < M < N)
PWM output
(N ≤ M)
Figure 13.7 Differences in PWM Output According to Duty Register Set Value
(OPS = 0 in PWPR_2)
13.3.9 PWM Buffe r Register_2A to 2D (P WBFR2_A to PWBFR_2D)
There are four PWBFR_2 registers. The transfer destination is determined by the value of the TDS
bit, and when a PWCYR_2 com pare m a tch occ urs, data is tra nsferre d from PWBFR_2A to
PWDTR_2A or PWDTR_2E, from PWBFR_2B to PWDT R_2B or PWDTR_2F, from
PWBFR_2C to PWDTR_2C or PW DTR_2G, and from PWBFR_2D t o PWDTR_2D or
PWDTR_2H.
Rev. 1.0, 02/02, page 356 of 502
Bit Bi t Name Initial Value R/W Reserved
15 to 13 1Reserved
These bits are always read as 1 and cannot be
modified.
12 TDS 0 R/W Tr a nsf er Dest in ation Select
Bit 12 selects the PWDTR_2 register t o which
data is t o be transferred.
PWBFR_2A
0: PWDTR_2A selected
1: PWDTR_2E selected
PWBFR_2B
0: PWDTR_2B selected
1: PWDTR_2F selected
PWBFR_2C
0: PWDTR_2C selected
1: PWDTR_2G select ed
PWBFR_2D
0: PWDTR_2D selected
1: PWDTR_2H selected
11 1
10 1Reserved
These bits are always read as 1 and cannot be
modified.
9DT90 R/W
8DT80 R/W
7DT70 R/W
6DT60 R/W
5DT50 R/W
4DT40 R/W
3DT30 R/W
2DT20 R/W
1DT10 R/W
0DT00 R/W
Duty
Bits 9 to 0 comprise the data sent to bits 9 to 0
in PWDTR_2.
Rev. 1.0, 02/02, page 357 of 502
13.4 Bus Master In t erf ace
13.4.1 16-Bit Data Registers
PWCYR_1, PWCYR_2, PWBFR_1A, PWBFR_1C, PWBFR_1E, PW BFR_1G, a nd PWBFR_2A
to PWBFR_2D are 16-bit registers. These registers are linked to the bus maste r by a 16-bit data
bus, and can be read or written in 16-bit units. They cannot be read or written by 8-bit access; 16-
bit access must alw ays be used.
H
L
PWCYR_1
Bus
master
Internal data bus
Bus
interface Module
data bus
Figure 13.8 16-Bit Regi ster Acce ss Operation (Bus Master ↔ PWCYR_1 (1 6 Bits))
13.4.2 8-Bit Data Registers
PWCR_1, PWCR_2, PWOCR_1, PW OCR_2, and PWPR_1, PW PR_2 are 8-bit registers t hat ca n
be rea d and written to in 8-bit uni ts. These regist ers are linked to the bus mast er by a 16-bit data
bus, and can be read or written by 16-bit access; in this case, the lower 8 bits are read as an
undefined val ue.
H
L
PWCR_1
Bus
master
Internal data bus
Bus
interface Module
data bus
Figure 13.9 8-Bit Regi ster Access Operation (Bus Master ↔ PWCR_ 1 (Uppe r 8 Bit s))
Rev. 1.0, 02/02, page 358 of 502
13.5 Operation
13.5.1 PWM Channel 1 O peration
PWM waveforms are output from pins PWM1A to PWM1H as shown i n figure 13.10.
Initial Setti ngs: Set the PWM output polarity in PWPR_1; enable the PWM1A to PWM1H pins
for PW M output with PWOCR_1; select the c lock to be input to PWCNT_1 wi th bits CKS2 to
CKS0 in PWCR_1; set the PWM conversion cycle in PWCYR_1; and set the first frame of data in
PWBFR_1A, PWBFR_1C, PWBFR_1E, and PWBFR_1G.
Activation: When the CST bit in PWCR_1 is set to 1, a compare match between PWCNT_1 and
PWCYR_1 i s generated. Data is transferred from PWBFR_1A to PW DTR_1A, from PWBFR_1C
to PWDTR_1C, from PWBFR_1E to PWDTR_1E, a nd from PWBFR_1G to PWDTR_1G.
PWCNT_1 starts counti ng up. At the same time the CMF bit in PWCR_1 is set, so that, if the IE
bit in PW CR_1 has bee n set, an interrupt can be requested.
Waveform Output: The PWM output s selected by the OTS bits in PW DTR_1A, PWDT R_1C,
PWDTR_1E, and PWDTR_1G go high when a com pare match occurs be tween PWCNT_1 and
PWCYR_1. The PWM outputs not selected are low. When a compare match occurs between
PWCNT_1 and PWDT R_1A, PW DTR_1C, PWDTR_1E, PWDTR_1G, the c orresponding PWM
output goe s low. If the corre sponding bit i n PWPR_1 is set to 1, the output is i nverted.
Next Frame: When a compare match occurs between PWCNT_1 and PWCYR_1, data is
transferred from PWBFR_1A to PWDT R_1A, from PWBFR_1C t o PWDTR_1C, from
PWBFR_1E to PWDTR_1E, and from PWBFR_1G to PWDTR_1G. PWCNT_1 is reset and starts
counting up from H' 000. The CMF bit in PWCR_1 is se t, and if the IE bit in PW CR_1 has been
set, an interrupt can be reque sted.
Stopping: When the CST bit in PWCR_1 is cleared to 0, PWCNT_1 is reset and stops. All PWM
outputs go low (or high if t he corre sponding bit i n PWPR_1 i s set to 1).
Rev. 1.0, 02/02, page 359 of 502
PWBFR_1A
PWCYR_1
PWM1A
PWDTR_1A
PWM1B
OTS (PWDTR_1A) = 1OTS (PWDTR_1A) = 0OTS (PWDTR_1A) = 1OTS (PWDTR_1A) = 0
Figure 13.10 PWM Channel 1 Operation
13.5.2 PWM Channel 2 O peration
PWM waveforms are output from pins PWM2A to PWM2H as shown i n figure 13.11.
Initial Setti ngs: Set the PWM output polarity in PWPR_2; enable the PWM2A to PWM2H pins
for PW M output with PWOCR_2; select the c lock to be input to PWCNT_2 wi th bits CKS2 to
CKS0 in PWCR_2; set the PWM conversion cycle in PWCYR_2; and set the first frame of data in
PWBFR_2A, PWBFR_2B, PWBFR_2C, a nd PWBFR_2D.
Activation: When the CST bit in PWCR_2 is set to 1, a compare match between PWCNT_2 and
PWCYR_2 i s generated. Data is transferred from PWBFR_2A to PW DTR_2A or PWDTR_2E,
from PWBFR_2B to PWDT R_2B or PWDT R_2F, from PWBFR_2C to PWDTR_2C or
PWDTR_2G, and from PWBFR_2D to PWDTR_2D or PWDTR_2H, ac cording to the va l ue of
the TDS bit. PWCNT _2 starts count ing up. At the same time the CMF bit in PWCR_2 is set, so
that, if the IE bit in PW CR_2 has bee n set, an interrupt can be re quested.
Waveform Output: The PWM output s go high whe n a com pare match occurs bet ween
PWCNT_2 and PWCYR_2. When a compare match occurs between PWCNT_2 and PWDTR_2A
to PWDTR_2H, the c orresponding PWM output goes low. If the c orresponding bit in PWPR_2 is
set to 1 , the o utput is invert ed.
Next Frame: When a compare match occurs between PWCNT_2 and PWCYR_2 data is
transferred from PWBFR_2A to PWDT R_2A or PWDTR_2E, from PWBFR_2B to PW DTR_2B
or PWDT R_2F, from PWBFR_2C to PWDTR_2C or PWDTR_2G, and from PWBFR_2D t o
PWDTR_2D or PWDTR_2H, according to the value of the TDS bit. PWCNT _2 is reset and starts
counting up from H' 000. The CMF bit in PWCR_2 is se t, and if the IE bit in PW CR_2 has been
set, an interrupt can be reque sted.
Rev. 1.0, 02/02, page 360 of 502
Stopping: When the CST bit in PWCR_2 is cleared to 0, PWCNT_2 is reset and stops.
PWDTR_2A to PWDTR_2H are reset. All PW M out puts go low (or high i f the corresponding bit
in PWPR_2 is set to 1).
TDS (PWBFR
_
2A) = 0 TDS (PWBFR
_
2A) = 1 TDS (PWBFR
_
2A) = 0
PWBFR_2A
PWCYR_2
PWM2A
PWDTR_2A
PWM2B
PWDTR_2E
Figure 13.11 PWM Channel 2 Operation
13.6 Interrupts
If the IE bit in PWCR is set to 1 when the CMF flag in PWCR is set to 1 by a compare match
between PW CNT and PWCYR, an interrupt is reque sted. Table 13.2 shows t he PWM interrupt
sources.
Table 13.2 PWM Interrupt Sources
Name Interrupt Source Interrupt Flag
CMI1 P WCYR _1 compare ma tch CMF
CMI2 P WCYR _2 compare ma tch CMF
13.7 Usage Note
Contention between Buffer Registe r Write and Compare Match: If a PW BFR writ e is
performed in the sta te immedi ately after a cycle re gister c ompare m atch, the buffer register and
duty register are overwritten. PWM output changed by the cycle register compare match is not
changed in overwrite of the duty register due to contention. This may result in unanticipated duty
output. In the case of channel 2, the duty register used as the transfer destination is selected by the
TDS bit of the buffe r register when an overwrite of the duty register occurs due to contention. This
can also result in a n unintended overwrite of the duty regi ster. Buffer regist er rewriting must be
completed before, exception ha ndling due to a compa re match interrupt, or the oc c urrence of a
cycle register compare match on detection of the rise of the CMF flag in PWCR.
Rev. 1.0, 02/02, page 361 of 502
T1 Tw Tw T2
ø
Address
Write signal
PWCNT
(lower 10 bits)
PWBFR
PWDTR
PWM output
CMF
Buffer register address
Compare match
0
MN
MN
Figure 13.12 Contenti on betwee n Buffer registe r Write and Compare Match
Rev. 1.0, 02/02, page 362 of 502
Rev. 1.0, 02/ 02, page 363 of 502
Section 14 LCD Controller/Driver (LCD)
This LSI has an on-chi p segm ent t ype L CD cont rol c i rcui t , LCD drive r, a nd power supply
circuit, enabling it to directly drive an LCD panel.
14.1 Features
• Display capacity
Duty Cycle Int ernal Dri ver
Static 28 SEG
1/3 28 SEG
1/4 28 SEG
• Display LCD RAM capacity
8 bits × 20 bytes (160 bit s)
Byte or word access to LCD RAM
• The segment out put pi ns ca n be used a s ports in groups of four.
• Common output pins not used because the duty cycle can be used for common double-
buffering (parallel connection).
In static mode, parallel connection of COM1 to COM2, and of COM3 to COM4 can be
used
• Choice of 11 frame frequencies
• A or B waveform selectable by software
• Built-in power supply split-resi stance
• Display possible in opera t ing m ode s other t ha n standby m ode and m odul e stop m ode
LCDSG01A_000020020200
Rev. 1.0, 02/ 02, page 364 of 502
Figure 14.1 shows a block diagram of the LCD controller/driver.
ø/8 to ø/1024
øSUB
CL2
CL1
SEGn, DO
LPCR
LCR
LCR2
Display timing generator
LCD RAM
20 bytes
Internal data bus
28-bit
shift
register
LCD drive
power supply
Segment
driver
Common
data latch Common
driver
M
V1
V2
V3
VSS
COM4
COM1
SEG28
SEG27
SEG26
SEG25
SEG24
SEG1
Legend:
LPCR: LCD port control register
LCR: LCD control register
LCR2: LCD control register 2
LPVCC
Figure 14.1 Block Diagram of LCD Controller/Driver
14.2 Input/Output Pins
Table 14.1 shows the LCD controller/driver pin configuration.
Table 14.1 Pin Configuration
Name Abbrev. I/O Function
Segment out put
pins SEG28 to SEG1 Output LCD segment dr ive pins
All pins are mult iplexed as port pins (setting
programmable)
Common out put
pins COM4 to CO M 1 Out put LCD common drive pins
Pins can be used in parallel with stat ic
LCD power supply
pins V1, V2, V3 — Used when a bypass capacitor is connected
externally, and when an ext er nal power
supply circuit is used
Rev. 1.0, 02/ 02, page 365 of 502
14.3 Register Descriptions
The LCD controller/driver has the following registers. For details on module stop control, see
section 19.1.3, Module Stop Control Registers A to D (MSTPCRA to MSTPCRD).
• LCD port control re giste r (L PCR)
• LCD control re gi ster (L CR)
• LCD control re gi ster 2 (L CR2)
14. 3 .1 LCD Po r t Cont r o l Regi st e r (LPCR)
LPCR selects the duty cycle, LCD driver, and pin functions.
Bit Bit Name I ni tial Val ue R/ W Descript i on
7DTS10 R/W
6DTS00 R/W
Duty Cycle Select 1 and 0
The combination of DTS1 and DTS0 selects
stat ic, 1/ 3, or 1/ 4 dut y. For details, see table
14.2.
5 CMX 0 R/W Common Funct ion Select
Specifies whether or not the same wavefor m is
to be output from m ultiple pins to increase the
common dr ive power when all common pins are
not used because of t he dut y set t ing. For det ails,
see table 14.2.
40Reserved
This bit should only be written with 0.
3SGS30 R/W
2SGS20 R/W
1SGS10 R/W
0SGS00 R/W
Segment Driver Select 3 t o 0
Bits 3 to 0 select the segment dr ivers t o be used.
For details, see table 14.3.
Rev. 1.0, 02/ 02, page 366 of 502
Table 14.2 Selection of the Duty Cycle and Common Func tions
Bit 7:
DTS1 Bit 6:
DTS0 Bit 5:
CMX Duty Cycle Comm on Dri ver s Notes
0 0 0 Static COM1 COM4, CO M 3, and CO M 2 can
be used as ports
1 COM 4 t o CO M 1 CO M 4, CO M 3, and CO M 2
output t he sam e waveform as
COM1
1 X — — Setting prohibited
1 0 0 1/ 3 dut y COM3 to COM 1 CO M 4 can be used as a por t
1 COM 4 t o CO M 1 CO M 4 use is prohibited
1 X 1/4 duty COM4 to CO M 1
Legend
X: Don’t care
Table 14.3 Selection of Segment Drivers
Function of Pins SEG28 to SEG1
Bit 3:
SGS3 Bit 2:
SGS2 Bit 1:
SGS1 Bit 0:
SGS0 SEG28 to
SEG21 SEG20 to
SEG17 SEG16 to
SEG13 SEG12 to
SEG9 SEG8 to
SEG5 SEG4 to
SEG1
0 0 0 0 Port Port Port Port Port Port
1 SEG Port Port Port Port Port
1 0 SEG SEG Port Port Port Port
1 SEG SEG SEG Port Port Port
1 0 0 SEG SEG SEG SEG Port Port
1 SEG SEG SEG SEG SEG Port
1 0 SEG SEG SEG SEG SEG SEG
1 Setting
prohibited Setting
prohibited Setting
prohibited Setting
prohibited Setting
prohibited Setting
prohibited
1 X X X Setting
prohibited Setting
prohibited Setting
prohibited Setting
prohibited Setting
prohibited Setting
prohibited
Legend
X: Don’t care
Rev. 1.0, 02/ 02, page 367 of 502
14. 3 .2 LCD Contr o l Regi st e r (LCR)
LCR performs LCD power supply split-resistance connection control and display data control,
and selects the frame frequency.
Bit Bit Name I ni t ial Val ue R/ W Descript ion
71Reserved
This bit is always read as 1 and cannot be
modified.
6 PSW 0 R/W LCD Power Supply Split-Resistance Connection
Control
Bit 6 can be used to disconnect t he LCD power
supply split-resistance fr om VCC when LCD display
is not required in a power- down mode, or when an
external power supply is used. W hen ACT is 0 or
in standby mode, the LCD power supply split-
resistance is disconnected fr om VCC r egar dless of
the set t ing of t his bit.
0: LCD power supply split-r esistance is
disconnected fr om VCC
1: LCD power supply split-r esistance is connect ed
to VCC
5 ACT 0 R/W Display Function Activate
Bit 5 specifies whether or not t he LCD
controller/ dr iver is used. Clearing this bit t o 0 halt s
operation of t he LCD contr oller/ dr iver . The LCD
drive power supply ladder resistance is also turned
off, regardless of the set t ing of t he PSW bit.
However, register cont ent s ar e retained.
0: LCD controller/ dr iver oper at ion halted
1: LCD controller/ dr iver oper at es
4 DI SP 0 R/W Disp lay Da ta Co ntr o l
Bit 4 specifies whether the LCD RAM contents ar e
displayed or blank data is displayed.
0: Blank data is displayed
1: LCD RAM data is displayed
3 CKS3 0 R/W
2 CKS2 0 R/W
1 CKS1 0 R/W
0 CKS0 0 R/W
Frame Fr equency Select 3 to 0
Bits 3 to 0 select the operating clock and the frame
frequency. For det ails, see t able 14. 4.
Rev. 1.0, 02/ 02, page 368 of 502
Table 14.4 Selection of the Operating Clock and Frame Frequency
Bit 3: Bit 2: Bi t 1: Bit 0: Frame Fr equency *1
CKS3 CKS2 CKS1 CKS0 Opera t ing Cl ock ø = 20 M Hz
0 X 0 0 øSUB 128 Hz*2
1 øSUB/ 2 64 Hz*2
1 X øSUB/4 32 Hz *2
1000ø
w/8 4880 Hz
1ø
w/16 2440 Hz
10ø
w/32 1220 Hz
1ø
w/64 610 Hz
100ø
w/128 305 Hz
1ø
w/256 152. 6 Hz
10ø
w/512 76. 3 Hz
1ø
w/1024 38. 1 Hz
Legend
X: Don’t care
Notes: 1. When 1/ 3 dut y is selected, the fr am e f r equency is 4/ 3 t imes the value shown.
2. This is the fram e f r equency when øSUB = 32.768 kHz.
14. 3 .3 LCD Contr o l Regi st e r 2 (L CR2 )
LCR2 controls switching between the A waveform and B waveform.
Bit Bit Name Ini t ial Val ue R/ W Descript i on
7 LCDAB 0 R/W A Wav e for m/ B W a v eform Switch in g Co ntr o l: Bit
7 specifies whether the A wavefor m or B
waveform is used as t he LCD drive waveform .
0: Drive using A waveform
1: Drive using B waveform
61
51
Reserved: These bits ar e always read as 1 and
cannot be modif ied.
4 to 0 0Reserved: These bit s ar e always read as 0 and
should only be written with 0.
Rev. 1.0, 02/ 02, page 369 of 502
14.4 Operation
14. 4 .1 Sett i ng s up to L CD Di spl a y
To perform LCD display, the hardware and software related items described below must first be
determined.
Hardwar e Se tt i ng s
• Panel display
As the impedance of the built-in power supply split-resistance is large, it may not be suitable
for driving a panel. If the display lacks sharpness, see section 14.4.4, Boosting the LCD
Drive Power Supply. When static is selected, the common output drive capability can be
increased. Set the CMX bit in LPCR to 1 when selecting the duty cycle. With a static cycle,
pins COM4 to COM1 output the same wa veform.
• LCD drive power supply setting
With the H8S/2282, there are two ways of providing LCD power: by using the on-chip power
supply circui t , or by using an e xt erna l power supply ci rc uit .
When an external power supply circuit is used for the LCD drive power supply, connect the
externa l power supply to t he V1 pin.
Software Settings
• Duty selection
Duty cycles can be selected by setting bits DTS1 and DTS0.
• Segment selection
The segment drivers to be used can be selected by setting bits SGS3 t o SGS0 .
• Frame frequency selection
The frame frequency can be selected by setting bits CKS3 to CKS0. The frame frequency
should be selected in accordance with the LCD panel specification. For the clock selection
method in watch mode, subactive mode, and subsleep mode, see section 14.4.3, Operation in
Power-Down Mode s.
• A or B waveform selection
Either the A or B waveform can be selected as the LCD waveform to be used by means of
the LCDAB bit.
• LCD drive power supply selection
When an e xt erna l power supply ci rc uit i s used, t urn the L CD drive power supply off by
clearing the PSW bit to 0.
Rev. 1.0, 02/ 02, page 370 of 502
14. 4 .2 Rel at i o nshi p betwe en LCD RAM a nd Di spl a y
The relationship between the LCD RAM and the display segments differs according to the duty
cycle. LCD RAM maps for the different duty cycles are shown in figures 14.2 to 14.4.
After setting the registers required for display, data is written to the part corresponding to the
duty using the same kind of instruction as for ordinary RAM, and display is started automatically
when turned on. Word- or byte-access instructions can be used for RAM setting.
Bit 7
H'FC40
H'FC45
COM4
Bit 6
COM3
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
SEG2
H'FC46 SEG2 SEG2 SEG2 SEG1 SEG1 SEG1 SEG1
SEG28 SEG28 SEG28 SEG28 SEG27 SEG27 SEG27 SEG27
H'FC53
COM2 COM1 COM4 COM3 COM2 COM1
Display space
Space not used
for display
Figure 14. 2 LCD RAM Map (1/4 Duty)
Rev. 1.0, 02/ 02, page 371 of 502
Bit 7
H'FC40
H'FC45
Bit 6
COM3
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
H'FC46 SEG2 SEG2 SEG2 SEG1 SEG1 SEG1
SEG28 SEG28 SEG28 SEG27 SEG27 SEG27
H'FC53
COM2 COM1 COM3 COM2 COM1
Display space
Space not used
for display
Figure 14. 3 LCD RAM Map (1/3 Duty)
Bit 7
COM1
Bit 6
COM1
Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
H'FC40
H'FC41 SEG12H'FC42 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5
SEG28H'FC44 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21
H'FC53
COM1 COM1 COM1 COM1 COM1 COM1
Space not used
for display
Space not
used for
display
Display
space
SEG4 SEG3 SEG2 SEG1
Figure 14.4 LCD RAM Map (Static Mode)
Rev. 1.0, 02/ 02, page 372 of 502
M
COM1
COM2
COM3
COM4
SEGn
V1
V2
V3
VSS
V1
V2
V3
VSS
V1
V2
V3
VSS
V1
V2
V3
VSS
V1
V2
V3
VSS
M
COM1
COM2
COM3
SEGn
V1
V2
V3
VSS
V1
V2
V3
VSS
V1
V2
V3
VSS
V1
V2
V3
VSS
M
COM1
SEGn
V1
VSS
V1
VSS
1 frame
Data
1 frame
Data
(a) Waveform with 1/4 duty
1 frame
Data
(b) Waveform with 1/3 duty
(c) Waveform with static output
Figure 14.5 Output Waveforms for Each Duty Cycle (A Waveform)
Rev. 1.0, 02/ 02, page 373 of 502
M
Data
COM1
SEGn
V1
VSS
V1
VSS
(c) Waveform with static output
(b) Waveform with 1/3 duty
M
Data
COM3
SEGn
COM1 V1
V2
V3
V
SS
V1
V2
V3
VSS
V1
V2
V3
VSS
V1
V2
V3
VSS
V1
V2
V3
VSS
V1
V2
V3
VSS
V1
V2
V3
VSS
V1
V2
V3
V
SS
V1
V2
V3
VSS
COM2
(a) Waveform with 1/4 duty
M
Data
COM1
COM2
COM3
COM4
SEGn
1 frame 1 frame 1 frame 1 frame
1 frame 1 frame 1 frame 1 frame
1 frame 1 frame 1 frame 1 frame
Figure 14.6 Output Waveforms for Each Duty Cycle (B Waveform)
Rev. 1.0, 02/ 02, page 374 of 502
Table 14.5 Output Levels
Data 0011
M 0101
Static Common output V1 VSS V1 VSS
Segment out put V1 VSS VSS V1
1/3 dut y Comm on out put V3 V2 V1 VSS
Segment out put V2 V3 VSS V1
1/4 dut y Comm on out put V3 V2 V1 VSS
Segment out put V2 V3 VSS V1
14.4.3 Operation in Power-Down Modes
The LCD controller/driver can be operated even in the power-down modes. The operating state
of the LCD controller/driver in the power-down modes is summarized in table 14.6.
In active (medium-speed) mode, the system clock is switched, and therefore the CKS3 to CKS0
bits must be modified to ensure that the frame frequency does not change.
In software standby mode , when boosti ng the L CD drive power supply, t he segme nt output a nd
common output pins retain their values, and the DC voltage could be applied to the LCD panel.
There fore , be fore e nt e ri ng softwa re st a ndby m ode, the SGS3 t o SGS0 bi t s must be se t t o 0 a nd
then DDR must be set t o 0 for port s being used for segm e nt out put or com m on output .
Tabl e 1 4 . 6 P o we r-Do wn M o de s a nd Di spl a y O pe rat i o n
Mode Reset Active Sleep Watch Subactive Subsleep Standby Module
Standby
Clock ø Runs Runs Runs Stops Stops Stops Stops Stops*3
øSUB Runs Runs Runs Runs Runs Runs Stops Stops*3
Display ACT = 0 Stops Stops Stops Stops Stops Stops Stops*1Stops
operation ACT = 1 Stops Functions Functions Functions*2Functions*2Functions*2Stops*1Stops
Notes: 1. The LCD drive power supply is turned off r egar dless of t he set ting of the PSW bit.
2. Display operation is perform ed only when øSUB, øSUB/2, or øSUB/4 is selected as the
clock.
3. The clock supplied to the LCD stops.
Rev. 1.0, 02/ 02, page 375 of 502
14.4. 4 Boosting the LCD Dr i v e P owe r Suppl y
When a panel is driven, the on-chip power supply capacity may be insufficient. In this case, the
power supply impedance must be reduced. This can be done by connecting bypass capacitors of
around 0.1 to 0.3 µF to pins V1 to V3, as shown in figure 14.7, or by adding a split-resistance
externally.
H8S/2282
LPV
CC
V
SS
V1
V2
V3
VR
R
R
R
R =
C = 0.1 to 0.3 µF
several kΩ to
several MΩ
Figure 14.7 Connection of External Split-Resistance
Rev. 1.0, 02/ 02, page 376 of 502
Rev. 1.0, 02/02, page 377 of 502
Section 15 RAM
This LSI ha s 4 kbytes of on-chi p high-spe ed static RAM. The RAM is conne cted to the CPU by a
16-bit da ta bus, enabling one-state access by the CPU to both byte data and word data.
The on-chip RAM can be enabled or disabled by m eans of the RAME bit in the system cont rol
reg i ste r (SYSCR ). For detail s on SYSCR, refer to section 3.2.2, Syste m Contr o l Regi ste r
(SYSCR).
Product Type Nam e ROM Type RAM
Capacit anc e RAM Address
HD64F2282 Flash memory ver sion 4 kbytes H'FFE000 to H'FFEFBF
HD6432282 4 kbytes H'FFE000 t o H'FFEFBF
H8S/2282
Series
HD6432281
Mask ROM version
4 kbytes H'FFE000 t o H'FFEFBF
Rev. 1.0, 02/02, page 378 of 502
Rev. 1.0, 02/02, page 379 of 502
Section 16 Flash Memory (F-ZTAT Version)
The features of the flash memory a re summarized below.
The block diagram of the flash memory is shown i n figure 16.1.
16.1 Features
• Size: 128 kbytes
• Progra mm ing/erase methods
The flash memory is programmed 128 bytes at a time. Erase is performed in single-block
units. The flash memory i s confi gured as follows: 32 kbytes × 2 blocks, 28 kbytes × 1
block, 16 kbytes × 1 block, 8 kbytes × 2 blocks, and 1 kbyte × 4 blocks. To erase the entire
flash memory, each block must be erased in turn.
• Reprogram ming ca pa bility
The flash memory c an be re programmed up to 100 times.
• Two on-bo ard progr am min g mod es
Boot mode
User program mode
Programm er mod e
On-board programming/erasing can be done in boot mode, in which the boot program built
into the chip is sta rted to e rase or program of the ent i re flash memory. In normal user
program mode, individual bloc ks can be e rased or programmed.
• Automatic bit rate adjustment
For data transfer in boot mode, thi s LSI's bi t rate ca n be aut omatically adjusted t o match
the transfer bit rate of the host.
• Programming/erasi ng protection
Sets hardware protection, software prote c tion, or error protection against fl a sh me mory
programming/erasing.
• Progra mm er mode
Flash memory ca n be programmed/erased in programmer mode using a PROM
programmer, as we ll as in on-board programming mode.
ROMF380A_000020020200
Rev. 1.0, 02/02, page 380 of 502
Module bus
Bus interface/controller
Flash memory
(128 kbytes)
Operating
mode
FLMCR2
Internal address bus
Internal data bus (16 bits)
FWE pin
Mode pin
EBR1
EBR2
RAMER
FLPWCR
FLMCR1
Flash memory control register 1
Flash memory control register 2
Erase block register 1
Erase block register 2
RAM emulation register
Flash memory power control register
Legend
FLMCR1:
FLMCR2:
EBR1:
EBR2:
RAMER:
FLPWCR:
Figure 16.1 Block Diagram of Flash M emory
16.2 Mode Transitions
When the mode pins and the FWE pin are set in the reset state and a reset-start is executed, this
LSI ente rs an operating m ode as shown i n figure 16.2. In user mode, fla sh memory can be rea d but
not progra mmed or erased.
The boot, user program and programmer modes a re provided as modes to write a nd erase the flash
memory.
The differe nces between boot mode a nd use r progra m mode are shown in table 16. 1.
Figure 16. 3 shows the operation flow for boot mode and fi gure 16.4 shows that for user progra m
mode.
Rev. 1.0, 02/02, page 381 of 502
Boot mode
On-board programming mode
User
program mode
User mode
(on-chip ROM
enabled)
Reset state
Programmer
mode
= 0
FWE = 1 FWE = 0
*1
*1
*2
Notes: Only make a transition between user mode and user program mode when the CPU is
not accessing the flash memory.
1. RAM emulation possible
2. This LSI transits to programmer mode by using the dedicated PROM programmer.
= 0
MD2 = 0,
MD0 = 1,
FWE = 1
= 0
= 0
MD2 = 1,
MD0 = 1,
FWE = 0
MD2 = 1,
MD0 = 1,
FWE = 1
Figure 16.2 Flash Me mory State Transitions
Table 16. 1 Differences between Boot Mode and User Progr am Mode
Boot Mode User Program Mode
Total erase Yes Yes
Block er ase No Yes
Programming control program*(2) (1) (2) (3)
(1) Erase/erase-verify
(2) Program/program-verify
(3) Emulation
Note: *To be provided by the user, in accordance wit h the recommended algor ithm.
Rev. 1.0, 02/02, page 382 of 502
Flash memory
This LSI
RAM
Host
Programming control
program
SCI
Application program
(old version)
New application
program
Flash memory
This LSI
RAM
Host
SCI
Application program
(old version)
Boot program area
New application
program
Flash memory
This LSI
RAM
Host
SCI
Flash memory
preprogramming
erase
Boot program
New application
program
Flash memory
This LSI
Program execution state
RAM
Host
SCI
New application
program
Boot program
Programming control
program
,
#
!"
1. Initial state
The old program version or data remains written
in the flash memory. The user should prepare the
programming control program and new
application program beforehand in the host.
2. Programming control program transfer
When boot mode is entered, the boot program in
this LSI (originally incorporated in the chip) is
started and the programming control program in
the host is transferred to RAM via SCI
communication. The boot program required for
flash memory erasing is automatically transferred
to the RAM boot program area.
3. Flash memory initialization
The erase program in the boot program area (in
RAM) is executed, and the flash memory is
initialized (to H'FF). In boot mode, total flash
memory erasure is performed, without regard to
blocks.
4. Writing new application program
The programming control program transferred
from the host to RAM is executed, and the new
application program in the host is written into the
flash memory.
Programming control
program
Boot programBoot program
Boot program area Boot program area
Programming control
program
Figure 16.3 Boot Mode
Rev. 1.0, 02/02, page 383 of 502
Flash memory
This LSI
RAM
Host
Programming/
erase control program
SCI
Boot program
New application
program
Flash memory
This LSI
RAM
Host
SCI
New application
program
Flash memory
This LSI
RAM
Host
SCI
Flash memory
erase
Boot program
New application
program
Flash memory
This LSI
Program execution state
RAM
Host
SCI
Boot program
!
,
Boot program
FWE assessment
program
Application program
(old version)
,
New application
program
1. Initial state
The FWE assessment program that confirms that
user program mode has been entered, and the
program that will transfer the programming/erase
control program from flash memory to on-chip
RAM should be written into the flash memory by
the user beforehand. The programming/erase
control program should be prepared in the host
or in the flash memory.
2. Programming/erase control program transfer
When user program mode is entered, user
software confirms this fact, executes transfer
program in the flash memory, and transfers the
programming/erase control program to RAM.
3. Flash memory initialization
The programming/erase program in RAM is
executed, and the flash memory is initialized (to
H'FF). Erasing can be performed in block units,
but not in byte units.
4. Writing new application program
Next, the new application program in the host is
written into the erased flash memory blocks. Do
not write to unerased blocks.
Programming/
erase control program
Programming/
erase control program
Programming/
erase control program
Transfer program
Application program
(old version)
Transfer program
FWE assessment
program
FWE assessment
program
Transfer program
FWE assessment
program
Transfer program
Figure 16.4 User Program Mode
16.3 Block Configuration
Figure 16. 5 shows the bl ock confi guration of 128-kbyte flash memory. The t hick lines indi cate
erasing uni t s, the na rrow lines indi cate programming units and the values are addresses. The flash
memory is divided i nto 32 kbytes (2 blocks), 28 kbytes (1 bl ock), 16 kbytes (1 bloc k), 8 kbytes (2
Rev. 1.0, 02/02, page 384 of 502
blocks), and 1 kbyte (4 bl ocks). Erasing is performed in these uni ts. Programm i ng i s performed
in 128-byte units starting from an address wi t h lowe r eight bits H'00 or H' 80.
EB0
Erase unit
1 kbyte
EB1
Erase unit
1 kbyte
EB2
Erase unit
1 kbyte
EB3
Erase unit
1 kbyte
EB4
Erase unit
28 kbytes
EB5
Erase unit
16 kbytes
EB6
Erase unit
8 kbytes
EB7
Erase unit
8 kbytes
EB8
Erase unit
32 kbytes
EB9
Erase unit
32 kbytes
H'000000 H'000001 H'000002 H'00007F
H'0003FF
H'00047F
H'00087F
H'000C7F
H'00107F
H'007FFF
H'00807F
H'00BFFF
H'0007FF
H'000BFF
H'000FFF
H'01FFFF
H'00C07F
H'00DFFF
H'00E07F
H'00FFFF
H'01007F
H'017FFF
H'01807F
H'000400 H'000401 H'000402
H'000780 H'000781 H'000782
H'000800 H'000801 H'000802
H'000B80 H'000B81 H'000B82
H'000F80 H'000F81 H'000F82
H'007F80 H'007F81 H'007F82
H'00BF80 H'00BF81 H'00BF82
H'00DF80 H'00DF81 H'00DF82
H'00FF80 H'00FF81 H'00FF82
H'017F80 H'017F81 H'017F82
H'01FF80 H'01FF81 H'01FF82
H'000C00 H'000C01 H'000C02
H'001000 H'001001 H'001002
H'008000 H'008001 H'008002
H'00C000 H'00C001 H'00C002
H'00E000 H'00E001 H'00E002
H'010000 H'010001 H'010002
H'018000 H'018001 H'018002
H'000380 H'000381 H'000382
Programming unit: 128 bytes
Programming unit: 128 bytes
Programming unit: 128 bytes
Programming unit: 128 bytes
Programming unit: 128 bytes
Programming unit: 128 bytes
Programming unit: 128 bytes
Programming unit: 128 bytes
Programming unit: 128 bytes
Programming unit: 128 bytes
Figure 16.5 Flash Me mory Block Configuration
Rev. 1.0, 02/02, page 385 of 502
16.4 Input/Output Pins
The flash memory is controlled by means of the pins shown in table 16.2.
Table 16. 2 Pin Configuration
Pin Name I/O Function
5(6
Input Reset
FWE I nput Flash program/erase protection by hardware
MD2 Input Sets this LSI’s operating m ode
MD1 Input Sets this LSI’s operating m ode
MD0 Input Sets this LSI’s operating m ode
TxD1 Output Ser ial transmit data output
RxD1 Input Serial receive data input
16.5 Register Descrip t i on s
The flash memory has the following registers.
• Flash memory control regi ster 1 (FLMCR1)
• Flash memory control regi ster 2 (FLMCR2)
• Erase bl ock register 1 (EBR1)
• Erase bl ock register 2 (EBR2)
• RAM emula tio n re gister (RAME R)
• Flash memory power control register (FLPWCR)
Rev. 1.0, 02/02, page 386 of 502
16. 5. 1 Fl a sh Memory Contr ol Regi st er 1 (FLMCR1)
FLMCR1 makes the fl ash m emory change t o program mode, program-verify m ode, e ra se m ode,
or erase-verify mode. For details on register setting, refer to section 16.8, Flash Memory
Programming/Erasing.
Bit Bit Name Initial Value R/W Description
7FWE — R Reflects the input level at the FWE pin. It is cleared
to 0 when a low level is input to the FWE pin, and
set to 1 when a high level is input.
6 SWE 0 R/W Soft ware Write Enable Bit
When this bit is set to 1, flash memory
programming/ erasing is enabled. W hen this bit is
cleared to 0, other FLMCR1 register bits and all
EBR1 bits cannot be set .
5 ESU 0 R/W Era s e Setup Bit
When this bit is set to 1, the flash mem ory changes
to the erase setup state. When it is cleared to 0,
the erase setup state is cancelled.
4 PSU 0 R/W Pro gram Setup Bit
When this bit is set to 1, the flash mem ory changes
to the program setup state. When it is cleared to 0,
the program setup st ate is cancelled. Set this bit t o
1 before sett ing the P1 bit in FLM CR1.
3 EV 0 R/W Erase-Verify
When this bit is set to 1, the flash mem ory changes
to erase-verify mode. When it is cleared to 0,
erase-verify m ode is cancelled.
2 PV 0 R/W Program-Verify
When this bit is set to 1, the flash mem ory changes
to program-verify mode. When it is cleared to 0,
program-verify mode is cancelled.
1E 0 R/WErase
When this bit is set to 1, and while the SWE1 and
ESU1 bits ar e 1, the flash mem ory changes to
erase m ode. When it is cleared to 0, erase m ode
is ca nc e lle d.
0 P 0 R/W Program
When this bit is set to 1, and while the SWE1 and
PSU1 bits ar e 1, the flash mem ory changes to
program m ode. When it is cleared to 0, program
mode is cancelled.
Rev. 1.0, 02/02, page 387 of 502
16. 5. 2 Fl ash Memory Co ntro l Regi ster 2 (FLMCR2 )
FLMCR2 di splays the sta te of fl a sh memory programming/erasing. FLMCR2 is a read-only
register, a nd should not be written to.
Bit Bit Name Initial Value R/W Description
7FLER 0 R Indicates that an err or has occurred during an
operation on flash memory (programming or
erasing). When FLER is set to 1, flash memory
goes to t he error-protection state.
See section 16.9.3, Error Protection, for details.
6 to
0— 0 R Reserved
These bits are always read as 0.
16.5.3 Er ase Block Register 1 (EBR1)
EBR1 and EBR2 specif y the flash memor y eras e area blo ck. EBR1 and EBR2 initial iz ed to H'00
when the SW E bit in FLMCR1 is 0. Do not set m ore than one bit in E BR1 and EBR2 toget he r at a
time, as this w ill caus e all the bi ts in EBR1 and EBR 2 to be au tomatically cleared to 0.
• EBR1
Bit Bit Name Initial Value R/W Description
7 EB7 0 R/ W When this bit is set t o 1, 8 kbytes of EB7
(H'00E000 to H'00FFFF) will be erased.
6 EB6 0 R/W W hen this bit is set to 1, 8 kbytes of EB6
(H'00 C000 to H'00DFFF) will be erased.
5 EB5 0 R/W When this bit is set to 1, 16 kbytes of EB5
(H'008000 to H'00BFFF) will be erased.
4 EB4 0 R/W W hen this bit is set to 1, 28 kbytes of EB4
(H'001000 to H'007FFF) will be erased.
3 EB3 0 R/W When this bit is set to 1, 1 kbyte of EB3 (H'000C00
to H'000FFF) will be erased.
2 EB2 0 R/W W hen this bit is set to 1, 1 kbyte of EB2 ( H'000800
to H'0 00BFF) will be erased.
1 EB1 0 R/W When this bit is set to 1, 1 kbyte of EB1 (H'000400
to H'0 007FF) will be erased.
0 EB0 0 R/W When this bit is set to 1, 1 kbyte of EB0 (H'000000
to H'0 003FF) will be erased.
Rev. 1.0, 02/02, page 388 of 502
• EBR2
Bit Bit Name Initial Value R/W Description
7
6
5
4
3
2
— 0 R/W Reserved
These bits are always read as 0.
1 EB9 0 R/W W hen this bit is set to 1, 32 kbytes of EB9
(H'018000 to H'01FFFF) will be erased.
0 EB8 0 R/W When this bit is set to 1, 32 kbytes of EB8
(H'010000 to H'017FFF) will be erased.
16. 5. 4 RAM Emula tio n Regi ster (RAMER)
RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating
real-time fl ash memory programming. RAMER settings should be made in user mode or user
program mode. To ensur e corr ect oper ation of the emu lation funct ion , the ROM for which RAM
emulation is performed should not be accessed im mediately after this register has bee n modifie d.
Normal execution of an access immediately after register modification is not guaranteed.
Bit Bit Name Initial Value R/W Description
7
6— 0 R Reserved
These bits are always read as 0.
5
4— 0 R/W Reserved
Only 0 should be wr itten to these bit s.
3 RAMS 0 R/ W RAM Se lect
Specifies select io n or non-sele c tion of flash
memory em ulation in RAM. When RAMS = 1, t he
flash memory is overlapped with part of RAM, and
all flash m emory block are program/erase-
protected.
2
1
0
RAM2
RAM1
RAM0
0
0
0
R/W
R/W
R/W
Flash Memory Area Selection
When the RAMS bit is set to 1, one of the following
flash mem ory areas are selected t o overlap the
RAM area of H’FFE000 to H’FFE3FF. The areas
correspond with 1-kbyte erase blocks.
00X: H’000000 to H’0003FF (EB0)
01X: H’000400 to H’0007FF (EB1)
10X: H’000800 to H’000BFF ( EB2)
11X: H’000C00 to H’000FFF (EB3)
Note: X: Don’t care
Rev. 1.0, 02/02, page 389 of 502
16.5.5 Flash Me mory Power Control Register (FLPWCR)
FLPWCR enables or disables a transition to the flash memory power-down mode when this LSI
switches to subactive mode. For details, refer to section 16.12, Flash Memory and Power-Down
Modes.
Bit Bit Name Initial Value R/W Description
7 PDWND 0 R/W Powe r-Do wn Disab le
When this bit is set to 1, the transition to flash
memory power-down mode is disabled.
6 to
0—0 R
Reserved
These bits always read 0.
16.6 On- Board Programming Modes
There are two m odes for programming/erasing of the flash memory; boot mode, whi ch enables on-
board programming/erasing, and programmer mode, in which programming/era sing is performe d
with a PROM programmer. On-board programming/erasing ca n also be perform ed in user
program mode. At reset-start in reset mode , this L SI changes to a mode depending on the MD pin
settings a nd FWE pin setting, as shown in table 16.3. The input level of each pin must be defined
four state s before the reset ends.
When changing to boot mode, the boot program built int o this LSI is i nitiated. The boot program
transfers t he programming c ontrol program from the exte rnally-connected host to on-chi p RAM
via SCI_1. After era sing the e ntire flash memory, the programming c ontrol progra m is executed.
This can be used for program ming ini t ial va l ues in the on-board state or for a forcible return when
programming/ erasing ca n no longer be done in user program mode. In user program mode ,
individual bl ocks can be era sed and programmed by branching to t he user program/erase c ontrol
program prepared by the user.
Table 16. 3 Setting On-Board Programmi ng Modes
MD2 MD0 FW E LSI State af t er Reset End
1 1 1 User Mode
0 1 1 Boot Mode
16.6.1 Boot Mode
Table 16. 4 shows the boot mode opera tions between reset end a nd branching to the programming
control program.
Rev. 1.0, 02/02, page 390 of 502
1. When boot mode i s used, the flash memory programming control program must be prepared in
the host beforeha nd. Prepare a programming c ontrol program in accordance with t he
description i n section 16.8, Fl ash Memory Programm ing/Erasing.
2. SCI_1 should be set t o asynchronous mode, and the t ransfer format as fol lows: 8-bit da ta, 1
stop bit, and no pa rity.
3. When the boot program is i nitiated, the chi p measures t he low-level pe riod of asynchronous
SCI communication data (H' 00) transmi tted continuousl y from the host. T he chip then
calculates the bit rat e of tra nsmission from the host, and adj usts the SCI_1 bit rate to match
that of the host. The reset should end with t he RxD pin high. The RxD and TxD pins should
be pulled up on the boa rd if necessary. Afte r the re set is complete, it takes a pproximately 100
states before the chip is ready to measure the low-level period.
4. After matching the bit rates, the chip transmits one H'00 byte to the host to indicate the
completion of bit rat e adjustment. The host should confirm that this a djustment end i ndication
(H'00) has been rec eived normally, and tra nsmit one H'55 byte to the chip. If reception could
not be performe d normally, initiate boot mode again by a reset. De pending on the host' s
transfer bit rate and system clock frequency of this LSI, there will be a discrepancy between
the bit ra tes of the host and t he chip. To operate the SCI properly, set the host's transfer bit
rat e an d sy s tem clo ck frequen cy of th is LS I within th e ra ng es listed in table 16 .5.
5. In boot mode, a part of the on-chip RAM are a is used by the boot program. The area H' FFE800
to H'FFEFBF i s the are a to whic h the progra mming c ontrol program is t ra nsferre d from the
host. T he boot program a rea cannot be used until the execution state in boot mode switches to
the programming control program.
6. Before bran chin g to the progra mming contro l progr am, th e chip termin at es transf er oper ations
by SCI_1 (by clearing the RE and TE bits in SCR to 0), howeve r the adjusted bi t rate val ue
remains se t in BRR. Therefore, the programming control program can still use it for transfer
of write data or verify data with the host. The TxD pin is high. The contents of the CPU
general re gisters are undefined immediately after branching to the programming control
program. These regi sters must be initialized at the beginning of the programming control
program, as the stack point er (SP), in part icular, is used impl icitly in subroutine calls, etc.
7. Boot mode can be cl eared by a reset. End the reset a fter driving the reset pin low, waiting at
least 20 states, and then setting the mode (MD) pins. Boot mode is also cleared when a WDT
overflow oc curs.
8. Do not c hange the MD pin input leve l s in boot mode.
9. All interrupts are disabled during programming or erasing of the flash memory.
Rev. 1.0, 02/02, page 391 of 502
Table 16.4 Boot Mode Oper ation
Item Host Operation Communications Contents LSI Operation
Boot mode
start Branches to boot program at reset-start.
Processing Contents Processing Contents
Bit rate
adjustment Continuously transmits data H'00 at
specified bit rate. H'00, H'00 ...... H'00
H'00
H'55
· Measures low-level period of receive data
H'00.
· Calculates bit rate and sets it in BRR of
SCI_1.
· Transmits data H'00 to host as adjustment
end indication.
Transmits data H'AA to host when data
H'55 is received.
Transmits data H'55 when data H'00
is received error-free.
Transmits number of bytes (N) of
programming control program to be
transferred as 2-byte data (low-order
byte following high-order byte)
Receives data H'AA.
Transmits 1-byte of programming
control program (repeated for
N times)
Receives data H'AA.
Transfer of
programming
control
program
Flash memory
erase
Boot program initiation
Echobacks the 2-byte data received.
Branches to programming control program
transferred to on-chip RAM and starts
execution.
Echobacks received data to host and also
transfers it to RAM (repeated for N times)
Checks flash memory data, erases all
flash memory blocks in case of written
data existing, and transmits data H'AA to
host. (If erase could not be done,
transmits data H'FF to host and aborts
operation.)
High-order byte and
low-order byte
H'XX
H'AA
Echoback
Echoback
H'FF
H'AA
Boot program
erase error
Table 16. 5 System Cl ock Frequencies for which Automati c Adjustment of LSI Bit Rate is
Possible
Host Bit Rate Syst em Clock Frequency Range of LSI
19,200 bps 20 MHz
9,600 bps 8 to 20 MHz
4,800 bps 4 to 20 MHz
16.6.2 Prog ra mming/Erasing in Us e r Program Mode
On-board programming/erasing of an individual flash memory bloc k can also be pe rformed in user
program mode by branching to a user program /erase c ontrol program. The user must set branching
conditions and provide on-board means of supplying programming da ta. The flash memory must
Rev. 1.0, 02/02, page 392 of 502
contain the user program/erase c ontrol program or a program that provides the user program/erase
control program from e xternal memory. As the flash memory itse lf cannot be rea d during
programming/ erasing, transfer t he user program/erase control program to on-chip RAM, as in boot
mode. Figure 16.6 shows a sample procedure for programm i ng/erasing in user progra m mode.
Prepare a user progra m/erase control program in a ccordance wit h the de scription in section 16.8,
Flash Me mory Programming/Erasing.
Yes
No
Program/erase?
Transfer user program/erase control
program to RAM
Reset-start
Branch to user program/erase control
program in RAM
Execute user program/erase control
program (flash memory rewrite)
Branch to flash memory application
program
Branch to flash memory application
program
FWE=high*
Clear FWE
Do not constantly apply a high level to the FWE pin. Only apply a high level to the FWE pin
when programming or erasing the flash memory. To prevent excessive programming or excessive
erasing, while a high level is being applied to the FWE pin, activate the watchdog timer in case of
handling CPU runaways.
Note: *
Figure 16.6 Programming/Erasing Flowchart Exampl e in Use r Program Mode
Rev. 1.0, 02/02, page 393 of 502
16.7 F lash Memory Emulation in RAM
A setting in the RAM emulation register (RAMER) enables part of RAM to be overlapped onto
the flash memory area so that data to be written to flash memory can be emulated in RAM in real
time. Emulati on can be performed in user mode or user program mode. Figure 16. 7 shows a n
example of emulation of real-time flash memory programming.
1. Set RAMER to overlap part of RAM onto th e area for whic h real-t ime programmin g is
required.
2. Em ulation is performed using the overlapping RAM.
3. Aft e r the program data ha s been confirmed, the RAMS bi t is cleared, thus rel easin g the RAM
overlap.
4. The data written in the overlapping RAM is written into the flash memory space (EB0).
Start of emulation program
Set RAMER
Write tuning data to overlap
RAM
Execute application program
Tuning OK?
Clear RAMER
Write to flash memory
emulation block
End of emulation program
No
Yes
Figure 16.7 Flowchart for Flash M emory Emulati on in RAM
Rev. 1.0, 02/02, page 394 of 502
An example in which fl a sh me mory bloc k area EB0 is overlappe d is shown in figure 16. 8.
1. The RAM area to be overlapped is fixed at a 1-kbyte area in the range H'FFE000 to H'FFE3FF.
2. The flash memory area to overlap is selected by RAMER from a 1-kbyte area of the EB0 to
EB3 bloc ks.
3. The overl app ed RAM area can be accessed from both the flash memor y addr ess es and RAM
addresses.
4. W hen the RAMS bi t in RAME R is se t to 1, program/erase protect i on is ena bled for all flash
memory bloc ks (em ulation protection). In this state, setting the P or E bit in FLMCR1 t o 1
does not cause a transit i on to program mode or era se mode.
5. A RAM a rea cannot be erase d by execution of software in accordance with the e rase
algorithm.
6. Block area EB0 contains the vector table. When performing RAM emulation, the vector table
is needed in the overlap RAM.
H'000000 Flash memory
(EB0) Flash memory
(EB0)
(EB1)
(EB2)
(EB3)
H'0003FF
H'000400
H'0007FF
H'000800
H'000BFF
H'000C00
H'000FFF
H'FFE000
H'FFE3FF
On-chip RAM
(1 kbyte)
On-chip RAM
(Shadow of
H'FFE000 to
H'FFE3FF)
Flash memory
(EB2)
On-chip RAM
(1 kbyte)
(EB3)
Normal memory map RAM overlap memory map
Figure 16.8 Example of RAM Overlap Operati on
Rev. 1.0, 02/02, page 395 of 502
16.8 F lash Memory Programming/Erasing
A software me t hod using the CPU is em pl oyed to program a nd erase flash me mory in the on-
board programming mode s. De pending on the FLMCR1 setting, the flash memory operates i n one
of the following four modes: Program mode, program-verify mode, erase mode, and erase-verify
mode. The program ming control program in boot mode a nd the user program/erase c ont rol
program in user program mode use these operating mode s in combination to perform
programming/ erasing. Flash memory programming and erasing should be performed in
accordance with the de scriptions in section 16.8. 1, Program /Program-Veri fy and section 16. 8.2,
Erase/Erase-Verify, respectively.
16.8.1 Program/Program-Verify
When writing data or programs to the flash memory, the program/ program-ver ify flowchart show n
in Figure 16.9 should be foll owed. Perform ing programming operations according to this
flowchart will enable data or programs t o be written to the flash m emory wit hout subjecting t he
chip to voltage stress or sacrificing program data reliability.
1. Programming must be done to an empty address. Do not reprogram an addre ss to which
programming ha s al ready been performed.
2. Programming shoul d be carried out 128 bytes at a time. A 128-byte data transfer must be
performed eve n if writing fewer t han 128 bytes. In this ca se, H'FF data must be written to the
extra addr es ses.
3. Prepare the foll owing data storage areas in RAM: A 128-byt e programming data area, a 128-
byte reprogramming data area, a nd a 128-byte addi t ional-programming data area. Perform
reprogramming data com putation and a dditional programming data computation according to
Figure 16. 9.
4. Consecutively t ransfer 128 bytes of data in byte units from the reprogramming dat a area or
additional-programming data area to t he flash memory. The program addre ss and 128-byte
data are latched in the flash memory. The lower eight bits of the start address in the flash
memory destination area must be H'00 or H'80.
5. The time during which the P bit is set to 1 is the programming time. Figure 16. 9 shows the
allowable programming times.
6. The watchdog timer (WDT) is set to pre vent overprogramming due to program runa way, etc.
An ove rfl ow cycle of (γ + z2 + α + β) µs is allowed.
7. For a dum m y writ e to a verify a ddress, write 1-byte data H'FF to an address whose lowe r two
bits are B'00. Verify data can be read in longwords from the addre ss to which a dummy writ e
was performe d.
8. The maximum number of repetitions of the program/ program-veri fy se quence of the same bit
must not exceed(N).
Rev. 1.0, 02/02, page 396 of 502
START
End of programming
Set SWE bit in FLMCR1
Start of programming
Write pulse application subroutine
Wait (x) µs
Apply Write Pulse
End Sub
Set PSU bit in FLMCR1
WDT enable
Disable WDT
Number of Writes n
1
2
3
4
5
6
7
8
9
10
11
12
13
998
999
1000
Note 6: Write Pulse Width
Write Time (z) µs
30
30
30
30
30
30
200
200
200
200
200
200
200
200
200
200
Wait ( ) µs
Set P bit in FLMCR1
Wait (z1) µs, (z2) µs, or (z3) µs
Clear P bit in FLMCR1
Wait ( ) µs
Clear PSU bit in FLMCR1
Wait ( ) µs
n= 1
m= 0
NG
NG
NG NG
OK
OK
OK
Wait ( ) µs
Wait ( ) µs
*2
*7
*7
*4
*7
*7
Start of programming
End of programming
*5*7
*7
*7
*1
Wait ( ) µs
Apply Write pulse of (z1) s or (z2) s
Sub-Routine-Call
Set PV bit in FLMCR1
H'FF dummy write to verify address
Read verify data
Write data =
verify data?
*4
*3
*7
*7
*7
*1
Transfer reprogram data to reprogram data area
Reprogram data computation
*4
Transfer additional-programming data to
additional-programming data area
Additional-programming data computation
Clear PV bit in FLMCR1
Clear SWE bit in FLMCR1
m = 1
Reprogram
See Note 6 for pulse width
m= 0 ?
Increment address
Programming failure
OK
Clear SWE bit in FLMCR1
Wait ( ) µs
NG
OK
6 ≥ n?
NG
OK
6 ≥ n ?
Wait ( ) µs
n ≥ (N)?
n ← n + 1
Original Data
(D) Verify Data
(V) Reprogram Data
(X) Comments
Programming completed
Still in erased state; no action
Programming incomplete;
reprogram
Note: * Use a 10 µs write pulse for additional programming.
Write 128-byte data in RAM reprogram
data area consecutively to flash memory
RAM
Program data storage
area (128 bytes)
Reprogram data storage
area (128 bytes)
Additional-programming
data storage area
(128 bytes)
Store 128-byte program data in program
data area and reprogram data area
Apply write Pulse (Additional programming) of (z3) µs
Sub-Routine-Call
128-byte
data verification completed?
Successively write 128-byte data from additional-
programming data area in RAM to flash memory
Reprogram Data Computation Table
Reprogram Data
(X')
Verify Data
(V)
Additional-
Programming Data
(Y)
1
1
1
1
0
1
0
000
1
1
Comments
Additional programming
to be executed
Additional programming
not to be executed
Additional programming
not to be executed
Additional programming
not to be executed
0
1
1
1
0
1
0
100
1
1
Additional-Programming Data Computation Table
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written to must be H'00 or H'80.
A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses.
2. Verify data is read in 16-bit (word) units.
3. Reprogram data is determined by the operation shown in the table below (comparison between the data stored in the program data area and the verify data). Bits for
which the reprogram data is 0 are programmed in the next reprogramming loop. Therefore, even bits for which programming has been completed will be subjected to
programming once again if the result of the subsequent verify operation is NG.
4. A 128-byte area for storing program data, a 128-byte area for storing reprogram data, and a 128-byte area for storing additional data must be provided in RAM.
The contents of the reprogram data area and additional data area are modified as programming proceeds.
5. A write pulse of 30 µs or 200 µs is applied according to the progress of the programming operation. See Note 6 for details of the pulse widths. When writing of
additional-programming data is executed, a 10 µs write pulse should be applied. Reprogram data X' means reprogram data when the write pulse is applied.
7. The values of x, y, z1, z2, z3, , , , , , and N are are shown in section 21.5, Flash Memory Characteristics.
*
*
*
*
*
*
Figure 16.9 Program/P rogram-Verify Fl owchart
Rev. 1.0, 02/02, page 397 of 502
16.8.2 Erase/Erase-Verify
When erasing flash me mory , the erase/er ase- ver ify flow char t show n in figure 16.10 sh ould be
followed.
1. Prewriting (set ting erase block da ta to all 0s) is not nec e ssary.
2. Era sing is performed in block units. Ma ke only a si ngle-bit specification i n erase bl ock
register1 (EBR1) and era se bl ock regist er2(EBR2). To erase multiple blocks, each block m ust
be erased in tur n.
3. The time during which the E bit is set to 1 is the flash memory erase time.
4. The watchdog timer (WDT) is set to pre vent overerasing due to program runaway, etc. An
overflow c ycle higher than (y + z + α + β) ms is allowed.
5. For a dummy writ e to a verify address, write 1-byte data H'FF to an address whose lower two
bits are B'00. Verify data can be read in longwords from the addre ss to which a dummy writ e
was performe d.
6. If the read data is not erased successfully, set erase mode again, and repeat the erase/erase-
verify sequence as before. T he maximum number of repetitions of the erase/erase-verify
sequence must not exc eed (N).
16. 8. 3 Int e rr upt Handli ng when Pr ogramming/Erasi ng Flash M emory
All interrupts, including the
10,
inte rrupt, are disa bled while flash memory is bei ng progra mmed
or erased, or while the boot program i s executing, for the following t hree reasons:
1. Inte rrupt during programm ing/erasing ma y cause a violation of the programming or erasing
algorithm, with the result that normal operation cannot be assured.
2. If interrupt exception handl ing st a rts before t he vector address is written or during
programming/ erasing, a correct vector ca nnot be fetched and the CPU malfunctions.
3. If an interrupt oc curs during boot program exec ution, normal boot m ode sequence ca nnot be
carried out.
Rev. 1.0, 02/02, page 398 of 502
START
End of erasing
Set SWE bit in FLMCR1
Wait (x)
µs
n = 1
Enable WDT
Set EBU bit in FLMCR2
Wait (y)
µs
Set E bit in FLMCR1
Wait (z)
ms
Clear E bit in FLMCR1
Wait (
α
)
µs
Clear ESU bit in FLMCR2
Wait (
β
)
µs
Disable WDT
Set EV bit in FLMCR1
Wait (
γ
)
µs
H'FF dummy write to verify address
Wait (
ε
)
µs
Read verify data
Clear EV bit in FLMCR1
Wait (
η
)
µs
Set block start address to verify address
Set EBR1, EBR2
NG
NG
NGNG
OK
OK
*
2
*
4
*
1
*
2
*
2
*
2
*
2
*
2
*
2
*
3
*
2
*
5
*
2
*
2
Verify data = all 1 ?
Clear SWE bit in FLMCR1
Increment
address
Erase failure
Wait ( )
µs
Last address of block ?
OK
End of
erasing of all erase
blocks ?
Clear EV bit in FLMCR1
Wait (
η
)
µs
OK
Wait ( )
µs
n ≥ N ?
Clear SWE bit in FLMCR1
n n + 1
Start of erase
Halt erase
Preprogramming (setting erase block data to all 0) is not necessary.
The values of x, y, z, , , , , , and are shown in section 21.5, Flash Memory Characteristics.
Verify data is read in 16-bit(W) units.
Set only one bit in EBR1 or EBR2. More than one bit cannot be set.
Erasing is performed in block units. To erase a number of blocks, the individual blocks must be erased sequentially.
1.
2.
3.
4.
5.
Notes:
Figure 16.10 Erase/Erase-Verify Flowchart
Rev. 1.0, 02/02, page 399 of 502
16.9 Program/Erase Protect ion
There are three kinds of flash memory program/erase protection; hardware protection, software
protection, and e rror protection.
16.9.1 Hardware Prote ction
Hardware protection re fers to a state in which programming/erasing of flash me m ory is forcibly
disabled or aborted be cause of a transition t o reset or standby mode. Fl ash memory c ontrol
register 1 (FLMCR1), flash memory c ontrol register 2 (FLMCR2), erase bl ock regi ster 1 (EBR1),
and erase block registe r2(E BR2) are initializ ed. In a reset via the
5(6
pin, the re set state is not
entered unless the
5(6
pin is held low until oscillation stabilizes after powering on. In the case of
a reset during operation, hold the
5(6
pin low for the
5(6
pulse width specified in the AC
Characteristics section.
16.9.2 Software Pr otection
Software protection can be implemented agai nst programming/e rasing of all flash memory blocks
by clearing the SW E bit i n FLMCR1. When software protection is i n effec t, setting t he P1 or E1
bit in FL MCR1 doe s not cause a transition to progra m mode or erase mode. By setting erase
block register 1 (EBR1) or e ra se block re gister2(EBR2), erase protection ca n be set for individual
blocks. When EBR1 and EBR2 are set to H'00, erase protection is set for all blocks.
Setting the RAMS bit in RAMER also imple ments prote ction against program ming/erasing of all
flash me m ory blocks.
16.9.3 Erro r Prote ction
In error protection, an error is detected when CPU runaway occurs during fla sh me m ory
programming/ erasing, or operation i s not performed in accordance with the progra m/erase
algorithm, and t he program/erase operation is aborted. Aborting the program/erase operati on
prevents damage to t he flash memory due to overprogramming or overerasing.
When the following errors are detected during programming/erasing of flash mem ory, the FLER
bit in FL MCR2 i s set to 1, and the error protection st ate is e ntered.
• When t he flash memory of the relevant a ddress area is read during progra mming/erasing
(including ve ctor read and instruction fet c h)
• Immediately a fter except ion handling (excluding a reset) during programming/erasing
• When a SLEEP instruction is execu ted during program ming/e rasing
The FLMCR1, FLMCR2, EBR1, and EBR2 se ttings are retained, however program mode or erase
mode is aborte d at the point at whi c h the error occurred. Program mode or erase mode cannot be
Rev. 1.0, 02/02, page 400 of 502
re-entered by re-setting the P or E bit. However, PV and EV bit setting is enabled, and a transition
can be made to verify mode . Error prote ction can be cleared only by a power-on reset.
16.10 Programm er Mode
In program mer mode, a PROM programmer can be used to perform programming/erasing via a
socket adapter, just as for a discre te flash memory. Use a PROM program mer that supports the
Hitachi 128-kbyte flash memory on-chip MCU device type (FZTAT128V5A).
16.11 P ower- Down S t ates for Flash Mem ory
In user mode , the f las h memor y will oper ate in either of th e follow in g states:
• Normal operating mode
The flash memory can be read and written to.
• Power-down mode: Part of the power supply circuitry is halted, and the flash memory can be
read when the LSI is operating on the subclock.
• Standby mode
All flash memory circuits are halted.
Table 16. 6 shows the c orrespondence between the operating modes of this LSI and the flash
memory. W hen the flash memory returns to its normal opera ting state from standby mode , a
period to stabilize the power supply circuits that were stopped is needed. When the flash memory
returns to its normal operating state, bits STS2 to STS0 in SBYCR must be set to provide a wait
time of at least 20 µs, even when the external clock is being used.
Table 16. 6 Flash Me mory Oper ating States
LSI Operating State Flash Memor y Operati ng State
High-speed mode
Medium-speed mode
Sleep mode
Normal mode
Subactive mode
Subsleep mode When PDWND = 0: Power-down mode (read-only)
When PDWND = 1: Norm al mode (r ead-only)
Watch mode
Software standby m ode
Hardware standby mode
Standby mode
16.12 Fl ash Memory and Power-Down Modes
In powe r-down m ode s, flash memory registe rs (FLMCR1, FLMCR2, EBR1, EBR2, RAME R, and
FLPWCR) cannot be read from or written to.
Rev. 1.0, 02/02, page 401 of 502
Section 17 Mask ROM
This mi c rocomputer series ha s 64 or 128 kbytes of on-chip mask ROM. On-chip ROM i s
connected t o the CPU via a 16-bi t data bus. Data in on-chip ROM can always be accessed by one
state.
H'000000
H'000002
H'01FFFE
H'000001
H'000003
H'01FFFF
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
Figure 17.1 Block Diagr am of 128-Kbyte Mask ROM (HD6432282)
H'000000
H'000002
H'00FFFE
H'000001
H'000003
H'00FFFF
Internal data bus (upper 8 bits)
Internal data bus (lower 8 bits)
Figure 17.2 Block Diagr am of 64-Kbyte M ask ROM (H D6432281)
Rev. 1.0, 02/02, page 402 of 502
Rev. 1.0, 02/02, page 403 of 502
Section 18 Cl ock Pulse Generator
This LSI has an on-chip clock pulse generator that generates the system clock (ø), the bus master
clock, internal clocks, and subclock. The clock pulse generator consists of an oscillator, PLL
circuit, subclock divider, clock selection circuit, medium-speed clock divider, and bus master
clock selection circuit. A block diagram of the clock pulse generator is shown in figure 18.1.
EXTAL
XTAL
SCK2 to SCK0
SCKCR
STC1, STC0
LPWRCR
Legend
LPWRCR : Low-power control register
SCKCR : System clock control register
Clock
oscillator PLL circuit
(1, 2, 4) Clock
selection
circuit
System clock
to ø pin
Subclock
to WDT1, LCD
Internal clock to
supporting modules Bus master clock
to CPU
Medium-
speed
clock divider
Subclock
divider
(division
by 128)
Bus
master
clock
selection
circuit
ø/2 to
ø/32
ø
ø
SUB
Figure 18.1 Block Diagr am of Clock Pulse G enerator
The frequency can be cha nged by means of the PLL circuit. Frequency cha nges a re perform e d by
software by settings i n the low-power control register (LPWRCR) and syst em clock c ontrol
register (SCKCR).
CPG0502A_000020020200
Rev. 1.0, 02/02, page 404 of 502
18.1 Register Descript i on s
The on-chip clock pulse generator has th e follow ing regist ers.
• System cl ock control regi ster (SCKCR)
• Low-power control register (LPWRCR)
18.1.1 System Cloc k Control Register (SCKCR)
SCKCR performs ø cl ock output control, selection of operation when the PLL ci rc uit frequency
mul tiplication factor is ch anged , an d med ium-speed mo de cont r ol.
Bit Bit Name Initial Value R/W Description
7 PSTOP 0 R/W ø Clock Output Disable
Controls ø output.
• High-speed Mode , Medium-S peed Mode
0: ø out put
1: Fixed high
• Sleep Mode
0: ø out put
1: Fixed high
• Software Standby Mode
0: Fixed high
1: Fixed high
• Hardware Standby M ode
0: High impedance
1: High impedance
6
5
4
—
—
—
0
0
0
—
—
—
Reserved
These bits are always read as 0.
3STCS 0 R/W
Frequency M ultiplication Factor Switching M ode
Select
Selects the oper ation when the PLL cir cuit
frequency mult iplication factor is changed.
0: Specified multip lic ation factor is valid afte r
transition to software standby mode
1: Specified multip lic ation factor is valid
immediately aft er the STC1 and STC0 bits are
rewritten
Rev. 1.0, 02/02, page 405 of 502
Bit Bit Name Initial Value R/W Description
2
1
0
SCK2
SCK1
SCK0
0
0
0
R/W
R/W
R/W
System Clock Select 0 t o 2
These bits select the bus master clock.
000: High-speed m ode
001: Medium-speed clock is ø/2
010: Medium-speed clock is ø/4
011: Medium-speed clock is ø/8
100: Medium-speed clock is ø/16
101: Medium-speed clock is ø/32
11X: Setting prohibited
Legend
X: Don’t care
Rev. 1.0, 02/02, page 406 of 502
18. 1. 2 L o w-Power Contr ol Register (LPWRCR)
LPWRCR performs power-down mode control, subclock generation control, oscillation circuit
feedback resistance control, and frequency multiplication factor setting.
Bit Bit Name Initial Value R/W Description
7DTON 0 R/W
6LSON 0 R/W
See section 19.1.2, Low-Power Control Regist er
(LPWRCR).
5−0R/W
Reserved
Only write 0 to this bit.
4 SUB STP 0 R/W Subclock Genera tion Control
0: Enables subclock generat ion
1: Disables subclock generation
3 RFCUT 0 R/W Os cillation Circuit Feedback Resistance Control
0: When the main clock is oscillating, sets the
feedback resis tanc e ON. When the main clock is
stopped, sets the feedba ck resis tanc e OFF .
1: Sets the f eedback resistance OFF.
Not e: Wit h a cryst a l resonato r, th e resonat or will
not operate if this bit is set t o 1.
2−0R/W
Reserved
Only write 0 to this bit.
1
0STC1
STC0 0
0R/W
R/W Frequency Multipli cation Factor
The STC bits specify the f r equency multiplication
factor of the PLL circuit.
00: ×1
01: ×2
10: ×4
11: Setting prohibited
Rev. 1.0, 02/02, page 407 of 502
18.2 Oscillator
Clock pul ses can be supplied by connecting a crystal resonator, or by input of an external clock.
In either case, the input clock shoul d not exceed 4 MHz t o 20 MHz.
18.2.1 Connecting a Crystal Resonator
Circuit Configuration: A crystal re sonator ca n be connected as shown in the example in fi gure
18.2. Select the damping resistance Rd according t o table 18.2. An AT-cut para llel-resonance
crystal shoul d be used.
EXTAL
XTAL R
d
C
L2
C
L1
C
L1
= C
L2
= 10 to 22 pF
Figure 18.2 Connection of Crystal Resonator (Example)
Table 18. 1 Damping Resistance Val ue
Frequency (MHz) 4 8 1 2 16 20
Rd (Ω) 500 200 0 0 0
Figure 18. 3 shows the e quivalent circuit of t he crysta l resonator. Use a crystal resonator that has
the characteristics shown in table 18.2.
XTAL
C
L
AT-cut parallel-resonance type
EXTAL
C
0
LR
s
Figure 18.3 Cr ystal Re sonator Equivalent Circuit
Table 18. 2 Crystal Resonator Charac teristics
Frequency (MHz) 4 8 12 16 20
RS max ( Ω) 120 80 60 50 40
C0 max (pF) 77777
Rev. 1.0, 02/02, page 408 of 502
18.2.2 External Clock Input
Circuit Configuration: An external clock signal can be input as shown in the examples in figure
18.4. If the XTAL pin is left open, ensure that stray capacitance does not exceed 10 pF. When
complementary clock is input to the XTAL pin, the external clock input should be fixed high in
standby mode.
EXTAL
XTAL
EXTAL
XTAL
External clock input
Open
External clock input
(a) XTAL pin left open
(b) Complementary clock input at XTAL pin
Fig ure 18.4 External Clock Input (Examples)
Table 18. 3 shows the i nput condi tions for the externa l clock.
Table 18.3 External Clock Input Conditions
VCC = 5.0 V ± 10%
Item Symbol Min Max Unit Test Conditi ons
External clock input low
pulse width tEXL 15 — ns
External clock input high
pulse width tEXH 15 — ns
External clock rise time tEXr —5 ns
External clock fall time tEXf —5 ns
Figure 18.5
0.4 0.6 tcyc ø ≥ 5 M HzClock lo w p ul se width
level tCL 80 — ns ø < 5 MHz
0.4 0.6 tcyc ø ≥ 5 M Hz
Clock high pulse width
level tCH 80 — ns ø < 5 MHz
Figure 21.2
Rev. 1.0, 02/02, page 409 of 502
t
EXH
t
EXL
t
EXr
t
EXf
V
CC
0.5
EXTAL
Fig ure 18.5 External Clock Input Timing
18.3 P LL Circuit
The PLL circuit multiplies the frequency of the clock from the oscillator by a factor of 1, 2, or 4.
The multiplication factor is set by the STC0 and STC1 bits in LPWRCR. The phase of the rising
edge of the internal clock is controlled so as to match that at the EXTAL pin.
When the multiplication factor of the PLL circuit is changed, the operation varies according to the
setting of the STCS bit in SCKCR.
When STCS = 0, the setting becomes val id after a transition to software standby mode. The
transition time count is performed in accordance with the setting of bits STS0 to STS2 in SBYCR.
For details on SBYCR, see section 19.1.1, Sta ndby Control Re gister (SBYCR).
1. The initial PLL circuit multiplication factor is 1.
2. STS0 to STS2 are set to give the specified transition time.
3. The target value is set in ST C0 and STC1, and a transition is made t o softwa re standby mode.
4. The clock pulse generator stops and the value set in STC0 and STC1 becomes valid.
5. Software standby mode is cleared, and a transition time is secured in accordance with the
set ti ng in STS0 to STS2.
6. After the set transition time has elapsed, this LSI resumes operation using the target
multiplication factor.
18.4 Subclock Divider
The subclock di vider divides the clock ge nerated by the oscillator by 128 to generate a subclock.
When using the subclock as a system clock, the compensation by software is needed.
18.5 Medium-Speed Clock Divider
The medium-speed c l ock divide r divides the system clock to generate ø/2, ø/ 4, ø/8, ø/16, and ø/32.
Rev. 1.0, 02/02, page 410 of 502
18.6 Bus Master Clock Sel ect io n Ci rcu it
The bus master clock se lection circuit sel ects the clock supplied to the bus master by setting the
bits SCK 2 to SCK0 in SCKCR. The bus master c l ock ca n be selected from high-speed mode, or
medium-speed clocks (ø/2 , ø/4, ø/8, ø/16 , and ø/32) .
18.7 Usage Notes
18.7.1 Note on Crystal Resonator
As various characteristics related to the crystal resonator are closely linked to the user's board
design, thorough evaluation i s necessary on the user' s part, using the re sonator connection
examples shown in this section as a guide. As the resonator circuit ratings will depend on the
floating capacitance of the resonator and the mounting circuit, the ratings should be determined in
consultation with the resonator manufacturer. The design must ensure that a voltage exceeding the
maximum rating is not applied to the oscillator pin.
18.7.2 Note on Board De sign
Whe n designin g th e b oar d, place the cr ystal reso nator an d its load cap acitors as close as poss ible
to the XTAL and EXTAL pins. Other signal lines should be routed away from the oscillator
circuit, as shown in figure 18.6. This is to prevent induction from interfer ing with correc t
oscillation.
C
L2
Avoid
Signal A Signal B
C
L1
This LSI
XTAL
EXTAL
Figure 18.6 Note on Board Design of Oscillator Circuit
Figure 18. 7 shows exte rnal circuitry rec ommended to be provided around the PLL circuit. Place
oscillation stabilization capacitor C1 and resistor R1 close to the PLLCAP pin, and ensure that no
other signal lines cross this line. Separate PLLVcL and PLLVss from t he other Vcc and Vss line s
at the board power supply source, and be sure t o insert bypass capacitors CB close to t he pins.
Rev. 1.0, 02/02, page 411 of 502
PLLCAP
PLLV
SS
V
CC
V
CL
V
SS
(Values are preliminary recommended values.)
Note: CB are laminated ceramic.
R1 : 3 k C1 : 470 pF
CB : 0.1 F CB : 0.1 F
Figure 18.7 External Circuitry Recommended for PLL Circuit
Rev. 1.0, 02/02, page 412 of 502
Rev. 1.0, 02/02, page 413 of 502
Section 19 Power-Down Modes
In addition to the normal program execution st ate, this L SI has power-down modes in which
operation of the CPU and osci llator is halted and power dissipation is re duced. Low-power
operation c an be achieved by individually control ling the CPU, on-chip periphe ral modules, and
so on.
This LSI's operating modes are as follows:
• High-speed mode
• Medium-spee d mode
• Su b active mode
• Sleep mode
• Subsleep mode
• Watch mode
• Module stop mode
• Software standby mode
• Hardware standby mode
Sleep mode and subsleep mode are CPU states, medium-speed mode is a CPU and bus master
state, subac tive mode is a CPU, bus maste r, and on-c hip peripheral function state, and module stop
mode is an on-chip peri pheral function (including bus masters other than the CPU) state. Some of
these states can be combined.
After a reset, the LSI operates in high-speed mode or module stop mode .
Figure 19. 1 shows the m ode tra nsition diagram. Table 19.1 shows t he conditions for transition to
each mode when a SLEEP instruction is executed, and table 19.2 shows the internal state of the
LSI in each mod e.
LPWS269A_000020020200
Rev. 1.0, 02/02, page 414 of 502
SSBY = 0
Reset state
Program-halted state
pin = High,
pin = Low
pin = High
program execution state
Sleep command
All interrupts
Interrupts
Interrupt*
1
,
LSON bit = 0
Interrupt*
1
,
LSON bit = 1
Sleep command
Sleep command
Sleep command
Sleep command
External interrupt
High-speed mode
(main clock)
Sleep command
After the oscillation
stabilization time
(STS2 to STS0), clock
switching exception
processing
SSBY = 1, PSS = 1,
DTON = 1, LSON = 0
Sleep command
Clock switching
exception processing
SSBY = 1, PSS = 1,
DTON = 1, LSON = 1
SSBY = 1
SSBY = 1
PSS = 1, DTON = 0
SSBY = 0
PSS = 1, LSON = 1
*1
*2
*3
*4
NMI, IRQ0, IRQ5, and WDT_1 interrupts
NMI, IRQ0, IRQ5, WDT_0 interrupt, and WDT_1 interrupts
All interrupts
NMI, IRQ0, and IRQ5
When a transition is made between modes by means of an interrupt, the transition cannot be made
on interrupt source generation alone. Ensure that interrupt handling is performed after accepting
the interrupt request.
From any state except hardware standby mode, a transition to the reset state occurs when
is driven Low.
From any state, a transition to hardware standby mode occurs when is driven low.
Always select high-speed mode before making a transition to watch mode or subactive mode.
Medium-speed
mode
(main clock)
Subactive
mode (subclock) Subsleep
mode (subclock)
Watch mode
(subclock)
*
3
*
4
*
2
pin = Low
Hardware
standby mode
Software
standby mode
Sleep mode
(main clock)
: Power-down mode: Transition after exception processing
Notes :
SCK2 to
SCK0 = 0 SCK2 to
SCK0 0
Figure 19.1 Mode Tr ansition Diagram
Rev. 1.0, 02/02, page 415 of 502
Tabl e 19. 1 Po wer -Do wn Mode Transi t ion Co ndi tio ns
Status of C ontrol Bit at
TransitionPre-
Transition
State SSBY PSS LSON DTON
State after Transit ion
Invoked by SLEEP
Instruction
State after Transit ion
back from Po we r-
Down Mode Invoked
by Interrupt
0*0*Sleep High-speed/Medium-
speed
0*1*
100*Software standby High-speed/Medium-
speed
101*
1 1 0 0 Watch High-speed
1 1 1 0 Watch Subactive
1101
High-
speed/
Medium-
speed
1 1 1 1 Subactive
00**
010*
011*Subsleep Subactive
10**
1 1 0 0 Watch High-speed
1 1 1 0 Watch Subactive
1 1 0 1 High-speed
Subactive
1111
Legend
* : Don’t care
: Setting prohibited
Rev. 1.0, 02/02, page 416 of 502
Table 19.2 LSI Internal States in Each Mode
Function High-
Speed Medium-
Speed Sleep Module
Stop Watch Subactive Subsleep Software
Standby Hardware
Standby
System clock pulse
generator Functioning Functioning Functioning Functioning Halted Halted Halted Halted Halted
Subclock generator Functioning Functioning Functioning Functioning Functioning Functioning Functioning Halted Halted
CPU Instructions
Registers Functioning Medium-
speed
operation
Halted
(retained) High/
medium-
speed
operation
Halted
(retained) Subclock
operation Halted
(retained) Halted
(retained) Halted
(undefined)
NMI
External
interrupts IRQ0 to
IRQ5
Functioning Functioning Functioning Functioning Functioning Functioning Functioning Functioning Halted
Peripheral
functions WDT_1 Functioning Functioning Functioning Subclock
operation Subclock
operation Subclock
operation Halted
(retained) Halted
(reset)
WDT_0 Functioning Functioning Functioning Halted
(retained) Subclock
operation Subclock
operation Halted
(retained) Halted
(reset)
TPU_0
TPU_1
TPU_2
Functioning Functioning Functioning Halted
(retained) Halted
(retained) Halted
(retained) Halted
(retained) Halted
(retained) Halted
(reset)
SCI_0 Functioning Functioning Functioning Halted
(reset) Halted
(reset) Halted
(reset) Halted
(reset) Halted
(reset) Halted
(reset)
SCI_1
RWM
HCAN
A/D
LCD Functioning Functioning Functioning Halted
(retained) Functioning Functioning Functioning Halted
(retained) Halted
(reset)
RAM Functioning Functioning Halted
(retained) Functioning Retained Functioning Retained Retained Retained
I/O Functioning Functioning Functioning Functioning Retained Functioning Retained Retained High
impedance
Notes: 1. “ Halted (retained)” means that int ernal register values are ret ained. The internal state is
“operation suspended.”
2. “ Halted (reset)” means that internal r egister values and internal states are initialized.
3. I n module st op mode, only modules for which a stop setting has been made are halted
(reset or re ta i n ed) .
4. W hen the LCD is operated in wat ch mode, subactive mode, or subsleep mode, select
the subclock as a system clock.
Rev. 1.0, 02/02, page 417 of 502
19.1 Register Descript i on s
Registers related to power-down mode s are shown be low. For details on the system cl oc k c ont rol
register (SCKCR), refer t o section 18.1.1, System Clock Control Register (SCKCR).
• System cl ock control regi ster (SCKCR)
• Standby cont rol register (SBYCR)
• Low-power control register (LPWRCR)
• Module stop control register A (MSTPCRA)
• Module stop control register B (MSTPCRB)
• Module stop control register C (MSTPCRC)
• Module stop control register D (MSTPCRD)
19. 1. 1 St a ndby Co nt r ol Regi ster ( SBYCR)
SBYCR performs software sta ndby mode c ontrol.
Bit Bit Name Initial Value R/W Description
7 SSBY 0 R/W Soft ware Standby
This bit specifies the transition mode after
exec utin g th e SLEEP instruction
0: Shi fts to sleep mod e whe n the SLEEP
instr uct io n is execute d
1: Shi fts to softwa re standby mode when the
SLEEP instr u ct ion is executed
This bit does not change when clearing the
software standby mode by using ext ernal interrupts
and shifting to normal operat ion. This bit should be
written with 0 when clear ing.
Rev. 1.0, 02/02, page 418 of 502
Bit Bit Name Initial Value R/W Description
6STS2 0 R/W
5STS1 0 R/W
4STS0 0 R/W
Standby Tim er Select 0 to 2
These bits select the MCU wait time for clock
stabiliz at ion when sof tware standby m ode is
cancelled by an external interrupt. W ith a cryst al
osc illa tor ( T able 1 9.3), s e le ct a wait tim e of 8 ms
(oscillation stabilization time) or more, depending
on the oper ating frequency. W ith an external clock,
select a wait time of 2 ms or more.
000: Standby tim e = 8192 states
001: Standby tim e = 16384 states
010: Standby tim e = 32768 states
011: Standby tim e = 65536 states
100: Standby tim e = 131072 states
101: Standby tim e = 262144 states
110: Reserved
111: Standby tim e = 16 states
3— 1 R/WReserved
Only 1 should be wr itten to this bit.
2 to
0— 0 — Reserved
These bits are always read as 0 and cannot be
modified.
19. 1. 2 L o w-Power Contr ol Register (LPWRCR)
LPWRCR is an 8-bit readabl e/writable register that perform s power-down mode control, subclock
generation control, oscillation circuit feedback resistance control, and frequency multiplication
factor setting.
Bit Bit Name Initial Value R/W Description
7DTON 0 R/W
Direct Transition ON Flag
0: When th e SLEEP instruction is execute d in high-
speed mode or medium -spee d mode , operation
shifts to sleep mode, softwa re standby mode , or
watch mode*.
When the SLEEP instruct ion is executed in
subactive m ode, operat ion shift s to subsleep
mode or watch mode.
1: When th e SLEEP instruction is execute d in high-
speed mode or medium -spee d mode , operation
shifts directly to subactive m ode*, or shifts to
sleep mode or software standby mode. When
the SLEEP instr uction is executed in subactive
mode, operat ion shifts directly to high-speed
mode, or shifts to subsleep m ode.
Rev. 1.0, 02/02, page 419 of 502
Bit Bit Name Initial Value R/W Description
6LSON 0 R/W
Low-Speed ON Flag
0: When th e SLEEP instruction is execute d in high-
speed mode or medium -spee d mode , operation
shifts to sleep mode, softwa re standby mode , or
watch mode*. When the SLEEP instruct io n is
executed in subactive m ode, operation shifts to
watch mode or shifts directly to high-speed
mode. Opera tion shif ts to high-speed mode
when wat ch mode is cancelled.
1: When th e SLEEP instruction is execute d in high-
speed mode, operation shifts to wat ch mode or
subactive mode*. When the SLEEP instruct ion
is executed in sub-active mode, operation shifts
to subsleep mode or watch mode. Operation
shifts to subact ive mode when watch mode is
cancelled.
50R/W
Reserved
This bit can be read from and written to. However,
do not writ e 1 to this bit.
4 SUBSTP 0 R/W Subclock Generation Control
0: Enables subclock generat ion
1: Disables subclock generation
3 RFCUT 0 R/W Osc illat ion Circuit Feedback Resistance Control
0: When the main clock is oscillating, sets the
feedback resis tanc e ON. When the main clock is
stopped, sets the feedba ck resis tanc e OFF .
1: Sets the f eedback resistance OFF.
Not e: W ith a cr yst a l resonato r, the resonato r will
not operate if this bit is set t o 1.
20R/W
Reserved
This bit can be read from and written to. However,
do not writ e 1 to this bit.
1STC1 0 R/W
0STC0 0 R/W
Frequency M ultiplication Factor Setting
These bits specify the frequency multiplication
factor of the PLL circuit.
00: x1
01: x2
10: x4
11: Setting prohibited
Note: * Always set high-speed mode when shift ing to watch mode or subact ive m ode.
Rev. 1.0, 02/02, page 420 of 502
19. 1. 3 Module Stop Contr ol Regi ster s A to D ( M STPCRA to MSTP CRD)
MSTPCR performs modul e stop mode control. Setting a bi t to 1 causes the corresponding module
to enter mod u le sto p mo de. Clearing th e bit to 0 clears th e mod ule stop mode .
• MSTPCRA
Bit Bit Name Initial Value R/W Module
7 MSTPA7*0R/W
6 MSTPA6*0R/W
5 MSTPA5 1 R/W 16-bit timer pulse unit (TPU)
4 MSTPA4*1R/W
3 MSTPA3*1R/W
2 MSTPA2*1R/W
1 MSTPA1 1 R/ W A/D converter
0 MSTPA0*1R/W
• MSTPCRB
Bit Bit Name Initial Value R/W Module
7 M STPB7 1 R/W Serial communication interface_0 ( SCI_0)
6 M STPB6 1 R/W Serial communication interface_1 ( SCI_1)
5 MSTPB5*1R/W
4 MSTPB4*1R/W
3 MSTPB3*1R/W
2 MSTPB2*1R/W
1 MSTPB1*1R/W
0 MSTPB0*1R/W
Rev. 1.0, 02/02, page 421 of 502
• MSTPCRC
Bit Bit Name Initial Value R/W Module
7 MSTPC7*1R/W
6 MSTPC6*1R/W
5 MSTPC5*1R/W
4 MSTPC4*1R/W
3 MSTPC3 1 R/W Hit ac h i Controller Area Network ( HCAN)
2 MSTPC2*1R/W
1 MSTPC1*1R/W
0 MSTPC0*1R/W
• MSTPCRD
Bit Bit Name Initial Value R/W Module
7 MSTPD7 1 R/W Mo tor co ntrol PWM timer (PWM)
6 MSTPD6 1 R/W LCD c o ntroller/drive r (LCD)
5Undefined
4Undefined
3Undefined
2Undefined
1Undefined
0Undefined
Note: *MSTPA7 and MSTPA6 are r eadable/writable bits with an initial value of 0 and should
always b e written with 0.
MSTPA4 to MSTPA2, MSTPA0, MSTPB5 to MSTPB0, MSTPC7 to MSTPC4 and MSTPC2
to MSTPC0 are readable/ writable bit s with an initial value of 1 and should always be written
with 1.
Rev. 1.0, 02/02, page 422 of 502
19.2 Mediu m - Sp eed Mode
When the SCK0 to SCK2 bits in SCKCR are set to 1, the operating mode changes to medium-
speed mode as soon as the current bus cycle ends. In medium-speed mode, the CPU operates on
t he opera ting clock (ø /2, ø/4, ø/8, ø/16, or ø/32 ) sp e cified b y t he SC K0 t o S CK 2 bits. O n-chip
peripheral module s other tha n bus masters always operate on t he high-speed clock (ø).
In medium-speed mode, a bus access is executed in the specified number of states with respect to
the bus master operating clock. For example, if ø/4 is selected as the operating clock, on-chip
memory is accessed i n four states, and int e rnal I/ O regist e rs in eight states.
Medium-speed mode is cleared by clearing all of bits SCK0 to SCK2 to 0. A transition is made to
high-speed mode and me dium-speed mode i s cleared at the end of the current bus cycle.
If the SLEEP instruction is executed when the SSBY bit in SBYCR is cleared to 0, a transition is
made to sleep mode. When sleep mode is cleared by an interrupt, medium-speed mode is restored.
When the SLEEP instruction is executed with the SSBY bit is set to 1, operation shifts to the
software sta ndby m ode. When software standby mode is cleared by an external int errupt, medium-
speed mode is restored.
Whe n the
5(6
pin is set low and medium-speed mode is cancelled, operation shifts to the reset
state. The same applies in the case of a reset caused by overflow of the watchdog timer.
Whe n the
67%<
pin is drive n low, a tr ansi tio n is made to hardw are standby mode.
Figure 19. 2 shows the t iming for transition t o and cle a rance of medium-spee d mode.
SCKCR SCKCR
ø,
supporting module clock
Bus master clock
Internal address bus
Internal write signal
Medium-speed mode
Figure 19.2 Medium-Speed Mode Transi tion and Clearance Timing
Rev. 1.0, 02/02, page 423 of 502
19.3 Sleep Mod e
19.3.1 Transition to Sleep M ode
If the SLEEP instruction is executed when the SSBY bit in SBYCR = 0, the CPU enters the sleep
mode. In sleep mode, CPU operation st ops, howe ver the conte nt s of the CPU's internal registers
are retained. Other peripheral modules do not stop.
19.3.2 Clearing Sleep Mode
Sleep mode is cleared by any interrupt, or signals at the
5(6
or
67%<
pi n.
• Exiting sleep mode by interrupts:
When an interrupt occurs, sleep mode is e xited a nd interrupt exception proce ssing sta rts. Sleep
mode is not exited if the interrupt i s disa bled, or if int errupts othe r than NMI are masked by the
CPU.
• Exiting sleep mode by
5(6
pi n:
Setting the
5(6
pin low selects the reset state. After the stipulated reset input duration, driving
the
5(6
pin high restart the CPU performing reset exception processing.
• Exiting sleep mode by
67%<
pi n:
Whe n the
67%<
pin le vel is driven low, a tra nsition is made to hardware standby mode.
Rev. 1.0, 02/02, page 424 of 502
19.4 Software Standby Mode
19.4.1 Tr ansi tion to Software Standby Mode
A transition is made to software standby mode if the SLEEP instruction is executed when the
SSBY bit i s set to 1. In this mode, the CPU, on-chip pe ripheral modul es, and oscillator, al l stop.
However, t he contents of the CPU's internal registers, on-chip RAM data, and t he states of on-chip
peripheral module s other tha n the SCI, PWM, HCAN, and A/D conve rter, and the states of I/O
ports, are retained. In this mode, the oscillator stops, and t herefore power dissipat ion is
significantly reduc e d.
19.4.2 Cle ari ng Software Standby Mode
Software sta ndby m ode is cl eared by an ext e rnal int errupt (NMI and
,54
to
,54
pins), or by
means of the
5(6
pin or
67%<
pi n.
• Clearing with a n interrupt
When an NMI, IRQ0, or IRQ5 interrupt reque st signal i s input, clock oscill ation starts, and
after the time set in bits STS0 to STS2 in SBYCR has elapsed, stable clocks are supplied to the
entire chip, software standby mode is cleared, and interrupt exception handling is started.
When clearing software standby mode with an IRQ0 to IRQ5 interrupt, set the corresponding
enable bit to 1 and ensure that no int errupt with a highe r priority than interrupts IRQ0 to IRQ5
is generated. Software standby mode c annot be cleared if the interrupt has been masked on the
CPU sid e.
• Clearing with the
5(6
pin
Whe n the
5(6
pin is driven low, clock oscillation is started. At the same time as clock
oscillation starts, clocks are supplied to the entire chip. Note that the
5(6
pi n mus t be held low
until clock oscillation stabilizes. When the
5(6
pin goes high, t he CPU be gins re set exception
handling.
• Clearing with the
67%<
pin
Whe n the
67%<
pin is drive n low, a tr ansi tio n is made to hardw are standby mode.
Rev. 1.0, 02/02, page 425 of 502
19.4.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode
Bits STS2 to STS0 i n SBYCR should be se t as describe d below.
• Using a crystal oscillato r:
Set bits STS0 to STS2 so that the standby time is at least 8 ms (the oscillation stabilization
time).
Table 19. 3 shows the sta ndby times for diffe rent operating freque ncies and settings of bits
STS0 to STS2.
• Using an extern al clock
The PLL circuit require s a time for stabilization. Set bits STS0 to STS2 so that the standby time is
at least 2 ms (the oscillation stabilization time).
Table 19. 3 Oscillation Stabilization Ti me Settings
STS2 STS1 STS0 St andby Time 20
MHz 16
MHz 12
MHz 10
MHz 8
MHz 6
MHz 4
MHz Unit
0 8192 states 0. 41 0.51 0. 68 0.8 1.0 1.3 2.0
0
1 16384 states 0.82 1.0 1.3 1.6 2.0 2.7 4.1
0 32768 states 1.6 2.0 2.7 3.3 4.1 5.5 8.2
0
1
1 65536 states 3.3 4.1 5.5 6.6 8.2 10.9 16.4
0 131072 states 6.6 8.2 10.9 13.1 16.4 21.8 32.80
1 262144 states 13.1 16.4 21.8 26.2 32.8 43.6 65.6
ms
0 Reserved ————————
1
11 16 states 0.8 1. 0 1.3 1.6 2. 0 1.7 4. 0 µs
: Recommended time setting
Rev. 1.0, 02/02, page 426 of 502
19.4.4 Software Standby Mo de Application Example
Figure 19. 3 shows an example in which a transit i on is made to software standby mode at a fal ling
edge on the NMI pin, and software standby mode i s cleared at a ri sing e dge on the NMI pi n.
In this example, an NMI interrupt is a cce pted with the NMIEG bi t in SYSCR cleared to 0 (falling
edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set
to 1, and a SLEEP instruction is executed, causing a transition to software standby mode.
Software sta ndby m ode is the n cleared a t the rising edge on the NMI pi n.
Oscillator
ø
NMI
NMIEG
SSBY
NMI exception
processing
NMIEG = 1
SSBY = 1 Oscillation
stabilization
time t
OSC2
Software standby mode
(power-down mode) NMI exception
processing
SLEEP command
Fi g ure 19.3 Software Sta ndby Mode Appli cat i o n Example
Rev. 1.0, 02/02, page 427 of 502
19.5 Hardware Standby Mode
19.5.1 T ransi t ion t o Hardwar e Sta ndby Mo de
Whe n the
67%<
pin is drive n low, a tr ansi tio n is made to hardw are standby mode from any mode.
In hardware standby mode , all functions ent er the re set state and stop opera tion, resulting in a
significant reduct i on in power dissipa tion. As long as the pre scribed voltage is supplie d, on-chip
RAM data is retained. I/O ports are set to the high-impedance state.
In order t o retain on-chip RAM dat a, the RAME bit in SYSCR should be c lea red to 0 before
driving the
67%<
pi n low .
Do not change the state of the mode pins (MD0 and MD2) while this LSI is in hardware standby
mode.
19. 5. 2 Cle ari ng Hardwa re St a ndby Mode
Hard w are stand by mo de is cl eared by means of the
67%<
pi n and t he
5(6
pin. When the
67%<
pin is driven high while the
5(6
pin is low, the reset state is set and clock oscillation is started.
Ensure that the
5(6
pin is held low until the clock oscillator stabilizes (at least 8 ms—the
oscillation stabilization time—when using a crystal oscillator). When the
5(6
pi n is s ubseque nt ly
driven high, a transition is made to the program execution state via the reset exception handling
state.
19. 5. 3 Har dware Sta ndby Mode Timi ng s
Tim i ng of Transi tion to Hardware Standby Mode :
1. To reta i n RAM content s with the RAME bit set to 1 in SYSCR
Drive the
5(6
signal low at least 10 states before the
67%<
si gnal goes l ow, as shown in
figure 19.4. Aft e r
67%<
has gone low,
5(6
has to wait for a t least 0 ns before becom ing high.
t
2
≥0ns
t
1
≥10t
cyc
Fi g ure 19 .4 Timi ng of Tra nsi tio n to Har dwar e Sta ndby Mo de
2. To retain RAM contents with the RAME bit cleared to 0 in SYSCR, or when RAM contents
do no t n eed to be retained
Rev. 1.0, 02/02, page 428 of 502
5(6
does n o t hav e to be driven low as in the above case.
Tim i ng of Recover y from Hardware St a ndby Mode:
Drive the
5(6
signal l ow approxima t ely 100 ns or l onger before
67%<
goes high to execute a
power-on reset.
t
OSC1
t≥100ns
Fi g ure 19 .5 Timi ng of Rec overy fro m Hardwar e Sta ndby Mode
19.6 Module Stop Mode
Module stop mod e can be set for individ ual on-chip peripheral modules.
When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of
the bus cycle and a transition is made to module stop mode. The CPU continues operating
independently.
When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module
starts operating at the e nd of the bus cycle. In module stop mode, the int ernal sta tes of modules
other than t he SCI (some SCI regi sters are re tained), PWM, HCAN, and A/D converter a re
retained.
After rese t clearanc e, all modules a re in module st op mode.
When an on-chi p periphe ral modul e is in module stop mode, read/writ e access to i ts registers is
disabled.
Rev. 1.0, 02/02, page 429 of 502
19.7 Watch Mode
19.7.1 Transition to Watch Mode
CPU operation makes a transition to watch mode when the SLEEP instruction is executed in high-
speed mode or subactive mode with the SSBY bit in SBYCR = 1, the DTON bit in LPWRCR = 0,
an d the PSS bit i n TCSR_1 (WDT _ 1) = 1.
In watch mode, the CPU is stopped and peripheral modules other than WDT_1 and LCD are also
stopped. The c ontents of the CPU's int ernal registers, on-chip RAM data, and the states of on-chip
peripheral module s other tha n the SCI, PWM, HCAN, and A/D conve rter, and the states of I/O
ports, are retained.
19.7.2 Canceling Watch Mode
Watch mode is canceled by any int errupt (W OVI1 int errupt, NMI pin, or
,54
to
,54
pin), or
signals at the
5(6
, or
67%<
pin.
Canceling Watch Mode by Interrupt : When an interrupt occu rs, watch mod e is canceled and a
transition is made to high-speed mode or medium-speed mode when the LSON bit in LPWRCR =
0 or to subactive mode when the LSON bit = 1. When a transition is made to high-speed mode, a
stable cloc k is supplied to all LSI circuits and interrupt exc e ption processing starts a fter the time
set in t he STS2 to STS0 bits of SBYCR ha s el a psed. In case of an IRQ0 to IRQ5 interrupt, watch
mode is not canceled if the corresponding enable bit has bee n cleared t o 0. In c ase of the interrupt
from the on-chip pe ripheral modul e s, if the interrupt enable registe r has been set to disable the
reception of that interrupt, or is masked by the CPU, watch mode is not canceled.
For the setting of the oscillation stabilization time when making a transition from watch mode to
high-speed mode, see section 19.4.3, Setting Osci l lation Stabilization Time after Clearing
Software Sta ndby Mode.
Canceling W atch Mode by
5
5(6
(6
pin: For canceling watch mode by the
5(6
pin, see sectio n
19.4.2, Cl earing Soft ware St a ndby Mode.
Canceling W atch Mode by
6
67%<
7%<
pin: When th e
67%<
pin is driven low, a transition is made to
hardware standby mode.
Rev. 1.0, 02/02, page 430 of 502
19.8 Subsleep Mode
19. 8. 1 T r a nsi t ion t o Subsleep Mode
When the SLEEP instruction is executed in subactive mode with the SSBY bit in SBYCR = 0, the
LSON bit in LPWRCR = 1, and the PSS bit in TCSR _1 (WDT_1) = 1, CPU operatio n shif t s to
subsleep mod e.
In subsleep mode, the CPU is stopped and peripheral modules other than WDT_0, WDT_1, and
LCD are also stopped. The contents of the CPU's internal registers, on-chip RAM data, and the
states of on-chip pe ripheral modules othe r than t he SCI, PWM, HCAN, and A/ D converter, and
the states of I/O ports, are retained.
19. 8. 2 Ca nc eling Subsleep Mode
Subsleep m ode is canceled by any interrupt (W OVI0 or WOVI1 inte rrupt, NMI pin, or
,54
to
,54
pin), or si gnals at the
5(6
or
67%<
pi n.
Canceling Subsleep Mode by Interrupt : When a n inte rrupt occurs, subsleep m ode is canceled
and interrupt exception processing starts.
In case of an IRQ0 to IRQ5 interrupt, subsle ep mode is not canceled if the corresponding enable
bit has been cleared to 0. In case of the interrupt from the on-c hip peri pheral m odules, if the
interrupt ena ble re gi ster has been set to disable the reception of t hat interrupt, or i s masked by the
CP U , sub s leep mo de is no t canceled.
Canceling Subsleep Mode by
5(
5(6
6
pin: For canc eling subs le ep mod e by the
5(6
pi n, see s ec tion
19.4.2, Cl earing Soft ware St a ndby Mode.
Canceling Subsleep Mode by
67%
67%<
<
pin: When the
67%<
pin is dr iven low, a transition is made
to hardware standby mode.
19.9 Subactive Mode
19. 9. 1 T r a nsi t ion t o Subactiv e Mode
CPU operation makes a transition to subactive mode when the SLEEP instruction is executed in
high-speed mode with the SSBY bi t in SBYCR = 1, the DTON bit in LPW RCR = 1, the LSON bi t
= 1, and the PSS bit in TCSR_1 (WDT _1) = 1. When an interrupt occurs in watch mode, and if the
LSON bit of LPWRCR is 1,a transition is ma de to subactive mode. And i f an int e rrupt occ urs in
subsleep mode, a transition is made to subactive mode.
Rev. 1.0, 02/02, page 431 of 502
In suba c tive mode, the CPU operate s at low spe ed on the subclock, and the program is executed
one after another. Peripheral modules other than WDT_0, WDT_1, and LCD are also stopped.
When operating the CPU in subactive mode, the SCK2 to SCK0 bits in SCKCR must be set to 0.
19. 9. 2 Ca nc eling Subactive Mode
Subactive mode is canceled by the SLEEP instruction or signals at the
5(6
or
67%<
pin.
Canceling Subactive Mode by SLEEP Instr ucti o n: When the SLEEP instruction is executed
wit h the SSB Y bit in SBYCR = 1, the DTON bit in LPWRCR = 0, and the PSS bit in TCSR_1
(WDT_1) = 1, subactive mode is canceled and a transition is made to watch mode. When the
SLEEP instruction is executed with the SSBY bit in SBYCR = 0, the LSON bit in LPWRCR = 1,
an d the PSS bit i n TCSR_ 1 (WDT_ 1 ) = 1, a transi ti o n is made t o sub sle ep mo de. When the
SLEEP instruction is executed with the SSBY bit in SBYCR = 1, the DTON bit in LPWRCR = 1,
th e L SON bit = 0, and the PSS bit in TCSR_1 (WDT_1 ) = 1, a direc t t ran sit i o n is made to high -
speed mode (SCK0 to SCK2 are all 0).
Canceling Subactive Mode by
5(
5(6
6
pin: Fo r canceling sub active mo de by the
5(6
pi n, see
section 19.4. 2, Clearing Softwa re Standby Mode.
Canceling Subactive Mode by
67%<
67%<
pin : When the
67%<
pin is driven low, a transition is
made to hardware standby mode.
19.10 Direct Tran sit i on s
There are three modes, high-spe ed, medium-speed, and subactive, in which the CPU executes
programs. When a direct transit i on is made, there is no interrupti on of program exec ution in
shifting be t ween high-speed and subactive mode s. Direct transi tions are enabled by setting the
DTON bit in LPWRCR to 1, then executing the SLEEP instruction. After a transition, direct
transition interrupt excep tion processing star ts.
19. 1 0.1 Di r ec t Tr ansitions from Hig h-Spee d Mode to Subac tive Mode
Execute the SLEEP instruction in high-speed mode with the SSBY bit in SBYCR = 1, the LSON
bi t in L PWRC R= 1, the DTON bit = 1, and the PSS bit in TCSR_1 (WDT _ 1) = 1, to ma ke a direct
transition to subactive mode.
19. 1 0.2 Di r ec t Tr ansitions from Subac tive Mode to High- Spee d Mode
Exec u te the SLEEP instr uct ion in subact ive mode wit h the SSBY bit in SBYCR = 1, the LSON bit
in LPW RCR = 0, the DTON bit = 1, an d the PSS bit in TCSR _1 (WDT _ 1) = 1, to m ake a direct
transition to high-speed mode a fter the time set in the STS2 to STS0 bits of SBYCR has ela psed.
Rev. 1.0, 02/02, page 432 of 502
19.11 ø Clock Output Disabling Function
The output of the ø clock can be controlled by means of the PSTOP bit in SCKCR and DDR for
the corresponding port. When the PSTOP bit is set to 1, the ø clock stops at the end of the bus
cycle, and ø out put goes high. ø cl oc k out put is ena bled when the PSTOP bit is cleared t o 0. Whe n
DDR for t he correspondi ng port is cl eared t o 0, ø c lock output is disabled and input port mode is
set. Table 19.4 shows the state of the ø pin in each processing state.
Table 19. 4 ø Pin State in Each Processing State
Register
Settings
DDR PSTOP
High-Speed
Mode
Medium-
Speed Mo de Subactive
Mode
Sleep Mo de
Subsleep
Mode
Software
Standby Mode
Watch Mo de
Direct
Transitions Hardware
Standby Mode
0X High
impedance High
impedance High
impedance High
impedance High
impedance
1 0 ø output øSUB output ø output Fixed hi gh High
impedance
1 1 Fi xed high Fixed high Fi xed high Fi xed high High
impedance
Legend
X: Don’t care
19.12 Usage Notes
19.12.1 I/O Port Status
The status of the I/O ports is retained in watch mode. Also, when the OPE bit is set to 1, the
address bus and bus control signals continue to be output. Therefore, whe n a high level is output,
the current consum ption is not diminished by the amount of current to support the hi gh level
output.
19.12.2 Current Dissipation during Oscillation Stabilization Wait Period
The current consumption increases during the oscillation stabilization wait period.
19. 1 2.3 O n- Chi p Peri pher a l Module Inter rupt
The on-chip pe ripheral module (TPU), that halts in subactive mode, cannot cancel that interrupt in
subactive m ode. Thus, if a transition i s made t o subactive mode when an interrupt has been
requested, i t will not be possible to c lear the CPU interrupt source.
Rev. 1.0, 02/02, page 433 of 502
Interrupts should therefore be disabled before exe c uting the SLEEP i nstruction, t hen entering
subactive mode or watch mode.
19.12.4 Writ ing to MSTPCR
MSTPCR sh ould only be wri tten to by t h e CPU.
Rev. 1.0, 02/02, page 434 of 502
Rev. 1.0, 02/02, page 435 of 502
Section 20 List of Registers
The address list gives information on the on-chip I/O register addresses, how the register bits are
configured, a nd the register st ates in each operating m ode. The information is gi ven as shown
below.
1. Regi ster addre sses (addre ss order)
• Registers a re listed from the lowe r alloc ation addresses.
• Registers are classified by func tional modu les.
• The access size is indicated.
2. Regi ster bit s
• Bit configurations of the registers are described in the same order as the register addresses.
• Reserved bits are indicated by in the bit name column.
• No entry in the bit-name column indicates that the whole register is allocated as a counter or
for holding data.
3. Register states in each operating mode
• Register states are described in the same order as the register addresses.
• The register states described here are for the basic operating modes. If there is a specific reset
for an on-chip peripheral modul e, refer t o the section on t hat on-chip peripheral module.
20.1 Regist er Ad d resses ( Ad d ress Or der)
The data bus width indicates the numbers of bits by which the register is accessed.
The number of access states indicates the number of states based on the specified reference clock.
Rev. 1.0, 02/02, page 436 of 502
Register Name Abbrevia-
tion Number
of Bits Address*Module
Data
Bus
Width
Number
of Access
States
Master control register M CR 8 H'F800 HCAN 16 4
General status regist er GSR 8 H'F801 HCAN 16 4
Bit configuration register BCR 16 H'F802 HCAN 16 4
Mailbox con figuration regis ter MBCR 16 H'F804 HCAN 16 4
Transmit wait register TXPR 16 H'F806 HCAN 16 4
Transmit wait cancel register TXCR 16 H'F808 HCAN 16 4
Transmit acknowledge register TXACK 16 H'F80A HCAN 16 4
Abort acknowledge register ABACK 16 H'F80C HCAN 16 4
Receiv e com plete re g ister RXPR 16 H'F8 0E HCAN 1 6 4
Remote reque st registe r RFPR 16 H'F810 HCA N 16 4
Int errupt regist er IRR 16 H'F812 HCAN 16 4
Mailbox int errupt mask regist er M BIMR 16 H'F814 HCAN 16 4
Int errupt mask register I M R 16 H'F816 HCAN 16 4
Receive er r or count er REC 8 H'F818 HCAN 16 4
Transmit error counter TEC 8 H'F819 HCAN 16 4
Unread message status register UMSR 16 H'F81A HCAN 16 4
Local acceptance filter mask L LAFML 16 H'F81C HCAN 16 4
Local acceptance filter mask H LAFMH 16 H'F81E HCAN 16 4
Message con trol 0[1] MC0[1] 8 H'F820 HCAN 16 4
Message con trol 0[2] MC0[2] 8 H'F821 HCAN 16 4
Message con trol 0[3] MC0[3] 8 H'F822 HCAN 16 4
Message con trol 0[4] MC0[4] 8 H'F823 HCAN 16 4
Message con trol 0[5] MC0[5] 8 H'F824 HCAN 16 4
Message con trol 0[6] MC0[6] 8 H'F825 HCAN 16 4
Message con trol 0[7] MC0[7] 8 H'F826 HCAN 16 4
Message con trol 0[8] MC0[8] 8 H'F827 HCAN 16 4
Rev. 1.0, 02/02, page 437 of 502
Register Name Abbrevia-
tion Number
of Bits Address*Module
Data
Bus
Width
Number
of Access
States
Message con trol 1[1] MC1[1] 8 H'F828 HCAN 16 4
Message con trol 1[2] MC1[2] 8 H'F829 HCAN 16 4
Message con trol 1[3] MC1[3] 8 H'F82A HCAN 16 4
Message con trol 1[4] MC1[4] 8 H'F82B HCAN 16 4
Message con trol 1[5] MC1[5] 8 H'F82C HCAN 16 4
Message con trol 1[6] MC1[6] 8 H'F82D HCAN 16 4
Message con trol 1[7] MC1[7] 8 H'F82E HCAN 16 4
Message con trol 1[8] MC1[8] 8 H'F82F HCAN 16 4
Message con trol 2[1] MC2[1] 8 H'F830 HCAN 16 4
Message con trol 2[2] MC2[2] 8 H'F831 HCAN 16 4
Message con trol 2[3] MC2[3] 8 H'F832 HCAN 16 4
Message con trol 2[4] MC2[4] 8 H'F833 HCAN 16 4
Message con trol 2[5] MC2[5] 8 H'F834 HCAN 16 4
Message con trol 2[6] MC2[6] 8 H'F835 HCAN 16 4
Message con trol 2[7] MC2[7] 8 H'F836 HCAN 16 4
Message con trol 2[8] MC2[8] 8 H'F837 HCAN 16 4
Message con trol 3[1] MC3[1] 8 H'F838 HCAN 16 4
Message con trol 3[2] MC3[2] 8 H'F839 HCAN 16 4
Message con trol 3[3] MC3[3] 8 H'F83A HCAN 16 4
Message con trol 3[4] MC3[4] 8 H'F83B HCAN 16 4
Message con trol 3[5] MC3[5] 8 H'F83C HCAN 16 4
Message con trol 3[6] MC3[6] 8 H'F83D HCAN 16 4
Message con trol 3[7] MC3[7] 8 H'F83E HCAN 16 4
Message con trol 3[8] MC3[8] 8 H'F83F HCAN 16 4
Message con trol 4[1] MC4[1] 8 H'F840 HCAN 16 4
Message con trol 4[2] MC4[2] 8 H'F841 HCAN 16 4
Message con trol 4[3] MC4[3] 8 H'F842 HCAN 16 4
Message con trol 4[4] MC4[4] 8 H'F843 HCAN 16 4
Message con trol 4[5] MC4[5] 8 H'F844 HCAN 16 4
Message con trol 4[6] MC4[6] 8 H'F845 HCAN 16 4
Message con trol 4[7] MC4[7] 8 H'F846 HCAN 16 4
Message con trol 4[8] MC4[8] 8 H'F847 HCAN 16 4
Rev. 1.0, 02/02, page 438 of 502
Register Name Abbrevia-
tion Number
of Bits Address*Module
Data
Bus
Width
Number
of Access
States
Message con trol 5[1] MC5[1] 8 H'F848 HCAN 16 4
Message con trol 5[2] MC5[2] 8 H'F849 HCAN 16 4
Message con trol 5[3] MC5[3] 8 H'F84A HCAN 16 4
Message con trol 5[4] MC5[4] 8 H'F84B HCAN 16 4
Message con trol 5[5] MC5[5] 8 H'F84C HCAN 16 4
Message con trol 5[6] MC5[6] 8 H'F84D HCAN 16 4
Message con trol 5[7] MC5[7] 8 H'F84E HCAN 16 4
Message con trol 5[8] MC5[8] 8 H'F84F HCAN 16 4
Message con trol 6[1] MC6[1] 8 H'F850 HCAN 16 4
Message con trol 6[2] MC6[2] 8 H'F851 HCAN 16 4
Message con trol 6[3] MC6[3] 8 H'F852 HCAN 16 4
Message con trol 6[4] MC6[4] 8 H'F853 HCAN 16 4
Message con trol 6[5] MC6[5] 8 H'F854 HCAN 16 4
Message con trol 6[6] MC6[6] 8 H'F855 HCAN 16 4
Message con trol 6[7] MC6[7] 8 H'F856 HCAN 16 4
Message con trol 6[8] MC6[8] 8 H'F857 HCAN 16 4
Message con trol 7[1] MC7[1] 8 H'F858 HCAN 16 4
Message con trol 7[2] MC7[2] 8 H'F859 HCAN 16 4
Message con trol 7[3] MC7[3] 8 H'F85A HCAN 16 4
Message con trol 7[4] MC7[4] 8 H'F85B HCAN 16 4
Message con trol 7[5] MC7[5] 8 H'F85C HCAN 16 4
Message con trol 7[6] MC7[6] 8 H'F85D HCAN 16 4
Message con trol 7[7] MC7[7] 8 H'F85E HCAN 16 4
Message con trol 7[8] MC7[8] 8 H'F85F HCAN 16 4
Message con trol 8[1] MC8[1] 8 H'F860 HCAN 16 4
Message con trol 8[2] MC8[2] 8 H'F861 HCAN 16 4
Message con trol 8[3] MC8[3] 8 H'F862 HCAN 16 4
Message con trol 8[4] MC8[4] 8 H'F863 HCAN 16 4
Message con trol 8[5] MC8[5] 8 H'F864 HCAN 16 4
Message con trol 8[6] MC8[6] 8 H'F865 HCAN 16 4
Message con trol 8[7] MC8[7] 8 H'F866 HCAN 16 4
Message con trol 8[8] MC8[8] 8 H'F867 HCAN 16 4
Rev. 1.0, 02/02, page 439 of 502
Register Name Abbrevia-
tion Number
of Bits Address*Module
Data
Bus
Width
Number
of Access
States
Message con trol 9[1] MC9[1] 8 H'F868 HCAN 16 4
Message con trol 9[2] MC9[2] 8 H'F869 HCAN 16 4
Message con trol 9[3] MC9[3] 8 H'F86A HCAN 16 4
Message con trol 9[4] MC9[4] 8 H'F86B HCAN 16 4
Message con trol 9[5] MC9[5] 8 H'F86C H CA N 16 4
Message con trol 9[6] MC9[6] 8 H'F86D H CA N 16 4
Message con trol 9[7] MC9[7] 8 H'F86E HCAN 16 4
Message con trol 9[8] MC9[8] 8 H'F86F HCAN 16 4
Message con trol 10[1] MC10 [1] 8 H'F870 HCAN 16 4
Message con trol 10[2] MC10 [2] 8 H'F871 HCAN 16 4
Message con trol 10[3] MC10 [3] 8 H'F872 HCAN 16 4
Message con trol 10[4] MC10 [4] 8 H'F873 HCAN 16 4
Message con trol 10[5] MC10 [5] 8 H'F874 HCAN 16 4
Message con trol 10[6] MC10 [6] 8 H'F875 HCAN 16 4
Message con trol 10[7] MC10 [7] 8 H'F876 HCAN 16 4
Message con trol 10[8] MC10 [8] 8 H'F877 HCAN 16 4
Message con trol 11[1] MC11 [1] 8 H'F878 HCAN 16 4
Message con trol 11[2] MC11 [2] 8 H'F879 HCAN 16 4
Message con trol 11[3] MC11 [3] 8 H'F87A HCAN 16 4
Message con trol 11[4] MC11 [4] 8 H'F87B HCAN 16 4
Message con trol 11[5] MC11 [5] 8 H'F87C HCAN 16 4
Message con trol 11[6] MC11 [6] 8 H'F87D HCAN 16 4
Message con trol 11[7] MC11 [7] 8 H'F87E HCAN 16 4
Message con trol 11[8] MC11 [8] 8 H'F87F HCA N 16 4
Message con trol 12[1] MC12 [1] 8 H'F880 HCAN 16 4
Message con trol 12[2] MC12 [2] 8 H'F881 HCAN 16 4
Message con trol 12[3] MC12 [3] 8 H'F882 HCAN 16 4
Message con trol 12[4] MC12 [4] 8 H'F883 HCAN 16 4
Message con trol 12[5] MC12 [5] 8 H'F884 HCAN 16 4
Message con trol 12[6] MC12 [6] 8 H'F885 HCAN 16 4
Message con trol 12[7] MC12 [7] 8 H'F886 HCAN 16 4
Message con trol 12[8] MC12 [8] 8 H'F887 HCAN 16 4
Rev. 1.0, 02/02, page 440 of 502
Register Name Abbrevia-
tion Number
of Bits Address*Module
Data
Bus
Width
Number
of Access
States
Message con trol 13[1] MC13 [1] 8 H'F888 HCAN 16 4
Message con trol 13[2] MC13 [2] 8 H'F889 HCAN 16 4
Message con trol 13[3] MC13 [3] 8 H'F88A HCAN 16 4
Message con trol 13[4] MC13 [4] 8 H'F88B HCAN 16 4
Message con trol 13[5] MC13 [5] 8 H'F88C HCAN 16 4
Message con trol 13[6] MC13 [6] 8 H'F88D HCAN 16 4
Message con trol 13[7] MC13 [7] 8 H'F88E HCAN 16 4
Message con trol 13[8] MC13 [8] 8 H'F88F HCA N 16 4
Message con trol 14[1] MC14 [1] 8 H'F890 HCAN 16 4
Message con trol 14[2] MC14 [2] 8 H'F891 HCAN 16 4
Message con trol 14[3] MC14 [3] 8 H'F892 HCAN 16 4
Message con trol 14[4] MC14 [4] 8 H'F893 HCAN 16 4
Message con trol 14[5] MC14 [5] 8 H'F894 HCAN 16 4
Message con trol 14[6] MC14 [6] 8 H'F895 HCAN 16 4
Message con trol 14[7] MC14 [7] 8 H'F896 HCAN 16 4
Message con trol 14[8] MC14 [8] 8 H'F897 HCAN 16 4
Message con trol 15[1] MC15 [1] 8 H'F898 HCAN 16 4
Message con trol 15[2] MC15 [2] 8 H'F899 HCAN 16 4
Message con trol 15[3] MC15 [3] 8 H'F89A HCAN 16 4
Message con trol 15[4] MC15 [4] 8 H'F89B HCAN 16 4
Message con trol 15[5] MC15 [5] 8 H'F89C HCAN 16 4
Message con trol 15[6] MC15 [6] 8 H'F89D HCAN 16 4
Message con trol 15[7] MC15 [7] 8 H'F89E HCAN 16 4
Message con trol 15[8] MC15 [8] 8 H'F89F HCA N 16 4
Message data 0[1 ] MD0[1] 8 H'F8B0 HCAN 16 4
Message data 0[2 ] MD0[2] 8 H'F8B1 HCAN 16 4
Message data 0[3 ] MD0[3] 8 H'F8B2 HCAN 16 4
Message data 0[4 ] MD0[4] 8 H'F8B3 HCAN 16 4
Message data 0[5 ] MD0[5] 8 H'F8B4 HCAN 16 4
Message data 0[6 ] MD0[6] 8 H'F8B5 HCAN 16 4
Message data 0[7 ] MD0[7] 8 H'F8B6 HCAN 16 4
Message data 0[8 ] MD0[8] 8 H'F8B7 HCAN 16 4
Rev. 1.0, 02/02, page 441 of 502
Register Name Abbrevia-
tion Number
of Bits Address*Module
Data
Bus
Width
Number
of Access
States
Message data 1[1 ] MD1[1] 8 H'F8B8 HCAN 16 4
Message data 1[2 ] MD1[2] 8 H'F8B9 HCAN 16 4
Message data 1[3 ] MD1[3] 8 H'F8BA HCAN 16 4
Message data 1[4 ] MD1[4] 8 H'F8BB HCAN 16 4
Message data 1[5 ] MD1[5] 8 H'F8BC H CA N 16 4
Message data 1[6 ] MD1[6] 8 H'F8BD H CA N 16 4
Message data 1[7 ] MD1[7] 8 H'F8BE HCAN 16 4
Message data 1[8 ] MD1[8] 8 H'F8BF HCAN 16 4
Message data 2[1 ] MD2[1] 8 H'F8C0 HCAN 16 4
Message data 2[2 ] MD2[2] 8 H'F8C1 HCAN 16 4
Message data 2[3 ] MD2[3] 8 H'F8C2 HCAN 16 4
Message data 2[4 ] MD2[4] 8 H'F8C3 HCAN 16 4
Message data 2[5 ] MD2[5] 8 H'F8C4 HCAN 16 4
Message data 2[6 ] MD2[6] 8 H'F8C5 HCAN 16 4
Message data 2[7 ] MD2[7] 8 H'F8C6 HCAN 16 4
Message data 2[8 ] MD2[8] 8 H'F8C7 HCAN 16 4
Message data 3[1 ] MD3[1] 8 H'F8C8 HCAN 16 4
Message data 3[2 ] MD3[2] 8 H'F8C9 HCAN 16 4
Message data 3[3 ] MD3[3] 8 H'F8CA H CA N 16 4
Message data 3[4 ] MD3[4] 8 H'F8CB H CA N 16 4
Message data 3[5 ] MD3[5] 8 H'F8CC H CA N 16 4
Message data 3[6 ] MD3[6] 8 H'F8CD H CA N 16 4
Message data 3[7 ] MD3[7] 8 H'F8CE H CA N 16 4
Message data 3[8 ] MD3[8] 8 H'F8CF HCAN 16 4
Message data 4[1 ] MD4[1] 8 H'F8D0 HCAN 16 4
Message data 4[2 ] MD4[2] 8 H'F8D1 HCAN 16 4
Message data 4[3 ] MD4[3] 8 H'F8D2 HCAN 16 4
Message data 4[4 ] MD4[4] 8 H'F8D3 HCAN 16 4
Message data 4[5 ] MD4[5] 8 H'F8D4 HCAN 16 4
Message data 4[6 ] MD4[6] 8 H'F8D5 HCAN 16 4
Message data 4[7 ] MD4[7] 8 H'F8D6 HCAN 16 4
Message data 4[8 ] MD4[8] 8 H'F8D7 HCAN 16 4
Rev. 1.0, 02/02, page 442 of 502
Register Name Abbrevia-
tion Number
of Bits Address*Module
Data
Bus
Width
Number
of Access
States
Message data 5[1 ] MD5[1] 8 H'F8D8 HCAN 16 4
Message data 5[2 ] MD5[2] 8 H'F8D9 HCAN 16 4
Message data 5[3 ] MD5[3] 8 H'F8DA H CA N 16 4
Message data 5[4 ] MD5[4] 8 H'F8DB H CA N 16 4
Message data 5[5 ] MD5[5] 8 H'F8DC H CA N 16 4
Message data 5[6 ] MD5[6] 8 H'F8DD H CA N 16 4
Message data 5[7 ] MD5[7] 8 H'F8DE H CA N 16 4
Message data 5[8 ] MD5[8] 8 H'F8DF HCAN 16 4
Message data 6[1 ] MD6[1] 8 H'F8E0 HCAN 16 4
Message data 6[2 ] MD6[2] 8 H'F8E1 HCAN 16 4
Message data 6[3 ] MD6[3] 8 H'F8E2 HCAN 16 4
Message data 6[4 ] MD6[4] 8 H'F8E3 HCAN 16 4
Message data 6[5 ] MD6[5] 8 H'F8E4 HCAN 16 4
Message data 6[6 ] MD6[6] 8 H'F8E5 HCAN 16 4
Message data 6[7 ] MD6[7] 8 H'F8E6 HCAN 16 4
Message data 6[8 ] MD6[8] 8 H'F8E7 HCAN 16 4
Message data 7[1 ] MD7[1] 8 H'F8E8 HCAN 16 4
Message data 7[2 ] MD7[2] 8 H'F8E9 HCAN 16 4
Message data 7[3 ] MD7[3] 8 H'F8EA HCAN 16 4
Message data 7[4 ] MD7[4] 8 H'F8EB HCAN 16 4
Message data 7[5 ] MD7[5] 8 H'F8EC H CA N 16 4
Message data 7[6 ] MD7[6] 8 H'F8ED H CA N 16 4
Message data 7[7 ] MD7[7] 8 H'F8EE HCAN 16 4
Message data 7[8 ] MD7[8] 8 H'F8EF HCAN 16 4
Message data 8[1 ] MD8[1] 8 H'F8F0 HCAN 16 4
Message data 8[2 ] MD8[2] 8 H'F8F1 HCAN 16 4
Message data 8[3 ] MD8[3] 8 H'F8F2 HCAN 16 4
Message data 8[4 ] MD8[4] 8 H'F8F3 HCAN 16 4
Message data 8[5 ] MD8[5] 8 H'F8F4 HCAN 16 4
Message data 8[6 ] MD8[6] 8 H'F8F5 HCAN 16 4
Message data 8[7 ] MD8[7] 8 H'F8F6 HCAN 16 4
Message data 8[8 ] MD8[8] 8 H'F8F7 HCAN 16 4
Rev. 1.0, 02/02, page 443 of 502
Register Name Abbrevia-
tion Number
of Bits Address*Module
Data
Bus
Width
Number
of Access
States
Message data 9[1 ] MD9[1] 8 H'F8F8 HCAN 16 4
Message data 9[2 ] MD9[2] 8 H'F8F9 HCAN 16 4
Message data 9[3 ] MD9[3] 8 H'F8FA HCAN 16 4
Message data 9[4 ] MD9[4] 8 H'F8FB HCAN 16 4
Message data 9[5 ] MD9[5] 8 H'F8FC HCAN 16 4
Message data 9[6 ] MD9[6] 8 H'F8FD HCAN 16 4
Message data 9[7 ] MD9[7] 8 H'F8FE HCAN 16 4
Message data 9[8 ] MD9[8] 8 H'F8FF HCAN 16 4
Message data 10[1 ] MD10 [1] 8 H'F900 HCAN 16 4
Message data 10[2 ] MD10 [2] 8 H'F901 HCAN 16 4
Message data 10[3 ] MD10 [3] 8 H'F902 HCAN 16 4
Message data 10[4 ] MD10 [4] 8 H'F903 HCAN 16 4
Message data 10[5 ] MD10 [5] 8 H'F904 HCAN 16 4
Message data 10[6 ] MD10 [6] 8 H'F905 HCAN 16 4
Message data 10[7 ] MD10 [7] 8 H'F906 HCAN 16 4
Message data 10[8 ] MD10 [8] 8 H'F907 HCAN 16 4
Message data 11[1 ] MD11 [1] 8 H'F908 HCAN 16 4
Message data 11[2 ] MD11 [2] 8 H'F909 HCAN 16 4
Message data 11[3 ] MD11 [3] 8 H'F90A HCAN 16 4
Message data 11[4 ] MD11 [4] 8 H'F90B HCAN 16 4
Message data 11[5 ] MD11 [5] 8 H'F90C HCAN 16 4
Message data 11[6 ] MD11 [6] 8 H'F90D HCAN 16 4
Message data 11[7 ] MD11 [7] 8 H'F90E HCAN 16 4
Message data 11[8 ] MD11 [8] 8 H'F90F HCAN 16 4
Message data 12[1 ] MD12 [1] 8 H'F910 HCAN 16 4
Message data 12[2 ] MD12 [2] 8 H'F911 HCAN 16 4
Message data 12[3 ] MD12 [3] 8 H'F912 HCAN 16 4
Message data 12[4 ] MD12 [4] 8 H'F913 HCAN 16 4
Message data 12[5 ] MD12 [5] 8 H'F914 HCAN 16 4
Message data 12[6 ] MD12 [6] 8 H'F915 HCAN 16 4
Message data 12[7 ] MD12 [7] 8 H'F916 HCAN 16 4
Message data 12[8 ] MD12 [8] 8 H'F917 HCAN 16 4
Rev. 1.0, 02/02, page 444 of 502
Register Name Abbrevia-
tion Number
of Bits Address*Module
Data
Bus
Width
Number
of Access
States
Message data 13[1 ] MD13 [1] 8 H'F918 HCAN 16 4
Message data 13[2 ] MD13 [2] 8 H'F919 HCAN 16 4
Message data 13[3 ] MD13 [3] 8 H'F91A HCAN 16 4
Message data 13[4 ] MD13 [4] 8 H'F91B HCAN 16 4
Message data 13[5 ] MD13 [5] 8 H'F91C HCAN 16 4
Message data 13[6 ] MD13 [6] 8 H'F91D HCAN 16 4
Message data 13[7 ] MD13 [7] 8 H'F91E HCAN 16 4
Message data 13[8 ] MD13 [8] 8 H'F91F HCAN 16 4
Message data 14[1 ] MD14 [1] 8 H'F920 HCAN 16 4
Message data 14[2 ] MD14 [2] 8 H'F921 HCAN 16 4
Message data 14[3 ] MD14 [3] 8 H'F922 HCAN 16 4
Message data 14[4 ] MD14 [4] 8 H'F923 HCAN 16 4
Message data 14[5 ] MD14 [5] 8 H'F924 HCAN 16 4
Message data 14[6 ] MD14 [6] 8 H'F925 HCAN 16 4
Message data 14[7 ] MD14 [7] 8 H'F926 HCAN 16 4
Message data 14[8 ] MD14 [8] 8 H'F927 HCAN 16 4
Message data 15[1 ] MD15 [1] 8 H'F928 HCAN 16 4
Message data 15[2 ] MD15 [2] 8 H'F929 HCAN 16 4
Message data 15[3 ] MD15 [3] 8 H'F92A HCAN 16 4
Message data 15[4 ] MD15 [4] 8 H'F92B HCAN 16 4
Message data 15[5 ] MD15 [5] 8 H'F92C HCAN 16 4
Message data 15[6 ] MD15 [6] 8 H'F92D HCAN 16 4
Message data 15[7 ] MD15 [7] 8 H'F92E HCAN 16 4
Message data 15[8 ] MD15 [8] 8 H'F92F HCAN 16 4
PWM control register_1 PWCR_1 8 H'FC00 PWM_1 16 4
PWM out put control register_1 PWOCR_18 H'FC02 PWM_1 16 4
PWM polarit y register _1 PWPR_1 8 H'FC04 PWM_1 16 4
PWM cycle register_1 PWCYR_116 H'FC06 PWM_1 16 4
PWM buf fer register_1A PWBFR_1A 16 H'FC08 PWM_1 16 4
PWM buf fer register_1C PWBFR_1C 16 H'FC0A PWM_1 16 4
PWM buf fer register_1E PWBFR_1E 16 H'FC0C PWM_1 16 4
PWM buf fer register_1G PWBFR_1G 16 H'FC0E PWM_1 16 4
Rev. 1.0, 02/02, page 445 of 502
Register Name Abbrevia-
tion Number
of Bits Address*Module
Data
Bus
Width
Number
of Access
States
PWM control register_2 PWCR_2 8 H'FC10 PWM_2 16 4
PWM out put control register_2 PWOCR_28 H'FC12 PWM_2 16 4
PWM polarit y register _2 PWPR_2 8 H'FC14 PWM_2 16 4
PWM cycle register_2 PWCYR_216 H'FC16 PWM_2 16 4
PWM buf fer register_2A PWBFR_2A 16 H'FC18 PWM_2 16 4
PWM buf fer register_2B PWBFR_2B 16 H'FC1A PWM_2 16 4
PWM buf fer register_2C PWBFR_2C 16 H'FC1C PWM_2 16 4
PWM buf fer register_2D PWBFR_2D 16 H'FC1E PWM_2 16 4
Port H dat a direct io n regist er PHDDR 8 H'FC20 PORT 16 4
Port J data direction register PJDDR 8 H'FC21 PORT 16 4
Port H dat a regist er PHDR 8 H'FC24 PORT 1 6 4
Port J dat a register PJDR 8 H'FC25 PORT 16 4
Port H register PORTH 8 H'FC28 PO RT 16 4
Port J regist er PO RTJ 8 H'FC29 PO RT 16 4
Transpor t register TRPRT 8 H'FC2E PORT 8 4
LCD port cont r ol register LPCR 8 H'FC30 LCD 16 4
LCD cont r ol register LCR 8 H'FC31 LCD 16 4
LCD control regist er 2 LCR2 8 H'FC32 LCD 16 4
Module stop control register D MSTPCRD8 H'FC60 SYSTEM 8 4
Standby control register SBYCR 8 H'FDE4 SYSTEM 8 2
Syst em contr ol register SYSCR 8 H'FDE5 SYSTEM 8 2
Syst em clock control r egist er SCKCR 8 H'FDE6 SYSTEM 8 2
Mod e control register MDCR 8 H'FDE7 SYSTEM 8 2
Module stop control register A MSTPCRA8 H'FDE8 SYSTEM 8 2
Module stop control register B MSTPCRB8 H'FDE9 SYSTEM 8 2
Module stop control register C MSTPCRC8 H'FDEA SYSTEM 8 2
Low- po wer control reg ister LPWRCR 8 H'FDEC SYSTEM 8 2
IRQ s ense co ntrol re gister H ISCR H 8 H' FE 12 INT 8 2
IRQ s ense co ntrol re gister L ISCRL 8 H' FE 13 IN T 8 2
IRQ enable register I ER 8 H'FE14 INT 8 2
IRQ status regist er ISR 8 H'FE15 I NT 8 2
Rev. 1.0, 02/02, page 446 of 502
Register Name Abbrevia-
tion Number
of Bits Address*Module
Data
Bus
Width
Number
of Access
States
Port 1 data direct ion register P1DDR 8 H'FE30 PORT 8 2
Port 3 data direct ion register P3DDR 8 H'FE32 PORT 8 2
Port A data direction register PADDR 8 H'FE39 PORT 8 2
Port B data direction register PBDDR 8 H'FE3A PORT 8 2
Port C dat a direct io n regist er PCDDR 8 H'FE3B PORT 8 2
Port D dat a direct io n regist er PDDDR 8 H'FE3C PORT 8 2
Port F data direction register PFDDR 8 H'FE3E PO RT 8 2
Port 3 open drain control register P3ODR 8 H'FE46 PORT 8 2
Port A open drain control register PAODR 8 H'FE47 PORT 8 2
Port B open drain control register PBODR 8 H'FE48 PORT 8 2
Port C open drain control register PCODR 8 H'FE49 PO RT 8 2
Timer start register TSTR 8 H'FEB0 TPU 16 2
Timer synchr o regist er TSYR 8 H'FEB 1 TPU 16 2
Interrupt priority register A IPRA 8 H'FEC0 INT 8 2
Interrupt priority register B IPRB 8 H'FEC1 INT 8 2
Interrupt priority register C IPRC 8 H'FEC2 INT 8 2
Interrupt priority register D IPRD 8 H'FEC3 INT 8 2
Interrupt priority register E IPRE 8 H'FEC4 INT 8 2
Interrupt priority register F IPRF 8 H'FEC5 INT 8 2
Interrupt priority register G IPRG 8 H'FEC6 INT 8 2
Interrupt priority register J IPRJ 8 H'FEC9 INT 8 2
Interrupt priority register K IPRK 8 H'FECA INT 8 2
Interrupt priority register M IPRM 8 H'FECC INT 8 2
RAM emulat ion register RAMER 8 H'FEDB FLASH
(F-ZTAT
version)
82
Port 1 data r egister P1DR 8 H'FF00 PORT 8 2
Port 3 data r egister P3DR 8 H'FF02 PORT 8 2
Port A data regis ter PADR 8 H'FF09 PORT 8 2
Rev. 1.0, 02/02, page 447 of 502
Register Name Abbrevia-
tion Number
of Bits Address*Module
Data
Bus
Width
Number
of Access
States
Port B data regis ter PBDR 8 H'FF0A PORT 8 2
Port C data regist er PCDR 8 H'FF0B PORT 8 2
Port D data regist er PDDR 8 H'FF0C PORT 8 2
Port F data register PFDR 8 H'FF0E PORT 8 2
Timer control register_0 TCR_0 8 H'FF10 TPU_0 16 2
Timer mode register_0 TMDR_0 8 H'FF11 TPU_0 16 2
Timer I/O control register H_0 TIORH_0 8 H'FF12 TPU_0 16 2
Timer I/O control register L_0 TIORL_0 8 H'FF13 TPU_0 16 2
Timer interrupt enable register_0 TIER_0 8 H'FF14 TPU_0 16 2
Timer statu s register_0 TSR_0 8 H'FF15 TPU_0 16 2
Timer co unter H_0 TCNTH_0 8 H'FF16 TPU_ 0 16 2
Timer counter L_0 TCNTL_0 8 H'FF17 TPU_0 16 2
Timer general register AH_0 TGRAH_0 8 H'FF18 TPU_0 16 2
Timer general register AL_0 TGRAL_0 8 H'FF19 TPU_0 16 2
Timer general register BH_0 TGRBH_0 8 H'FF1A TPU_0 16 2
Timer general register BL_0 TGRBL_0 8 H'FF1B TPU_0 16 2
Timer general register CH_0 TGRCH_0 8 H'FF1C TPU_0 16 2
Timer general register CL_0 TG RCL_0 8 H'FF1D TPU_0 16 2
Timer general register DH_0 TGRDH_0 8 H'FF1E TPU_0 16 2
Timer general register DL_0 TG RDL_0 8 H'FF1F TPU_0 16 2
Timer control register_1 TCR_1 8 H'FF20 TPU_1 16 2
Timer mode register_1 TMDR_1 8 H'FF21 TPU_1 16 2
Timer I/O control register_1 TIOR _1 8 H'FF22 TPU_1 16 2
Timer interrupt enable register_1 TIER_1 8 H'FF24 TPU_1 16 2
Timer statu s register_1 TSR_1 8 H'FF25 TPU_1 16 2
Timer co unter H_1 TCNTH_1 8 H'FF26 TPU_ 1 16 2
Timer counter L_1 TCNTL_1 8 H'FF27 TPU_1 16 2
Timer general register AH_1 TGRAH_1 8 H'FF28 TPU_1 16 2
Timer general register AL_1 TGRAL_1 8 H'FF29 TPU_1 16 2
Timer general register BH_1 TGRBH_1 8 H'FF2A TPU_1 16 2
Timer general register BL_1 TGRBL_1 8 H'FF2B TPU_1 16 2
Timer control register_2 TCR_2 8 H'FF30 TPU_2 16 2
Timer mode register_2 TMDR_2 8 H'FF31 TPU_2 16 2
Rev. 1.0, 02/02, page 448 of 502
Register Name Abbrevia-
tion Number
of Bits Address*Module
Data
Bus
Width
Number
of Access
States
Timer I/O control register_2 TIOR _2 8 H'FF32 TPU_2 16 2
Timer interrupt enable register_2 TIER_2 8 H'FF34 TPU_2 16 2
Timer statu s register_2 TSR_2 8 H'FF35 TPU_2 16 2
Timer counterH_2 TCNTH_2 8 H'FF36 TPU_2 16 2
Timer counter L_2 TCNTL_2 8 H'FF37 TPU_2 16 2
Timer general register AH_2 TGRAH_2 8 H'FF38 TPU_2 16 2
Timer general register AL_2 TGRAL_2 8 H'FF39 TPU_2 16 2
Timer general register BH_2 TGRBH_2 8 H'FF3A TPU_2 16 2
Timer general register BL_2 TGRBL_2 8 H'FF3B TPU_2 16 2
Timer control/status regis ter_0 TCSR_0 8 H'FF74 WDT_0 16 2
Timer counter_0 TCNT_0 8 H'FF75 WDT_0 16 2
Reset control /status regis ter RS TCS R 8 H'FF77 WDT_0 16 2
Serial mode registe r_0 SMR_0 8 H'FF78 SCI_0 8 2
Bit rate register_0 BRR_0 8 H'FF79 SCI_0 8 2
Serial control register_0 SCR_0 8 H'FF7A SCI_0 8 2
Transmit data register_0 TDR_0 8 H'FF7B SCI_0 8 2
Serial status r egister_0 SSR_0 8 H'FF7C SCI_0 8 2
Receive dat a register _0 RDR_0 8 H'FF7D SCI_0 8 2
Smart card mode regist er_0 SCMR_0 8 H'FF7E SCI_0 8 2
Serial mode registe r_1 SMR_1 8 H'FF80 SCI_1 8 2
Bit rate register_1 BRR_1 8 H'FF81 SCI_1 8 2
Serial control register_1 SCR_1 8 H'FF82 SCI_1 8 2
Transmit data register_1 TDR_1 8 H'FF83 SCI_1 8 2
Serial status r egister_1 SSR_1 8 H'FF84 SCI_1 8 2
Receive dat a register _1 RDR_1 8 H'FF85 SCI_1 8 2
Smart card mode regist er_1 SCMR_1 8 H'FF86 SCI_1 8 2
A/D data regist er AH ADDRAH 8 H'FF9 0 A/D 8 2
A/D data regist er AL ADDRAL 8 H'FF91 A/D 8 2
A/D data regist er BH ADDRBH 8 H'FF9 2 A/D 8 2
A/D data regist er BL ADDRBL 8 H'FF93 A/D 8 2
A/D data regist er CH ADDRCH 8 H'FF94 A/D 8 2
A/D data regist er CL ADDRCL 8 H'FF95 A/D 8 2
Rev. 1.0, 02/02, page 449 of 502
Register Name Abbrevia-
tion Number
of Bits Address*Module
Data
Bus
Width
Number
of Access
States
A/D data regist er DH ADDRDH 8 H'FF96 A/D 8 2
A/D data regist er DL ADDRDL 8 H'FF97 A/D 8 2
A/D c ontrol/status regist er ADCSR 8 H'FF98 A/ D 8 2
A/D contr ol register ADCR 8 H'FF99 A/D 8 2
Timer control/status regis ter_1 TCSR_1 8 H'FFA2 WDT_1 16 2
Timer counter_1 TCNT_1 8 H'FFA3 WDT_1 16 2
Flash memory control register 1 FLMCR1 8 H'FFA8 FLASH
(F-ZTAT
version)
82
Flash memory control register 2 FLMCR2 8 H'FFA9 FLASH
(F-ZTAT
version)
82
Erase block regist er 1 EBR1 8 H'FFAA FLASH
(F-ZTAT
version)
82
Erase block regist er 2 EBR2 8 H'FFAB FLASH
(F-ZTAT
version)
82
Flash memory power control regist er FLPWCR 8 H'FFAC FLASH
(F-ZTAT
version)
82
Port 1 reg i ster P ORT1 8 H' FFB 0 PORT 8 2
Port 3 reg i ster P ORT3 8 H' FFB 2 PORT 8 2
Port 4 reg i ster P ORT4 8 H' FFB 3 PORT 8 2
Port A register PORTA 8 H'FFB9 PORT 8 2
Port B register PORTB 8 H'FFBA PO RT 8 2
Port C registe r PORTC 8 H'FFBB PORT 8 2
Port D registe r PORTD 8 H'FFBC PORT 8 2
Port F register PORTF 8 H'FFBE PORT 8 2
Note : Lower 16 bits of the address .
20.2 Register Bit s
Register bit names of the on-chip peripheral modu les ar e descr ibed below .
Each line covers eight bits, and 16-bit registers are shown as 2 lines.
Rev. 1.0, 02/02, page 450 of 502
Register
Abbrev. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
MCR MCR7 MCR5 MCR2 MCR1 MCR0 HCAN
GSR GSR3 GSR2 GSR1 GSR0
BCR BCR7 BCR6 BCR5 BCR4 BCR3 BCR2 BCR1 BCR0
BCR15 BCR14 BCR13 BCR12 BCR11 BCR10 BCR9 BCR8
MBCR MBCR7 MBCR6 MBCR5 MBCR4 MBCR3 MBCR2 MBCR1
MBCR15 MBCR14 MBCR13 MBCR12 MBCR11 MBCR10 MBCR9 MBCR8
TXPR TXPR7 TXPR6 TXPR5 TXPR4 TXPR3 TXPR2 TXPR1
TXPR15 TXPR14 TXPR13 TXPR12 TXPR11 TXPR10 TXPR9 TXPR8
TXCR TXCR7 TXCR6 TXCR5 TXCR4 TXCR3 TXCR2 TXCR1
TXCR15 TXCR14 TXCR13 TXCR12 TXCR11 TXCR10 TXCR9 TXCR8
TXACK TXACK7 TXACK6 TXACK5 TXACK4 TXACK3 TXACK2 TXACK1
TXACK15 TXACK14 TXACK13 TXACK12 TXACK11 TXACK10 TXACK9 TXACK8
ABACK ABACK7 ABACK6 ABACK5 ABACK4 ABACK3 ABACK2 ABACK1
ABACK15 ABACK14 ABACK13 ABACK12 ABACK11 ABACK10 ABACK9 ABACK8
RXPR RXPR7 RXPR6 RXPR5 RXPR4 RXPR3 RXPR2 RXPR1 RXPR0
RXPR15 RXPR14 RXPR13 RXPR12 RXPR11 RXPR10 RXPR9 RXPR8
RFPR RFPR7 RFPR6 RFPR5 RFPR4 RFPR3 RFPR2 RFPR1 RFPR0
RFPR15 RFPR14 RFPR13 RFPR12 RFPR11 RFPR10 RFPR9 RFPR8
IRR IRR7 IRR6 IRR5 IRR4 IRR3 IRR2 IRR1 IRR0
IRR12 IRR9 IRR8
MBIMR MBIMR7 MBIMR6 MBIMR5 MBIMR4 MBIMR3 MBIMR2 MBIMR1 MBIMR0
MBIMR15 MBIMR14 MBIMR13 MBIMR12 MBIMR11 MBIMR10 MBIMR9 MBIMR8
IMR IMR7 IMR6 IMR5 IMR4 IMR3 IMR2 IMR1
IMR12 IMR9 IMR8
REC Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
TEC Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
UMSR UMSR7 UMSR6 UMSR5 UMSR4 UMSR3 UMSR2 UMSR1 UMSR0
UMSR15 UMSR14 UMSR13 UMSR12 UMSR11 UMSR10 UMSR9 UMSR8
LAFML LAFML7 LAFML6 LAFML5 LAFML4 LAFML3 LAFML2 LAFML1 LAFML0
LAFML15 LAFML14 LAFML13 LAFML12 LAFML11 LAFML10 LAFML9 LAFML8
Rev. 1.0, 02/02, page 451 of 502
Register
Abbrev. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
LAFMH LAFMH7 LAFMH6 LAFMH5 LAFMH1 LAFMH0 HCAN
LAFMH15 LAFMH14 LAFMH13 LAFMH12 LAFMH11 LAFMH10 LAFMH9 LAFMH8
MC0[1] DLC3 DLC2 DLC1 DLC0
MC0[2]
MC0[3]
MC0[4]
MC0[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16
MC0[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21
MC0[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0
MC0[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8
MC1[1] DLC3 DLC2 DLC1 DLC0
MC1[2]
MC1[3]
MC1[4]
MC1[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16
MC1[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21
MC1[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0
MC1[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8
MC2[1] DLC3 DLC2 DLC1 DLC0
MC2[2]
MC2[3]
MC2[4]
MC2[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16
MC2[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21
MC2[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0
MC2[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8
MC3[1] DLC3 DLC2 DLC1 DLC0
MC3[2]
MC3[3]
MC3[4]
MC3[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16
MC3[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21
MC3[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0
Rev. 1.0, 02/02, page 452 of 502
Register
Abbrev. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
MC3[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8 HCAN
MC4[1] DLC3 DLC2 DLC1 DLC0
MC4[2]
MC4[3]
MC4[4]
MC4[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16
MC4[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21
MC4[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0
MC4[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8
MC5[1] DLC3 DLC2 DLC1 DLC0
MC5[2]
MC5[3]
MC5[4]
MC5[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16
MC5[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21
MC5[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0
MC5[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8
MC6[1] DLC3 DLC2 DLC1 DLC0
MC6[2]
MC6[3]
MC6[4]
MC6[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16
MC6[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21
MC6[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0
MC6[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8
MC7[1] DLC3 DLC2 DLC1 DLC0
MC7[2]
MC7[3]
MC7[4]
MC7[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16
MC7[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21
MC7[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0
MC7[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8
Rev. 1.0, 02/02, page 453 of 502
Register
Abbrev. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
MC8[1] DLC3 DLC2 DLC1 DLC0 HCAN
MC8[2]
MC8[3]
MC8[4]
MC8[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16
MC8[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21
MC8[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0
MC8[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8
MC9[1] DLC3 DLC2 DLC1 DLC0
MC9[2]
MC9[3]
MC9[4]
MC9[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16
MC9[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21
MC9[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0
MC9[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8
MC10[1] DLC3 DLC2 DLC1 DLC0
MC10[2]
MC10[3]
MC10[4]
MC10[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16
MC10[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21
MC10[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0
MC10[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8
MC11[1] DLC3 DLC2 DLC1 DLC0
MC11[2]
MC11[3]
MC11[4]
MC11[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16
MC11[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21
MC11[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0
MC11[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8
Rev. 1.0, 02/02, page 454 of 502
Register
Abbrev. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
MC12[1] DLC3 DLC2 DLC1 DLC0 HCAN
MC12[2]
MC12[3]
MC12[4]
MC12[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16
MC12[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21
MC12[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0
MC12[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8
MC13[1] DLC3 DLC2 DLC1 DLC0
MC13[2]
MC13[3]
MC13[4]
MC13[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16
MC13[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21
MC13[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0
MC13[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8
MC14[1] DLC3 DLC2 DLC1 DLC0
MC14[2]
MC14[3]
MC14[4]
MC14[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16
MC14[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21
MC14[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0
MC14[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8
MC15[1] DLC3 DLC2 DLC1 DLC0
MC15[2]
MC15[3]
MC15[4]
MC15[5] ID-20 ID-19 ID-18 RTR IDE ID-17 ID-16
MC15[6] ID-28 ID-27 ID-26 ID-25 ID-24 ID-23 ID-22 ID-21
MC15[7] ID-7 ID-6 ID-5 ID-4 ID-3 ID-2 ID-1 ID-0
MC15[8] ID-15 ID-14 ID-13 ID-12 ID-11 ID-10 ID-9 ID-8
Rev. 1.0, 02/02, page 455 of 502
Register
Abbrev. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
MD0[1] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 HCAN
MD0[2] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD0[3] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD0[4] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD0[5] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD0[6] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD0[7] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD0[8] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD1[1] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD1[2] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD1[3] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD1[4] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD1[5] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD1[6] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD1[7] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD1[8] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD2[1] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD2[2] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD2[3] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD2[4] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD2[5] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD2[6] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD2[7] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD2[8] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD3[1] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD3[2] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD3[3] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD3[4] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD3[5] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD3[6] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD3[7] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD3[8] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Rev. 1.0, 02/02, page 456 of 502
Register
Abbrev. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
MD4[1] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 HCAN
MD4[2] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD4[3] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD4[4] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD4[5] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD4[6] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD4[7] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD4[8] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD5[1] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD5[2] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD5[3] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD5[4] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD5[5] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD5[6] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD5[7] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD5[8] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD6[1] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD6[2] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD6[3] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD6[4] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD6[5] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD6[6] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD6[7] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD6[8] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD7[1] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD7[2] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD7[3] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD7[4] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD7[5] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD7[6] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD7[7] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD7[8] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Rev. 1.0, 02/02, page 457 of 502
Register
Abbrev. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
MD8[1] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 HCAN
MD8[2] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD8[3] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD8[4] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD8[5] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD8[6] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD8[7] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD8[8] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD9[1] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD9[2] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD9[3] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD9[4] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD9[5] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD9[6] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD9[7] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD9[8] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD10[1] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD10[2] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD10[3] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD10[4] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD10[5] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD10[6] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD10[7] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD10[8] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD11[1] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD11[2] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD11[3] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD11[4] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD11[5] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD11[6] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD11[7] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD11[8] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Rev. 1.0, 02/02, page 458 of 502
Register
Abbrev. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
MD12[1] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 HCAN
MD12[2] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD12[3] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD12[4] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD12[5] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD12[6] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD12[7] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD12[8] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD13[1] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD13[2] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD13[3] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD13[4] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD13[5] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD13[6] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD13[7] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD13[8] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD14[1] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD14[2] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD14[3] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD14[4] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD14[5] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD14[6] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD14[7] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD14[8] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD15[1] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD15[2] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD15[3] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD15[4] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD15[5] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD15[6] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD15[7] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MD15[8] Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Rev. 1.0, 02/02, page 459 of 502
Register
Abbrev. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
PWCR_1 IE CMF CST CKS2 CKS1 CKS0 PWM_1
PWOCR_1 OE1H OE1G OE1F OE1E OE1D OE1C OE1B OE1A
PWPR1_ OPS1H OPS1G OPS1F OPS1E OPS1D OPS1C OPS1B OPS1A
PWCYR_1 Bit 9 Bit 8
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWBFR_1A OTS DT9 DT8
DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0
PWBFR_1C OTS DT9 DT8
DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0
PWBFR_1E OTS DT9 DT8
DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0
PWBFR_1GOTS DT9 DT8
DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0
PWCR_2 IE CMF CST CKS2 CKS1 CKS0 PWM_2
PWOCR_2 OE2H OE2G OE2F OE2E OE2D OE2C OE2B OE2A
PWPR_2 OPS2H OPS2G OPS2F OPS2E OPS2D OPS2C OPS2B OPS2A
PWCYR2 Bit 9 Bit 8
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PWBFR_2A TDS DT9 DT8
DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0
PWBFR_2B TDS DT9 DT8
DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0
PWBFR_2C TDS DT9 DT8
DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0
PWBFR_2D TDS DT9 DT8
DT7 DT6 DT5 DT4 DT3 DT2 DT1 DT0
PHDDR PH7DDR PH6DDR PH5DDR PH4DDR PH3DDR PH2DDR PH1DDR PH0DDR PORT
PJDDR PJ7DDR PJ6DDR PJ5DDR PJ4DDR PJ3DDR PJ2DDR PJ1DDR PJ0DDR
PHDR PH7DR PH6DR PH5DR PH4DR PH3DR PH2DR PH1DR PH0DR
PJDR PJ7DR PJ6DR PJ5DR PJ4DR PJ3DR PJ2DR PJ1DR PJ0DR
PORTH PH7 PH6 PH5 PH4 PH3 PH2 PH1 PH0
PORTJ PJ7 PJ6 PJ5 PJ4 PJ3 PJ2 PJ1 PJ0
TRPRT TRPB TRPA
Rev. 1.0, 02/02, page 460 of 502
Register
Abbrev. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
LPCR DTS1 DTS0 CMX SGS3 SGS2 SGS1 SGS0 LCD
LCR PSW ACT DISP CKS3 CKS2 CKS1 CKS0
LCR2 LCDAB
MSTPCRD MSTPD7 MSTPD6 SYSTEM
SBYCR SSBY STS2 STS1 STS0
SYSCR INTM1 INTM0 NMIEG RAME
SCKCR PSTOP STCS SCK2 SCK1 SCK0
MDCR MDS2 MDS0
MSTPCRA MSTPA7 MSTPA6 MSTPA5 MSTPA4 MSTPA3 MSTPA2 MSTPA1 MSTPA0
MSTPCRB MSTPB7 MSTPB6 MSTPB5 MSTPB4 MSTPB3 MSTPB2 MSTPB1 MSTPB0
MSTPCRC MSTPC7 MSTPC6 MSTPC5 MSTPC4 MSTPC3 MSTPC2 MSTPC1 MSTPC0
LPWRCR DTON LSON SUBSTP RFCUT STC1 STC0
ISCRH IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA INT
ISCRL IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA
IER IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E
ISR IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F
P1DDR P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR PORT
P3DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR
PADDR PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR
PBDDR PB7DDR PB6DDR PB5DDR PB4DDR PB3DDR PB2DDR PB1DDR PB0DDR
PCDDR PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR
PDDDR PD7DDR PD6DDR PD5DDR PD4DDR
PFDDR PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR
P3ODR P35ODR P34ODR P33ODR P32ODR P31ODR P30ODR
PAODR PA7ODR PA6ODR PA5ODR PA4ODR PA3ODR PA2ODR PA1ODR PA0ODR
PBODR PB7ODR PB6ODR PB5ODR PB4ODR PB3ODR PB2ODR PB1ODR PB0ODR
PCODR PC7ODR PC6ODR PC5ODR PC4ODR PC3ODR PC2ODR PC1ODR PC0ODR
TSTR CST2 CST1 CST0 TPU
TSYR SYNC2 SYNC1 SYNC0 common
Rev. 1.0, 02/02, page 461 of 502
Register
Abbrev. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
IPRA IPR6 IPR5 IPR4 IPR2 IPR1 IPR0 INT
IPRB IPR6 IPR5 IPR4 IPR2 IPR1 IPR0
IPRC IPR6 IPR5 IPR4 IPR2 IPR1 IPR0
IPRD IPR6 IPR5 IPR4 IPR2 IPR1 IPR0
IPRE IPR6 IPR5 IPR4 IPR2 IPR1 IPR0
IPRF IPR6 IPR5 IPR4 IPR2 IPR1 IPR0
IPRG IPR6 IPR5 IPR4 IPR2 IPR1 IPR0
IPRJ IPR6 IPR5 IPR4 IPR2 IPR1 IPR0
IPRK IPR6 IPR5 IPR4 IPR2 IPR1 IPR0
IPRM IPR6 IPR5 IPR4 IPR2 IPR1 IPR0
RAMER RAMS RAM2 RAM1 RAM0 FLASH
(F-ZTAT
version)
P1DR P17DR P16DR P15DR P14DR P13DR P12DR P11DR P10DR PORT
P3DR P35DR P34DR P33DR P32DR P31DR P30DR
PADR PA7DR PA6DR PA5DR PA4DR PA3DR PA2DR PA1DR PA0DR
PBDR PB7DR PB6DR PB5DR PB4DR PB3DR PB2DR PB1DR PB0DR
PCDR PC7DR PC6DR PC5DR PC4DR PC3DR PC2DR PC1DR PC0DR
PDDR PD7DR PD6DR PD5DR PD4DR
PFDR PF6DR PF5DR PF4DR PF3DR PF2DR
TCR_0 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU_0
TMDR_0 BFB BFA MD3 MD2 MD1 MD0
TIORH_0 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0
TIORL_0 IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0
TIER_0 TTGE TCIEV TGIED TGIEC TGIEB TGIEA
TSR_0 TCFV TGFD TGFC TGFB TGFA
TCNTH_0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
TCNTL_0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
TGRAH_0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
TGRAL_0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
TGRBH_0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
TGRBL_0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
TGRCH_0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
TGRCL_0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Rev. 1.0, 02/02, page 462 of 502
Register
Abbrev. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
TGRDH_0 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8 TPU_0
TGRDL_0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
TCR_1 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU_1
TMDR_1 MD3 MD2 MD1 MD0
TIOR_1 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0
TIER_1 TTGE TCIEU TCIEV TGIEB TGIEA
TSR_1 TCFD TCFU TCFV TGFB TGFA
TCNTH_1 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
TCNTL_1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
TGRAH_1 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
TGRAL_1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
TGRBH_1 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
TGRBL_1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
TCR_2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 TPSC0 TPU_2
TMDR_2 MD3 MD2 MD1 MD0
TIOR_2 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0
TIER_2 TTGE TCIEU TCIEV TGIEB TGIEA
TSR_2 TCFD TCFU TCFV TGFB TGFA
TCNTH_2 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
TCNTL_2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
TGRAH_2 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
TGRAL_2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
TGRBH_2 Bit15 Bit14 Bit13 Bit12 Bit11 Bit10 Bit9 Bit8
TGRBL_2 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
TCSR_0 OVF WT/
,7
TME CKS2 CKS1 CKS0 WDT_0
TCNT_0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
RSTCSR WOVF RSTE RSTS
SMR_0*3C/
$
CHR PE O/
(
STOP MP CKS1 CKS0 SCI_0
(GM) (BLK) (PE) (O/
(
) (BCP1) (BCP0) (CKS1) (CKS0)
BRR_0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SCR_0 TIE RIE TE RE MPIE TEIE CKE1 CKE0
TDR_0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
Rev. 1.0, 02/02, page 463 of 502
Register
Abbrev. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
SSR_0*3TDRE RDRF ORER FER PER TEND MPB MPBT SCI_0
(TDRE) (RDRF) (ORER) (ERS) (PER) (TEND) (MPB) (MPBT)
RDR_0 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SCMR_0 SDIR SINV SMIF
SMR_1*3C/
$
CHR PE O/
(
STOP MP CKS1 CKS0 SCI_1
(GM) (BLK) (PE) (O/
(
) (BCP1) (BCP0) (CKS1) (CKS0)
BRR_1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SCR_1 TIE RIE TE RE MPIE TEIE CKE1 CKE0
TDR_1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SSR_1*3TDRE RDRF ORER FER PER TEND MPB MPBT
(TDRE) (RDRF) (ORER) (ERS) (PER) (TEND) (MPB) (MPBT)
RDR_1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
SCMR_1 SDIR SINV SMIF
ADDRAH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 A/D
ADDRAL AD1 AD0
ADDRBH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
ADDRBL AD1 AD0
ADDRCH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
ADDRCL AD1 AD0
ADDRDH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
ADDRDL AD1 AD0
ADCSR ADF ADIE ADST SCAN CH2 CH1 CH0
ADCR TRGS1 TRGS0 CKS1 CKS0
TCSR_1 OVF WT/
,7
TME PSS RST/
10,
CKS2 CKS1 CKS0 WDT_1
TCNT_1 Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
FLMCR1 FWE SWE ESU PSU EV PV E P
FLMCR2 FLER
EBR1 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0
EBR2 EB9 EB8
FLPWCR PDWND
FLASH
(F-ZTAT
version)
Rev. 1.0, 02/02, page 464 of 502
Register
Abbrev. Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
PORT1 P17 P16 P15 P14 P13 P12 P11 P10 PORT
PORT3 P35 P34 P33 P32 P31 P30
PORT4 P47 P46 P45 P44 P43 P42 P41 P40
PORTA PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
PORTB PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0
PORTC PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
PORTD PD7 PD6 PD5 PD4
PORTF PF7 PF6 PF5 PF4 PF3 PF2
Notes: 1. For buffer operation.
2 . For free oper ation.
3. Some bit functions differ in normal serial communication interface mode and Smart Card interface
m ode. The bit functions in Sm art Card interface mode are encl osed in parentheses.
Rev. 1.0, 02/02, page 465 of 502
20.3 Register S t at es in Each Operat in g Mode
Register
Abbrev. Reset
High-
Speed
Medium
-Speed Sleep
Module
Stop Watch Subactive Subsleep
Software
Standby
Hardware
Standby Module
MCR Initialized Initialized Initialized Initialized Initialized Initialized Initialized HCAN
GSR Initialized Initialized Initialized Initialized Initialized Initialized Initialized
BCR Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MBCR Initialized Initialized Initialized Initialized Initialized Initialized Initialized
TXPR Initialized Initialized Initialized Initialized Initialized Initialized Initialized
TXCR Initialized Initialized Initialized Initialized Initialized Initialized Initialized
TXACK Initialized Initialized Initialized Initialized Initialized Initialized Initialized
ABACK Initialized Initialized Initialized Initialized Initialized Initialized Initialized
RXPR Initialized Initialized Initialized Initialized Initialized Initialized Initialized
RFPR Initialized Initialized Initialized Initialized Initialized Initialized Initialized
IRR Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MBIMR Initialized Initialized Initialized Initialized Initialized Initialized Initialized
IMR Initialized Initialized Initialized Initialized Initialized Initialized Initialized
REC Initialized Initialized Initialized Initialized Initialized Initialized Initialized
TEC Initialized Initialized Initialized Initialized Initialized Initialized Initialized
UMSR Initialized Initialized Initialized Initialized Initialized Initialized Initialized
LAFML Initialized Initialized Initialized Initialized Initialized Initialized Initialized
LAFMH Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC0[1] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC0[2] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC0[3] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC0[4] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC0[5] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC0[6] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC0[7] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC0[8] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC1[1] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC1[2] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC1[3] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC1[4] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC1[5] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC1[6] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Rev. 1.0, 02/02, page 466 of 502
Register
Abbrev. Reset
High-
Speed
Medium
-Speed Sleep
Module
Stop Watch Subactive Subsleep
Software
Standby
Hardware
Standby Module
MC1[7] Initialized Initialized Initialized Initialized Initialized Initialized Initialized HCAN
MC1[8] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC2[1] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC2[2] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC2[3] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC2[4] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC2[5] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC2[6] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC2[7] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC2[8] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC3[1] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC3[2] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC3[3] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC3[4] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC3[5] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC3[6] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC3[7] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC3[8] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC4[1] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC4[2] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC4[3] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC4[4] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC4[5] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC4[6] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC4[7] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC4[8] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC5[1] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC5[2] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC5[3] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC5[4] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC5[5] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC5[6] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC5[7] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC5[8] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Rev. 1.0, 02/02, page 467 of 502
Register
Abbrev. Reset
High-
Speed
Medium
-Speed Sleep
Module
Stop Watch Subactive Subsleep
Software
Standby
Hardware
Standby Module
MC6[1] Initialized Initialized Initialized Initialized Initialized Initialized Initialized HCAN
MC6[2] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC6[3] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC6[4] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC6[5] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC6[6] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC6[7] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC6[8] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC7[1] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC7[2] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC7[3] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC7[4] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC7[5] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC7[6] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC7[7] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC7[8] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC8[1] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC8[2] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC8[3] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC8[4] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC8[5] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC8[6] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC8[7] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC8[8] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC9[1] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC9[2] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC9[3] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC9[4] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC9[5] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC9[6] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC9[7] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC9[8] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC10[1] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC10[2] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
Rev. 1.0, 02/02, page 468 of 502
Register
Abbrev. Reset
High-
Speed
Medium
-Speed Sleep
Module
Stop Watch Subactive Subsleep
Software
Standby
Hardware
Standby Module
MC10[3] Initialized Initialized Initialized Initialized Initialized Initialized Initialized HCAN
MC10[4] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC10[5] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC10[6] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC10[7] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC10[8] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC11[1] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC11[2] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC11[3] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC11[4] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC11[5] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC11[6] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC11[7] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC11[8] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC12[1] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC12[2] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC12[3] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC12[4] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC12[5] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC12[6] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC12[7] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC12[8] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC13[1] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC13[2] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC13[3] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC13[4] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC13[5] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC13[6] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC13[7] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC13[8] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC14[1] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC14[2] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC14[3] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC14[4] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
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Register
Abbrev. Reset
High-
Speed
Medium
-Speed Sleep
Module
Stop Watch Subactive Subsleep
Software
Standby
Hardware
Standby Module
MC14[5] Initialized Initialized Initialized Initialized Initialized Initialized Initialized HCAN
MC14[6] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC14[7] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC14[8] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC15[1] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC15[2] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC15[3] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC15[4] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC15[5] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC15[6] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC15[7] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MC15[8] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD0[1] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD0[2] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD0[3] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD0[4] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD0[5] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD0[6] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD0[7] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD0[8] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD1[1] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD1[2] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD1[3] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD1[4] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD1[5] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD1[6] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD1[7] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD1[8] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD2[1] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD2[2] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD2[3] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD2[4] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD2[5] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD2[6] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
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Abbrev. Reset
High-
Speed
Medium
-Speed Sleep
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Stop Watch Subactive Subsleep
Software
Standby
Hardware
Standby Module
MD2[7] Initialized Initialized Initialized Initialized Initialized Initialized Initialized HCAN
MD2[8] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD3[1] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD3[2] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD3[3] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD3[4] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD3[5] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD3[6] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD3[7] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD3[8] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD4[1] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD4[2] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD4[3] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD4[4] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD4[5] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD4[6] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD4[7] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD4[8] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD5[1] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD5[2] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD5[3] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD5[4] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD5[5] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD5[6] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD5[7] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD5[8] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD6[1] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD6[2] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD6[3] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD6[4] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD6[5] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD6[6] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD6[7] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD6[8] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
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Register
Abbrev. Reset
High-
Speed
Medium
-Speed Sleep
Module
Stop Watch Subactive Subsleep
Software
Standby
Hardware
Standby Module
MD7[1] Initialized Initialized Initialized Initialized Initialized Initialized Initialized HCAN
MD7[2] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD7[3] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD7[4] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD7[5] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD7[6] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD7[7] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD7[8] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD8[1] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD8[2] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD8[3] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD8[4] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD8[5] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD8[6] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD8[7] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD8[8] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD9[1] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD9[2] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD9[3] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD9[4] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD9[5] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD9[6] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD9[7] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD9[8] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD10[1] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD10[2] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD10[3] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD10[4] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD10[5] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD10[6] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD10[7] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD10[8] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD11[1] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD11[2] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
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Register
Abbrev. Reset
High-
Speed
Medium
-Speed Sleep
Module
Stop Watch Subactive Subsleep
Software
Standby
Hardware
Standby Module
MD11[3] Initialized Initialized Initialized Initialized Initialized Initialized Initialized HCAN
MD11[4] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD11[5] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD11[6] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD11[7] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD11[8] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD12[1] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD12[2] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD12[3] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD12[4] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD12[5] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD12[6] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD12[7] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD12[8] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD13[1] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD13[2] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD13[3] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD13[4] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD13[5] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD13[6] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD13[7] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD13[8] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD14[1] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD14[2] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD14[3] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD14[4] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD14[5] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD14[6] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD14[7] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD14[8] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD15[1] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD15[2] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD15[3] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD15[4] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
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Abbrev. Reset
High-
Speed
Medium
-Speed Sleep
Module
Stop Watch Subactive Subsleep
Software
Standby
Hardware
Standby Module
MD15[5] Initialized Initialized Initialized Initialized Initialized Initialized Initialized HCAN
MD15[6] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD15[7] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
MD15[8] Initialized Initialized Initialized Initialized Initialized Initialized Initialized
PWCR_1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized PWM_1
PWOCR_1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized
PWPR_1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized
PWCYR_1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized
PWBFR_1A Initialized Initialized Initialized Initialized Initialized Initialized Initialized
PWBFR_1C Initialized Initialized Initialized Initialized Initialized Initialized Initialized
PWBFR_1E Initialized Initialized Initialized Initialized Initialized Initialized Initialized
PWBFR_1G Initialized Initialized Initialized Initialized Initialized Initialized Initialized
PWCR_2 Initialized Initialized Initialized Initialized Initialized Initialized Initialized PWM_2
PWOCR_2 Initialized Initialized Initialized Initialized Initialized Initialized Initialized
PWPR_2 Initialized Initialized Initialized Initialized Initialized Initialized Initialized
PWCYR_2 Initialized Initialized Initialized Initialized Initialized Initialized Initialized
PWBFR_2A Initialized Initialized Initialized Initialized Initialized Initialized Initialized
PWBFR_2B Initialized Initialized Initialized Initialized Initialized Initialized Initialized
PWBFR_2C Initialized Initialized Initialized Initialized Initialized Initialized Initialized
PWBFR_2D Initialized Initialized Initialized Initialized Initialized Initialized Initialized
PHDDR Initialized PORT
PJDDR Initialized
PHDR Initialized
PJDR Initialized
PORTH Initialized
PORTJ Initialized
TRPRT Initialized
LPCR Initialized Initialized LCD
LCR Initialized Initialized
LCR2 Initialized Initialized
MSTPCRD Initialized SYSTEM
SBYCR Initialized
SYSCR Initialized
SCKCR Initialized
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Abbrev. Reset
High-
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Medium
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Standby
Hardware
Standby Module
MDCR Initialized SYSTEM
MSTPCRA Initialized
MSTPCRB Initialized
MSTPCRC Initialized
LPWRCR Initialized
ISCRH Initialized Initialized INT
ISCRL Initialized Initialized
IER Initialized Initialized
ISR Initialized Initialized
P1DDR Initialized PORT
P3DDR Initialized
PADDR Initialized
PBDDR Initialized
PCDDR Initialized
PDDDR Initialized
PFDDR Initialized
P3ODR Initialized
PAODR Initialized
PBODR Initialized
PCODR Initialized
TSTR Initialized Initialized TPU
TSYR Initialized Initialized
IPRA Initialized Initialized INT
IPRB Initialized Initialized
IPRC Initialized Initialized
IPRD Initialized Initialized
IPRE Initialized Initialized
IPRF Initialized Initialized
IPRG Initialized Initialized
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Abbrev. Reset
High-
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Medium
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Hardware
Standby Module
IPRJ Initialized Initialized INT
IPRK Initialized Initialized
IPRM Initialized Initialized
RAMER Initialized Initialized FLASH
(F-ZTAT
version)
P1DR Initialized PORT
P3DR Initialized
PADR Initialized
PBDR Initialized
PCDR Initialized
PDDR Initialized
PFDR Initialized
TCR_0 Initialized Initialized TPU_0
TMDR_0 Initialized Initialized
TIORH_0 Initialized Initialized
TIORL_0 Initialized Initialized
TIER_0 Initialized Initialized
TSR_0 Initialized Initialized
TCNTH_0 Initialized Initialized
TCNTL_0 Initialized Initialized
TGRAH_0 Initialized Initialized
TGRAL_0 Initialized Initialized
TGRBH_0 Initialized Initialized
TGRBL_0 Initialized Initialized
TGRCH_0 Initialized Initialized
TGRCL_0 Initialized Initialized
TGRDH_0 Initialized Initialized
TGRDL_0 Initialized Initialized
TCR_1 Initialized Initialized TPU_1
TMDR_1 Initialized Initialized
TIOR_1 Initialized Initialized
TIER_1 Initialized Initialized
TSR_1 Initialized Initialized
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Abbrev. Reset
High-
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TCNTH_1 Initialized Initialized TPU_1
TCNTL_1 Initialized Initialized
TGRAH_1 Initialized Initialized
TGRAL_1 Initialized Initialized
TIOR_2 Initialized Initialized
TIER_2 Initialized Initialized
TSR_2 Initialized Initialized
TCNTH_2 Initialized Initialized
TCNTL_2 Initialized Initialized
TGRAH_2 Initialized Initialized
TGRAL_2 Initialized Initialized
TGRBH_2 Initialized Initialized
TGRBL_2 Initialized Initialized
TCSR_0 Initialized Initialized WDT_0
TCNT_0 Initialized Initialized
RSTCSR Initialized Initialized
SMR_0 Initialized Initialized Initialized Initialized Initialized Initialized Initialized SCI_0
BRR_0 Initialized Initialized Initialized Initialized Initialized Initialized Initialized
SCR_0 Initialized Initialized Initialized Initialized Initialized Initialized Initialized
TDR_0 Initialized Initialized Initialized Initialized Initialized Initialized Initialized
SSR_0 Initialized Initialized Initialized Initialized Initialized Initialized Initialized
RDR_0 Initialized Initialized Initialized Initialized Initialized Initialized Initialized
SCMR_0 Initialized Initialized Initialized Initialized Initialized Initialized Initialized
SMR_1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized SCI_1
BRR_1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized
SCR_1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized
TDR_1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized
SSR_1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized
RDR_1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized
SCMR_1 Initialized Initialized Initialized Initialized Initialized Initialized Initialized
ADDRAH Initialized Initialized Initialized Initialized Initialized Initialized Initialized A/D
ADDRAL Initialized Initialized Initialized Initialized Initialized Initialized Initialized
ADDRBH Initialized Initialized Initialized Initialized Initialized Initialized Initialized
ADDRBL Initialized Initialized Initialized Initialized Initialized Initialized Initialized
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Abbrev. Reset
High-
Speed
Medium
-Speed Sleep
Module
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Software
Standby
Hardware
Standby Module
ADDRCH Initialized Initialized Initialized Initialized Initialized Initialized Initialized A/D
ADDRCL Initialized Initialized Initialized Initialized Initialized Initialized Initialized
ADDRDH Initialized Initialized Initialized Initialized Initialized Initialized Initialized
ADDRDL Initialized Initialized Initialized Initialized Initialized Initialized Initialized
ADCSR Initialized Initialized Initialized Initialized Initialized Initialized Initialized
ADCR Initialized Initialized Initialized Initialized Initialized Initialized Initialized
TCSR_1 Initialized Initialized WDT_1
TCNT_1 Initialized Initialized
FLMCR1 Initialized Initialized
FLMCR2 Initialized Initialized
EBR1 Initialized Initialized
EBR2 Initialized Initialized
FLPWCR Initialized Initialized
FLASH
(F-ZTAT
version)
PORT1 Initialized PORT
PORT3 Initialized
PORT4 Initialized
PORTA Initialized
PORTB Initialized
PORTC Initialized
PORTD Initialized
PORTF Initialized
Note: is not initialized.
Rev. 1.0, 02/02, page 478 of 502
Rev. 1.0, 02/02, page 479 of 502
Section 21 Electrical Characteristics (Preliminary)
21.1 Absolute Maximum Ratings
Table 21.1 lists the absolute maximum ratings.
Tabl e 2 1.1 Absolute Maximum Rat i ng s
Item Symbol Value Unit
Power supply voltage VCC, LP VCC –0.3 to +7.0 V
PWMVCC –0.3 to +7.0 V
Input voltage (XTAL, EXTAL) Vin –0.3 to VCC + 0.3 V
Input voltage (port 4) Vin –0. 3 to AVCC +0.3 V
Input voltage (except XTAL,
EXTAL, and port 4) Vin –0.3 to VCC +0.3 V
Input voltage (port s H and J) Vin –0.3 to PW M VCC +0.3 V
Analog power supply voltage AVCC –0.3 to +7.0 V
Analog input voltage VAN –0.3 to AVCC +0.3 V
Operating temperature Topr Regular specifica tions : –20 to +75 °C
Wide-range specifications: –40 to +85 °C
Storage tempe rature Tstg –55 to +125 °C
Caution: Permanent damage to this LSI may result if absolute m aximum rating ar e exceeded.
Rev. 1.0, 02/02, page 480 of 502
21.2 DC Characteristics
Table 21.2 lists the DC characteristics. Table 21.3 lists the permissible output currents.
Table 21.2 DC Characteristics
Conditions: VCC = LPV CC = 4. 5 V to 5.5 V , AV CC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V,
VSS = AVSS = PWMVSS = PLLVSS = 0 V, T a = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-r ange spec ifi cations)*1
Item Symbol Min Typ Max Unit Test
Conditions
VT–VCC × 0.2——V
VT+——V
CC × 0.7 V
Schmitt trigger
input voltage
,54
to
,54
,
ports 1, 3, A to
D, F, H, J VT+ – V T–VCC × 0.05——V
Input high
voltage
5(6
,
67%<
,
NMI,
MD2 , MD0,
FWE
VIH VCC × 0.9 — VCC + 0.3 V
EXTAL VCC × 0.7 — VCC + 0.3 V
SCK0, SCK1,
RxD0, RxD1,
HRxD
VCC × 0.7 — V CC + 0.3 V
Port 4 AVCC × 0.7 — A VCC + 0.3 V
Input low
voltage
5(6
,
67%<
,
NMI,
MD2 , MD0,
FWE
VIL –0.3 — VCC × 0.1 V
EXTAL –0.3 — VCC × 0.2 V
SCK0, SCK1,
RxD0, RxD1,
HRxD
–0.3 — VCC × 0.2 V
Port 4 –0. 3 — AVCC × 0.2 V
Output high All output pins VOH VCC – 0.5——VI
OH = –200 µA
voltage VCC – 1.0——VI
OH = –1 mA
Output low
voltage All output pins VOL ——0.4VI
OL = 1.6 mA
Input leakage
5(6
| Iin |— — 1.0 µAV
in = 0.5 t o
current
67%<
, NMI,
MD2 , MD0,
FWE, HRxD
——1.0µAV
CC – 0.5 V
Port 4 — — 1.0 µA Vin = 0.5 to
AVCC – 0.5 V
Rev. 1.0, 02/02, page 481 of 502
Item Symbol Min Typ Max Unit Test
Conditions
Input
5(6
Cin — — 30 pF Vin = 0 V
capacitance NMI — — 30 pF f = 1 MHz
All input pins
except
5(6
and NMI
— — 15 pF Ta = 25°C
Current
dissipation*2Normal
operation ICC*3—TBD
(VCC = 5. 0
V)
TBD
(VCC = 5. 5
V)
mA f = 20 MHz
Sleep mode — TBD
(VCC = 5. 0
V)
TBD
(VCC = 5. 5
V)
mA f = 20 MHz
All modules
stopped —TBD—mAf = 20 MHz,
VCC = 5.0 V
(reference
values)
Medium-
speed mode
(ø/32)
—TBD—mAf = 20 MHz,
VCC = 5.0 V
(reference
values)
Subactive
mode TBD TBD TBD mA Using the
subclock
Subsleep
mode TBD TBD TBD mA
Watch mode TBD TBD TBD mA
Standby — TBD TBD µA Ta ≤ 50 °C
mode — — TBD µA 50°C < Ta
Operating LPICC —TBDTBDmA
—TBDTBDµAT
a ≤ 50° C
LCD power-
supply port
power supply
current
In standby
mode — — TBD µA 50°C < Ta
During A/D
conversion AlCC —TBDTBDmAAV
CC = 5.0 V
Analog
power supply
current Idle — — TBD µA
RAM standby voltage VRAM 2.0——V
Rev. 1.0, 02/02, page 482 of 502
Notes: 1. I f the A/ D conver ter is not used, do not leave the AVCC and AVSS pins open. Apply a
voltage bet ween 4.5 V and 5.5 V t o the AVCC pin by conne cting them to VCC, for
instance.
2. C urrent dis sip ation val ues are for VIH = VCC (EXTAL), AVCC (port 4), PWMVCC, LPVCC, or
VCC (other), and VIL = 0 V, with all output pins unloaded.
3. ICC depends on VCC and f as follows:
ICC max = TBD ( normal oper a t ion)
ICC max = TBD ( sleep mode)
Tabl e 21. 3 Per m i ssi ble Out put Curre nt s
Conditions: VCC = LPV CC = 4. 5 V to 5.5 V , AV CC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V,
VSS = AVSS = PWMVSS = PLLVSS = 0 V, T a = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-r ange spec ifi cations)*1
It em Test Conditions Symbol Mi n Typ Max Unit
All output pins except
PWM1A to 1H and
PWM2A to 2H
IOL ——TBDmA
Ta = 75 to 85°C I OL ——TBDmA
Ta = 25°C — — TBD mA
Permissible
output low
current (per
pin) PWM1A to 1H,
PWM2A to 2H
Ta = –40°C — — TBD m A
Total of all out put pins
except PWM1A to 1H
and PWM2A to 2H
ΣIOL ——TBDmA
Ta = 75 to 85°C ΣIOL ——TBDmA
Ta = 25°C — — TBD mA
Permissible
output low
current (total)
Total of PWM1A to 1H
and PWM2A to 2H
Ta = –40°C — — TBD m A
All output pins except
PWM1A to 1H and
PWM2A to 2H
–IOH ——TBDmA
Ta = 75 to 85°C –I OH ——TBDmA
Ta = 25°C — — TBD mA
Permissible
output high
current (per
pin) PWM1A to 1H,
PWM2A to 2H
Ta = –40°C — — TBD m A
Total of all out put pins
except PWM1A to 1H
and PWM2A to 2H
Σ–IOH ——TBDmA
Ta = 75 to 85°C Σ–IOH ——TBDmA
Ta = 25°C — — TBD mA
Permissible
output high
current (total)
Total of PWM1A to 1H
and PWM2A to 2H
Ta = –40°C — — TBD m A
Not e : T o p ro tect chip re lia b ility, d o not exce ed the out put c urrent valu es in ta ble 21.3.
Rev. 1.0, 02/02, page 483 of 502
21.3 AC Characteristics
Figure 21.1 shows the test conditions for the AC characteristics.
5 V
R
L
R
H
C
LSI output pin
C = 30pF: All ports
R
L
= 2.4 kΩ
R
H
= 12 Ω
Input/output timing measurement levels
• Low level : 0.8 V
• High level : 2.0 V
Figure 21.1 Output Load Cir cuit
21.3.1 Clock Timing
Table 21.4 lists the clock timing
Table 21. 4 Clock Timi ng
Conditions : VCC = LPV CC = 4.5 V to 5.5 V, AVCC = 4.5 V t o 5.5 V, PWMVCC = 4.5 V to 5.5 V,
VSS = AVSS = PWMVSS = PLLVSS = 0 V, φ = 4 MHz to 20 MHz,
Ta = –20°C to + 75°C (regular specific ations), Ta = –40°C to +85°C (wide-range
specifications)
It em Symbol Min Max Unit Test Conditions
Clock cycle time t cyc 50 250 ns Figure 21.2
Clock high pulse width tCH 15 — ns
Clock lo w p ul se width tCL 15 — ns
Clock rise time tCr —5 ns
Clock fa ll time tCf —5 ns
Os c illa tion stabiliz a tion time at
reset (c ry stal) tOSC1 20 — ms Figure 21.3
Os c illa tion stabiliz a tion time in
software standby (crystal) tOSC2 8 — ms Figure 19.3
External clock output
st a biliz a tion delay t ime tDEXT 2 — m s Figure 21.3
Rev. 1.0, 02/02, page 484 of 502
t
Cr
t
CL
t
Cf
t
CH
φ
t
cyc
Fi g ure 21.2 System Clock Timing
t
OSC1
t
OSC1
EXTAL
V
CC
φ
t
DEXT
t
DEXT
Figure 21.3 Oscillation Stabilization Timing
Rev. 1.0, 02/02, page 485 of 502
21.3.2 Control Si gnal Timing
Table 21.5 lists the control signal timing.
Tabl e 21. 5 Control Sig nal Timing
Conditions: VCC = LPV CC = 4. 5 V to 5.5 V , AV CC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V,
VSS = AVSS = PWMVSS = PLLVSS = 0 V, φ = 4 MHz to 20 MHz,
Ta = –20°C to + 75°C (regular specific ations), Ta = –40°C to +85°C (wide-range
specifications)
It em Symbol Min Max Unit Test Conditions
5(6
setup t ime tRESS 200 — ns Figure 21.4
5(6
pulse width tRESW 20 — tcyc
NMI setup time tNMIS 150 — ns Figure 21.5
NMI hold t ime tNMIH 10 — ns
NMI pulse width (exiting
software standby mode) tNMIW 200 — ns
,54
setup time tIRQS 150 — ns
,54
hold time tIRQH 10 — ns
,54
pulse width (exiting
software standby mode) tIRQW 200 — ns
t
RESW
t
RESS
φ
t
RESS
Fi g ure 21.4 Rese t Input Timing
Rev. 1.0, 02/02, page 486 of 502
φ
t
IRQS
Edge input
t
IRQH
t
NMIS
t
NMIH
t
IRQS
Level input
NMI
t
NMIW
t
IRQW
Fi g ure 21.5 Interrupt Input Tim i ng
Rev. 1.0, 02/02, page 487 of 502
21. 3. 3 T i m i ng of On-Chip Supporting Module s
Table 21. 6 lists the timing of on-chip supporting modules.
Tabl e 21. 6 Ti m i ng of On-Chip Suppor ting Module s
Conditions : VCC = LPV CC = 4.5 V to 5.5 V, AVCC = 4.5 V t o 5.5 V, PWMVCC = 4.5 V to 5.5 V,
VSS = AVSS = PWMVSS = PLLVSS = 0 V, φ = 4 MHz to 20 MHz,
Ta = –20°C to + 75°C (regular specific ations), Ta = –40°C to +85°C (wide-range
specifications)
It em Symbol Mi n M ax Unit Test Conditions
I/O port Output dat a delay
time tPWD — 50 ns Figure 21.6
Input data setup time tPRS 30 —
Input data hold time tPRH 30 —
TPU Timer output delay
time tTOCD — 50 ns Figure 21. 7
Timer input setup
time tTICS 30 —
Timer clock input
setup time tTCKS 30 — ns Figure 21.8
Timer
clock Single
edge tTCKWH 1.5 — tcyc
pulse
width Both
edges tTCKWL 2.5 —
SCI Input
clock Asynchro-
nous tScyc 4—t
cyc Figur e 21.9
cycle Synchro-
nous 6—
Input clock pulse
width tSCKW 0.4 0.6 tScyc
Input clock rise t ime t SCKr —1.5t
cyc
Input clock fall time tSCKf —1.5
Transmit data delay
time tTXD — 50 ns Figure 21.10
Receive data setup
time (synchronous) tRXS 50 —
Receive dat a hold
time (synchronous) tRXH 50 —
Rev. 1.0, 02/02, page 488 of 502
It em Symbol Mi n M ax Unit Test Conditions
A/D
converter Trigger input setup
time tTRGS 30 — ns Figure 21.11
HCAN*Transmit data delay
time tHTXD — 100 ns Figure 21.12
Transmit data setup
time tHRXS 100 —
Transmit data hold
time tHRXH 100 —
PWM Pulse output delay
time tMPWMOD — TBD ns Figure 21.13
Note: *The HCAN input signal is asynchronous. However, its state is judged to have changed at
the rising-edge (two clock cycles) of the system clock signal (ø) shown in figure 21.12. The
HCAN output signal is also asynchronous. Its st ate changes are based on the r ising-edge
(two clock cycles) of the system clock signal (ø) shown in f igure 21.12.
Rev. 1.0, 02/02, page 489 of 502
φ
Port 1, 3, 4
A to D, F, H, J (read)
t
PRS
T
1
T
2
t
PWD
t
PRH
Port 1, 3, A to D, F,
H, J (write)
φ
Port H, J (read)
t
PRS
T
1
T
2
t
PWD
t
PRH
Port H, J (write)
T
3
T
4
Fi g ure 21.6 I/O Port Input/ Output Ti ming
φ
t
TICS
t
TOCD
Output compare
output*
Input capture
input*
Note : * TIOCA0 to TIOCA2, TIOCB0 to TIOCB2, TIOCC0, TIOCD0
Fi g ure 21 .7 TPU Input/ O ut put Timing
Rev. 1.0, 02/02, page 490 of 502
t
TCKS
φ
t
TCKS
TCLKA to TCLKD
t
TCKWH
t
TCKWL
Fi g ure 21.8 TPU Clock Input Tim i ng
t
Scyc
t
SCKr
t
SCKW
SCK0, SCK1
t
SCKf
Fi g ure 21.9 SCK Cloc k Input Timi ng
SCK0, SCK1
TxD0, TxD1
(transmit data)
RxD0, RxD1
(receive data)
t
TXD
t
RXH
t
RXS
Fi g ure 21.10 SCI Input/O ut put Ti ming (Clock Synchronous Mode )
φ
t
TRGS
Fi g ure 21.11 A/D Converter Exter nal Tri g ger Input Timing
Rev. 1.0, 02/02, page 491 of 502
V
OL
V
OL
φ
HTxD
(transmit data)
HRxD
(receive data)
t
HTXD
t
HRXS
t
HRXH
Fi g ure 21 .12 HCAN Input/O ut put Timing
PWM1A to PWM1H,
PWM2A to PWM2H
t
MPWMOD
Figure 21.13 Motor Control PWM Output Timing
Rev. 1.0, 02/02, page 492 of 502
21.4 A/D Conversion Characteristics
Table 21.7 lists the A/D conversion characteristics.
Tabl e 21. 7 A/D Co nv ersion Charact eristic s
Conditions : VCC = LPV CC = 4.5 V to 5.5 V, AVCC = 4.5 V t o 5.5 V, PWMVCC = 4.5 V to 5.5 V,
VSS = AVSS = PWMVSS = PLLVSS = 0 V, φ = 4 MHz to 20 MHz,
Ta = –20°C to + 75°C (regular specific ations), Ta = –40°C to +85°C (wide-range
specifications)
Item Min Typ Max Unit
Resolution 10 10 10 bits
Conversion time 10 — 200 µs
Analog input capacitance — — 20 pF
Permissible signal-source
impedance ——5 kΩ
Nonlinearity error — — ±3. 5 LSB
Offset error — — ±3.5 LSB
Full-s c ale error — — ±3. 5 LSB
Quantization — ±0.5 — LSB
Abs ol ute a ccu racy — — ± 4.0 LS B
Rev. 1.0, 02/02, page 493 of 502
21.5 Flash Memory Charact eristics
Table 21.8 lists the flash memory characteristics.
Table 21.8 Flash Memory Characteristics
Conditions: VCC = PWMVCC = LPV CC = 4.5 V to 5.5 V, AVCC = 4. 5 V to 5.5 V ,
VSS = PWMVSS = PLLVSS = AVSS = 0 V, Ta = 0 to +75°C (Progra mming/erasing
operating temperature range: regular specifications)
Item Symbol Min Typ Max Unit Test
Condition
Programming time*1, *2, *4tP— 10 200 ms/128 bytes
Erase time*1, *3, *5tE— 100 1200 ms/block
Reprogramming count NWEC — — 100 Times
Program min g Wai t tim e after SWE bit setting*1tsswe 11—µs
Wait time after PSU bit setting*1tspsu 50 50 — µs
Wait time after P bit setting*1, *4tsp30 28 30 32 µs Programming
time wait
tsp200 198 200 202 µs Programming
time wait
tsp10 8 1012µs Additional-
programming
time wait
Wait time a fter P bit clear*1tcp 55—µs
Wait time a fter PSU bit clear*1tcpsu 55—µs
Wait time after PV bit setting*1tspv 44—µs
Wait time after H'FF dummy write*1tspvr 22—µs
Wait time after PV bit clear*1tcpv 22—µs
Wait time after SWE bit clear*1tcswe 100 100 — µs
M aximum programming count*1, *4N — — 1000 Times
Erase Wai t time after SWE bit sett ing*1tsswe 11—µs
Wait time after ESU bit setting*1tsesu 100 100 — µs
Wait time after E bit setting*1, *5tse 10 10 100 ms Erase time
wait
Wait time a fter E bit clear*1tce 10 10 — µs
Wait time a fter ESU bit clear*1tcesu 10 10 — µs
Wait time after EV bit setting*1tsev 20 20 — µs
Wait time after H'FF dummy write*1tsevr 22—µs
Wait time after EV bit clear*1tcev 44—µs
Wait time after SWE bit clear*1tcswe 100 100 — µs
M aximum erase count*1, *5N 12 — 120 Times
Rev. 1.0, 02/02, page 494 of 502
Notes: 1. Follow the progr am/erase algorithms when making the time settings.
2. Progr amming t ime per 128 bytes. (Indicates the total tim e during which t he P bit is set
in flash memory control register 1 ( FLMCR1). Does not include the program-verify
time.)
3. Time to erase one block. (Indicates t he total t im e during which the E bit is set in
FLMCR1. Does not include the erase-verify time.)
4. To specify the maximum programming time value (tp (max)) in the 128-byte
programming algorith m, set the max. value (1000 ) for the maximum progra m ming count
(N).
The wait time after P bit sett ing should be changed as follows according to t he value of
the programming counter ( n).
Programming counter ( n) = 1 t o 6: tsp30 = 30 µs
Programming counter ( n) = 7 t o 1000: tsp200 = 200 µs
(Additional progra m ming)
Programming counter ( n) = 1 t o 6: tsp10 = 10 µs
5. Fo r the m axi m um eras e time (t E(max)), the following relationship applies between the
wait time after E bit setting (tse) and the maximum er ase count (N):
tE(max) = Wait time after E bit setting (tse) x maximu m e rase co u nt (N)
To set the maximum erase time, the values of (tse) and (N) should be set so as to satisfy
the above formula.
Examples: When tse = 100 ms, N = 12 times
When tse = 10 ms, N = 120 times
Rev. 1.0, 02/02, page 495 of 502
21.6 LCD Characteristics
Table 21.9 lists the LCD characteristics.
Table 21.9 LCD Characteristics — Preliminary —
Conditions: VCC = LPV CC = 4. 5 V to 5.5 V , AV CC = 4.5 V to 5.5 V, PWMVCC = 4.5 V to 5.5 V,
VSS = AVSS = PWMVSS = PLLVSS = 0 V, T a = –20°C to +75°C (regular
specifications), Ta = –40°C to +85°C (wide-r ange spec ifi cations)*1
Item Symbol Pins Test
Condition Min Typ Max Unit Remarks
Segment driver step-
down volt age VDS SEG1 to
SEG28 ID = 2 µA0.6 V *1
Common dr iver step-
down volt age VDC COM1 to
COM4 ID = 2 µA0.3 V *1
LCD power- s upply
split-resistance RLCD V1 to VSS 40 300 1000 kΩ
LCD voltage VLCD V1 4.5 LPVCC V*2
Not e s : *1 The value shows the step-down voltage f r om the power-supply pins V1, V2, V3, and
Vss to the respect ive segm ent pin or common pin.
*2 When the LCD voltage is supplied externally, the following relat ion should be
ma intain ed: LPVc c ≥ V1 ≥ V2 ≥ V3 ≥ Vss.
Rev. 1.0, 02/02, page 496 of 502
Rev. 1.0, 02/02, page 497 of 502
Appendix
A. I/O P ort Stat es in Each Pin Stat e
Port Name
MCU
Operating
Mode Reset
Hardware
Standby
Mode
Software
Standby
Mode Subactive
Mode
Program
Execution
State Sleep
Mode
Port 1 7 T T Keep I /O port I/O port
Port 3 7 T T Keep I /O port I/O port
Port 4 7 T T T I nput port I nput port
Port A 7 T T Keep I /O port I/O port
Port B 7 T T Keep I /O port I/O port
Port C 7 T T Keep I /O port I/O port
Port D 7 T T Keep I /O port I/O port
PF7 7 T T [DDR = 0]
T
[DDR = 1]
H
[DDR = 0]
T
[DDR = 1]
H
[DDR = 0]
T
[DDR = 1]
Clock out put
PF6
PF5
PF4
PF3
PF2
PF0
7 T T Keep I/O port I/O port
Port H 7 T T Keep I /O port I/O port
Port J 7 T T Keep I /O port I/O port
HTxD 7 H T H H Output
HRxD 7 Input T T T Input
Legend
H: Hig h level
T: High impedance
Keep: Input por t becomes high-impedance, output por t retains st ate
Rev. 1.0, 02/02, page 498 of 502
B. Product Lineup
Product Type Name Model Marking Package (Code)
H8S/2282 F-ZTAT version HD64F2282 HD64F2282 100-pin QFP (FP-10 0A)
Mask ROM version HD6432282 HD6432282(***) 100- pin QFP (FP-100A)
H8S/2281 Mask ROM version HD6432281 HD6432281(***) 100- pin QFP (FP-100A)
Legend
(***): RO M code
Note: The above products include those under development or being planned. For the status of
each product, cont act a Hitachi sales off ice.
C. Package Dim ensions
The packa ge dimension tha t is shown i n the Hitachi Semiconduct or Package Data Book has
priority.
Hitachi Code
JEDEC
EIAJ
Mass
(reference value)
FP-100A
-
-
1.7 g
Unit: mm
*Dimension including the plating thickness
Base material dimension
0.13 M
0˚
-
10˚
*
0.32 ± 0.08
*0.17 ± 0.05
3.10 Max
1.2 ± 0.2
24.8 ± 0.4
20
80 51
50
31
30
1
100
81
18.8 ± 0.4
14
0.15
0.65
2.70
2.4
0.20+0.10
- 0.20
0.58 0.83
0.30 ± 0.06
0.15 ± 0.04
Figure C.1 FP-100A Package Dimensions
Rev. 1.0, 02/02, page 499 of 502
Index
16-Bit T imer Pulse Unit ........................131
Buffer Operation ...............................165
Buffer Operation Timing ...................186
Counter Operation.............................158
Input Capture Function......................162
Input Capture Signal Timing..............184
Output Compare Output Timing ........184
Phase Countin g Mode........................174
PWM Modes.....................................169
Synchronous Operation .....................164
TCNT Count Timing.........................183
Waveform Output by Compare Match160
A/D Con verter.......................................327
A/D Conversion Time........................335
Analog Input Channel........................330
Externa l Trigger ................................337
Scan Mode........................................334
Single Mode......................................334
Address Map...........................................50
Address Space.........................................16
Addressing Modes ...................................38
Absolute Address ................................39
Immediate...........................................40
Memory Indirect ..................................40
Program-Counter Relative ...................40
Register Direct ....................................38
Register In direct..................................38
Register In direct with Displacement.....38
Regi ster indirect wi th post-increment...39
Register indirect with pre-decrement....39
Bcc .........................................................34
bus cycle.................................................83
Clock Pulse Generator...........................403
Condition Field .......................................37
Condition-Code Register (CCR)..............20
data d ire ction register (DDR)...................87
data register (D R)....................................87
Effective Address.............................. 38, 41
Effective Address Extension....................37
Exception Handling.................................51
Interrupts.............................................56
Reset Exception Handling....................53
Stack Status.........................................58
Traces..................................................56
Trap In struction...................................57
Exception Handling Vector Table............52
Extended Control Register (EXR)............19
flash memor y.........................................379
Boot Mode.........................................389
Emulation..........................................393
Erase/Erase-Verify.............................397
erasing units......................................383
Program/Program-Verify...................395
User Pr ogram Mode...........................391
General Registers ....................................18
Hitachi Con troller Area Network (HCAN)
..........................................................279
CAN Bus Interface ............................324
Hardwar e Reset .................................307
HCAN Halt Mode..............................322
HCAN Sleep Mode............................319
Message Reception............................316
Message Transmission.......................313
Softwar e Reset...................................307
IC card (Smart Card) inter face.......215, 264
Instruction Set.........................................26
Arithmetic Operation s Instructions.......29
Bit Manipulation In structions...............32
Block Data Tr ansfer In structions..........36
Br anch Instructions..............................34
Data Transfer Instruction s....................28
Logic Operations Instruction s ..............31
Shift Instruction s .................................31
System Con trol Instruction s.................35
Interrupt
ADI...................................................337
CMI ..................................................360
ERI....................................................275
ERS0.................................................323
NMI ....................................................69
Rev. 1.0, 02/02, page 500 of 502
OVR0................................................323
RM0..................................................323
RM1..................................................323
RXI...................................................275
SLE0................................................. 323
TCI...................................................181
TEI ...................................................275
TGI...................................................181
TXI...................................................275
WOVI...............................................211
Interrupt Control Modes..........................73
Interrupt Controller .................................61
Interrupt Exception Han dling Vector Table
...........................................................70
Interrupt Mask Bit...................................21
LCD Controller/Driver..........................363
Common Drivers...............................366
Duty C ycle........................................ 363
LCD Display.....................................369
LCD RAM ........................................370
Segmen t Driver s................................366
memor y cycle ..........................................83
Motor Contr ol PWM Timer................... 343
PWM Channel 1................................358
PWM Channel 2................................359
On-Boar d Programming Modes.............389
open-drain control register (ODR ) ...........87
Operating Mode Selection .......................47
Operation Field.......................................37
Power-Down Modes .............................. 413
Direct Trans itio ns..............................43 1
Hardwar e Standby Mod e ................... 427
Medium-Speed Mode........................ 422
Module Stop Mode............................ 428
Sleep Mode.......................................423
Softwar e Standby Mode..................... 424
Subactive Mode.................................430
Subsleep Mode..................................430
Watch Mode......................................429
Program Coun ter (PC).............................19
Program/Erase Protection......................399
Programmer Mode ................................400
Register
ABACK ............................................291
ADCR...............................................333
ADCSR.............................................331
ADDR...............................................330
BCR..................................................285
BRR..................................................231
EBR..................................................387
FLMCR1...........................................386
FLMCR2...........................................387
FLPWCR ..........................................389
GSR..................................................283
IER .....................................................65
IMR ..................................................299
IPR......................................................64
IRR ...................................................294
ISCR...................................................66
ISR......................................................68
LAFM...............................................302
LCR..................................................367
LCR2 ................................................368
LPCR................................................365
LPWRCR.................................. 406, 418
MBCR...............................................287
MBIMR.............................................298
MC....................................................304
MCR.................................................282
MD ...................................................306
MDCR ................................................47
MSTPCR...........................................420
P1DDR................................................91
P1DR ..................................................91
P3DDR..............................................101
P3DR ................................................101
P3ODR..............................................102
PADDR.............................................106
PADR................................................106
PAODR.............................................107
PBDDR.............................................108
PBDR................................................109
PBODR.............................................109
PCDDR.............................................111
PCDR................................................111
PCODR.............................................112
Rev. 1.0, 02/02, page 501 of 502
PDDDR.............................................113
PDDR ...............................................113
PFDDR .............................................116
PFDR................................................117
PHDDR.............................................120
PHDR ...............................................120
PJDDR..............................................124
PJDR.................................................124
PORT1................................................92
PORT3..............................................102
PORT4..............................................105
PORTA.............................................107
PORTB.............................................109
PORTC.............................................111
PORTD.............................................115
PORTF..............................................117
PORTH.............................................121
PORTJ ..............................................125
PWBFR1...........................................352
PWBFR2...........................................355
PWCNT............................................349
PWCR...............................................347
PWCYR............................................350
PWDTR1 ..........................................350
PWDTR2 ..........................................353
PWOCR............................................347
PWPR...............................................349
RAMER............................................388
RDR..................................................218
REC..................................................300
RFPR................................................293
RSR ..................................................218
RSTCSR ...........................................207
RXPR................................................292
SBYCR.............................................417
SCKCR.............................................404
SCMR...............................................230
SCR ..................................................223
SMR..................................................219
SSR...................................................226
SYSCR................................................48
TCNT........................................ 155, 203
TCR..................................................137
TCSR................................................203
TDR..................................................218
TEC ..................................................300
TGR..................................................156
TIER.................................................150
TIOR.................................................142
TMDR...............................................140
TRPRT..............................................128
TSR........................................... 153, 218
TSTR................................................156
TSYR................................................157
TXACK.............................................290
TXCR................................................289
TXPR................................................288
UMSR...............................................301
Register Field..........................................37
Reset.......................................................53
Serial Comm unication Int er face (SCI) .. .215
Asyn chronous Mode..........................238
Bit Rate.............................................231
Break.................................................276
Clocked Synchron ous Mode...............255
fr amin g error .....................................245
Mark State.........................................277
Multiprocessor Communication Fun ction
......................................................249
overrun error .....................................245
par ity error ........................................245
stack pointer (SP) ....................................18
W atchdog Ti mer....................................201
Int erv a l Timer Mode..........................210
overflow............................................211
W atchdog Ti mer Mode......................208
Rev. 1.0, 02/02, page 502 of 502
H8S/2282 Series Hardware Manual
Publication Date: 1st Edition, Februa ry 2002
Published by: Busine ss Planning Division
Semiconductor & Integrated Circuits
Hitachi, Ltd.
Edited by: Technical Documentation Group
Hitachi Kodai ra Se miconductor Co., Ltd.
Copyright © Hitachi, Ltd., 2002. All rights reserved. Print ed in Japa n.
