3.75 kV, 6-Channel, SPIsolator Digital
Isolator for SPI with Delay Clock
Data Sheet
ADuM3150
FEATURES
Supports up to 40 MHz SPI clock speed in delay clock mode
Supports up to 17 MHz SPI clock speed in 4-wire mode
4 high speed, low propagation delay, SPI signal isolation
channels
2 data channels at 250 kbps
Delayed compensation clock line
20-lead SSOP with 5.1 mm creepage
High temperature operation: 125°C
High common-mode transient immunity: >25 kV/µs
Safety and regulatory approvals
UL recognition per UL 1577
3750 V rms for 1 minute
CSA Component Acceptance Notice 5A
VDE certificate of conformity
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 565 V peak
APPLICATIONS
Industrial programmable logic controllers (PLC)
Sensor isolation
FUNCTIONAL BLOCK DIAGRAM
ENCODE
CLK
DELAY
CONTROL
BLOCK
DECODE
DECODE ENCODE
ENCODE DECODE
ENCODE DECODE
V
DD1
GND
1
MCLK
MO
MI
MSS
V
IA
V
OB
V
DD2
GND
2
SCLK
SI
SO
SSS
V
OA
V
IB
1
2
3
4
5
6
7
8
20
19
18
17
16
15
14
13
DCLK
GND
1
NIC
GND
2
9
10
12
11
ADuM3150
12367-001
CONTROL
BLOCK
Figure 1.
GENERAL DESCRIPTION
The ADuM31501 is a 6-channel SPIsolator™ digital isolator
optimized for isolated serial peripheral interfaces (SPIs). Based
on the Analog Devices, Inc., iCoupler® chip scale transformer
technology, the low propagation delay in the CLK, MO/SI,
MI/SO, and SS SPI bus signals supports SPI clock rates of up to
17 MHz. These channels operate with 14 ns propagation delay
and 1 ns jitter to optimize timing for SPI.
The ADuM3150 isolator also provides two additional independent
low data rate isolation channels, one channel in each direction.
Data in the slow channels is sampled and serialized for a 250 kbps
data rate with 2.5 µs of jitter.
The ADuM3150 supports a delay clock output on the master
side of the device. This output can be used with an additional
clocked port on the master to support 40 MHz clock performance.
See the Delay Clock section for more information.
Table 1. Related Products
Product
Description
ADuM3151/ADuM3152/
ADuM3153
3.75 kV, multichannel SPI isolator
ADuM3154 3.75 kV, multiple slave SPI isolator
ADuM4150 5 kV, high speed, clock delayed
SPIsolator
ADuM4151/ADuM4152/
ADuM4153
5 kV, multichannel SPI isolator
ADuM4154
5 kV, multiple slave SPI isolator
1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,262,600; and 7,075,329. Other patents are pending.
Rev. A Document Feedback
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ADuM3150 Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Electrical Characteristics—5 V Operation................................ 3
Electrical Characteristics—3.3 V Operation ............................ 5
Electrical Characteristics—Mixed 5 V/3.3 V Operation ........ 7
Electrical Characteristics—Mixed 3.3 V/5 V Operation ........ 9
Package Characteristics ............................................................. 11
Regulatory Information ............................................................. 11
Insulation and Safety Related Specifications .......................... 11
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
Insulation Characteristics .......................................................... 12
Recommended Operating Conditions .................................... 12
Absolute Maximum Ratings ......................................................... 13
ESD Caution................................................................................ 13
Pin Configuration and Function Descriptions ........................... 14
Typical Performance Characteristics ........................................... 15
Applications Information .............................................................. 16
Introduction ................................................................................ 16
Printed Circuit Board (PCB) Layout ....................................... 17
Propagation Delay Related Parameters ................................... 18
DC Correctness and Magnetic Field Immunity ..................... 18
Power Consumption .................................................................. 19
Insulation Lifetime ..................................................................... 19
Outline Dimensions ....................................................................... 21
Ordering Guide .......................................................................... 21
REVISION HISTORY
3/15—Rev. 0 to Rev. A
Changes to Features Section and Table 1 ...................................... 1
Changes to Table 3 ............................................................................ 4
Changes to Table 5 ............................................................................ 6
Changes to Table 7 ............................................................................ 8
Changes to Table 9 .......................................................................... 10
Changes to Table 10, Regulatory Information Section, and
Table 11 ............................................................................................ 11
Changes to Table 13 and Figure 2 ................................................. 12
Changes to Figure 4 to Figure 7 .................................................... 15
Changes to High Speed Channels Section .................................. 16
Changes to Power Consumption Section .................................... 19
7/14—Revision 0: Initial Versi on
Rev. A | Page 2 of 21
Data Sheet ADuM3150
SPECIFICATIONS
ELECTRICAL CHARACTERISTICS—5 V OPERATION
All typical specifications are at TA = 25°C and VDD1 = VDD2 = 5 V. Minimum and maximum specifications apply over the entire
recommended operation range: 4.5 V ≤ VDD1 ≤ 5.5 V, 4.5 V ≤ VDD2 ≤ 5.5 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching
specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
Table 2. Switching Specifications
Parameter Symbol
A Grade B Grade
Unit Test Conditions/Comments Min Typ Max Min Typ Max
MCLK, MO, SO
SPI Clock Rate SPIMCLK 10 17 MHz
Data Rate Fast (MO, SO) DRFAST 40 40 Mbps Within PWD limit
Propagation Delay tPHL, tPLH 25 12 14 ns 50% input to 50% output
Pulse Width PW 12.5 12.5 ns Within PWD limit
Pulse Width Distortion
PWD
2
2
ns
|t
PLH
− t
PHL
|
Codirectional Channel Matching1 tPSKCD 2 2 ns
Jitter, High Speed JHS 1 1 ns
MSS
Data Rate Fast DRFAST 40 40 Mbps Within PWD limit
Propagation Delay tPHL, tPLH 21 25 21 25 ns 50% input to 50% output
Pulse Width PW 12.5 12.5 ns Within PWD limit
Pulse Width Distortion PWD 2 2 ns |tPLH − tPHL|
Setup Time2 MSSSETUP 1.5 10 ns
Jitter, High Speed JHS 1 1 ns
DCLK
Data Rate
40
40
MHz
Propagation Delay tPHL, tPLH 50 35 ns tPMCLK + tPSO + 3 ns
Pulse Width Distortion PWD 3 3 ns |tPLH − tPHL|
Pulse Width PW 12 12 ns Within PWD limit
Clock Delay Error DCLKERR 0 4.5 12 1 5.5 12 ns tPDCLK − (tPMCLK + tPSO)
Jitter JDCLK 1 1 ns
VIA, VIB
Data Rate Slow DRSLOW 250 250 kbps Within PWD limit
Propagation Delay tPHL, tPLH 0.1 2.6 0.1 2.6 µs 50% input to 50% output
Pulse Width
PW
4
4
µs
Within PWD limit
Jitter, Low Speed JLS 2.5 2.5 µs
VIx3 Minimum Input Skew4 tVIx SKEW 10 10 ns
1 Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier.
2 The MSS signal is glitch filtered in both speed grades, whereas the other fast signals are not glitch filtered in the B grade. To guarantee that MSS reaches the output
ahead of another fast signal, set up MSS prior to the competing signal by different times depending on speed grade.
3 VIx = VIA or VIB.
4 An internal asynchronous clock, not available to users, samples the low speed signals. If edge sequence in codirectional channels is critical to the end application, the
leading pulse must be at least 1 tVIx SKEW time ahead of a later pulse to guarantee the correct order or simultaneous arrival at the output.
Rev. A | Page 3 of 21
ADuM3150 Data Sheet
Table 3. For All Grades1, 2, 3
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
SUPPLY CURRENT
1 MHz, A Grade and B Grade IDD1 5 8.5 mA CL = 0 pF, DRFAST = 1 MHz,
DRSLOW = 0 MHz
IDD2 6.5 11 mA CL = 0 pF, DRFAST = 1 MHz,
DRSLOW = 0 MHz
17 MHz, B Grade IDD1 15 23 mA CL = 0 pF, DRFAST = 17 MHz,
DRSLOW = 0 MHz
IDD2 13.5 21 mA CL = 0 pF, DRFAST = 17 MHz,
DRSLOW = 0 MHz
DC SPECIFICATIONS
MCLK, MSS, MO, SO, VIA, VIB
Input Threshold
Logic High
V
IH
0.7 × V
DDx
V
Logic Low VIL 0.3 × VDDx V
Input Hysteresis VIHYST 500 mV
Input Current per Channel II −1 +0.01 +1 µA 0 V ≤ VINPUT ≤ VDDx
SCLK, SSS, MI, SI, VOA, VOB, DCLK
Output Voltages
Logic High VOH VDDx − 0.1 5.0 V IOUTPUT = −20 µA, VINPUT = VIH
VDDx − 0.4 4.8 V IOUTPUT = −4 mA, VINPUT = VIH
Logic Low VOL 0.0 0.1 V IOUTPUT = 20 µA, VINPUT = VIL
0.2 0.4 V IOUTPUT = 4 mA, VINPUT = VIL
VDD1, VDD2 Undervoltage Lockout UVLO 2.6 V
Supply Current for High Speed Channel
Dynamic Input IDDI(D) 0.080 mA/Mbps
Dynamic Output IDDO(D) 0.046 mA/Mbps
Supply Current for All Low Speed Channels
Quiescent Side 1 Current IDD1(Q) 4.4 mA
Quiescent Side 2 Current IDD2(Q) 6.1 mA
AC SPECIFICATIONS
Output Rise/Fall Time tR/tF 2.5 ns 10% to 90%
Common-Mode Transient Immunity4 |CM| 25 35 kV/µs VINPUT = VDDx, VCM = 1000 V
Transient magnitude = 800 V
1 VDDx = VDD1 or VDD2.
2 VINPUT is the input voltage of any of the MCLK, MSS, MO, SO, VIA, or VIB pins.
3 IOUTPUT is the output current of any of the SCLK, DCLK, SSS, MI, SI, VOA, or VOB pins.
4 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining output voltages within the VOH and VOL limits. The common-mode
voltage slew rates apply to both rising and falling common-mode voltage edges.
Rev. A | Page 4 of 21
Data Sheet ADuM3150
ELECTRICAL CHARACTERISTICS—3.3 V OPERATION
All typical specifications are at TA = 25°C and VDD1 = VDD2 = 3.3 V. Minimum and maximum specifications apply over the entire
recommended operation range: 3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching
specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
Table 4. Switching Specifications
Parameter Symbol
A Grade B Grade
Unit Test Conditions/Comments Min Typ Max Min Typ Max
MCLK, MO, SO
SPI Clock Rate SPIMCLK 8.3 12.5 MHz
Data Rate Fast (MO, SO)
DR
FAST
40
40
Mbps
Within PWD limit
Propagation Delay tPHL, tPLH 30 20 ns 50% input to 50% output
Pulse Width PW 12.5 12.5 ns Within PWD limit
Pulse Width Distortion PWD 3 3 ns |tPLH − tPHL|
Codirectional Channel Matching1 tPSKCD 3 3 ns
Jitter, High Speed JHS 1 1 ns
MSS
Data Rate Fast DRFAST 40 40 Mbps Within PWD limit
Propagation Delay
t
PHL
, t
PLH
30
30
ns
50% input to 50% output
Pulse Width PW 12.5 12.5 ns Within PWD limit
Pulse Width Distortion PWD 3 3 ns |tPLH − tPHL|
Setup Time2 MSSSETUP 1.5 10 ns
Jitter, High Speed JHS 1 1 ns
DCLK
Data Rate 40 40 MHz
Propagation Delay tPHL, tPLH 60 40 ns tPMCLK + tPSO + 3 ns
Pulse Width Distortion PWD 3 3 ns |tPLH − tPHL|
Pulse Width PW 12 12 ns Within PWD limit
Clock Delay Error DCLKERR −4 +2.4 +9 −3 +2.5 +8 ns tPDCLK − (tPMCLK + tPSO)
Jitter JDCLK 1 1 ns
VIA, VIB
Data Rate Slow DRSLOW 250 250 kbps Within PWD limit
Propagation Delay tPHL, tPLH 0.1 2.6 0.1 2.6 µs 50% input to 50% output
Pulse Width PW 4 4 µs Within PWD limit
Jitter, Low Speed JLS 2.5 2.5 µs
V
Ix3
Minimum Input Skew
4
t
VIx SKEW
10
10
ns
1 Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier.
2 The MSS signal is glitch filtered in both speed grades, whereas the other fast signals are not glitch filtered in the B grade. To guarantee that MSS reaches the output
ahead of another fast signal, set up MSS prior to the competing signal by different times depending on speed grade.
3 VIx = VIA or VIB.
4 An internal asynchronous clock, not available to users, samples the low speed signals. If edge sequence in codirectional channels is critical to the end application, the
leading pulse must be at least 1 tVIx SKEW time ahead of a later pulse to guarantee the correct order or simultaneous arrival at the output.
Rev. A | Page 5 of 21
ADuM3150 Data Sheet
Table 5. For All Grades1, 2, 3
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
SUPPLY CURRENT
1 MHz, A Grade and B Grade IDD1 3.5 6 mA CL = 0 pF, DRFAST = 1 MHz,
DRSLOW = 0 MHz
IDD2 4.9 8 mA CL = 0 pF, DRFAST = 1 MHz,
DRSLOW = 0 MHz
17 MHz, B Grade IDD1 9.5 20 mA CL = 0 pF, DRFAST = 17 MHz,
DRSLOW = 0 MHz
IDD2 8 16 mA CL = 0 pF, DRFAST = 17 MHz,
DRSLOW = 0 MHz
DC SPECIFICATIONS
MCLK, MSS, MO, SO, VIA, VIB
Input Threshold
Logic High
V
IH
0.7 × V
DDx
V
Logic Low VIL 0.3 × VDDx V
Input Hysteresis VIHYST 500 mV
Input Current per Channel II −1 +0.01 +1 µA 0 V ≤ VINPUT ≤ VDDx
SCLK, SSS, MI, SI, VOA, VOB, DCLK
Output Voltages
Logic High VOH VDDx − 0.1 5.0 V IOUTPUT = −20 µA, VINPUT = VIH
VDDx − 0.4 4.8 V IOUTPUT = −4 mA, VINPUT = VIH
Logic Low VOL 0.0 0.1 V IOUTPUT = 20 µA, VINPUT = VIL
0.2 0.4 V IOUTPUT = 4 mA, VINPUT = VIL
VDD1, VDD2 Undervoltage Lockout UVLO 2.6 V
Supply Current for High Speed Channel
Dynamic Input IDDI(D) 0.086 mA/Mbps
Dynamic Output IDDO(D) 0.019 mA/Mbps
Supply Current for All Low Speed Channels
Quiescent Side 1 Current IDD1(Q) 2.9 mA
Quiescent Side 2 Current IDD2(Q) 4.6 mA
AC SPECIFICATIONS
Output Rise/Fall Time tR/tF 2.5 ns 10% to 90%
Common-Mode Transient Immunity4 |CM| 25 35 kV/µs VINPUT = VDDx, VCM = 1000 V
Transient magnitude = 800 V
1 VDDx = VDD1 or VDD2.
2 VINPUT is the input voltage of any of the MCLK, MSS, MO, SO, VIA, or VIB pins.
3 IOUTPUT is the output current of any of the SCLK, DCLK, SSS, MI, SI, VOA, or VOB pins.
4 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining output voltages within the VOH and VOL limits. The common-mode
voltage slew rates apply to both rising and falling common-mode voltage edges.
Rev. A | Page 6 of 21
Data Sheet ADuM3150
ELECTRICAL CHARACTERISTICS—MIXED 5 V/3.3 V OPERATION
All typical specifications are at TA = 25°C and VDD1 = 5 V, V DD2 = 3.3 V. Minimum and maximum specifications apply over the entire
recommended operation range: 4.5 V ≤ VDD1 ≤ 5.5 V, 3.0 V ≤ VDD2 ≤ 3.6 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching
specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
Table 6. Switching Specifications
Parameter Symbol
A Grade B Grade
Unit Test Conditions/Comments Min Typ Max Min Typ Max
MCLK, MO, SO
SPI Clock Rate SPIMCLK 9.2 15.6 MHz
Data Rate Fast (MO, SO)
DR
FAST
40
40
Mbps
Within PWD limit
Propagation Delay tPHL, tPLH 27 16 ns 50% input to 50% output
Pulse Width PW 12.5 12.5 ns Within PWD limit
Pulse Width Distortion PWD 3 2 ns |tPLH − tPHL|
Codirectional Channel Matching1 tPSKCD 2 2 ns
Jitter, High Speed JHS 1 1 ns
MSS
Data Rate Fast DRFAST 40 40 Mbps Within PWD limit
Propagation Delay
t
PHL
, t
PLH
27
26
ns
50% input to 50% output
Pulse Width PW 12.5 12.5 ns Within PWD limit
Pulse Width Distortion PWD 2 2 ns |tPLH − tPHL|
Setup Time2 MSSSETUP 1.5 10 ns
Jitter, High Speed JHS 1 1 ns
DCLK
Data Rate 40 40 MHz
Propagation Delay tPHL, tPLH 50 35 ns tPMCLK + tPSO + 3 ns
Pulse Width Distortion PWD 3 3 ns |tPLH − tPHL|
Pulse Width PW 12 12 ns Within PWD limit
Clock Delay Error DCLKERR −5 0 +7 −5 +1.2 +9 ns tPDCLK − (tPMCLK + tPSO)
Jitter JDCLK 1 1 ns
VIA, VIB
Data Rate Slow DRSLOW 250 250 kbps Within PWD limit
Propagation Delay tPHL, tPLH 0.1 2.6 0.1 2.6 µs 50% input to 50% output
Pulse Width PW 4 4 µs Within PWD limit
Jitter, Low Speed JLS 2.5 2.5 µs
V
Ix3
Minimum Input Skew
4
t
VIx SKEW
10
10
ns
1 Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier.
2 The MSS signal is glitch filtered in both speed grades, whereas the other fast signals are not glitch filtered in the B grade. To guarantee that MSS reaches the output
ahead of another fast signal, set up MSS prior to the competing signal by different times depending on speed grade.
3 VIx = VIA or VIB.
4 An internal asynchronous clock, not available to users, samples the low speed signals. If edge sequence in codirectional channels is critical to the end application, the
leading pulse must be at least 1 tVIx SKEW time ahead of a later pulse to guarantee the correct order or simultaneous arrival at the output.
Rev. A | Page 7 of 21
ADuM3150 Data Sheet
Table 7. For All Grades1, 2, 3
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
SUPPLY CURRENT
1 MHz, A Grade and B Grade IDD1 5.3 8.5 mA CL = 0 pF, DRFAST = 1 MHz,
DRSLOW = 0 MHz
IDD2 4.9 8 mA CL = 0 pF, DRFAST = 1 MHz,
DRSLOW = 0 MHz
17 MHz, B Grade IDD1 16 23 mA CL = 0 pF, DRFAST = 17 MHz,
DRSLOW = 0 MHz
IDD2 10 16 mA CL = 0 pF, DRFAST = 17 MHz,
DRSLOW = 0 MHz
DC SPECIFICATIONS
MCLK, MSS, MO, SO, VIA, VIB
Input Threshold
Logic High
V
IH
0.7 × V
DDx
V
Logic Low VIL 0.3 × VDDx V
Input Hysteresis VIHYST 500 mV
Input Current per Channel II −1 +0.01 +1 µA 0 V ≤ VINPUT ≤ VDDx
SCLK, SSS, MI, SI, VOA, VOB, DCLK
Output Voltages
Logic High VOH VDDx − 0.1 5.0 V IOUTPUT = −20 µA, VINPUT = VIH
VDDx − 0.4 4.8 V IOUTPUT = −4 mA, VINPUT = VIH
Logic Low VOL 0.0 0.1 V IOUTPUT = 20 µA, VINPUT = VIL
0.2 0.4 V IOUTPUT = 4 mA, VINPUT = VIL
VDD1, VDD2 Undervoltage Lockout UVLO 2.6 V
Supply Current for All Low Speed Channels
Quiescent Side 1 Current IDD1(Q) 4.4 mA
Quiescent Side 2 Current IDD2(Q) 4.6 mA
AC SPECIFICATIONS
Output Rise/Fall Time tR/tF 2.5 ns 10% to 90%
Common-Mode Transient Immunity4 |CM| 25 35 kV/µs VINPUT = VDDx, VCM = 1000 V
Transient magnitude = 800 V
1 VDDx = VDD1 or VDD2.
2 VINPUT is the input voltage of any of the MCLK, MSS, MO, SO, VIA, or VIB pins.
3 IOUTPUT is the output current of any of the SCLK, DCLK, SSS, MI, SI, VOA, or VOB pins.
4 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining output voltages within the VOH and VOL limits. The common-mode
voltage slew rates apply to both rising and falling common-mode voltage edges.
Rev. A | Page 8 of 21
Data Sheet ADuM3150
ELECTRICAL CHARACTERISTICS—MIXED 3.3 V/5 V OPERATION
All typical specifications are at TA = 25°C, VDD1 = 3.3 V and VDD2 = 5 V. Minimum and maximum specifications apply over the entire
recommended operation range: 3.0 V ≤ VDD1 ≤ 3.6 V, 4.5 V ≤ VDD2 ≤ 5.5 V, and −40°C ≤ TA ≤ +125°C, unless otherwise noted. Switching
specifications are tested with CL = 15 pF and CMOS signal levels, unless otherwise noted.
Table 8. Switching Specifications
Parameter Symbol
A Grade B Grade
Unit Test Conditions/Comments Min Typ Max Min Typ Max
MCLK, MO, SO
SPI Clock Rate SPIMCLK 9.2 15.6 MHz
Data Rate Fast (MO, SO)
DR
FAST
40
40
Mbps
Within PWD limit
Propagation Delay tPHL, tPLH 27 16 ns 50% input to 50% output
Pulse Width PW 12.5 12.5 ns Within PWD limit
Pulse Width Distortion PWD 2 2 ns |tPLH − tPHL|
Codirectional Channel Matching1 tPSKCD 3 3 ns
Jitter, High Speed JHS 1 1 ns
MSS
Data Rate Fast DRFAST 40 40 Mbps Within PWD limit
Propagation Delay
t
PHL
, t
PLH
26
26
ns
50% input to 50% output
Pulse Width PW 12.5 12.5 ns Within PWD limit
Pulse Width Distortion PWD 3 3 ns |tPLH − tPHL|
Setup Time2 MSSSETUP 1.5 10 ns
Jitter, High Speed JHS 1 1 ns
DCLK
Data Rate 40 40 MHz
Propagation Delay tPHL, tPLH 60 40 ns tPMCLK + tPSO + 3 ns
Pulse Width Distortion PWD 3 3 ns |tPLH − tPHL|
Pulse Width PW 12 12 ns Within PWD limit
Clock Delay Error DCLKERR 2 7 13 2 6.8 11 ns tPDCLK − (tPMCLK + tPSO)
Jitter JDCLK 1 1 ns
VIA, VIB
Data Rate Slow DRSLOW 250 250 kbps Within PWD limit
Propagation Delay tPHL, tPLH 0.1 2.6 0.1 2.6 µs 50% input to 50% output
Pulse Width PW 4 4 µs Within PWD limit
Jitter, Low Speed JLS 2.5 2.5 µs
V
Ix3
Minimum Input Skew
4
t
VIx SKEW
10
10
ns
1 Codirectional channel matching is the absolute value of the difference in propagation delays between any two channels with inputs on the same side of the isolation barrier.
2 The MSS signal is glitch filtered in both speed grades, whereas the other fast signals are not glitch filtered in the B grade. To guarantee that MSS reaches the output
ahead of another fast signal, set up MSS prior to the competing signal by different times depending on speed grade.
3 VIx = VIA or VIB.
4 An internal asynchronous clock, not available to users, samples the low speed signals. If edge sequence in codirectional channels is critical to the end application, the
leading pulse must be at least 1 tVIx SKEW time ahead of a later pulse to guarantee the correct order or simultaneous arrival at the output.
Rev. A | Page 9 of 21
ADuM3150 Data Sheet
Table 9. For All Grades1, 2, 3
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
SUPPLY CURRENT
1 MHz, A Grade and B Grade IDD1 3.5 6 mA CL = 0 pF, DRFAST = 1 MHz,
DRSLOW = 0 MHz
IDD2 6.8 11 mA CL = 0 pF, DRFAST = 1 MHz,
DRSLOW = 0 MHz
17 MHz, B Grade IDD1 12.5 20 mA CL = 0 pF, DRFAST = 17 MHz,
DRSLOW = 0 MHz
IDD2 14 21 mA CL = 0 pF, DRFAST = 17 MHz,
DRSLOW = 0 MHz
DC SPECIFICATIONS
MCLK, MSS, MO, SO, VIA, VIB
Input Threshold
Logic High
V
IH
0.7 × V
DDx
V
Logic Low VIL 0.3 × VDDx V
Input Hysteresis VIHYST 500 mV
Input Current per Channel II −1 +0.01 +1 µA 0 V ≤ VINPUT ≤ VDDx
SCLK, SSS, MI, SI, VOA, VOB, DCLK
Output Voltages
Logic High VOH VDDx − 0.1 5.0 V IOUTPUT = −20 µA, VINPUT = VIH
VDDx − 0.4 4.8 V IOUTPUT = −4 mA, VINPUT = VIH
Logic Low VOL 0.0 0.1 V IOUTPUT = 20 µA, VINPUT = VIL
0.2 0.4 V IOUTPUT = 4 mA, VINPUT = VIL
VDD1, VDD2 Undervoltage Lockout UVLO 2.6 V
Supply Current for All Low Speed Channels
Quiescent Side 1 Current IDD1(Q) 2.9 mA
Quiescent Side 2 Current IDD2(Q) 6.1 mA
AC SPECIFICATIONS
Output Rise/Fall Time tR/tF 2.5 ns 10% to 90%
Common-Mode Transient Immunity4 |CM| 25 35 kV/µs VINPUT = VDDx, VCM = 1000 V
Transient magnitude = 800 V
1 VDDx = VDD1 or VDD2.
2 VINPUT is the input voltage of any of the MCLK, MSS, MO, SO, VIA, or VIB pins.
3 IOUTPUT is the output current of any of the SCLK, DCLK, SSS, MI, SI, VOA, or VOB pins.
4 |CM| is the maximum common-mode voltage slew rate that can be sustained while maintaining output voltages within the VOH and VOL limits. The common-mode
voltage slew rates apply to both rising and falling common-mode voltage edges.
Rev. A | Page 10 of 21
Data Sheet ADuM3150
PACKAGE CHARACTERISTICS
Table 10.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
Resistance (Input-to-Output)1
R
I-O
1012
Ω
Capacitance (Input-to-Output)1 CI-O 1.0 pF f = 1 MHz
Input Capacitance2 CI 4.0 pF
IC Junction-to-Case Thermal Resistance θJC 68.5 °C/W 4-layer JEDEC test board, JESD 51-7 specification
1 The device is considered a 2-terminal device: Pin 1 through Pin 10 are shorted together, and Pin 11 through Pin 20 are shorted together.
2 Input capacitance is from any input data pin to ground.
REGULATORY INFORMATION
The ADuM3150 is approved by the organizations listed in Tabl e 11. See Table 16 and the Insulation Lifetime section for recommended
maximum working voltages for specific cross-isolation waveforms and insulation levels.
Table 11.
UL CSA VDE
Recognized under 1577 Component
Recognition Program1
Approved under CSA Component Acceptance Notice 5A Certified according to DIN V VDE V
0884-10 (VDE V 0884-10):2006-122
3750 V rms Single Protection Basic insulation per CSA 60950-1-07+A1+A2 and IEC
60950-1 2nd Ed.+A1+A2, 510 V rms (721 V peak) maximum
working voltage3
Reinforced insulation, 565 V peak
File E214100
File 205078
File 2471900-4880-0001
1 In accordance with UL 1577, the ADuM3150 is proof tested by applying an insulation test voltage ≥ 4500 V rms for 1 second (current leakage detection limit = 10 µA).
2 In accordance with DIN V VDE V 0884-10, the ADuM3150 is proof tested by applying an insulation test voltage ≥ 525 V peak for 1 second (partial discharge detection
limit = 5 pC). The asterisk (*) marked on the component designates DIN V VDE V 0884-10 approval.
3 See Table 16 for recommended maximum working voltages under various operating conditions.
INSULATION AND SAFETY RELATED SPECIFICATIONS
Table 12.
Parameter Symbol Value Unit Conditions
Rated Dielectric Insulation Voltage 3750 V rms 1-minute duration
Minimum External Air Gap (Clearance) L(I01) 5.1 mm min Measured from input terminals to output terminals,
shortest distance through air
Minimum External Tracking (Creepage) L(I02) 5.1 mm min Measured from input terminals to output terminals,
shortest distance path along body
Minimum Internal Gap (Internal Clearance) 0.017 mm min Insulation distance through insulation
Tracking Resistance (Comparative Tracking Index) CTI >400 V DIN IEC 112/VDE 0303 Part 1
Material Group II Material Group (DIN VDE 0110, 1/89, Table 1)
Rev. A | Page 11 of 21
ADuM3150 Data Sheet
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 INSULATION CHARACTERISTICS
This isolator is suitable for reinforced electrical isolation only within the safety limit data. Maintenance of the safety data is ensured by
protective circuits. The asterisk (*) marked on packages denotes DIN V VDE V 0884-10 approval.
Table 13.
Description Test Conditions/Comments Symbol Characteristic Unit
Installation Classification per DIN VDE 0110
For Rated Mains Voltage ≤ 150 V rms I to IV
For Rated Mains Voltage ≤ 300 V rms I to III
For Rated Mains Voltage ≤ 400 V rms I to II
Climatic Classification
40/105/21
Pollution Degree per DIN VDE 0110, Table 1 2
Maximum Working Insulation Voltage VIORM 565 V peak
Input-to-Output Test Voltage, Method b1 VIORM × 1.875 = Vpd(m), 100% production test,
tini = tm = 1 sec, partial discharge < 5 pC
Vpd(m) 1059 V peak
Input-to-Output Test Voltage, Method a
After Environmental Tests Subgroup 1
VIORM × 1.5 = Vpd(m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
V
pd(m)
848
V peak
After Input and/or Safety Test Subgroup 2
and Subgroup 3
VIORM × 1.2 = Vpd(m), tini = 60 sec, tm = 10 sec,
partial discharge < 5 pC
Vpd(m) 678 V peak
Highest Allowable Overvoltage VIOTM 5000 V peak
Surge Isolation Voltage VIOSM(TEST) = 10 kV, 1.2 µs rise time, 50 µs, 50% fall
time
VIOSM 6250 V peak
Safety Limiting Values Maximum value allowed in the event of a failure
(see Figure 2)
Case Temperature TS 150 °C
Safety Total Dissipated Power IS1 1.4 W
Insulation Resistance at T
S
V
IO
= 500 V
R
S
>109
Ω
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
00
200150100
50
12367-002
SAFE LIMITING POWER (W)
AMBI E NT TE M P E RATURE ( °C)
Figure 2. Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN V VDE V 0884-10
RECOMMENDED OPERATING CONDITIONS
Table 14.
Parameter Symbol Min Max Unit
Operating Temperature Range TA −40 +125 °C
Supply Voltage Range1 VDD1, VDD2 3.0 5.5 V
Input Signal Rise/Fall Times 1.0 ms
1 See the DC Correctness and Magnetic Field Immunity section for information
on the immunity to external magnetic fields.
Rev. A | Page 12 of 21
Data Sheet ADuM3150
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 15.
Parameter Rating1
Storage Temperature (TST) Range −65°C to +150°C
Ambient Operating Temperature
(TA) Range
−40°C to +125°C
Supply Voltages (VDD1, VDD2) −0.5 V to +7.0 V
Input Voltages (VIA, VIB, MCLK, MO,
SO, MSS)
−0.5 V to VDDx + 0.5 V
Output Voltages (SCLK, DCLK, SSS,
MI, SI, VOA, VOB)
−0.5 V to VDDx + 0.5 V
Average Output Current per Pin2 −10 mA to +10 mA
Common-Mode Transients3 −100 kV/μs to +100 kV/μs
1 VDDx = VDD1 or VDD2.
2 See Figure 2 for maximum safety rated current values across temperature.
3 Refers to common-mode transients across the insulation barrier. Common-
mode transients exceeding the absolute maximum ratings may cause
latch-up or permanent damage.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Table 16. Maximum Continuous Working Voltage1
Parameter Max Unit Constraint
AC 60 Hz RMS
Voltage
400 V rms 20 year lifetime at 0.1% failure
rate, zero average voltage
DC Voltage 722 V peak Limited by the creepage of the
package, Pollution Degree 2,
Material Group II2, 3
1 See the Insulation Lifetime section for details.
2 Other pollution degree and material group requirements yield a different
limit.
3 Some system level standards allow components to use the printed wiring
board (PWB) creepage values. The supported dc voltage may be higher for
those standards.
ESD CAUTION
Rev. A | Page 13 of 21
ADuM3150 Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
V
DD1 1
GND
12
MCLK
3
MO
4
20
19
18
17
MI
5
MSS
6
V
IA 7
16
15
14
V
OB 813
DCLK
912
GND
1
V
DD2
GND
2
SCLK
SI
SO
SSS
V
OA
V
IB
NIC
GND
2
10 11
NIC = NO I NTERNAL CONNECTION. THIS PIN
IS NOT INT E RNALLY CONNE CTED AND
SERVES NO FUNCT IO N.
12367-003
ADuM3150
(No t t o Scal e)
TOP VIEW
Figure 3. Pin Configuration
Table 17. Pin Function Descriptions
Pin No. Mnemonic Direction Description
1 VDD1 Power Input Power Supply for Side 1. A bypass capacitor from VDD1 to GND1 to local ground is required.
2,10 GND1 Return Ground 1. Ground reference for Isolator Side 1.
3 MCLK Clock SPI Clock from the Master Controller.
4 MO Input SPI Data from the Master MO/SI Line.
5 MI Output SPI Data from Slave to the Master MI/SO Line.
6 MSS Input Slave Select from the Master. This signal uses an active low logic. The slave select pin may require as
much as 10 ns setup time from the next clock or data edge, depending on speed grade.
7
V
IA
Input
Low Speed Data Input A.
8 VOB Output Low Speed Data Output B.
9 DCLK Output Delayed Clock Output. This pin provides a delayed copy of the MCLK.
11,19 GND2 Return Ground 2. Ground reference for Isolator Side 2.
12 NIC None No Internal Connection. This pin is not internally connected and serves no function in the ADuM3150.
13 VIB Input Low Speed Data Input B.
14
V
OA
Output
Low Speed Data Output A.
15 SSS Output Slave Select to the Slave. This signal uses an active low logic.
16 SO Input SPI Data from the Slave to the Master MI/SO Line.
17 SI Output SPI Data from the Master to the Slave MO/SI Line.
18 SCLK Output SPI Clock from the Master Controller.
20
V
DD2
Power
Input Power Supply for Side 2. A bypass capacitor from V
DD2
to GND
2
to local ground is required.
Table 18. Power Off Default State Truth Table (Positive Logic)1
VDD1 State VDD2 State Side 1 Outputs Side 2 Outputs SSS Notes
Unpowered Powered Z Z Z Outputs on an unpowered side are high impedance within
one diode drop of ground
Powered Unpowered Z Z Z Outputs on an unpowered side are high impedance within
one diode drop of ground
1 Z is high impedance.
Rev. A | Page 14 of 21
Data Sheet ADuM3150
TYPICAL PERFORMANCE CHARACTERISTICS
0
1
2
3
4
5
7
6
020 40 60 80
DATA RATE (Mbp s)
3.3V
5.0V
12367-004
DYNAMIC SUPPLY CURRE NT
PER I NP UT CHANNEL (mA)
Figure 4. Typical Dynamic Supply Current per Input Channel vs. Data Rate for
5.0 V and 3.3 V Operation
12367-005
0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
020 40 60 80
DATA RATE (Mbp s)
3.3V
5.0V
DYNAMIC SUPPLY CURRE NT
PER O UTPUT CHANNEL (mA)
Figure 5. Typical Dynamic Supply Current per Output Channel vs. Data Rate
for 5.0 V and 3.3 V Operation
0
5
10
15
20
25
35
30
020 40 60 80
I
DD1
SUPPLY CURRE NT (mA)
DATA RATE (M bp s)
3.3V
5.0V
12367-006
Figure 6. Typical IDD1 Supply Current vs. Data Rate for 5.0 V and 3.3 V Operation
0
5
10
15
20
25
020 40 60 80
I
DD2
SUPPLY CURRENT (mA)
DATA RATE (Mbp s)
3.3V
5.0V
12367-007
Figure 7. Typical IDD2 Supply Current vs. Data Rate for 5.0 V and 3.3 V Operation
0
2
4
6
8
10
12
14
16
–40 10 60 110
PROPAGATION DELAY (n s)
AMBIENT TEMPERATURE (° C)
3.3V
5.0V
12367-008
Figure 8. Typical Propagation Delay vs. Ambient Temperature for High Speed
Channels Without Glitch Filter (See the High Speed Channels Section for
Additional Information)
–40 10 60 110
AMBIENT TEMPERATURE (° C)
3.3V
5.0V
0
5
10
15
20
25
PROPAGATION DELAY (n s)
12367-009
Figure 9. Typical Propagation Delay vs. Ambient Temperature for High Speed
Channels with Glitch Filter (See the High Speed Channels Section for
Additional Information)
Rev. A | Page 15 of 21
ADuM3150 Data Sheet
APPLICATIONS INFORMATION
INTRODUCTION
The ADuM3150 is part of a family of devices created to optimize
isolation of SPI for speed and provide additional low speed
channels for control and status monitoring functions. The
isolators are based on differential signaling iCoupler technology
for enhanced speed and noise immunity.
High Speed Channels
The ADuM3150 has four high speed channels. The first three,
CLK, MI/SO, and MO/SI (the slash indicates the connection of
the particular input and output, forming a datapath across the
isolator that corresponds to an SPI bus signal), are optimized
for either low propagation delay in the B grade, or high noise
immunity in the A grade. The difference between the grades is
the addition of a glitch filter to these three channels in the A
grade version, which increases propagation delay. The B grade
version, with a maximum propagation delay of 14 ns, supports a
maximum clock rate of 17 MHz in a standard 4-wire SPI.
However, because the glitch filter is not present in the B grade
version, ensure that spurious glitches of less than 10 ns are not
present.
Glitches of less than 10 ns in the B grade devices can cause the
second edge of the glitch to be missed. This pulse condition is
seen as a spurious data transition on the output that is corrected
by a refresh or the next valid data edge. It is recommended to
use A grade devices in noisy environments.
The relationship between the SPI signal paths and the pin
mnemonics of the ADuM3150 and data directions is
summarized in Table 19.
Table 19. Pin Mnemonic Correspondence to SPI Signal Path
Names
SPI Signal Path
Master
Side 1
Data
Direction
Slave
Side 2
CLK MCLK
→
SCLK
MO/SI
MO
→
SI
MI/SO MI
←
SO
SS MSS → SSS
The datapaths are SPI mode agnostic. The CLK and MO/SI SPI
datapaths are optimized for propagation delay and channel-to-
channel matching. The MI/SO SPI datapath is optimized for
propagation delay. The device does not synchronize to the clock
channel, so there are no constraints on the clock polarity or the
timing with respect to the data lines. To allow compatibility
with nonstandard SPI interfaces, the MI pin is always active,
and does not tristate when the slave select is not asserted. This
precludes tying several MI lines together without adding a
tristate buffer or multiplexor.
The SS (slave select bar) is typically an active low signal. It can
have many different functions in SPI and SPI like busses. Many
of these functions are edge triggered; therefore, the SS path
contains a glitch filter in both the A grade and the B grade. The
glitch filter prevents short pulses from propagating to the output
or causing other errors in operation. The MSS signal requires a
10 ns setup time in the B grade prior to the first active clock
edge to allow for the added propagation time of the glitch filter.
Low Speed Data Channels
The low speed data channels are provided as economical
isolated datapaths where timing is not critical. The dc value of
all high and low speed inputs on a given side of the device is
sampled simultaneously, packetized, and shifted across an
isolation coil. The high speed channels are compared for dc
accuracy, and the low speed data is transferred to the appropriate
low speed outputs. The process is then reversed by reading the
inputs on the opposite side of the device, packetizing them, and
sending them back for similar processing. The dc correctness
data for the high speed channels is handled internally, and the
low speed data is clocked to the outputs simultaneously.
This bidirectional data shuttling is regulated by a free running
internal clock. Because data is sampled at discrete times based
on this clock, the propagation delay for a low speed channel is
between 400 ns and 1.7 µs depending on where the input data
edge changes with respect to the internal sample clock.
Figure 10 illustrates the behavior of the low speed channels.
• Point A: The data may change as much as 2.5 µs before it is
sampled, then it takes about 100 ns to propagate to the
output. This appears as 2.5 μs of uncertainty in the
propagation delay time.
• Point B: Data pulses that are less than the minimum low
speed pulse width may not be transmitted at all because
they may not be sampled.
INPUT A
OUTPUT A
SAMPLE CLOCK
OUTPUT CLOCK
AB
AB
12367-010
Figure 10. Low Speed Channel Timing
Rev. A | Page 16 of 21
Data Sheet ADuM3150
Delay Clock
The DCLK function is provided to allow SPI data transfers at
speeds beyond the limitations usually set by propagation delay.
The maximum speed of the clock in a 4-wire SPI application is
set by the requirement that data shifts out on one clock edge
and returning data shifts in on the complementary clock edge.
In isolated systems, the delay through the isolator is significant.
The first clock edge, telling the slave to present its data, must
propagate through the isolator. The slave acts upon it and data
propagates back through the isolator to the master. The data
must arrive back at the master before the complementary clock
edge for the data to shift properly into the master.
For the example shown in Figure 11, if an isolator had a 50 ns
propagation delay, it would require more than 100 ns for the
response from the slave to arrive back at the master. This means
that the fastest clock period for the SPI bus is 200 ns or 5 MHz,
and assumes ideal conditions, such as no trace propagation
delay or delay in the slave for simplicity.
MASTER ISOLATOR SLAVE
CLK
MOSI
MISO
12367-011
Figure 11. Standard SPI Configuration
To avoid this limitation on the SPI clock, a second receive buffer
can be used as shown in Figure 12, together with a clock signal
that is delayed to match the data coming back from the slave.
The proper delay of the clock was accomplished in the past by
sending a copy of the clock back through a matching isolator
channel and using the delayed clock to shift the slave data into a
secondary buffer. Using an extra channel is costly because it
consumes an additional high speed isolator channel.
MASTER ISOLATOR SLAVE
CLK
MOSI
MISO
DCLK
12367-012
Figure 12. High Speed SPI Using Isolation Channel Delay
The ADuM3150 eliminates the need for the extra high speed
channel by implementing a delay circuit on the master side, as
shown in Figure 13. DCLK is trimmed at the production test to
match the round trip propagation delay of each isolator. The
DCLK signal can be used as if the clock signal had propagated
alongside the data from the slave in the scheme outlined
previously.
MASTER
ADuM3150
SLAVE
CLK
MOSI
MISO
DCLK DELAY
12367-013
Figure 13. High Speed SPI Using Precision Clock Delay
This configuration can operate at clock rates of up to 40 MHz.
The MI/SO data is shifted into the secondary receive buffer by
DCLK and then transferred internally by the master to its final
destination. The ADuM3150 does not need to use an extra
expensive isolator channel to achieve these data transfer speeds.
Note that the SS channel is not shown here for clarity.
PRINTED CIRCUIT BOARD (PCB) LAYOUT
The ADuM3150 digital isolator requires no external interface
circuitry for the logic interfaces. Power supply bypassing is
strongly recommended at both input and output supply pins:
VDD1 and VDD2 (see Figure 14). The capacitor value must be
between 0.01 µF and 0.1 µF. The total lead length between both
ends of the capacitor and the input power supply pin should not
exceed 20 mm.
BYPASS < 2mm
12367-014
VDD1
GND1
MCLK
MO
MI
MSS
VIA
VOB
VDD2
GND2
SCLK
SI
SO
SSS
VOA
VIB
DCLK
GND1
NIC
GND2
ADuM3150
Figure 14. Recommended PCB Layout
In applications involving high common-mode transients, it is
important to minimize board coupling across the isolation barrier.
Furthermore, design the PCB layout so that any coupling that
does occur equally affects all pins on a given component side.
Failure to ensure this may cause voltage differentials between
pins exceeding the absolute maximum ratings of the device,
thereby leading to latch-up or permanent damage.
Rev. A | Page 17 of 21
ADuM3150 Data Sheet
PROPAGATION DELAY RELATED PARAMETERS
Propagation delay is a parameter that describes the time it takes
a logic signal to propagate through a component. The input-to-
output propagation delay time for a high-to-low transition can
differ from the propagation delay time of a low-to-high
transition.
INPUT
OUTPUT
tPLH tPHL
50%
50%
12367-015
Figure 15. Propagation Delay Parameters
Pulse width distortion is the maximum difference between
these two propagation delay values, and an indication of how
accurately the timing of the input signal is preserved.
Channel-to-channel matching refers to the maximum amount
the propagation delay differs between channels within a single
ADuM3150 component.
DC CORRECTNESS AND MAGNETIC FIELD
IMMUNITY
Positive and negative logic transitions at the isolator input cause
narrow (~1 ns) pulses to be sent via the transformer to the decoder.
The decoder is bistable and is, therefore, either set or reset by
the pulses indicating input logic transitions. In the absence of
logic transitions at the input for more than ~1.2 µs, a periodic
set of refresh pulses indicative of the correct input state are sent
via the low speed channel to ensure dc correctness at the output.
If the low speed decoder receives no pulses for more than
approximately 5 µs, the input side is assumed to be unpowered or
nonfunctional, in which case, the isolator output is forced to a
high-Z state by the watchdog timer circuit.
The limitation on the magnetic field immunity of the device is
set by the condition in which induced voltage in the transformer
receiving coil is sufficiently large to either falsely set or reset the
decoder. The following analysis defines such conditions. The
ADuM3150 is examined in a 3 V operating condition because it
represents the most susceptible mode of operation for this product.
The pulses at the transformer output have amplitudes greater
than 1.5 V. The decoder has a sensing threshold of about 1.0 V,
therefore establishing a 0.5 V margin in which induced voltages
are tolerated. The voltage induced across the receiving coil is
given by
V = (−dβ∕dt)∑πrn2; n = 1, 2, …, N
where:
β is the magnetic flux density.
rn is the radius of the nth turn in the receiving coil.
N is the number of turns in the receiving coil.
Given the geometry of the receiving coil in the ADuM3150 and
an imposed requirement that the induced voltage be, at most,
50% of the 0.5 V margin at the decoder, a maximum allowable
magnetic field is calculated as shown in Figure 16.
MAG NETI C FI E LD F RE QUENCY ( Hz )
MAXIMUM ALLOWABLE MAGNETIC FLUX
DENSI TY ( kgau ss)
1k
0.001
100
100M
10
1
0.1
0.01
10k 100k 1M 10M
12367-016
Figure 16. Maximum Allowable External Magnetic Flux Density
For example, at a magnetic field frequency of 1 MHz, the
maximum allowable magnetic field of 0.5 kgauss induces
a voltage of 0.25 V at the receiving coil. This is about 50% of the
sensing threshold and does not cause a faulty output transition.
If such an event occurs, with the worst-case polarity, during a
transmitted pulse, it would reduce the received pulse from >1.0 V
to 0.75 V. This is still well above the 0.5 V sensing threshold of
the decoder.
The preceding magnetic flux density values correspond to specific
current magnitudes at given distances away from the ADuM3150
transformers. Figure 17 expresses these allowable current magni-
tudes as a function of frequency for selected distances. The
ADuM3150 is very insensitive to external fields. Only extremely
large, high frequency currents very close to the component may
potentially be concerns. For the 1 MHz example noted, placing
a 1.2 kA current 5 mm away from the ADuM3150 affects
component operation.
MAG NETI C FI E LD F RE QUENCY ( Hz )
MAXI MUM AL LO WABL E CURRE NT (kA)
1000
100
10
1
0.1
0.011k 10k 100M100k 1M 10M
DISTANCE = 5mm
DISTANCE = 1m
DISTANCE = 100mm
12367-017
Figure 17. Maximum Allowable Current for
Various Current to ADuM3150 Spacings
Note that at combinations of strong magnetic field and high
frequency, any loops formed by PCB traces may induce
sufficiently large error voltages to trigger the thresholds of
succeeding circuitry. Take care to avoid PCB structures that
form loops.
Rev. A | Page 18 of 21
Data Sheet ADuM3150
POWER CONSUMPTION
The supply current at a given channel of the ADuM3150
isolator is a function of the supply voltage, the data rate of the
channel, and the output load of the channel and whether it is a
high or low speed channel.
The low speed channels draw a constant quiescent current
caused by the internal ping-pong datapath. The operating
frequency is low enough that the capacitive losses caused by the
recommended capacitive load are negligible compared to the
quiescent current. The explicit calculation for the data rate is
eliminated for simplicity, and the quiescent current for each side
of the isolator due to the low speed channels can be found in
Table 3, Ta ble 5, Table 7, and Table 9 for the particular operating
voltages. These quiescent currents add to the high speed current
as shown in the following equations for the total current for
each side of the isolator. Dynamic currents are from Table 3 and
Table 5 for the respective voltages.
For Side 1, the supply current is given by
IDD1 = IDDI(D) × (fMCLK + fMO + fMSS) +
fMI × (IDDO(D) + ((0.5 × 10−3) × CL(MI) × VDD1)) +
fDCLK × (IDDO(D) + ((0.5 × 10−3) × CL(DCLK) × VDD1))
+ IDD1(Q)
For Side 2, the supply current is given by
IDD2 = IDDI(D) × fSO +
fSCLK × (IDDO(D) + ((0.5 × 10−3) × CL(SCLK) × VDD2)) +
fSI × (IDDO(D) + ((0.5 × 10−3) × CL(SI) × VDD2)) +
fSSx × (IDDO(D) + ((0.5 × 10−3) × CL(SSx) × VDD2)) + IDD2(Q)
where:
IDDI(D), IDDO(D) are the input and output dynamic supply currents
per channel (mA/Mbps).
CL(x) is the load capacitance of the specified output (pF).
VDDx is the supply voltage of the side being evaluated (V).
fx is the logic signal data rate for the specified channel (Mbps).
IDD1(Q), IDD2(Q) are the specified Side 1 and Side 2 quiescent
supply currents (mA).
Figure 4 and Figure 5 show the supply current per channel as a
function of data rate for an input and unloaded output. Figure 6
and Figure 7 show the total IDD1 and IDD2 supply current as a
function of data rate for ADuM3150 channel configurations
with all high speed channels running at the same speed and the
low speed channels at idle.
INSULATION LIFETIME
All insulation structures eventually break down when subjected
to voltage stress over a sufficiently long period. The rate of
insulation degradation is dependent on the characteristics of the
voltage waveform applied across the insulation as well as on the
materials and material interfaces.
There are two types of insulation degradation of primary interest:
breakdown along surfaces exposed to the air and insulation
wear out. Surface breakdown is the phenomenon of surface
tracking and the primary determinant of surface creepage
requirements in system level standards. Insulation wear out is
the phenomenon where charge injection or displacement
currents inside the insulation material cause long-term
insulation degradation.
Surface Tracking
Surface tracking is addressed in electrical safety standards by
setting a minimum surface creepage based on the working
voltage, the environmental conditions, and the properties of the
insulation material. Safety agencies perform characterization
testing on the surface insulation of components that allows the
components to be categorized in different material groups.
Lower material group ratings are more resistant to surface
tracking and therefore can provide adequate lifetime with
smaller creepage. The minimum creepage for a given working
voltage and material group is in each system level standard and
is based on the total rms voltage across the isolation, pollution
degree, and material group. The material group and creepage
for the ADuM3150 isolator is presented in Table 12.
Insulation Wear Out
The lifetime of insulation caused by wear out is determined by
its thickness, material properties, and the voltage stress applied.
It is important to verify that the product lifetime is adequate at
the application working voltage. The working voltage supported
by an isolator for wear out may not be the same as the working
voltage supported for tracking. It is the working voltage
applicable to tracking that is specified in most standards.
Testing and modeling have shown that the primary driver of long-
term degradation is displacement current in the polyimide
insulation causing incremental damage. The stress on the
insulation can be broken down into broad categories, such as:
dc stress, which causes very little wear out because there is no
displacement current, and an ac component time varying
voltage stress, which causes wear out.
The ratings in certification documents are usually based on
60 Hz sinusoidal stress because this reflects isolation from line
voltage. However, many practical applications have combinations
of 60 Hz ac and dc across the barrier as shown in Equation 1.
Because only the ac portion of the stress causes wear out, the
equation can be rearranged to solve for the ac rms voltage, as is
shown in Equation 2. For insulation wear out with the
polyimide materials used in this product, the ac rms voltage
determines the product lifetime.
22
DC
RMSACRMS VVV +=
(1)
or
22
DCRMSRMSAC
VVV −=
(2)
where:
VAC RMS is the time varying portion of the working voltage.
VDC is the dc offset of the working voltage.
VRMS is the total rms working voltage.
Rev. A | Page 19 of 21
ADuM3150 Data Sheet
Calculation and Use of Parameters Example
The following is an example that frequently arises in power
conversion applications. Assume that the line voltage on one
side of the isolation is 240 VAC RMS and a 400 VDC bus voltage is
present on the other side of the isolation barrier. The isolator
material is polyimide. To establish the critical voltages in
determining the creepage clearance and lifetime of a device, see
Figure 18 and the following equations.
ISOLATION VOLTAGE
TIME
V
AC RMS
V
RMS
V
DC
12367-018
V
PEAK
Figure 18. Critical Voltage Example
The working voltage across the barrier from Equation 1 is
22
DCRMSACRMS VVV +=
22 400240 +=
RMS
V
VRMS = 466 V
This is the working voltage used together with the material
group and pollution degree when looking up the creepage
required by a system standard.
To determine if the lifetime is adequate, obtain the time varying
portion of the working voltage. The ac rms voltage can be
obtained from Equation 2.
22
DC
RMS
RMSAC
V
V
V−
=
22
400466 −=
RMSAC
V
VAC RMS = 24 V rms
In this case, ac rms voltage is simply the line voltage of 240 V rms.
This calculation is more relevant when the waveform is not
sinusoidal. The value is compared to the limits for working
voltage in Tabl e 16 for expected lifetime, less than a 60 Hz sine
wave, and it is well within the limit for a 50 year service life.
Note that the dc working voltage limit in Table 16 is set by the
creepage of the package as specified in IEC 60664-1. This value
may differ for specific system level standards.
Rev. A | Page 20 of 21
Data Sheet ADuM3150
OUTLINE DIMENSIONS
COMPLIANT TO JE DE C S TANDARDS MO-150- AE
060106-A
20 11
10
1
7.50
7.20
6.90
8.20
7.80
7.40
5.60
5.30
5.00
SEATING
PLANE
0.05 M IN
0.65 BSC
2.00 M AX
0.38
0.22
COPLANARITY
0.10
1.85
1.75
1.65
0.25
0.09
0.95
0.75
0.55
8°
4°
0°
Figure 19. 20-Lead Shrink Small Outline Package [SSOP]
(RS-20)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
No. of
Inputs,
VDD1 Side
No. of
Inputs,
VDD2 Side
Maximum
Data Rate
(MHz)
Maximum
Propagation
Delay, 5 V (ns)
Isolation
Rating
(V ac)
Temperature
Range
Package
Description
Package
Option
ADuM3150ARSZ 4 2 10 25 3750 −40°C to +125°C 20-Lead SSOP RS-20
ADuM3150ARSZ-RL7 4 2 10 25 3750 −40°C to +125°C 20-Lead SSOP,
7” Tape and Reel
RS-20
ADuM3150BRSZ 4 2 17 14 3750 −40°C to +125°C 20-Lead SSOP RS-20
ADuM3150BRSZ-RL7 4 2 17 14 3750 −40°C to +125°C 20-Lead SSOP,
7” Tape and Reel
RS-20
EVAL-ADuM3150Z Evaluation Board
1 Z = RoHS Compliant Part.
©2014–2015 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D12367-0-3/15(A)
Rev. A | Page 21 of 21
