To our custo mers,
Old Company Name in Catalogs and Other Documents
On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology
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April 1st, 2010
Renesas Electronics Corporation
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Rev.2.00, Aug.01.2003, page 1 of 9
H5N3003P
Silicon N Channel MOS FET
High Speed Power Switching REJ03G0007-0200Z
(Previous ADE-208-1547A(Z))
Rev.2.00
Aug.01.2003
Features
Low on-resistance
Low leakage current
High Speed Switching
Outline
TO-3P
123
D
S
G
1. Gate
2. Drain (Flange)
3. Source
H5N3003P
Rev.2.00, Aug.01.2003, page 2 of 9
Absolute Maximum Ratings
(Ta = 25°C)
Item Symbol Ratings Unit
Drain to source voltage VDSS 300 V
Gate to source voltage VGSS ±30 V
Drain current ID40 A
Drain peak current ID (pulse) Note1 160 A
Body-drain diode reverse drain
current IDR 40 A
Body-drain diode reverse
drain peak current IDR (pulse) Note1 160 A
Avalanche current IAPNote3 30 A
Channel dissipation PchNote2 150 W
Channel to case Thermal
Impedance θch-c 0.833 °C /W
Channel temperature Tch 150 °C
Storage temperature Tstg –55 to +150 °C
Notes: 1. PW 10 µs, duty cycle 1%
2. Value at Tc = 25°C
3. Tch 150°C
H5N3003P
Rev.2.00, Aug.01.2003, page 3 of 9
Electrical Characteristics
(Ta = 25°C)
Item Symbol Min Typ Max Unit Test Conditions
Drain to source breakdown voltage V(BR)DSS 300 V ID = 10mA, VGS = 0
Zero gate voltage drain current IDSS ——1 µAV
DS = 300V, VGS = 0
Gate to source leak current IGSS ——±0.1µAV
GS = ±30V, VDS = 0
Gate to source cutoff voltage VGS(off) 3.0 4.0 V VDS = 10V, ID = 1mA
Forward transfer admittance |yfs|2035—S I
D = 20A, VDS = 10VNote4
Static drain to source on state
resistance RDS(on) 0.058 0. 069 ID = 20A, VGS= 10VNote4
Input capacitance Ciss 5150 pF VDS = 25V
Output capacitance Coss 560 pF VGS = 0
Reverse transfer capacitance Crss 90 pF f = 1MHz
Turn-on delay time td(on) 60 ns ID= 20A
Rise time tr 185 ns RL = 7.5
Turn-off delay time td(off) 220 ns VGS = 10V
Fall time tf 150 ns Rg=10
Total gate charge Qg 130 nC VDD = 240V
Gate to source charge Qgs 25 nC VGS = 10V
Gate to drain charge Qgd 60 nC ID = 40A
Body–drain diode for ward voltage VDF —1.01.5V I
F = 40A, VGS = 0
Body–drain diode reverse recov ery
time trr 280 ns IF = 40A, VGS = 0
diF/dt=100A/µs
Body–drain diode reverse recov ery
charge Qrr 2.5 µC
Notes: 4. Pulse test
H5N3003P
Rev.2.00, Aug.01.2003, page 4 of 9
Main Characteristics
200
150
100
50
050 100 150 200
300
100
30
10
3
1
1310
30 100 300 1000
100
80
60
40
20
04 8 12 16 20
100
80
60
40
20
02468
10
0.3
0.1
1000
Ta = 25°C
10 V
V
GS
= 5 V
5.5 V
Tc = 75°C
25°C
–25°C
Channel Dissipation Pch (W)
Case Temperature Tc (°C)
Power vs. Temperature Derating
Drain to Source Voltage V
DS
(V)
Drain Current I
D
(A)
Maximum Safe Operation Area
Drain to Source Voltage V
DS
(V)
Drain Current I
D
(A)
Typical Output Characteristics
100 µs
1 ms
PW = 10 ms (1shot)
DC Operation (Tc = 25°C)
10 µs
6 V
7 V
8 V
Operation in
this area is
limited by R
DS(on)
Gate to Source Voltage V
GS
(V)
Drain Current I
D
(A)
Typical Transfer Characteristics
V
DS
= 10 V
Pulse Test
Pulse Test
H5N3003P
Rev.2.00, Aug.01.2003, page 5 of 9
Gate to Source Voltage V
GS
(V)
Drain to Source Saturation Voltage vs.
Gate to Source Voltage
Drain to Source Saturation Voltage
V
DS(on)
(V)
5
4
3
2
1
048
12 16 20 1 5 20 10021050
0.2
0.1
0.05
0.02
0.01
0.2
0.16
0.12
0.08
0.04
–40 0 40 80 120 160
0
0.2 0.5 2 5 20 50 100
100
20
50
5
10
2
0.5
1
0.2 110
25°C
Tc = –25°C
75°C
V = 10 V
GS
10 A
20 A
I = 40 A
D
I = 40 A
D
20 A
10 A
V = 10 V,15 V
GS
Pulse Test
Drain to Source on State Resistance
R
DS(on)
()
Static Drain to Source on State Resistance
vs. Drain Current
Drain Current I
D
(A)
Pulse Test
Case Temperature Tc (°C)
Static Drain to Source on State Resistance
R
DS(on)
()
Static Drain to Source on State Resistance
vs. Temperature
Pulse Test
Drain Current I
D
(A)
Forward Transfer Admittance vs.
Drain Current
Forward Transfer Admittance |yfs| (S)
DS
V = 10 V
Pulse Test
H5N3003P
Rev.2.00, Aug.01.2003, page 6 of 9
Switching Time t (ns)
Drain Current ID (A)
Switching Characteristics
Typical Capacitance vs.
Drain to Source Voltage
Capacitance C (pF)
Drain to Source Voltage VDS (V)
0.1 0.3 1 3 10 30 100
1000
200
500
100
20
50
10
0 20 40 60 80 100
20000
50000
10000
1000
2000
5000
500
400
300
200
100
0
20
16
12
8
4
40 80 120 160 200
0
10000
1000
10
100
0.1 0.3 1 3 10 30 100
200
500
100
50
V = 50 V
100 V
240 V
DS
V = 0
f = 1 MHz
GS
Ciss
Coss
Crss
I = 40 A
D
V
DD
V
GS
Body-Drain Diode Reverse
Recovery Time
di / dt = 100 A / µs
V = 0, Ta = 25°C
GS
V = 240 V
100 V
50 V
DS
r
t
d(on)
t
d(off)
t
tf
V = 10 V, V = 150 V
PW = 10 µs, duty < 1 %
R =10
GS DD
G
r
t
Reverse Drain Current IDR (A)
Reverse Recovery Time trr (ns)
Gate Charge Qg (nC)
Drain to Source Voltage VDS (V)
Gate to Source Voltage VGS (V)
Dynamic Input Characteristics
tf
H5N3003P
Rev.2.00, Aug.01.2003, page 7 of 9
00.4 0.8 1.2 1.6 2.0
100
80
60
40
20
5
4
3
2
1
-50 0 50 100 150 200
0
Case Temperature Tc (°C)
Gate to Source Cutoff Voltage
vs. Case Temperature
Gate to Source Cutoff Voltage
V (V)
GS(off)
V = 10 V
DS
Vin Monitor
D.U.T.
Vin
10 V
R
L
V
= 150 V
DD
tr
td(on)
Vin
90% 90%
10%
10%
Vout
td(off)
Vout
Monitor
10
90%
10%
t
f
Source to Drain Voltage VSD (V)
Reverse Drain Current IDR (A)
Reverse Drain Current vs.
Source to Drain Voltage
Pulse Test
Switching Time Test Circuit Waveform
V = 0 V
GS
10 V
5 V
I = 10mA
D
1mA
0.1mA
H5N3003P
Rev.2.00, Aug.01.2003, page 8 of 9
3
1
0.3
0.1
0.03
0.01
10 µ100 µ1 m 10 m 100 m 1 10
DM
P
PW
T
D = PW
T
ch – c(t) = s (t) • ch – c
ch – c = 0.833°C/W, Tc = 25°C
θ γ θ
θ
Tc = 25°C
D = 1
0.5
0.2
0.1
0.05
0.02
0.01
1shot pulse
Pulse Width PW
(
s
)
Normalized Transient Thermal Impedance γ s (t)
Normalized Transient Thermal Impedance vs. Pulse Width
H5N3003P
Rev.2.00, Aug.01.2003, page 9 of 9
Package Dimensions
φ3.2 ± 0.2
4.8 ± 0.2
1.5
0.3
2.8
0.6 ± 0.2
1.0 ± 0.2
18.0 ± 0.5 19.9 ± 0.2
15.6 ± 0.3
0.5
1.0
5.0 ± 0.3
1.6
1.4 Max 2.0
2.0
14.9 ± 0.2
3.6 0.9
1.0
5.45 ± 0.55.45 ± 0.5
Package Code
JEDEC
JEITA
Mass
(reference value)
TO-3P
Conforms
5.0 g
As of January, 2003
Unit: mm
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them. Trouble with semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of
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