316144-07
July 2010
Numonyx® Omneo™ P8P PCM
128-Mbit Parallel Phase Change Memory
Datasheet
Product Features
High Performance Read/Write
— 115 ns initial read access
— 135 ns initial read access
— 25 ns 8-word asynchronous-page read
Architecture
— Asymmetrically-blocked architecture
— Four 32-KByte parameter blocks: top or
bottom configuration
—128-KByte main blocks
— Serial Peripheral Interface (SPI) to enable
lower pin count on-board programming
Phase Change Memory (PCM)
— Chalcogenide phase change storage
element
— Bit alterable write operation
Voltage and Power
—V
CC (core) voltage: 2.7 V – 3.6 V
—V
CCQ (I/O) voltage: 1.7 V – 3.6 V
— Standby current: 80 µA (Typ)
Quality and Reliability
— More than 1,000,000 write cycles
— 90 nm PCM technology
Temperature
— Operating temperature -30 °C to +85 °C
(135ns initial read access)
— Operating temperature 0 °C to +70 °C
(115ns initial read access)
Security
— One-Time Programmable Regi sters:
• 64 unique factory device identifier bits
• 2112 user-programmable OTP bits
— Selectable OTP Space in Main Array:
• Four pre-defined 32-KByte blocks (top or
bottom configuration)
• Three adjacent Main Blocks available for
boot code or other secure information
— Absolute write protection: VPP = VSS
— Power-transition erase/program lockout
— Individual zero-latency block locking
— Individual block lock-down
Simplified Software Management
— No block erase or cleanup required
— Bit “twiddle” in either direction (1:0, 0:1)
— 35 µs (Typ) program suspend
— 35 µs (Typ) erase suspend
— Numonyx™ Flash Data Integr ator optimized
— Scalable Command Set and Extended
Command Set compatible
— Common Flash Interface capable
Density and Packaging
— 128 Mbit density
— 56-Lead TSOP package
— 64-Ball Numonyx Easy BGA package
Datasheet July 2010
2316144-07
Legal Lines and Discla ime rs
INFORMA TION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR
OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND
CONDITIONS OF SALE FOR SUCH PRODUCTS, NUMONYX ASSUMES NO LIABILITY WHAT SOEVER, AND NUMONYX DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY, RELATING TO SALE AND/OR USE OF NUMONYX PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELA TING TO FITNESS FOR A
PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Numonyx
products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.
Numonyx B.V. may make changes to specifications and product descriptions at any time, without notice.
Numonyx B.V. may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that rela te to the prese nted
subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel or
otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.
Designers must not rely on the absence or characteristics of any features or ins tructi ons mark ed “r eserve d” or “u ndefin ed.” Numonyx reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Contact your local Numonyx sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Numonyx literature may be obtained by visiting the
Numonyx webbiest at http://www.numonyx.com.
Numonyx, the Numonyx logo, StrataFlash, Axcell, Forté, and Omneo are trademarks or registered trademarks of Numon y x B.V. or its subsidiaries in
other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2010, Numonyx, B.V., All Rights Reserved.
July 2010 Datasheet
316144-07 3
Numonyx® Omneo™ P8P Datasheet
1.0 Product Description...................................................................................................6
1.1 Introduction .......................................................................................................6
1.2 Product Overview................................................................................................7
1.3 Memory Map............. .......... .. ........... .......... ... .......... ........... .. .......... ........... .. ........9
2.0 Package Information...............................................................................................11
2.1 56-Lead TSOP...................................................................................................11
2.2 64-Ball Easy BGA Package..................................................................................12
3.0 Pinouts and Ballouts................................................................................................14
4.0 Signals ....................................................................................................................16
5.0 Bus Operations........................................................................................................17
5.1 Reads..............................................................................................................17
5.2 Writes..............................................................................................................17
5.3 Output Disable............ .. ........... .. .......... ........... .. .......... .. ........... .. ........... .......... ..17
5.4 Standby...........................................................................................................17
5.5 Reset...............................................................................................................18
6.0 Command Set ..........................................................................................................19
6.1 Device Command Cod e s............ .......... .. ........... .. .......... ........... .. ........... .. .......... ..19
6.2 Device Command Bus Cycle s ........... .......... .. ... .......... .. .. ........... .. ........... .. .. ..........20
7.0 Read Operation........................................................................................................22
7.1 Read Array Command............... .. .. .......... .. ........... .......... ... .......... .. ........... .. ........22
7.2 Read Identifier C ommand.......... .. .......... .. ........... .. .. ........... .. .......... .. ........... .. ......22
7.3 Read Query Command........................ ........... .. .......... .. ........... .. ........... .. .......... ..23
7.4 Other ID Mode Data...........................................................................................23
7.5 Query (CFI) Data ..............................................................................................23
8.0 Program Operations ................................................................................................24
8.1 Word Program ..................................................................................................24
8.2 Bit Alterable Word Write Command......................................................................25
8.3 Buffered Program Command. .. ... .......... .. .. ........... .. .. ........... .. .......... .. .. ........... .. .. ..25
8.4 Bit Alterable Buffer Write....................................................................................26
8.5 Bit Alterable Buffer Program ...............................................................................26
8.6 Program Suspend..............................................................................................27
8.7 Program Resume...............................................................................................27
8.8 Program Protection............................................................................................27
9.0 Erase.......................................................................................................................28
9.1 Block Erase ......................................................................................................28
9.2 Erase Suspend Command...................................................................................28
9.3 Erase Resume...................................................................................................29
10.0 Security Mode..........................................................................................................30
10.1 Block Locking....................................................................................................30
10.2 Permanent One Time Programmable (OTP) Block Locking .......................................33
11.0 Registers.................................................................................................................36
11.1 Read Status Regi ster ... .......... ... .. .......... ........... .. .......... .. ........... .. ........... .. ..........36
11.2 System Protection Registers ...............................................................................37
12.0 Serial Peripheral Interface (SPI) .............................................................................40
12.1 SPI Overview...................... .. ........... .......... ... .......... ........... .. .......... ........... .. ......40
12.2 SPI Signal Names............ .. ........... .. .. .......... ... .......... .. ........... .. .......... ... .......... .. ..40
12.3 SPI Memory Orginization........... .......... .. .. ........... .. .. ........... .. .. .......... .. ... .......... .. ..41
Numonyx® Omneo™ P8P Datasheet
Datasheet July 2010
4316144-07
12.4 SPI Instruction..................................................................................................43
13.0 Power and Reset Specification .................................................................................56
13.1 Power-Up and Powe r-Down................ .. .......... ... .......... .. ........... .......... .. ........... .. ..56
13.2 Reset Specifications ...........................................................................................56
13.3 Power Suppl y De coupling......................... .. ........... .. .. ........... .. .......... .. ........... .. ....57
14.0 Max Ratings and Operating Conditions.....................................................................58
14.1 Absolute Maximum Ratings .................................................................................58
14.2 Operating Conditions..........................................................................................58
14.3 Endurance ........................................................................................................59
15.0 Electrical Specifications ...........................................................................................60
15.1 DC Current Characteristics....................... ...........................................................60
15.2 DC Voltage Char acte ristics............. .. .......... .. .. ........... .. ........... .. .. .......... ... .. ..........61
16.0 AC Characteristics....................................................................................................62
16.1 AC Test Conditions................... ........... .. ........... .. .......... .. ........... .......... ... .......... ..62
16.2 Capacitance ......................................................................................................62
16.3 AC Read Specifications ........... .. ... .. .......... .. ........... .. .. ........... .. .......... .. .. ........... .. ..63
16.4 AC Write Specifications...................... .. .. ........... .. .......... .. .. ........... .. .. ........... .. ......65
16.5 SPI AC Specifications .........................................................................................68
17.0 Program and Erase Characteristics...........................................................................71
18.0 Ordering Information...............................................................................................72
A Supplemental Reference Information.......................................................................73
A.1 Flow Charts.......................................................................................................73
A.2 Write State Machine...........................................................................................80
A.3 Common Flash Interface.....................................................................................84
July 2010 Datasheet
316144-07 5
Numonyx® Omneo™ P8P Datasheet
Revision History
Date Revision Description
December 14th, 2006 0 Initial Advance Information Datasheet
March, 2007 1 Advance Information Datasheet
July, 2007 2
Fixed the spelling error and deleted a repeated sentence on page 10
Added Section 2.3 “64-Ball EBGA Package” on pag e 12
Added Figure 1 “EBGA Mechanical Specifications” on page 12
Added Table 1 “EBGA Package Dimensions” on page 12
Added note 6 on page 67
Updated note 5 on page 68
Fixed an error on the A33 Device Code on page 93 “from 881E8 Hex, to 881E Hex”
April 2008 03 Applied Numonyx branding.
February 200906 04
Changed the Operating Temperature on the Title page as well as Table 19
Changed the Writing Endurance to 100,000
No Read while at Streaming Mode in Section 4.4
Changed the stand by current to 160usec in Section 7.2
Added note 5 in Table 19 footnotes
Changed the read latency to 115nsec. Also, changed the values of R1 and R2 to 115nsec in
Section 7.4
July 2009 05
Removed Numonyx Confidential
Removed Streaming Mode references
Changed all A33 references to P8P
Revised Easy BGA Package Dimensions (Table 4)
Revised SPI Section (Ch-12)
Changes Erase & Program Suspend Specification
Changed P2 Specification
Changed W250 non-streaming mode legacy programming
Applied Numonyx DS formatting
April 2010 06
Added Numonyx® Omneo™ Branding
Added Program on all 1’s command (D1h) to Table- 20
Added Edurance table to operating co nditions section
Updated AC/DC Specifications: P3 (max), ICCS (typ), ICCS/ICCD/ICCES/ICCWS (typ), ICCR
(typ/max), Capacitance ( max), tCLQV (max), tHHQX (max), Buffer Program (ty p/max), Block
Erase (typ/max), Suspend Latency (max)
July 2010 07
Added -30 to +85C (Cover Page, Section 14)
Added 32-Byte alignment Note to Program Operation (Section 8)
Removed Storage Temp Range (Section 14)
Revised AC Read Spec for -30 to +85C (Section 16.3)
Revised SPI AC Spec for -30 to +85C (Section 16.5)
Revised Ordering INformation (Section 18)
Numonyx® Omneo™ P8P Datasheet
Datasheet July 2010
6316144-07
1.0 Product Description
1.1 Introduction
Numonyx® Omneo™ Phase Change Memory for embedded applications offers all of the
best attributes from other memory types in a new, highly scalable and flexible
technology.
Phase Change Memory (PCM) is a new type of nonv olatile semiconductor memory that
stores information through a reversible structural phase change in a chalcogenide
material. The material exhibits a change in material properties, both electrical and
optical, when changed from the amorphous (disordered) to the polycrystalline
(regularly ordered) state. In the case of Phase Change Memory, information is stored
via the change in resistance the chalcogenide material experiences upon undergoing a
phase change. The material also changes optical properties after experiencing a phase
change, a characteristic that has been successfully mastered for use in current
rewritable optical storage devices such as rewritable CDs and DVDs.
The PCM storage element consists of a thin film of chalcogenide contacted by a resistive
heating element. In PCM, the phase change is induced in the memory cell by highly
localized Joule heating caused by an induced current at the m aterial junction . During a
write operation, a small volume of the chalcogenide material is made to ch ange phase.
The phase change is a reversible process, and is modulated by the magnitude of
injected current, the applied voltage, and the duration of the heating pulse.
PCM combines the benefits of traditional floating gate flash, both NOR-type and NAND-
type, with some of the key attributes of RAM and EEpROM. Like NOR flash and RAM
technology, PCM offers fast random access times. Like NAND flash, PCM has the ability
to write moderately fast. And like RAM and EEpROM, PCM supports bit alterable writes
(overwrite). Unlike flash, no separate erase step is required to change information from
0 to 1 and 1 to 0. Unlike RAM, however, the technology is nonvolatile with data
retention comparable NOR flash. However, at the current time, PCM technology appears
to have a write cycling endur ance better than that of NAND or NOR flash, but less than
that of RAM.
Unlike other proposed alternative memories, PCM technology uses a conventional
CMOS process with the addition of a few additional layers to form the memory storage
element. Overall, the basic memory manufacturing process used to make PCM is less
complex than that of NAND, NOR or DRAM.
Historically, systems have adopted many different types of memory to meet different
needs within a design. Some systems might include boot memory, configuration
memory, data storage memory, high speed execution memory, and dynamic working
memory. The demands of many of today’ s designs require better performance from the
memory subsystem and a reduction in the overall component count. PCM provides
many of the attributes of different kinds of memory found in a typical design, enabling
the opportunity to consolidate or eliminate of different types of memory.
The combination of fast random access with high speed, bit alterable writes in a
nonvolatile memory is a capability only offered in complex, low density technologies
such as parallel EEpROM or battery-backed RAM. The PCM feature set is intended to
facilitate easy evaluation and adoption in systems and to enable the consolidation of
memory functions into a single device. In some cases, PCM may enable new usages or
new solutions to existing problems, in a manner that is more efficient, higher
performance and/or more cost effective.
July 2010
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Numonyx® Omneo™ P8P Datasheet
1.2 Product Overview
The Numonyx® Omneo™ P8P PCM provides the convenience and ease of NOR flash
emulation while providing a set of Super Set features that exploit the inherent
capabilities of the PCM technology. The device emulates most of the features of the
Numonyx™ Axcel™ Embedded Memory (P33). This is intended to ease the evaluation
and design of Numonyx® Omneo™ P8P PCM into existing hardware and software
development platforms. This basic features set is supplemented by the Super Set
Features. The Super Set Features are intended to allow the designer to exploit the
inherent capabilities of the phase change memory technology, and to enable the
eventual simplification of hardware and software in the design. This section describes
an overview of the features and capabilities of Numonyx® Omneo™ P8P PCM.
•Density: Numonyx® Omneo™ P8P PCM product family begins with a 128-Mbit
density.
•Packages: Numonyx® Omneo™ P8P PCM devices are available in 64 Ball Easy
BGA and 56 Lead TSOP packages. These ar e the same pinouts and packages as the
existing P33 NOR flash devices.
•Low Power: Designed for low voltage systems, Numonyx® Omneo™ P8P PCM
supports read, write and erase operations at a core supply of 2.7V VCC. P8P offers
additional power savings through standby mode. Standby mode is initiated when
the system deselects the device by driving CE inactive, which significantly reduces
power consumption.
•NOR-Compatible Program and Emulated Erase Operation: Numonyx®
Omneo™ P8P PCM provides a complete set of commands that are compatible with
industry-standard command sequences used by NOR-type flash. An internal Write
State Machine (WSM) automatically executes the algorithms and timings necessary
for block erase and write. Each emulated block erase operation results in the
contents of the addressed block being written to all “1s” (ones). Data can be
programmed in word or buffer increments. Erase-suspend allows system software
to pause an erase command so it can read or program data in another block.
Program suspend allows system software to pause programming so it can read
from other locations within the device. The Status Re gister indicates when the
WSM’s block erase, or progra m operation is finished.
•Write Buffer: A 64 byte/32 word Write Buffer is also included to allow optimum
write performance. By using the write buffer, data is overwritten or programmed in
buffer increments. This feature improves system program performance more than
20 times over independent byte writes.
•Command User Interface: As with floating gate flash, a Command User Interface
(CUI) serves as the interface between the system processor and internal oper ation
of the device. A valid command sequence written to the CUI initiates device
automation.
•Data Protection: Numonyx® Omneo™ P8P PCM block locking enables zero-
latency block locking/unlocking and permanent locking. Permanent block locking
provides enhanced security for boot code. The combination of these two locking
features provides complete locking solution for code and data.
•CFI Compliant: A flash-compatible Common Flash Interface (CFI) permits
software algorithms to be used for entire families of devices. This allows device-
independent, JEDEC ID-independent, and forward- and backward-compatible
software support for the specified flash device families.
Numonyx® Omneo™ P8P Datasheet
Datasheet July 2010
8316144-07
•Bit Alterability or Overwrite: PCM technology supports the ability to change
each memory bit independently from 0 to 1 or 1 to 0 without an intervening block
erase operation. Bit Alterability enables software to write to the non-volatile
memory in a similar manner as writing to RAM or EEpROM without the overhead of
erasing blocks prior to write. Bit Alterable writes use similar command sequences
as word programming and Buffer Programming.
•Serial Peripheral Interface (SPI): SPI allows for in-system programming
through a minimal pin count interface. This interface is provided in addition to a
traditional parallel system interface. This feature has been added to facilitate the
on-board, in-system programming of code into the Numonyx® Omneo™ P8P PCM
device, after it has been soldered to a circuit board. Pre-programming of code prior
to high temperature board attach is not recommended with the P8P device.
Although the device reliability across the operating temperature range is typically
superior to that of floating gate flash, the P8P device may be subject to thermally-
activated distur bs at hig he r temperatures. However, no permanent device damage
occurs during either leaded and lead-free board attach.
July 2010
316144-07 9
Numonyx® Omneo™ P8P Datasheet
1.3 Memory Map
This section cover the memory map for the Top and Bottom boot devices
Table 1: Top Parameter Memory Map
Programming Region
Number Size
(KW) Blk 128-Mbit
7
16 130 7FC000-7FFFFF
16 129 7F8000-7FBFFF
16 128 7F4000-7F7FFF
16 127 7F0000-7F3FFF
64 126 7E0000-7EFFFF
…
…
…
64 112 700000-70FFFF
6
64 111 6F0000-6FFFFF
…
…
…
64 96 600000-60FFFF
5
64 95 5F0000-5FFFFF
…
…
…
64 80 500000-50FFFF
4
64 79 4F0000-4FFFFF
…
…
…
64 64 400000-40FFFF
3
64 63 3F0000-3FFFFF
…
…
…
64 48 300000-30FFFF
2
64 47 2F0000-2FFFFF
…
…
…
64 32 200000-20FFFF
1
64 31 1F0000-1FFFFF
…
…
…
64 16 100000-10FFFF
0
64 15 0F0000-0FFFFF
…
…
…
64 0 000000-00FFFF
Numonyx® Omneo™ P8P Datasheet
Datasheet July 2010
10 316144-07
Table 2: Bottom Parameter Memory Map
Programming Region
Number Size
(KW) Blk 128-Mbit
7
64 130 7F0000-7FFFFF
…
…
…
64 115 700000-70FFFF
6
64 114 6F0000-6FFFFF
…
…
…
64 99 600000-60FFFF
5
64 98 5F0000-5FFFFF
…
…
…
64 83 500000-50FFFF
4
64 82 4F0000-4FFFFF
…
…
…
64 67 400000-40FFFF
3
64 66 3F0000-3FFFFF
…
…
…
64 51 300000-30FFFF
2
64 50 2F0000-2FFFFF
…
…
…
64 35 200000-20FFFF
1
64 34 1F0000-1FFFFF
…
…
…
64 19 100000-10FFFF
0
64 18 0F0000-0FFFFF
…
…
…
64 4 010000-01FFFF
16 3 00C000-00FFFF
16 2 008000-00BFFF
16 1 004000-007FFF
16 0 000000-003FFF
July 2010
316144-07 11
Numonyx® Omneo™ P8P Datasheet
2.0 Package Information
This section covers the mechanical specification for the available packages.
2.1 56-Lead TSOP
Figure 1: TSOP Mechanical Specifications
A
0
L
Detail A
Y
D
C
Z
Pin 1
E
D
1
b
Detail B
See Detail A
e
See Detail B
A
1
Seating
Plane
A
2
See Note 2
See Notes 1 and 3
Table 3: TSOP Package Dimensions (Sheet 1 of 2)
Product Information Symbol Millimeters Inches Notes
Min Nom Max Min Nom Max
Package Height A - - 1.200 - - 0.047
Standoff A10.050 - - 0.002 - -
Package Body Thickness A20.965 0.995 1.025 0.038 0.039 0.040
Lead Width b 0.100 0.150 0.200 0.004 0.006 0.008
Lead Thickness c 0.100 0.150 0.200 0.004 0.006 0.008
Package Body Len gth D118.200 18.400 18.600 0.717 0.724 0.732
Package Body Width E 13.800 14.000 14.200 0.543 0.551 0.559
Numonyx® Omneo™ P8P Datasheet
Datasheet July 2010
12 316144-07
2.2 64-Ball Easy BGA Package
Lead Pitch e - 0.500 - - 0.0197 -
Terminal Dimension D 19.800 20.00 20.2 00 0.780 0.787 0.795
Lead Tip Length L 0.500 0.600 0.700 0.020 0.024 0.028
Lead Count N - 56 - - 56 -
Lead Tip Angle θ0° 3° 5° 0° 3° 5°
Seating Plane Coplanarity Y - - 0.1 00 - - 0.004
Lead to Package Offset Z 0.150 0.250 0.350 0.006 0.010 0.014
Notes:
1. One dimple on package denotes Pin 1.
2. If two dimples, then the larger dimple denotes Pin 1.
3. Pin 1 will always be in the upper left corner of the package, in reference to the product mark.
4. Daisy Chain Evaluation Unit information is at Numonyx® Omneo™ P8P PCM Memory Packaging Technology
Table 3: TSOP Package Dimensions (Sheet 2 of 2)
Product Information Symbol Millimeters Inches Notes
Min Nom Max Min Nom Max
Figure 2: Easy BGA Mechanical Specifications
E
Seating
Plane
S1
S2
e
Top View - Bal l side down Bottom View - Ball Side Up
Y
A
A1
D
Ball A1
Corner
A2
Note: Drawing not t o scale
A
B
C
D
E
F
G
H
87654321
87654321
A
B
C
D
E
F
G
H
b
Bal l A 1
Corner
July 2010
316144-07 13
Numonyx® Omneo™ P8P Datasheet
Table 4: Easy BGA Package Dimensions
Product Information Symbol Millimeters Notes
Min Nom Max
Package Height (128-Mbit) A - - 1.20
Ball Height A1 0.25 - -
Package Body Thickness (128-Mbit) A2 - 0.78 -
Ball (Lead) Width b 0.33 0.43 0.53
Package Body Width D 9.90 10.00 10.10
Package Body Length E 7.90 8.00 8.10
Pitch e - 1.00 -
Ball (Lead) Count N - 64 -
Seating Plane Coplanarity Y - - 0.10
Corner to Ball A1 Distance Along D S1 1.40 1.50 1.60
Corner to Ball A1 Distance Along E S2 0.49 0.50 0.51
Notes:
1. Daisy Chain Evaluation Unit information is at Numonyx® Omneo™ P8P PCM Memory Packaging Technology
Numonyx® Omneo™ P8P Datasheet
Datasheet July 2010
14 316144-07
3.0 Pinouts and Ballouts
Notes:
1. A1 is the least significant address bit to be compatible with x8 addressing s ystems. Even th ough Numonyx® Omneo™ P8P
PCM is a 16 bit data bus.
2. A23 is valid for 128-Mbit densities and above.
Figure 3: 56-Lead TSOP Pinout (128-Mbit)
56-Lead TSOP Pinout
14 m m x 20 m m
Top Vi ew
1
3
4
2
5
7
8
6
9
11
12
10
13
15
16
14
17
19
20
18
21
23
24
22
25
27
28
26
56
54
53
55
52
50
49
51
48
46
45
47
44
42
41
43
40
38
37
39
36
34
33
35
32
30
29
31
NC
A2
A3
A5
A6
A4
A7
A18
A19
A8
A20
WE#
VCC
WP#
VSS
A22
A23
A21
A9
A11
A12
A10
A13
A15
A16
A14
A1
VSS
OE#/HOLD#
CE#/S#
VCC
DQ8
DQ1
DQ0
DQ9
DQ2
DQ10
VCCQ
DQ3
VSS
RST#
DQ11
C
DQ4
DQ12
D
DQ5
DQ6
DQ14
DQ13
DQ7
A17
Q
DQ15
SERIAL
VPP
July 2010
316144-07 15
Numonyx® Omneo™ P8P Datasheet
Figure 4: 64-Ball Easy BGA Ballout (128-Mbit)
Notes:
1. A1 is the least significant address bit to be compatibl e with x8 addressing systems, even though Numo nyx® Omneo™ P8P
PCM is a 16 bit data bus.
2. A23 is valid for 128-Mbit densities
A23
18
234567
Easy BGA
Top View- Ball side down Easy BGA
Bottom View- Ball side up
1
8234
5
67
H
G
F
E
D
C
B
A
A4A5A11Vccq RST#A16A17 Vccq
A1A6A8A13 VppA18A22 Vcc
A3A7A10A15 A12A20A21 WP#
RFU D8D1D9D4 D3D15 C
SERIAL
OE#/
HOLD# D0D10D12 D11QD
WE# RFUD2D5 VccqD14 D6
H
G
F
E
D
C
B
A
A2VssA9A14 CE#/S#A19RFU RFUA2 Vss A9 A14CE#/S# A19 RFURFU
RFU Vssq Vcc D13Vss D7 RFUVssq RFUVssqVccD13 VssD7RFU Vssq
A3 A7 A10 A15A12 A20 A21WP#
A4 A5 A11 VccqRST# A16 A17Vccq
RFUD8 D1 D9 D4D3 D15C
SERIAL OE#/
HOLD#
D0 D10 D12D11 QD
WE#A23 RFU D2 D5Vccq D14D6
A1 A6 A8 A13Vpp A18 A22Vcc
Numonyx® Omneo™ P8P Datasheet
Datasheet July 2010
16 316144-07
4.0 Signals
Table 5: Ball/Pin Descriptions
Symbol Type Name and Function
A[MAX:1] Input ADDRESS INPUTS: Device address inputs. 128-Mbit: A[23:1]
Note: that the address bus for TSOP and Eas y BGA starts at A1. Numonyx® Omneo™ P8P PCM uses x16
addressing. The package is x8 addressing to be compatible with J3 or P30 products.
DQ[15:0] Input/
Output DATA INPUT/OUTPUTS: Inputs data a nd commands du ring writes (internally la tched). Outputs da ta
during read operations. Data signals float when CE# or OE# are VIH. or RST# is VIL.
CE# or S# Input CHIP ENABLE: CE#-low activates internal control logic, I/O buffers, decoders, and sense amps. CE#-
high deselects the device, places it in standby state, and places data outputs at high-Z.
SPI SPI Select: S# low activates command writes to the SPI interface. Rising S# to VIH completes (or
terminates) the SPI command cycle; it also sets Q to high-Z.
OE# or
HOLD# Input OUTPUT ENABLE: Active low OE# enables the device’s output data buffers during a read cycle. With
OE# at VIH, device data outputs are placed in high-Z state.
SPI SPI HO LD#: When asserted, suspends the current cycle and sets Q to high-Z until de-asserted.
RST# Input RESET CHIP: When low, RST# resets internal automation and inhibits write operations. This provides
data protection during power transitions. RST#-high enables normal operation. The device is in 8-Word
page mode array read after reset exits.
WE# Input WRITE ENABLE: controls Command User Interface (CUI) and array writes. Its rising edge latches
addresses and data.
WP# Input
WRITE PROTECT: Disables/enables the lock-down function.
When WP# is VIL, the lock-down mechanism is enabled and software canno t unlock bl ocks mark ed
lock-down.
When WP# is VIH, the lock-down mechanism is disabled and blocks previously locked-down are
now locked; software can unlock and lock them. After WP# goes low, blocks previously marked lock-
down revert to that state.
CSPISPI Clock: Synchronization clock for input and output data
DSPI
SPI Data Input: Serial data input for Op Codes, address and program data bytes. Input data is clock e d
in on the rising edge of C, starting with the MSB.
QSPI
SPI Data Output: Serial data output for read data. Output data is clocked out, triggered by the falling
edge of C, starting with the MSB.
SERIAL SPI
SPI Enable: SERIAL is a port select switching be tween the nor mal paral lel or serial inter face. When Vss,
the normal (non-SPI) Numonyx® O mneo™ P8P PCM interface is enabled; all other SPI inputs are Don't
Care, and Q is at High-Z. When Vcc, SPI mode is enabled, all non-SPI inputs are Don't Care, and all
outputs are at High-Z.
This pin has an internal weak pull down resistor to select the normal parallel interface when users leave
the pin floating. A CAM can be used to permanently disable this feature.
VPP Pwr
ERASE AND WR ITE POWER: A valid VPP voltage allows erase or programming. Memory contents can’t
be altered when VPP ≤ VPPLK.
Set VPP = VCC for in-system progr am and er ase oper ations. To accommodate resistor o r diode drops from
the system supply, VPP’s VIH level can be as low as VPPLMIN.
Program/erase voltage is normally 1.7 V–3.6 V.
VCC Pwr DEVICE POWER SUPPLY: Writes are inhibited at VCC ≤ VLKO. Device operations at invalid VCC voltages
should not be attempted.
VCCQ Pwr OUTPUT POWER SUPPLY: Enables all outputs to be driven at VCCQ. This input may be tied directly to
VCC if VCCQ is to function within the VCC range.
VSS Pwr GROUND: connects device circuitry to system ground.
VSSQ Pwr I/O GROUND: Tie to GND
NC NO CONNECT: No internal connection; can be driven or floated.
DU DON’T USE: Don’t connect to power supply or other signals.
RFU RESERVED FOR FUTURE USE: Don’t connect to other signals.
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5.0 Bus Operations
CE# at VIL and RST# at VIH enables device read operations. Addresses are always
assumed to be v alid. OE#-low activates the outputs and gates selected data onto the I/
O bus. WE#-low enables device write operations. When the VPP voltage ≤ VPPLK
(lockout voltage), only read operations are enabled.
Notes:
1. See Table 8, “Command Sequences in x16 Bus Mode” on page 20 for valid DIN during a write operation.
2. X = D on’t care (L or H)
3. OE# and WE# should never be asserted simultaneously. If done so, OE# overrides WE#.
5.1 Reads
To perform a read operation, RST# and WE# must be deasserted while CE# and OE#
are asserted. CE# is the device-select control. When asserted, it enables the flash
memory device. OE# is the data-output control. When asserted, the addressed flash
memory data is driven onto the I/O bus.
5.2 Writes
To perform a write operation, both CE# and WE# are asserted while RST# and OE# are
deasserted. During a write operation, address and data are latched on the rising edge
of WE# or CE#, which ever occurs first. Table 7, “Command Codes and Descriptions” on
page 19 shows the bus cycle sequence for each of the supported device commands,
while Table 8, “Command Sequences in x16 Bus Mode” on page 20 describes each
command. See Section 16.0, “AC Characteristics” on page 62 for signal-timing details.
Note: W rite operations with inv alid VCC and/or VPP voltages can produce spurious results and sh ould
not be attempted.
5.3 Output Disable
When OE# is deasserted, device outputs DQ[15:0] are disabled and place d in a high-
impedance (High-Z) state, WA IT is also placed in High-Z.
5.4 Standby
When CE# is deasserted the device is deselected and placed in standby, substantially
reducing power consumption. In standby, the data outputs are placed in High-Z,
independent of the level placed on OE#. Standby current, ICCS, is the average current
measured over any 5 ms time interval, 5 μs after CE# is deasserted. During standby,
average current is measured over the same time interval 5 μs afte r CE# is deasserted.
Table 6: Bus Operations
State RST# CE# OE# WE# DQ[15:0] Note
Read (Main Array) VIH VIL VIL VIH DOUT
Read (Status, Query, Identifier) VIH VIL VIL VIH DOUT
Output Disable VIH VIL VIH VIH High-Z
Standby VIH VIH XXHigh-Z2
Reset VIL XXXHigh-Z2
Write VIH VIL VIH VIL DIN 1
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When the device is deselected (while CE# is deasserted) during a program or erase
operation, it continues to co nsume active power until the progr am or er ase operation is
completed.
5.5 Reset
As with any automated device, it is important to assert RST# when the system is reset.
When the system comes out of reset, the system processor attempts to read from the
flash memory if it is the system boot device. If a CPU reset occurs with no flash
memory reset, improper CPU initialization may occur because the flash memory may
be providing status information rather than array data. Flash memory devices from
Numonyx allow proper CPU initialization following a system reset through the use of the
RST# input. RST# should be controlled by the same low-true reset signal that resets
the system CPU.
After initial power-up or reset, the device defau lts to asynchronous Read Array mode,
and the Status Register is set to 0x80. Asserting RST# de-energizes all internal
circuits, and places the output drivers in High-Z. When RST# is asserted, the device
shuts down the operation in progress, a process which takes a minimum amount of
time to complete. When RST# has been deasserted, the device is reset to
asynchronous Read Array state.
Note: If RST# is asserted during a program or erase operation, the oper ation is terminated and the
memory contents at the aborted location (for a program) or block (for an erase) are no longer
valid, because the data may have been only partially written or erased.
When returning from a reset (RST# deasserted), a minimum wait is required before the
initial read access outputs valid data. Also, a minimum delay is required after a reset
before a write cycle can be initiated. After this wake-up interval passes, normal
operation is restored. See Section 16.0, “AC Characteristics” on page 62 for details
about signal-timing.
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6.0 Command Set
6.1 Device Command Codes
The system CPU provides control of all in-system read, write, and erase operations of
the device via the system bus. The on-chip Write State Machine (WSM) manages all
block-erase and word-program algorithms.
Device commands are written to the Command User Interface (CUI) to control all flash
memory device operations. The CUI does not occupy an addressable memory location;
it is the mechanism through which the flash device is controlled.
Table 7: Command Codes and Descriptions
Mode
Code Device Mode Description
Read
FFh Read Array Places device in read array mode so that data signals output array data on DQ[15:0].
70h Read Status
Register Places the device in Status Register read mode. Status data is output on DQ[7:0]. The device
automatically enters this mode after a program or erase command is issued to it.
90h Read ID Code Puts the device in read identifier mode. Device reads from the addresses output manufacturer/
device codes, block lock status, or protection register data on DQ[15:0].
98h Read Query Puts the device in read query mode. Device reads from the address given outputting the
Common Flash Interface information on DQ[7:0]
50h Clear Status
Register
The WSM can set the Status Register’s block lock (SR.1), VPP (SR.3), program (SR.4), and
erase (SR.5) status bits to “1” but cannot clear them. Device reset or
the Clear Status Register command at any device address clears those bits to “0.”
Program
40h Program
Set-Up
This preferred program command’s first cycle prepares the CUI for a program operation. The
second cycle latches address and data and executes the WSM Program algorithm at this
location. Status Register updates occur when CE# or
OE# is toggled. A Read Array command is required to read array data after programming.
10h Alt Set-up Equivalent to a Program Set-Up command (40h).
42h Bit Alterable
Write
The command sequence is the same as Word Program (40h). The difference is the state o f the
PCM memory cell can change fr om a 0 to 1 or 1 to 0, unlik e a flash memory ce ll, which can only
change from 1 to 0 during programming.
E8h Buffered
Program This command loads a variable number of bytes up to the buffer size 32 words onto the
program buffer.
EAh Bit Alterable
Buffered Write This command sequence is the similar to Buffere d Program, but the buffer write command is bit
alterable or overwrite operation. The command sequence is the same as E8h.
DEh Buffer Program
on all 1s This command is the same as Buffered Program, but user indicates that the pagee is already
set to all 1s. The command sequence is the same as E8h
D0h Buffered Write
Confirm The confirm command is issued after the d ata streaming for writing into the buffer is done. This
initiates the WSM to carry out the buffered programing algorithm.
Erase
20h Block Erase
Set-Up
Prepares the CUI for Block Erase. The device emulates erasure of the block addressed by the
Erase Confirm command by writing all ones. If the next comman d is not Er ase Confirm, the CUI
(a) sets Status Register bits SR.4 and SR.5 to “1,”
(b) places the device in the read Status Register mode, and
(c) waits for another command.
D0h Erase Confirm If the first command was Erase Set-Up (20h), the CUI latches address and data
then emulates erasure of the block indicated by the Erase confirm cycle address.
Suspend
B0h Write or
Erase Suspend
This command issued at any device address initiates suspension of the currently executing
program/erase operation. The Status Register, invoked by a Read Status Register command,
indicates successful suspend operation by setting (1) status bits SR.2 (write suspend) or SR.6
(erase suspend) and SR.7. The WSM remains in the Suspend mode regardless of the control
signal states, except RST# = VIL.
D0h Suspend
Resume This command issued at any device address resumes suspended program or
erase operation.
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Note: Don’t use unassigned (reserved) commands
6.2 Device Command Bus Cycles
Device operations are initiated by writing specific device commands to the Command
User Interface (CUI). Several commands are used to modify array data including Word
Program and Block Er ase commands. Writing either command to the CUI initiates a
sequence of internally-timed functions that culminate in the completion of the
requested task. However, the operation can be aborted by either asserting RST# or by
issuing an appropriate suspend command
Block Locking
60h Lock Set-Up Prepares the CUI for lock config uration. If the next command is not Block-Lock, Unlock, or Lock-
Down the CUI sets SR.4 and SR.5 to indicate command sequence error.
01h Lock Block If the previous command was Lock Set-Up (60h), the CUI locks the addressed block.
D0h Unlock Block After a Lock Set-Up (60h) command the CUI latches the address and unlocks the addressed
block.
2Fh Lock-Down After a Lock Set-Up (60h) command, the C UI latches the address and locks-down the
addressed block.
Protection
C0h Protection
Program
Set-Up
Prepares the CUI for a p rotection register p rogram oper ation. The seco nd cycle latches address,
data, and starts the WSM’ s protection register pr ogram or lock algorithm. Toggling CE# or OE#
updates the PCM Status Re gister data. To read array data after programming issue a Read
Array command.
Table 7: Command Codes and Descriptions
Mode
Code Device Mode Description
Table 8: Command Sequences in x16 Bus Mode
Mode Command Bus
Cycles
First Bus Cycle Second Bus Cycle
Oper Addr(1) Data(2) Oper Addr(1) Data(2)
Read
Read Array/Reset 1 Write DnA FFh - - -
Read Device Identifiers ≥ 2 Write DnA 90h Read DBA+IA ID
Read Query ≥ 2 Write DnA 98h Read DBA+QA QD
Read Status Registe r 2 Write BA 70h Read BA SRD
Clear Status Register 1 Write X 50h - - -
Program
Program 2 Write WA 40h or 10h Write WA WD
Bit Alterable Program 2 Write WA 42h Write PA PD
Buffered Program(3) > 2 Write WA E8h Write WA N-1
Bit Alterable Buffered
Program(3) >2 Write WA EAh Write WA N-1
Buffered Program on all 1s >2 Wr ite WA DEh Write WA N-1
Erase Block E rase 2 Write BA 20h Write BA D0h
Suspend Program/Erase Suspend 1 Write X B0h - - -
Program/Erase Resume 1 Write X D0h - - -
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Block
Lock
Lock Block 2 Write BA 60h Write BA 01h
Unlock Block 2 Write BA 60h Write BA D0h
Lock-down Block 2 Write BA 60h Write BA 2Fh
Protection Protection Program 2 Write PA C0h Write PA PD
Lock Protection Program 2 Write LPA C0h Write LPA FFFDh
Notes:
1. First command cycle address should be the same as the operation’s target address.
X = Any valid address within the device.
IA = Identification code address.
BA = Address within the block.
LPA = Lock Protection Address (from the CFI). P8P LPA is at 0080h.
PA = 4-word protection address in the user programmable area of device identification plane.
DnA = Address within the device.
DBA = Device Base Address. (A[MAX:1]=0h)
PRA = Program Region
QA = Query code address.
WA = Word address of memory location to be written.
2. SRD = Data read from the status register.
WD = Data to be written at location WA.
ID = Identifier code data.
PD =User programmable protection data.
QD = Query code data on DQ[7:0].
N = Data count to be loaded into the device to indicate how many words would be written into the buffer. Because the
internal registers count from 0, the user writes N-1 to load N words.
3. The second cycle of the Buffere d Progr am command, wh ich is the count being loaded into the buffer is followed by data
streaming up to 32 words and then a confirm command is issued which triggers the programming operation. Refer to
the Appendix B, “Buffered Program Flowchart”.
Table 8: Command Sequences in x16 Bus Mode
Mode Command Bus
Cycles
First Bus Cycle Second Bus Cycle
Oper Addr(1) Data(2) Oper Addr(1) Data(2)
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7.0 Read Operation
Numonyx® Omneo™ P8P PCM has several read modes: read array, read device
identifier codes, read query (CFI codes) and read Status Register. P8P read modes are:
•Read array mode: read returns PCM array data from the addressed locations.
•Read identifier mode: reads returns manufacturer device identifier data, block
lock status, and protection register data.
•Read query mode: read returns device CFI (or query) data.
•Read Status Register mode: read returns the device Status Register data. A
system processor can check the Status Register to determine the device’s state or
monitor program or erase progress.
7.1 Read Array Command
The R ead Array command places (or resets) the device to read array mode. Upon initial
device power-up or after reset (RST# transitions from VIL to VIH), the device defaults
to read array mode. If an Erase- or Program-Suspend command suspends the WSM, a
subsequent Read Array command will place the device in read array mode. The Read
Array command functions independently of VPP voltage.
7.2 Read Identifier Command
The read identifier mode is used to access the manufacturer/device identifier, block lock
status, and protection register codes. The identifier space occupies the address range
supplied by the Read Identifier command (90h) address.
Notes:
1. DBA = Device Base Address. (A[MAX:18] = DBA). Numonyx reserves other configuration address locations.
2. BBA = Block Base Address.
3. DQ[7:2] are invalid and should be ignored.
Table 9: Read Identifier Table
Item Address(1,2) Data
Manufacturer Code DBA + 000000h 0089h
Device Code DBA + 000001h ID (see Table 10)
Block Lock Configuration
BBA + 000002h
Lock
• Block Is Unlocked DQ0 = 0
• Block Is Locked DQ0 = 1
• Block Is not Locked-Down DQ1 = 0
• Block Is Locked-Down DQ1 = 1
• Reserved for Future Use(3) DQ[7:2]
Lock Protection Register 0 DBA + 000080h PR-LK0
64-bit Factory-Programmable Protection Register DBA + 000081h–000084h Protection Register Data
64-bit User-Programmable Protection Register DBA + 000085h–000088h Protection Register Data
Lock Protection Register 1 DBA + 000089h Protection Register Data
16x128 bit User-Programmable Protection Registers DBA + 00008Ah–0000109h PR-LK1
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Table 10: Device ID Table
7.3 Read Query Command
The Query space comes to the foreground and occupies the device address range
supplied by the Read Query command address. The mode outputs Common Flash
Interface (CFI) data when the device addresses are read. Appendix A, “Common Flash
Interface” on page 84 shows the query mode information and addresses. Write the
Read Array command to return to read array mode.
The read performance of this CFI data follows the same timings as the main array.
7.4 Other ID Mode Data
Other ID mode data besides the Protection registers (such as block locking information
and the device JEDEC ID) may be accessed as long as there are no ongoing write or
erase operations.
7.5 Query (CFI) Data
Query data is read by sending the Read Query command to the device. Reading the
Query data is subject to the same restrictions as reading the Protection Registers.
Device
Device Code (Byte/Word)
Mode
Hex Binary
High Byte Low Byte
128 Mb 881E 10001000 00011110 Top Boot
128 Mb 8821 10001000 00100001 Bottom Boot
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8.0 Program Operations
There are five kinds of write operations available in Numonyx® Omneo™ P8P PCM.
• Word Program (40h, or 10h)
• Bit Alterable Word Write (42h)
• Buffered Program (E8h)
• Bit Alterable Buffered Write (EAh)
• Buffered Program on all 1’s (DEh)
Writing a progra m command to the device initiates internally timed sequences that
write the requested word.
Note: All program operations must stay with in 32-byte page. Writing must be aligned to a
32-byte page boundry (ex: 0x0, 0x8, 0x10, 0x18, 0x20, etc.). All addresses must lie
within the starting address plus the buffer size. All transmitted data that goes beyond
the 32-byte page boundry are not guaranteed.
The WSM executes a sequence of internally timed events to write desired bits at the
addressed location and verify that the bits are sufficiently written. For Word
Progra mmin g the memory changes specifically addressed bits to “0”. “1” bits do not
change the memory cell contents. This allows individual data-bits to be programmed
(“0”) while “1” bits serve as data masks. Fo r Bit Alterable Word Write, the memory cell
can change from “0” to “1” or “1” to a “0”.
The Status Register can be examined for write progress and errors by reading any
address within the device during a write operation. Issuing a Read Status Register
command brings the Status Register to the foreground allowing write progress to be
monitored or detected at other device addresses. Status Register bit SR.7 indicates
device write status while the write sequence executes. CE# or OE# toggle (during
polling) updates the Status Register. Valid commands that can be issued to the writing
device during write are Read Status Register, Write Suspend, Read Identifier, Read
Query, and Read Arra y. However R ead Array will return unknown data while the device
is busy.
When writing completes, Status Register bit SR.4 indicates write success if zero (0) or
failure if set (1). If SR.3 is set (1), the WSM couldn’t execute the write command
because VPP was outside acceptable limits. If SR.1 is set (1), the write operation
targeted a locked block and was aborted. Attempting to write in an erase suspended
block will result in failure and SR.4 will be set (1).
After examining the Status Register, it should be cleared by the Clear Status Register
command before issuing a new command. The device remains in Status Register mode
until another command is written to that device. Any command can follow once writing
completes.
8.1 Word Program
The system processor writes the Word Program Setup command (40h/10h) to the
device followed by a second write that specifies the address and data to be
programmed. The device accessed during both of the command cycles automatically
outputs Status Register data when the device address is read. The device accessed
during the second cycle (the data cycle) of the program command sequence will be
where the data is programmed. See Section 32, “Buffer Program or Bit Alter able Buffer
Write Flowchart” on page 75.
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When VPP is greater than VPPLK, program-and erase-currents are drawn through the
VCC input. If VPP is driven by a logic signal, VPP must remain above VPPMIN to perform
in-system PCM modifications. Figure 5, “Example VPP Power Supply Configuration” on
page 27 shows PCM power supply usage in various configur ations.
8.2 Bit Alterable Word Write Command
The Bit Alterable Word Write Command executes just like Word Program Command
(40h/10h), using a two-write command sequence. The Bit Alterable Write Setup
command (42h) is written to the CUI followed by the specific address and data to be
written. The WSM will start executing the programming algorithm, but the data written
to CUI will be directly overwritten into the PCM memory unlike flash memory, which can
only be written from 1 to 0 without a prior erase of the entire block. See Table 12, “Bit
Alterability vs. Flash Bit-Masking” on page 26. This overwrite function eliminates Flash
Bit Masking, which means software cannot use a “1” in a data mask to produce no
change of the memory cell, as might occur with floating gate flash.
8.3 Buffered Program Command
A Buffered Program command sequence initiates the loading of a variable number of
words, up to the buffer size (32 words), into the program buffer and after that into the
PCM device. First, the Buffer ed Program setup command is issued along with the Block
Address (Section 32, “Buffer Program or Bit Alterable Buffer Write Flowchart” on
page 75). When Status Register bit 7 is set to 1, the buffer is ready for loading. Now a
word count is given to the part with the Block Address.
On the next write, a device starting address is given along with the Program Buffer
data. Subsequent writes provide additional device addresses and data, depending on
the count. All subsequent addresses must lie within the starting address plus the buffer
size. Maximum programming performance and lower power are obtained by aligning
the starting address at the beginning of a 32 word boundary. A misaligned starting
address is not allowed and will result in inv alid data. After the final buffer data is given,
a Program Buffer Confirm command is issued. This initiates the WSM (Write State
Machine) to begin copying the buffer data to the PCM array.
If a command other than Buffered Program Confirm command (D0h) is written to the
device, an “Invalid Command/Sequence” error will be generated and Status Register
bits SR.5 and SR.4 will be set to a “1.” For additional buffer writes, issue another
Program Buffer Setup command and check SR.7. If an error occurs while writing, the
device will stop writing, and Status Register bit SR.4 will be set to a “1” to indicate a
program failure. The internal WSM verify only detects errors for “1”s that do not
successfully program to “0”s.
If a program error is detected, the Status Register should be cleared by the user before
issuing the next program command. Additionally, if the user attempts to program past
the block boundary with a Program Buffer command, the device will abort the Progr am
Buffer operation. This will generate an “Invalid Command/Sequence” error and Status
Register bits SR.5 and SR.4 will be set to a “1. All bus cycles in the buffered
programming sequence should be addressed to the same block. If a buffered
programming is attempted while the VPP ≤ VPPLK, Status R egister bits SR.4 and SR.3 will
be set to “1”.
Buffered write attempts with inv alid VCC and VPP voltages produce spurious results and
should not be attempted. Buffered program operations with VIH < RST# < VHH may
produce spurious results and should not be attempted.
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Successful programming requires that the addressed block’s locking status to be
cleared. If the block is locked down, then the WP# pin must be raised high and then the
block could be unlocked to execute a program operation. An attempt to program a
locked block results in setting of SR.4 and SR.1 to a ‘1’ (i.e. “Error in Programming”).
8.4 Bit Alterable Buffer Write
The Bit Alterable Buffer Write command sequence is the same as for Buffer Program.
For command sequence see Section 8.3, “Buffered Program Command” on page 25.
The primary difference between the two Buffer commands is when the Write State
Machine starts executing, the data written to the buffer will be directly overwritten into
the PCM memory, unlike Flash Memory, which can only go from “1” to “0” before an
erase of the entire block. See Table 12, “Bit Alterability vs. Flash Bit-Masking” on
page 26. This overwrite function eliminates Flash Bit Masking, which means software
cannot use a “1” in a data mask for no change of the memory cell, as might occur with
floating gate flash.
The advantage of Bit Alterability is no block erase is needed prior to writing a block,
which minimizes system overhead for software management of data, and ultimately
improves latency, determinism, and reduces power consumption because of reduction
of system overhead. Storing of counter variables can easily be handled by using PCM
memory because a “0” can change to a “1” or a “1” can change to a “0”.
8.5 Bit Alterable Buffer Program
This mode is sometimes referred to as PreSET Buffered Program.
‘Program on all 1s’ is similar to program mode (“1”s treated as masks; “0”s written to
cells) with the assumption that all the locations in the addressed page have previously
been SET (“1”s). [Performance of Buffer Program on All 1s expected to be better than
buffered program mode because the pre-read step before programming is eliminated.]
The command sequence for Buffered Program on all 1s is the same as Buffered
Progr am Comm an d (E8h).
Table 11: Buffered Programming and Bit Alterable Buffer Write Timing Requirements
Alignment Programming Time Example
32-word/64-byte Aligned tPROG/PB Start Address = 1FFF10h; End Address = 1FFF2Fh
Table 12: Bit Alterability vs. Flash Bit-Masking
Programming
Function Command
Issued Memory Cell
Current State Data From
User Memory Cell
After Programming
Flash
Bit-Masking
40h or E8h 0 0 0
40h or E8h 0 1 0
40h or E8h 1 0 0
40h or E8h 1 1 1
Bit
Alterability
42h or EAh 0 0 0
42h or EAh 0 1 1
42h or EAh 1 0 0
42h or EAh 1 1 1
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8.6 Program Suspend
Issuing the Program Suspend command while progr amming suspends the
programming oper ation. This allows data to be accessed from the device other than the
one being programmed. The Program Suspend command can be issued to any device
address. A program operation can be suspended to perform reads only. Additionally, a
program operation that is running during an erase suspend can be suspended to
perform a read operation.
When a programming operation is executing, issuing the Program Suspend command
requests the WSM to suspend the programming algorithm at predetermined points. The
device continues to output Status Register data after the Program Suspend command is
issued. Programming is suspended when Status Register bits SR[7,2] are set.
To read data from the device, the Read Array command must be issued. Read Array,
Read Status Register, Read Device Identifier, Read CFI, and Program Resume are valid
commands during a program suspend.
During a program suspend, deasserting CE# places the device in standby, reducing
active current. VPP must remain at its programming level, and WP# must remain
unchanged while in program suspend. If RST# is asserted, the device is reset.
8.7 Program Resume
The Resume command instructs the device to continue programming, and
automatically clears Status R egister bits SR[7,2]. This command can be written to any
address. If error bits are set, the Status Register should be cleared before issuing the
next instruction. RST# must remain deasserted.
8.8 Program Protection
Holding the VPP input at VIL provides absolute hardware write protection for all PCM-
device blocks. If VPP is below VPPLK, write or erase operations halt and an error is
posted in Status Register bit SR.3. The block lock registers are not affected by the VPP
level; they may be modified and read even if VPP is below VPPLK.
Figure 5: Example VPP Power Supply Configuration
• VPP supply during factory programming
• Complete Write/Erase protection with VPP ≤ VPPLK
System suppl y VCC
VPP
VPP
VCC
VPP
• Low Voltage an d VPP Factory Programmi ng
System suppl y
VPP
• Low-voltage programming
• Absolute write protection via logic signal
System supply VCC
VPP
Prot# (logic signal)
• Low-voltage programming
System supply VCC
VPP
≤ 10K Ω
VPPSUPPLY .EMF
1 2
3 4
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9.0 Erase
Unlike floating gate flash, PCM does not require a high voltage block erase operation to
change all the bits in a block to “1.” As a bit alterable technology, each bit is capable of
independently being changed from a “0” to a “1” and from a “1” to a “0”. With floating
gate flash, a high voltage potential must be placed in parallel upon a group of bits
called an erase block. Each bit within the block may be changed independently from “1”
to a “0”, but only may be changed from a “1” to a “0” through a grouped erase
operation. To maintain compatibility with legacy flash system software, Numonyx®
Omneo™ P8P PCM mimics or emulates a flash erase by writing each bit within a block
to “1”, thereby emulating flash-style erase.
9.1 Block Erase
The system processor writes the Erase Setup command (20h) to the device followed by
a second Confirm (D0h) command write that specifies the address of the block to be
erased. The device during both of the command cycles automatically outputs Status
Register data when the device address is read. See Section 33, “Block Erase Flowchart”
on page 76.
After writing the command, the device automatically enters read status mode. The
device Status Register bit SR.7 will be set (“1”) when the er ase completes. If the er ase
fails, Status Register bit SR.5 will be set (“1”). SR.3 = “1” indicates an invalid VPP
voltage. SR.1 = “1” indicates an erase operation was attempted on a lock ed block. CE#
or OE# toggle (during polling) updates the Status Register.
If an error bit is set, the Status Register can be cleared by issuing the Clear Status
Register command before attempting the next operation. The device will remain in
Status Register mode until another command is written to the device. Any command
can follow once erase completes. Only one block can be in erase mode at a time.
9.2 Erase Suspend Command
The Write/Erase Suspend command halts an in-progress write or erase operation. The
command can be issued at any device address. The Suspend command allows data to
be accessed from memory locations other than the one block being written or the block
being erased.
A Write operation can be suspended to perform reads only at any location except the
address being programmed. An Erase operation can be suspended to perform either a
write or a read operation within any block except the block that is erase suspended. A
Write command nested within a suspended Erase can subsequently be suspended to
read yet another location. Once the write/erase process starts, the Suspend command
requests that the WSM suspend the write/erase sequence at predetermined points in
the algorithm. An operation is suspended when status bits SR.7 and SR.6 and/or SR.2
display “1.” tSUSP/P/tSUSP/E specifies suspend latency.
To read data from other blocks within the device (other than an erase-suspended
block), a Read Array command can be written. During Erase Suspend, a Write
command can be issued to a block other than the erase-suspended block. Block erase
cannot resume until write operations initiated during erase suspend complete. Read
Array, Rea d Status Register, Read Identifier (ID), Read Query, and Write Resume are
valid commands during Write or Erase Suspend. Additionally, Clear Status Register,
Program, Write Susp end, Erase Resume, Lock Block, Unlock Block, and Lock-Down
Block are valid commands during Erase Suspend.
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Numonyx® Omneo™ P8P Datasheet
During a suspend, CE# = VIH places the device in standby state, which reduces supply
current. VPP must remain at its program level and WP# must remain unchanged while
in suspend mode.
The Resume (D0h) command instructs the WSM to continue writing/erasing and
automatically clears Status Register bits SR.2 (or SR.6) and SR.7. If Status Register
error bits are set, the Status Register can be cleared before issuing the next
instruction. RST# must remain at VIH. See Section 31, “Write Suspend/Resume
Flowchart” on page 74 and Section 34, “Erase Suspend/Resume Flowchart” on
page 77.
If software compatibility with the Numonyx™ P33 device is desired, a minimum tERS/SUSP
time (See Section 17.0, “Program and Erase Characteristics” on page 71) should elapse
between an Er ase command and a subsequent Erase Su spend command to ensure that
the device achieves sufficient cumulative erase time. Occasional Erase-to-Suspend
interrupts do not cause problems, but out -of -spec Er ase-to-Suspend commands issued
too frequently to a P33 device may produce uncertain results. However, this
specification is not required for this PCM device.
9.3 Erase Resume
The Erase Resume command instructs the device to continue erasing, and
automatically clears status register bits SR[7,6]. This command can be written to any
address. If status register error bits are set, the Status Register should be cleared
before issuing the next instruction. RST# must remain deasserted (see Figure 31,
“Write Suspend/Resume Flowchart” on page 74).
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10.0 Security Mode
The device features security modes used to protect the information stored in the flash
memory array. The following sections describe each security mode in detail.
10.1 Block Locking
There are two types of block locking on Numonyx® Omneo™ P8P PCM:
• Zero Latency Block Locking
• Selectable One Time Programmable (OTP) Block Locking
This type of locking allows for permanent locking of the parameter blocks and 3
main blocks.
10.1.1 Zero Latency Block Locking
Individual instant block locking protects code and data. It allows software to control
block locking or it can require hardware interaction before locking can be changed. Any
block can be locked or unlocked with no latency. Locked blocks cannot be written or
erased; they can only be read. Write or erase operations to a locked block returns a
Status Register bit SR.1 error. The following sections discuss the locking operations.
State [WP#, LA T1, LA T0] specifies lock states (WP# = WP# state, LA T1= internal Block
Lock Down latch status, LAT0 = internal Block Lock latch status). Figure 6, “Block
Locking State Diagram” on page 33 defines possible locking states. The following
summarizes the locking functionality.
• All blocks power-up in the locked state. Then Unlock and Lock commands can
unlock or lock them
• The Lock-Down command locks and prevents a block from being unlocked when
WP#=V
IL
WP#=V
IH overrides lock-down so commands can unlock/lock blocks
If a previously locked-down block is given a Lock/Unlock/Lock-Down command
and WP# returns to VIL then those blocks will return to lock-down
Lock-Down is cleared only when the device is reset or powered-down.
The block lock registers are not affected by the VPP level; they may be modified and
read even if VPP is below VPPLK.
The following sections describe how to lock, unlock, and lock-down a block. Table 14 on
page 32 shows the state table for the locking functions. See also Section 35, “Locking
Operations Flowchart” on page 78.
10.1.2 Lock Block
All blocks default power-up or reset state is locked (states [001] or [101]) to fully
protect it from alteration. Write or erase operations to a locked block return a Status
Register bit SR.1 error. The Lock Block command sequence can lock an unlocked block.
Table 13: Block Locking Truth Table
VPP WP# RST# Block Write Protection Block Lock Bits
XXV
IL All blocks write/erase protected Block lock bits may not be changed
≤ VPPLK VIL VIH All blocks write/erase protected Lock-Down block states may not be
changed
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Numonyx® Omneo™ P8P Datasheet
10.1.3 Unlock Block
The Unlock Block command unlocks locked blocks (if block isn’t locked-down) so they
can be programmed or erased. Unlocked blocks return to the locked state at device
reset or p ower-down.
10.1.4 Lock-Down Block
Locked-down blocks (state 3 or [011]) are protected from write and erase operations
(just like locked blocks), but software commands alone cannot change their protection
state. When WP# is VIH, the lock-down function is disabled (state 7 or [111]), and an
Unlock command (60h/D0h) must be issued to unlocked locked-down block (state 6 or
[110]), prior to modifying data in these blocks. To return an unlocked block to locked-
down state, a Lock command (60h/01h) must be issued prior to changing WP# to VIL
(state 7 or [111] and then state 3 or [011]). A locked or unlocked block can be locked-
down by writing the Lock-Down Block command sequence. Locked-down blocks revert
to the locked state at device reset or power-down.
10.1.5 WP# Lock-Down Control
WP# = VIH overrides the block lock -down. See Table 13, “Block Locking Truth Table” on
page 30. The WP# signal controls the lock-down function. WP# = 0 protects lock-down
blocks [011] from write, erase, and lock status changes. When WP# = 1, the lock-
down function is disabled [111] and a software command can individually unlock
locked-down blocks [110] so they can be erased and written. When the lock-down
function is disabled, locked-down blocks remain locked, and must first be unlocked by
writing the Unlock command prior to modifying data in these blocks. These blocks can
then be re-locked [111] and unlocked [110] while WP# remains high.
When WP# goes low, blocks in re-locked state [111] returns to locked-down state
[011]. However, WP# going low changes blocks at unlocked state [110] to [010] or
“virtual lock-down” state. When the lock status of a “virtual lock-down” blocks is read,
it appears to be a “locked-down” state to user when WP# is VIL. Blocks in “virtual lock-
down” will be immediately unlocked when WP# is VIH. Therefore, to avoid “virtual lock-
down”, a Lock command must be issued to an unlocked block prior to WP# going low.
Device reset or power-down resets all blocks to the locked state[101] or [001],
including locked-down blocks.
10.1.6 Block Lock Status
Every block’s lock status can be read in the device’s read identifier mode. To enter this
mode, write 90h to the device. Subsequent reads at Block base-address + 00002h
output that block’s lock status. Data bits DQ0 and DQ1 represent the lock status. DQ0
indicates the block lock/unlock state as set by the Lock command and cleared by the
Unlock command. It is also automatically set when entering Lock-Down. DQ1 indicates
lock-down state as set by the Lock-Down command. It cannot be cleared by software,
only by device reset or power-down. See Table 14, “Block Locking State Transitions” on
page 32.
≤ VPPLK VIH VIH All blocks write/erase protected All Lock-Down block states may be
changed
> VPPLK VIL VIH All Lock-Down and Locked
blocks write/erase protected Lock-Down block states may not be
changed
> VPPLK VIH VIH All Lock-Down and Locked
blocks write/erase protected All Lock-Down block states may be
changed
Table 13: Block Locking Truth Table
VPP WP# RST# Block Write Protection Block Lock Bits
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10.1.7 Locking Operations During Erase Suspend
Block lock configurations can be performed during an erase suspend by using the
standard locking command sequences to unlock, lock, or lock-down a block. This is
useful when another block needs to be updated while an erase operation is suspended.
To change block locking during an erase operation, first write the Erase Suspend
command, then check the Status Register until it indicates that the erase operation has
suspended. Next write the desired lock command sequence to a block; the lock state
will be changed. After completing lock, read, or program operations, resume the erase
operation with the Erase Resume command (D0h).
If a block is locked or locked-down during a suspended erase of the same block, the
locking status bits will change immediately. But, when resumed, the erase operation
will complete. Locking operations cannot occur during write suspend. Appendix A,
“Write State Machine” on page 80 shows valid commands during erase suspend.
Nested lock or write commands during erase suspend can return ambiguous Status
Register results. 60h followed by 01h commands lock a block. A Configuration Setup
command (60h) followed by an invalid command produces a lock command Status
Register error (SR.4 and SR.5 = 1). If this error occurs during erase suspend, SR.4 and
SR.5 remain at 1 after the erase resumes. When erase completes, the previous locking
command error hides the Status Register’s erase errors. A similar situation occurs if a
write operation error is nested within an erase suspend.
Notes:
1. Additional illegal states are shown but are not recommended for normal, non-erroneous operational modes.
2. “Erase/Write Allowed?” shows whether a block’s current locking state allows erase or write.
3. At power-up or device reset, blocks default to locked state [001] if WP# = 0, the recommended default.
4. Blocks in “virtual lock -down” appear to be in locked-down state when WP#=VIL. WP# = 1 changes [010] to unlocked state
[110].
5. “This column shows results of writing the four locking commands or WP# toggle from the current locking state.
Table 14: Block Locking State Transitions
Current State Erase/Write
Allowed?(1)
Lock Com mand Input Res ult
(Next State) (5) WP#
Toggle
Result
(Next
State)
Locking
Status
Readout
WP# LAT
1LAT
0Name UnLock Lock Lock-
Down D1 D0
0 0 0 Unlocked Yes 000 001 011 100 0 0
0 0 1 Locked (default) (1) No 000 001 011 101 0 1
0 1 0 Virtual lock-down (4) No 011 011 011 110 1 1
0 1 1 Locked-Down No 011 011 011 111 1 1
1 0 0 Unlocked Yes 100 101 111 000 0 0
1 0 1 Locked No 100 101 111 001 0 1
1 1 0 Lock-Down Disabled Yes 110 111 111 010 1 0
1 1 1 Lock-Down Disabled No 110 111 111 011 1 1
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Numonyx® Omneo™ P8P Datasheet
10.2 Permanent One Time Programmable (OTP) Block Locking
The parameter blocks and first 3 main blocks for a bottom parameter device (or if
device configured as a top parameter device this would be the last 3 main blocks and
the par ameter blocks) can be made O TP, so further write and er ase oper ations to these
blocks are disallowed, effectively permanently programming the blocks. This is
achieved by programming bits 2, 3, 4, and 5 in the PR -L OCK0 register at offset 0x80 in
ID Space. The OTP locking bit mapping may be seen in Table 15, “Selectable OTP Block
Locking Feature” on page 34 below.
Bit 6 in the PR -LOCK0 register at offset 0x80 in ID space is defined as the Configuration
Lock bit. When bit 6 is cleared (at zero), the device shall disable further programming
of the OTP Lock bits, thereby effectively “freezing” their state. Putting bit 6 at zero shall
not affect the ability to write any other bits in the non OTP regions or in the System
Protection Registers. Reference Table 16, “Selectable OTP Block Locking Programming
of PR-LOCK0” on page 34 for Configuration Lock bit (Bit 6 in PR-LOCK0) control of
allowed states when other bits of the register are programmed.
The read operations of these permanently locked blocks are always supported
regardless of the state of their corresponding Permanent Lock bits. Zero Latency Block
Locking must be used until the block is permanently lock ed with the OTP Block Locking.
Program and er ase oper ations for these blocks remain fully supported until that block’s
Permanent Lock bit is cleared.
Program or erase operations to a permanently locked block returns a Status Register
bit SR.1 error.
Programming of the Permanent OTP Block Locking bits is not allowed during Erase
Suspend of a Permanent Lockable Block.
Figure 6: Block Locking State Diagram
Locked
W P# Hardware Control
[x01]
Unlocked
[x00]
Locked-
Down
[011]
Software
Locked
[111]
Hardware
Locked
[011 ]
Unlocked
[110]
4,5 5
Sof tware Bl ock Lock (0x60/0x01) or Sof tware Block Unl ock (0x 60/0xD 0)
Sof tware Bl ock Lock-Down (0x60/ 0x2F)
WP# hardware cont rol
1. [a,b ,c] represen ts [WP#, DQ1, DQ0]. X = Don’t Care
2. DQ1 indicates Block Lock -Down status. DQ1 = ‘ 0’, Lock-Down has not bee issued to this block.
DQ1 = ’1', Lock-Down has been issued to this block.
3. DQ0 indicates block lock status . DQ0 = ‘0’ , block is unlocked. DQ0 = ‘1’, block is locked .
4. Locked-down = Hardware + Software locked.
5. [011] states should be tracked system software to determ ine difference between Hardware
Locked and Locked-Down states.
Power-Up/Reset
Notes:
Numonyx® Omneo™ P8P Datasheet
Datasheet July 2010
34 316144-07
Note: The Selectable Block Locking will not be indicated in the Zero Latency Block Lock
Status. See Section 10.1.6, “Block Lock Status” on page 31 for more information. Read
PR-LOCK0 register to determine Block Lock Status for these blocks.
Table 15: Selectable OTP Block Locking Feature
Bit Number @ Offset
0x80 in CFI Space Function When Set (‘1b) Function When Cleared (‘0b)
2 Blocks not permanently locked Write/erase disabled for all parameter blocks
Bottom Boot - Blocks 0-3
Top Boot 128M - Blocks 127-130
3 Block not permanently locked Write/erase disabled for first Main Block
Bottom Boot - Block 4
Top Boot 128M - Block 126
4 Block not permanently locked Write/erase disabled for second Main Block
Bottom Boot - Block 5
Top Boot 128M - Block 125
5 Block not permanently locked Write/erase disabled for third Main Block
Bottom Boot - Block 6
Top Boot 128M - Block 124
6 Able to change PR-LOCK0[5:2] Bits Program disabled for PR-LOCK0[5:2]
Table 16: Selectable OTP Block Locking Programming of PR-LOCK0
Bit 6 Program to
[5:2] Program to
[1:0] Status Register Abort
Program Status of Data in 80H OTP
Space
unlocked don’t care don’t care no fail bits set NO Changed
locked YES YES program fail/ lock fail YES No Change
locked YES NO program fail/ lock fail YES No Change
locked NO YES no fail bits set NO Changed
Figure 7: Selectable OTP Locking Illustration (Bottom Parameter Device Example)
PR-LOCK0
Parameter Blocks - Block 0-3
0
x000000 (Parameter A r ray)
0x80 (OTP Array)
Main Array Block 4
Main Array Block 5
Main Array Block 6
0x010000 (Main Array)
0x020000 (Main Array)
0x030000 (Main Array)
{
6 5 4 3 2
BOOT_ROM.WMF
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Numonyx® Omneo™ P8P Datasheet
10.2.1 WP# Lock-Down Control for Selectable OTP Lock Blocks
Once the block has been permanently locked with OTP bit, WP# at VIH does not
override the lock down of the blocks those bits control.
10.2.2 Selectable OTP Locking Implementation Details
Clearing (write to “0”) any of the four Permanent Lock bits shall effectively cause the
following commands to fail with a block locking error when issued to their
corresponding blocks: Buffer Program command, Bit-Alterable Buffer Write command,
Word Program command, Bit -Alterable W or d Write command, and Erase command. No
other commands shall be affected.
Programming the P ermanent Lock bits or the Configuration Lock bit shall be done using
the Protection Register Programming command. As with all bits in the CFI/OTP space
once the Permanent Lock or the Configuration bits are programmed, they may not be
erased (set) again.
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36 316144-07
11.0 Registers
11.1 Read Status Register
The device’s Status Register displays program and erase operation status. A device’s
status can be read after writing the Read Status Register command. The Status
Register can also be read following a Program, Erase, or Lock Block command
sequence. Subsequent single reads from the device outputs its status until another
valid command is written.
The last of OE# or CE# falling edge latches and updates the Status Register content.
DQ[7:0] output is the Status Register bits; DQ[15:8] output 00h. See Table 17, “Status
Register Definitions” on page 36.
Issuing a Read Status, Block Lock, Program, or Erase command to the device places it
in the Read Status mode. Status Register bit SR.7 (DWS — Device Write Status)
provides program/erase status of the device. Status Register bi ts SR .1 -SR.6 present
information about the WSM’s program, erase, suspend, VPP, and block-lock status
mode.
Table 17: Status Register Definitions
DRS ESS ES PS VPPS PSS DPS PRW
SR.7 SR.6 SR.5 SR.4 SR.3 SR.2 SR.1 SR.0
Status Register Bits Notes:
SR.7 = Device Write/Erase Status (DRS)
0 = Device WSM is Busy
1 = Device WSM is Ready
SR.7 indicates erase or program completion in the device. SR.1–6 are invalid
while SR.7 = “0.”
SR.6 = Erase Suspend Status (ESS)
0 = Erase in progress/
completed
1 = Erase suspended
After issuing an Erase Sus pend command, the WSM halts and sets (1) SR.7 and
SR.6. SR .6 remains set un til the device rece ives an Erase Resume command.
SR.5 = Erase Status (ES)
0 = Successful erase
1 = Erase error
SR.5 is set (1) if an attempted erase failed.
A Command Sequence Error is indicated when SR.4, SR.5 and SR.7 are set.
SR.4 = Write Status (PS)
0 = Successful write
1 = Write error
SR.4 is set (1) if the WSM failed to program.
A Command Sequence Error is indicated when SR.4, SR.5 and SR.7 are set.
SR.3 = VPP Status (VPPS)
0 = VPP OK
1 = VPP low detect, operation
aborted
The WSM indicates the VPP level after program or erase starts. SR.3 does not
provide continuous VPP feedback and isn’t guaranteed when VPP < VPPLK
SR.2 = Write Suspend Status (PSS)
0 = Write in progress/
completed
1 = Write suspended
After receiving a Write Suspend command, the WSM halts execution and sets
(1) SR.7 & SR.2, which remains set until a Resume command is received.
SR.1 = Device Protect Status (DPS)
0 = Unlocked
1 = Aborted erase/program
attempt on locked block
If an erase or progr am oper ation is attempted to a lock ed block (if WP# = VIL),
the WSM sets (1) SR.1 and aborts the operation.
SR.0 Super Page Write Status (PWS)
0 = Reserved
1 = Reserved Reserved
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Numonyx® Omneo™ P8P Datasheet
11.1.1 Clear Status Register Command
The Clear Status Register command clears the Status R egister. The command functions
independently of the applied VPP voltage. The WSM can set (1) Status Register bits
SR[7:0] and clear (0) bits 2, 6, and 7. Because bits 1, 3, 4 and 5 indicate various error
conditions, they can only be cleared by the Clear Status Register command. By allowing
system software to reset these bits, several operations (such as cumulatively
programming several addresses or erasing multiple blocks in sequence) may be
performed before reading the Status Register to determine error occurrence. The
Status Register should be cleared before beginning another command or sequence.
Device reset (RST# = VIL) also clears the Status Register.
11.2 System Protection Registers
The device contains two 64-bit, and sixteen 128-bit individually lockable protection
registers that can increase system security or hinder device substitution by containing
values that mate the PCM component to the system’s CPU or ASIC.
One 64-bit protection register is programmed at the Numonyx factory with an non-
changeable unique 64-bit number. The other 64-bit and sixteen 128-bit protection
registers are blank so customers can program them as desired. Once programmed,
each customer segment can be locked to prevent further reprogramming.
11.2.1 Read Protection Register
The Read Identifier command allows Protection register data to be read 16 bits at a
time from addresses shown in Table 9, “Read Identifier Table” on page 22. To read the
Protection Register, first issue the Read Device Identifier command at Device Base
Address to place the device in the Read Device Identifier mode. Next, perform a read
operation at the device’s base address plus the address offset corresponding to the
register to be read. Table 9, “Read Identifier Table” on page 22 shows the address
offsets of the Protection R egisters and Lock R egisters. R egister data is read 16 bits at a
time. Refer Appendix , “Protection Register Addressing” on page 39.
11.2.2 Program Protection Register
The Protection Program command should be issued followed by the data to be
programed at the specified location. It programs the 64 user protection register 16 bits
at a time. Table 9, “Read Identifier Table” on page 22 and in Table 18 on page 39 show
allowable addresses. See also Figure 36, “Protection Register Programming Flowchart”
on page 79. Addresses A[MAX:11] are ignored when programming the OTP, and OTP
program will succeed if A[10:1] are within th e prescribed protection addressing range;
otherwise an error is indicated by SR4 = 1.
11.2.3 Lock Protection Register
Each of the protection registers are lockable by programming their respective lock bits
in the PR -LOCK0 or PR -LOCK1 registers. Bit 0 of the Lock -R egister -0 is programmed by
Numonyx to lock-in the unique device number. The physical address of the PR-LOCK0
register is 80h as seen in Figure 8, “Protection Register Memory Map” on page 38. Bit 1
of the Lock-Register -0 can be programmed by the user to lock the upper 64-bit
portion. (Refer Table 18, “Protection Register Addressing” on page 39.). The bits in
both PR-LOCK registers are made of “PCM cells” that may only be programmed to ‘0’
and may not be altered.
Note: Bit0 of the Lock-Register, PR-LOCK0, is a don’t care, so users must mask out this bit
when reading PR-LOCK0 register. This number is guarantee d to persist through board
attach.
Numonyx® Omneo™ P8P Datasheet
Datasheet July 2010
38 316144-07
For the 2K OTP space, the re exists an additional 16-bit lock register called PR_LOCK1.
Each bit in the PR_LOCK1 register locks a 128-bit segment of the 2K-OTP space.
Therefore, the 16 128-bit segments of the 2K OTP space can be locked individually.
Hence, any 128-bit segment can be first programmed and then locked using the
protection program command followed by protection register data. The PR-LOCK1
register is physically located at the address 89h as shown in the Figure 8, “Protection
Register Memory Map” on page 38.
After PR -LOCK register bits have been programmed, no further changes can be made to
the protection registers' stored values. Protection Program commands written to a
locked section result in a Status Register error (Program Error bit SR.4 and Lock Error
bit SR.1 are set to 1). Once locked, Protection register states are not reversible.
Figure 8: Protection Register Memory Map
…
Lock Register 1
Lock Register 0
4 Words (64 bits)
User Programmed
Group 1
4 Words (64 bits)
Intel Factory Programmed
Group 0
8 Words
User Programmed
Group 2
8 Words
User Programmed
Group 17
84h
88h
85h
81h
80h
89h
8Ah
91h
102h
109h
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Numonyx® Omneo™ P8P Datasheet
11.2.3.1 OTP Protection Register Addressing details
Note: Addresses A9-A23 should be set to zero.
Table 19: 2K OTP Space Addressing
Note: DBA - Device Base Address. Typically this would start from Address 0.
Table 18: Protection Register Addressing
Word Use ID Offset A8 A7 A6 A5 A4 A3 A2 A1
LOCK Both DBA + 000080h 1 0 0 0 0 0 0 0
0 Numonyx DBA + 000081h 1 0 0 0 0 0 0 1
1 Numonyx DBA + 000082h 1 0 0 0 0 0 1 0
2 Numonyx DBA + 000083h 1 0 0 0 0 0 1 1
3 Numonyx DBA + 000084h 1 0 0 0 0 1 0 0
4 Customer DBA + 000085h 1 0 0 0 0 1 0 1
5 Customer DBA + 000086h 1 0 0 0 0 1 1 0
6 Customer DBA + 000087h 1 0 0 0 0 1 1 1
7 Customer DBA + 000088h 1 0 0 0 1 0 0 0
Word Use ID Offset A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1
Lock Customer DBA+000089h 0 0 0 0 0 1 0 0 0 1 0 0 1
0 Customer DBA+00008Ah 0 0 0 0 0 1 0 0 0 1 0 1 0
: : : : : : : :::::::::
: : : : : : : :::::::::
127 Customer DBA+000109h 0 0 0 0 1 0 0 0 0 1 0 0 1
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40 316144-07
12.0 Serial Peripheral Interface (SPI)
12.1 SPI Overview
A Serial Peripher al Interface has been added as a secondary interface on Numonyx®
Omneo™ P8P PCM to enable low cost, low pin count on-board programming. This
interface gives access to the P8P memory by using only seven signals, instead of a
conventional parallel interface that may take 45 signals or more. The seven signals
consist of six SPI-only signals plus one signal that is shared with the conventional
interface.
When the SPI mode is enabled, all non-SPI P8P output signals are tri-stated, and all
non-SPI P8P inputs signals are ignored (made “don't care”). When the conventional
interface is enabled, the SPI-only output is tri-stated, and the SPI-only inputs are
ignored (made “don't care”).
Note: The SPI interface can only be enable upon power-up, and to enable this interface the
SERIAL pin must be tied to Vcc for the interface to be factional. Once the SPI interface
is enable it is the only interface that can be accessed until the part is powered down.
The SPI mode may be disabled. Please contact Numonyx for more information.
12.2 SPI Signal Names
For P8P, the six additional SPI-only signals are implemented in addition to the power
pins. VCC, VCCQ, and VPP are valid power pins during Serial mode and must be
connected during SPI mode operation. Four of the six additional SPI signals do not
share functions with the regular interface. For pin and signal descriptions of all P8P pins
see Table 5, “Ball/Pin Descriptions” on page 16. Two pins are shared between the
interface modes: S# is the same pin as CE#, and HOLD# is the same pin as OE#. The
signals that are unique to the SPI mode and require a separate connection are C, D, Q ,
and SERIAL.
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Numonyx® Omneo™ P8P Datasheet
12.3 SPI Memory Organization
The memory is organized as:
• 16,772,216 bytes (8 bits each)
• 128 sectors (128 Kbytes each)
• 131,072 pages (64 bytes each)
Each page can be individually prog rammed (bits are programmed from ‘1’ to ‘0’) or
written (bit alterable: ‘1’ can be altered to ‘0’ and ‘0’ can be altered to ‘1’). The device
is sector or bulk erasable (bits are erased from ‘0’ to ‘1’).
Table 6. Memory organization
Sector Address range Sector Address range
127 FE0000 FFFFFF 102 CC0000 CDFFFF
126 FC0000 FDFFFF 101 CA0000 CBFFFF
125 FA0000 FBFFFF 100 C80000 C9FFFF
124 F80000 F9FFFF 99 C60000 C7FFFF
123 F60000 F7FFFF 98 C40000 C5FFFF
122 F40000 F5FFFF 97 C20000 C3FFFF
121 F20000 F3FFFF 96 C00000 C1FFFF
120 F00000 F1FFFF 95 BE0000 BFFFFF
119 EE0000 EFFFFF 94 BC0000 BDFFFF
118 EC0000 EDFFFF 93 BA0000 BBFFFF
117 EA0000 EBFFFF 92 B80000 B9FFFF
116 E80000 E9FFFF 91 B60000 B7FFFF
115 E60000 E7FFFF 90 B40000 B5FFFF
114 E40000 E5FFFF 89 B20000 B3FFFF
113 E20000 E3FFFF 88 B00000 B1FFFF
112 E00000 E1FFFF 87 AE0000 AFFFFF
111 DE0000 DFFFFF 86 AC0000 ADFFFF
110 DC0000 DDFFFF 85 AA0000 ABFFFF
109 DA0000 DBFFFF 84 A80000 A9FFFF
108 D80000 D9FFFF 83 A60000 A7FFFF
107 D60000 D7FFFF 82 A40000 A5FFFF
106 D40000 D5FFFF 81 A20000 A3FFFF
105 D20000 D3FFFF 80 A00000 A1FFFF
104 D00000 D1FFFF 79 9E0000 9FFFFF
103 CE0000 CFFFFF 78 9C0000 9DFFFF
77 9A0000 9BFFFF 42 540000 55FFFF
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76 980000 99FFFF 41 520000 53FFFF
75 960000 97FFFF 40 500000 51FFFF
74 940000 95FFFF 39 4E0000 4FFFFF
73 920000 93FFFF 38 4C0000 4DFFFF
72 900000 91FFFF 37 4A0000 4BFFFF
71 8E0000 8FFFFF 36 480000 49FFFF
70 8C0000 8DFFFF 35 460000 47FFFF
69 8A0000 8BFFFF 34 440000 45FFFF
68 880000 89FFFF 33 420000 43FFFF
67 860000 87FFFF 32 400000 41FFFF
66 840000 85FFFF 31 3E0000 3FFFFF
65 820000 83FFFF 30 3C0000 3DFFFF
64 800000 81FFFF 29 3A0000 3BFFFF
63 7E0000 7FFFFF 28 380000 39FFFF
62 7C0000 7DFFFF 27 360000 37FFFF
61 7A0000 7BFFFF 26 340000 35FFFF
60 780000 79FFFF 25 320000 33FFFF
59 760000 77FFFF 24 300000 31FFFF
58 740000 75FFFF 23 2E0000 2FFFFF
57 720000 73FFFF 22 2C0000 2DFFFF
56 700000 71FFFF 21 2A0000 2BFFFF
55 6E0000 6FFFFF 20 280000 29FFFF
54 6C0000 6DFFFF 19 260000 27FFFF
53 6A0000 6BFFFF 18 240000 25FFFF
52 680000 69FFFF 17 220000 23FFFF
51 660000 67FFFF 16 200000 21FFFF
50 640000 65FFFF 15 1E0000 1FFFFF
49 620000 63FFFF 14 1C0000 1DFFFF
48 600000 61FFFF 13 1A0000 1BFFFF
47 5E0000 5FFFFF 12 180000 19FFFF
46 5C0000 5DFFFF 11 160000 17FFFF
45 5A0000 5BFFFF 10 140000 15FFFF
44 580000 59FFFF 9 120000 13FFFF
Table 6. Memory organization (Continued)
Sector Address range Sector Address range
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Numonyx® Omneo™ P8P Datasheet
12.4 SPI Instruction
Serial data input D is sampled on the first rising edge of Serial Clock (C) after Chip
Select (S#) is driven Low. Then, the one-byte instruction code must be shifted in to the
device, most significant bit first, on serial data input DQ0, each bit being latched on the
rising edges of Serial Clock (C).
The instruction set is listed in Table 20 on page 44.
Every instruction sequence starts with a one-byte instruction code. Depending on the
instruction, this might be followed by address bytes, or by data bytes, or by both or
none.
In the case of a read data bytes (READ), read data bytes at higher speed
(F AST_READ), read status register (RDSR) or read identification (RDID) instruction, the
shifted-in instruction sequence is followed by a data-out sequence. Chip Select (S#)
can be driven High after any bit of the data-out sequence is being shifted out.
In the case of a page program (PP), sector erase (SE), write status register (WRSR),
write enable (WREN), or write disable (WRDI), Chip Select (S#) must be driven High
exactly at a byte boundary, otherwise the instruction is rejected, and is not executed.
That is, Chip Select (S#) must driven High when the number of clock pulses after Chip
Select (S#) being driven Low is an exact multiple of eight.
All attempts to access the memory array during a write status register cycle, program
cycle erase cycle are ignored, and the internal write status register cycle, program
cycle, erase cycle continues unaffected.
Note: Output Hi-Z is defined as the point where data out is no longer driven
43 560000 57FFFF 8 100000 11FFFF
7 0E0000 0FFFFF 3 060000 07FFFF
6 0C0000 0DFFFF 2 040000 05FFFF
5 0A0000 0BFFFF 1 020000 03FFFF
4 080000 09FFFF 0 000000 01FFFF
Table 6. Memory organization (Continued)
Sector Address range Sector Address range
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44 316144-07
12.4.1 Write enable (WREN)
The write enable (WREN) instruction sets the write enable latch (WEL) bit.
The write enable latch (WEL) bit must be set prior to every page program (PP), sector
erase (SE), or write status register (WRSR) instruction.
The write enable (WREN) instruction is entered by driving Chip Select (S) Low, sending
the instruction code, and then driving Chip Select (S) High.
Figure 9: Write enable (WREN) instruction sequence
Table 20: Instruction set
Instruction Description One-byte instruction code Address
bytes Dummy
bytes Data
bytes
WREN Write enable 0000 0110 06h 0 0 0
WRDI Write disable 0000 0100 04h 0 0 0
RDID Read identification 1001 1111 9Fh 0 0 1 to 3
RDSR Read status register 0000 0101 05h 0 0 1 to ∞
WRSR Write status register 0000 0001 01h 0 0 1
READ Read data bytes 0000 0011 03h 3 0 1 to ∞
FAST_READ Read data bytes at higher speed 0000 1011 0Bh 3 1 1 to ∞
PP
Page program (Legacy Program) 0000 0010 02h 3 0 1 to 64
Page program (Bit-alterable write) 0010 0010 22h 3 0 1 to 64
Page program (On all 1’s) 1101 0001 D1h 3 0 1 to 64
SE Sector erase 1101 1000 D8h 3 0 0
C
DQ0
AI13731
S
DQ1
21 34567
High Impedance
0
Instruction
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12.4.2 Write disable (WRDI)
The write disable (WRDI) instruction resets the write enable latch (WEL) bit.
The write disable (WRDI) instruction is entered by driving Chip Select (S#) Low,
sending the instruction code, and then driving Chip Select (S#) High.
The write enable latch (WEL) bit is reset under the following conditions:
•Power-up
• Write disable (WRDI) instruction completion
• Write status register (WRSR) instruction completion
• Page program (PP) instruction completion
• Sector erase (SE) instruction completion
Figure 10: Write disable (WRDI) instruction sequence
C
DQ0
AI13732
S
DQ1
21 34567
High Impedance
0
Instruction
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12.4.3 Read identification (RDID)
The read identification (RDID) instruction allows to read the device identification data:
• Manufacturer identification (1 byte)
• Device identification (2 bytes)
The manufacturer identification is assigned by JEDEC, and has the value 20h for
Numonyx.
Any read identification (RDID) instruction while an erase or program cycle is in
progress, is not decoded, and has no effect on the cycle that is in progress.
The device is first selected by driving Chip Select (S#) Low. Then, the 8-bit instruction
code for the instruction is shifted in. After this, the 24-bit device identification stored in
the memory will be shifted out on serial data output (DQ1). Each bit is shifted out
during the falling edge of Serial Clock (C).
The read identification (RDID) instruction is terminated by driving Chip Select (S#)
High at any time during data output.
When Chip Select (S#) is driven High, the device is put in the standby power mode.
Once in the standby power mode, the device waits to be selected, so that it can
receive, decode and execute instructions.
Figure 11: Read identification (RDID) instruction sequence and data-out sequence
C
D
S
2134 5 6 7 8 9 10 11 12 13 14 15
Instruction
0
AI06809c
Q
Manufacturer identication
High Impedance
MSB
Device identication
MSB
15 14 13 3 2 1 0
16 17 18 28 29 30 31
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12.4.4 Read status register (RDSR)
The read status register (RDSR) instruction allows the status register to be read. The
status register may be read at any time, even while a program, erase, write status
register is in progress. When one of these cycles is in progress, it is recommended to
check the write in progress (WIP) bit before sending a new instruction to the device. It
is also possible to read the status register continuously, as shown in Figure 12 on
page 49
RDSR is the only instruction accepted by the device while a program, erase, write
status register operation is in progress.
The status and control bits of the status register are as follows:
12.4.4.1 WIP bit
The write in progress (WIP) bit indicates whether the memory is busy with a write
status register, program, erase cycle. When set to ‘1’, such a cycle is in progress, when
reset to ‘0’ no such cycle is in progress.
While WIP is ‘1’, RDSR is the only instruction the device will accept; all other
instructions are ignored.
12.4.4.2 WEL bit
The write enable latch (WEL) bit indicates the status of the internal write enable latch.
When set to ‘1’ the internal write enable latch is set, when set to ‘0’ the internal write
enable latch is reset and no write status register, program, erase instruction is
accepted.
12.4.4.3 BP3, BP2, BP1, BP0 bits
The block protect (BP3, BP2, BP1, BP0) bits are non-volatile. They define the size of the
area to be software protected against program (or write) and er ase instructions. These
bits are written with the write status register (WRSR) instruction. When one or more of
the block protect (BP3 , BP2 , BP1, BP 0) bi ts is set to ‘1’, the relevant memory area (as
defined in Table 1) becomes protected against page program (PP), dual input fast
program (DIFP), quad input fast program (QIFP), and sector erase (SE) instructions.
The block protect (BP3, BP2, BP1, BP0) bits can be written provided that the hardware
protected mode has not been set.The bulk erase (BE) instruction is executed if, and
only if, all block protect (BP3, BP2, BP1, BP0) bits are 0.
Table 21: Status regist er format
b7 b0
SRWD BP3 TB BP2 BP1 BP0 WEL WIP
Status regist er w rite protect
RFU
RFU
Write enable latch bit
Write in progress bit
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48 316144-07
b
12.4.4.4 Top/bottom bit
Reads as 0
12.4.4.5 SRWD bit
The status register write disable (SRWD) bit is operated in conjunction with the write
protect (W) signal. The status register write disable (SRWD) bit and the write protect
(W) signal allow the device to be put in th e hardware protected mode (when the status
register write disable (SRWD) bit is set to ‘1’, and write protect (W) is driven Low). In
this mode, the non-volatile bits of the status register (SRWD, TB, BP3, BP2, BP1, BP0)
become read-only bits and the write status register (WRSR) instruction is no longer
accepted for execution.
Table 7. Protected area sizes
Sta tus register contents Memory content
TB
bit BP
bit 3 BP
bit 2 BP
bit 1 BP
bit 0 Protected area Unprotected area
0 0 0 0 0 none All sectors1 (Sectors 0 to 127)
0 0 0 0 1 Upper 128th (Sector 127) Sectors 0 to 126
0 0 0 1 0 Upper 64th (Sectors 126 to 127) Sectors 0 to 125
0 0 0 1 1 Upper 32nd (Sectors 124 to 127) Sectors 0 to 123
0 0 1 0 0 Upper 16th (Sectors 120 to 127) Sectors 0 to 119
0 0 1 0 1 Upper 8th (Sectors 112 to 127) Sectors 0 to 111
0 0 1 1 0 Upper quarter (Sectors 96 to 127) Sectors 0 to 95
0 0 1 1 1 Upper half (Sectors 64 to 127) Sectors 0 to 63
01X
(2) X(2) X(2) All sectors (Sectors 0 to 127) None
1 0 0 0 0 none All sectors(1) (Sectors 0 to 127)
1 0 0 0 1 Lower 128th (Sector 0) Sectors 1 to 127
1 0 0 1 0 Lower 64th (Sectors 0 to 1) Sectors 2 to 127
1 0 0 1 1 Lower 32nd (Sectors 0 to 3) Sectors 4 to 127
1 0 1 0 0 Lower 16th (Sectors 0 to 7) Sectors 8 to 127
1 0 1 0 1 Lower 8th (Sectors 0 to15) Sectors 16 to 127
1 0 1 1 0 Lower 4th (Sectors 0 to 31) Sectors 32 to 127
1 0 1 1 1 Lower half (Sectors 0 to 63) Sectors 64 to 127
11X
(2) X(2) X(2) All sectors (Sectors 0 to 127) None
1. The device is ready to accept a bulk erase instruction if, and only if, all block protect (BP3, BP2, BP1, BP0) are 0
2. X can be 0 or 1
1.
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Numonyx® Omneo™ P8P Datasheet
Figure 12: Read status register (RDSR) instruction sequence and data-out sequence
C
DQ0
S
21 3456789101112131415
Instruction
0
AI13734
DQ1 76543210
Status register out
High Impedance
MSB
76543210
Status register out
MSB
7
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12.4.5 Write status register (WRSR)
The write status register (WRSR) instruction allows new values to be written to the
status register. Before it can be accepted, a write enable (WREN) instruction must
previously have been executed. After the write enable (WREN) instruction has been
decoded and executed, the device sets the write enable latch (WEL).
The write status register (WRSR) instruction is entered by driving Chip Select (S#)
Low, followed by the instruction code and the data byte on serial data input (DQ0).
The write status register (WRSR) instruction has no effect on b1 and b0 of the status
register.
Chip Select (S#) must be driven High after the eighth bit of the data byte has been
latched in. If not, the write status register (WRSR) instruction is not executed. As soon
as Chip Select (S#) is driven High, the self-timed write status register cycle (whose
duration is tW) is initiated. While the write status register cycle is in progress, the
status register may still be read to check the value of the write in progress (WIP) bit.
The write in progress (WIP) bit is 1 during the self-timed write status register cycle,
and is 0 when it is completed. When the cycle is completed, the write enable latch
(WEL) is reset.
The write status register (WRSR) instruction allows the user to change the values of the
block protect (BP3, BP2, BP1, BP0) bits, to define the size of the area that is to be
treated as read-only. The write status register (WRSR) instruction also allows the user
to set and reset the status register write disable (SRWD) bit in accordance with the
Write Protect (W) signal. The status register write disable (SRWD) bit and Write Protect
(W) signal allow the device to be put in th e hardware protected mode (HPM). The write
status register (WRSR) instruction is not executed once the hardware protected mode
(HPM) is entered.
Read Status Register (RDSR) is the only instruction accepted while WRSR operation is
in progress; all other instructions are ignored.
Figure 13: Write status register (WRSR) instruction sequence
C
DQ0
AI13735
S
DQ1
21 3456789101112131415
High Impedance
Instruction Status
register in
0
765432 0
1
MSB
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12.4.6 Read data bytes (READ)
The device is first selected by driving Chip Select (S#) Low. The instruction code for the
read data bytes (READ) instruction is followed by a 3-byte address A[23:0], each bit
being latched-in during the rising edge of Serial Clock (C). Then the memory contents,
at that address, is shifted out on serial data output (Q), each bit being shifted out, at a
maximum frequency fR, during the falling edge of Serial Clock (C).
The first byte addressed can be at any location. The address is automatically
incremented to the next higher address after each byte of data is shifted out. The
whole memory can, therefore, be read with a single read data bytes (READ)
instruction. When the highest address is reached, the address counter rolls over to
000000h, allowing the read sequence to be continued indefinitely.
The read data bytes (READ) instruction is terminated by driving Chip Select (S#) High.
Chip Select (S#) can be driven High at any time during data output. Any read data
bytes (READ) instruction, while an erase, program, write cycle is in progress, is
rejected without having any effects on the cycle that is in progress.
Figure 14: Read data bytes ( READ) instruction sequence and data-out sequence
C
DQ0
AI13736b
S
DQ1
23
21 345678910 2829303132333435
2221 3210
36 37 38
76543 1 7
0
High Impedance Data out 1
Instruction 24-bit address (1)
0
MSB
MSB
2
39
Data out 2
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12.4.7 Read data bytes at higher speed (FAST_READ)
The device is first selected by driving Chip Select (S#) Low . The instruction code for the
read data bytes at higher speed (FAST_READ) instruction is followed by a 3-byte
address A[23:0] and a dummy byte, each bit being latched-in during the rising edge of
Serial Clock (C). Then the memory contents, at that address, are shifted out on serial
data output (Q) at a maximum frequency fC, during the falling edge of Serial Clock (C).
The first byte addressed can be at any location. The address is automatically
incremented to the next higher address after each byte of data is shifted out. The
whole memory can, therefore, be read with a single read data bytes at higher speed
(FAST_REA D) instruction. When the highest address is reached, the address counter
rolls over to 000000h, allowing the read sequence to be continued indefinitely.
The read data bytes at higher speed (FAST_READ) instruction is terminated by driving
Chip Select (S#) High. Chip Select (S#) can be driven High at any time during data
output. Any read data bytes at higher speed (FAST_READ) instruction, while an erase,
program, write, or cycle is in progress, is rejected without having any effects on the
cycle that is in progress.
Figure 15: Read data bytes at higher speed (FAST_READ) instruction sequence
and data-out sequence
C
DQ0
AI13737b
S
DQ1
23
21 345678910 28293031
2221 3210
High Impedance
Instruction 24-bit address
(1)
0
C
DQ0
S
DQ1
32 33 34 36 37 38 39 40 41 42 43 44 45 46
765432 0
1
DATA OUT 1
Dummy byte
MSB
76543210
DATA OUT 2
MSB MSB
7
47
765432 0
1
35
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12.4.8 Page program (PP)
Note: This definition applies to all flavors of Pag e Program: Legacy P rogram, Bit-alterab le.
The page program (PP) instruction allows bytes to be programmed/written in the
memory. Before it can be accepted, a write enable (WREN) instruction must previously
have been executed. After the write enable (WREN) instruction has been decoded, the
device sets the write enable latch (WEL).
The page program (PP) instruction is entered by driving Chip Select (S#) Low, followed
by the instruction code, three address bytes and at least one data byte on serial data
input (DQ0). If the 6 least significant address bits (A5-A0) are not all zero, all
transmitted data that goes beyond the end of the current page are programmed from
the start address of the same page (from the address whose 6 least significant bits
(A5-A0) are all zero). Chip Select (S#) must be driven Low for the entire duration of
the sequence.
If more than 64 bytes are sent to the device, previously latched data are discarded and
the last 64 data bytes are guaranteed to be programmed/written correctly within the
same page. If less than 64 data bytes are sent to device, they are correctly
programmed/written at the requested addresses without having any effects on the
other bytes of the same page. (With Program on all 1s, the entire page should already
have been set to all 1s (FFh).)
For optimized timings, it is recommended to use the page program (PP) instruction to
program all consecutive targeted bytes in a single sequence versus using several page
program (PP) sequences with each containing only a few bytes.
Chip Select (S#) must be driven High after the eighth bit of the last data byte has been
latched in, otherwise the page program (PP) instruction is not executed.
As soon as Chip Select (S#) is driven High, the self-timed page program cycle (whose
duration is tPP) is initiated. While the page program cycle is in progress, the status
register may be read to check the value of the write in progress (WIP) bit. The write in
progress (WIP) bit is 1 during the self-timed page program cycle, and is 0 when it is
completed. At some unspecified time before the cycle is completed, the write enable
latch (WEL) bit is reset. RDSR is the only instruction accepted while a Page Program
operation is in progress; all other instructions are ignored.
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54 316144-07
Figure 16: Page program (PP) instruction sequence
C
DQ0
AI13739b
S
4241 43 44 45 46 47 48 49 50 52 53 54 5540
C
DQ0
S
23
21 345678910 2829303132333435
2221 3210
36 37 38
Instruction 24-bit address (1)
0
765432 0
1
Data byte 1
39
51
765432 0
1
Data byte 2
765432 0
1
Data byte 3 Data byte 256
2079
2078
2077
2076
2075
2074
2073
765432 0
1
2072
MSB MSB
MSB MSB MSB
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12.4.9 Sector erase (SE)
The sector erase (SE) instruction sets to ‘1’ (FFh) all bits inside the chosen sector.
Before it can be accepted, a write enable (WREN) instruction must previously have
been executed. After the write enable (WREN) instruction has been decoded, the device
sets the write enable latch (WEL).
The sector erase (SE) instruction is entered by driving Chip Select (S#) Low, followed
by the instruction code, and three address bytes on serial data input (DQ0). Any
address inside the sector is a valid address for the sector erase (SE) instruction. Chip
Select (S#) must be driven Low for the entire duration of the sequence.
Chip Select (S#) must be driven High after the eighth bit of the last address byte has
been latched in, otherwise the sector erase (SE) instruction is not executed. As soon as
Chip Select (S#) is driven High, the self-timed sector erase cycle (whose duration is
tSE) is initiated. While the sector erase cycle is in progress, the status register may be
read to check the value of the write in progress (WIP) bit. The write in progress (WIP)
bit is 1 during the self-timed sector erase cycle, and is 0 when it is completed. At some
unspecified time before the cycle is completed, the write enable latch (WEL) bit is
reset. RDSR is the only instruction accepted while device is busy with erase operation;
all other instructions are ignored.
A sector erase (SE) instruction applied to a page which is protected by the block protect
(BP3, BP2, BP1, BP0) bits is not executed.
Figure 17: Sector erase (SE) instruction sequence
24-bit address
(1)
C
DQ1
AI13742b
S
21 3456789 293031
Instruction
0
23 22 2 0
1
MSB
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13.0 Power and Reset Specification
13.1 Power-Up and Power-Down
Upon power-up the flash memory interface is defined by the SERIAL pin being at Vss
(parallel) or Vcc (serial).
• During power-up if the SERIAL pin is at Vss the flash memory will be a x16 parallel
interface.
• During power-up if the SERIAL pin is at Vcc the flash memory will be a SPI
interface.
After the interface is defined it can not be changed until a full power-down is completed
and a power-up sequence is reinitiated.
Power supply sequencing is not required if VPP is connected to VCC or VCCQ. Otherwise
VCC and VCCQ should attain their minimum operating voltage before applying VPP.
Power supply transitions should only occur when RST# is low. This protects the device
from accidental programming or erasure during power transitions.
13.2 Reset Specifications
Asserting RST# during a system reset is important with automated program/erase
devices because systems typically expect to read from flash memory when coming out
of reset. If a CPU reset occurs without a flash memory reset, proper CPU initialization
may not occur. This is because the flash memory may be providing status information,
instead of array data as expected. Connect RST# to the same active low reset signal
used for CPU initialization.
Also, because the device is disabled when RST# is asserted, it ignores its control inputs
during power-up/down. Inv alid bus conditions are masked, providing a level of memory
protection.
Table 22: Power and Reset
Num Symbol Parameter(1) Min Max Unit Notes
P1 tPLPH RST# pulse width low 100 - ns 1,2,3,4
P2 tPLRH RST# low to device reset during erase - 40
us
1,3,4,7
RST# low to device reset during program - 40 1,3,4,7
P3 tVCCPH VCC Power valid to RST# de-assertion (high) 100 - 1,4,5,6
Notes:
1. These specifications are valid for all device versions (packages an d speeds).
2. The device may reset if tPLPH is < tPLPH MIN, but this is not guaranteed.
3. Not applicable if RST# is tied to Vcc.
4. Sampled, but not 100% tested.
5. When RST# is tied to the VCC supply, device will not be ready until tVCCPH after VCC ≥ VCCMIN.
6. When RST# is tied to the VCCQ supply, device will not be ready until tVCCPH after VCC ≥ VCCMIN.
7. Reset completes within tPLPH if RST# is asserted while no erase or program operation is executing.
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13.3 Power Supply Decoupling
Flash memory devices require careful power supply de-coupling. Three basic power
supply current considerations are 1) standby current levels, 2) active current levels,
and 3) transient peaks produced when CE# and OE# are asserted and deasserted.
When the device is accessed, many internal conditions change. Circuits within the
device enable charge-pumps, and internal logic states change at high speed. All of
these internal activities produce transient signals. Transient current magnitudes depend
on the device outputs’ capacitive and inductive loading. Two-line control and correct
de-coupling capacitor selection suppress transient voltage peaks.
Because Numonyx flash memory devices draw their power from VCC, VPP, and VCCQ,
each power connection should have a 0.1 µF ceramic capacitor to ground. High-
frequency, inherently low-inductance capacitors should be placed as close as possible
to package leads.
Additionally, for every eight devices used in the system, a 4.7 µF electrolytic capacitor
should be placed between power and ground close to the devices. The bulk capacitor is
meant to overcome voltage droop caused by PCB trace inductance.
Figure 18: Reset Operation Waveforms
(
A) Reset during
read mode
(B) Reset during
program or block erase
P1
≤
P2
(C) Reset during
program or block erase
P1
≥
P2
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
RST# [P]
RST# [P]
RST# [P]
Abort
Complete
Abort
Complete
V
CC
0V
V
CC
(D) VCC Power-up to
RST# high
P1 R5
P2
P3
P2 R5
R5
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Datasheet July 2010
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14.0 Max Ratings and Operating Conditions
14.1 Absolute Maximum Ra tings
Warning: Stressing the device beyond the “Absolute Maximum Ratings” may cause permanent
damage. These are stress ratings only.
Notes:
1. All specified voltages are with respect to Vss. During i nfrequent non-periodic tr ansitions, the v oltage potential between Vss
and input/output pins may undershoot to -2.0v for periods <20 ns or overshoot to VCCQ + 2.0v for periods <20 ns.
2. During infrequent non-p eriodic tr ansitions the v oltage potent ial between Vss and the supplies may un dershoot to -2.0v fo r
periods <20 ns or overshoot to VSUPPLY (max) + 2.0v for periods <20 ns.
3. Output shorted for no more than one second. No more than one output shorted at a time.
4. For functional operating voltages, please refer to Section 27, “DC Voltage Characteristics” on page 61
5. Make sure that VCCQ is less or equal to VCC in value, otherwise the device fails to oper ate co rrectly” in the nex t revision of
the datasheet.
14.2 Operating Conditions
Note: Operation beyond the “Operating Conditions” is not recommended and extended exposure
beyond the “Operating Conditions” may affect device reliability.
Table 23: Absolute Maximum Ratings
Parameter Maximum Rating
Voltage on any signal (except VCC, Vccq, VPP)(1) –2.0 V to +5.6v, <20ns
VPP voltage(2,4) –2.0 V to +5.6v, <20ns
VCC voltage(2,4) –2.0 V to +5.6v, <20ns
VCCQ voltage(2,4,5) –2.0 V to +5.6v, <20ns
Output short circuit current(3) 100 mA
Table 24: Operating Conditions
Symbol Parameter Min Max Units Notes
TCOperating Temperature (115 ns) 0 +70 °C 1
TCOperating Temperature (135 ns) -30 +85 °C
VCC VCC Supply Voltage 2.7 3.6
VVCCQ I/O Supply Voltage CMOS inputs 1.7 3.6 2
TTL inputs 2.4 3.6
VPP VPP Voltage Supply (Logic Level) 0.9 3.6 3
Notes:
1. TC = Case Temperature.
2. VCCQ = 1.7v - 3.6v range is intended for CMOS inputs and the 2.4v - 3.6v is intended for TTL inputs.
3. In typical operation VPP program voltage is VPPL.
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14.3 Endurance
Numonyx® Omneo™ P8P PCM endurance is different than traditional non-volatile
memory. For PCM a “write cycle” is defined as any time a bit changes within a 32-byte
page.
Table 25: Endurance
Parameter Condition Min Units Notes
Write Cycle Main Block (VPP = VPPH)1,000,000 Cycles per
32-Byte Page 1
Parameter Block (VPP = VPPH)1,000,000
Notes:
1. In typical operation VPP program voltage is VPPL.
Numonyx® Omneo™ P8P Datasheet
Datasheet July 2010
60 316144-07
15.0 Electrical Specifications
15.1 DC Current Characteristics
Note: Refer Table 27 on page 61 for the Notes relevant to this table.
Table 26: DC Current Characteristics
Sym Parameter(1) Note
CMOS Inputs
VCCQ
1.7v - 3.6v
TTL Inputs
VCCQ
2.4v - 3.6v Unit Test Condition
Typ Max Typ Max
ILI Input Load 9 ±1 ±2 µA VCC = VCCMAX
VCCQ = VCCQMAX
VIN = VCCQ or GND
ILO Output
Leakage DQ15-0 ±1 ±10 µA VCC = VCCMAX
VCCQ = VCCQMAX
VIN = VCCQ or GND
ICCS
ICCD
VCC
Standby,
Power Down 128-Mbit 11 80 160 80 160 µA
VCC = VCCMAX, VCCQ = VCCQMAX
CE# = VCCQ, RST# = VCCQ
WP# = VIH
Must reach stated ICCS ≤ 5µS after
CE# = VIH
ICCR
Average
VCC
Read
Asynchronous single
word
f = 5MHz (1 CLK) 30 42 30 42 mA Internal 8 Word
Read VCC = VCCMAX
CE# = VIL
OE# = VIH
Inputs: VIH or
VIL
Page Mode
f = 13 MHz (9 CLK) 15 20 15 20 mA 8 Word Read
ICCW,
ICCE
VCC Write,
VCC Erase 3,4,5,
12 35 50 36 51 mA program/erase in progress
ICCWS
ICCES VCC Write Suspend
VCC Erase Suspend 6Refer to ICCS for each density
above. µA CE# = VCCQ, suspend in progress
IPPS
IPPWS
IPPES
VPP Standby
VPP Write Suspend
VPP Erase Suspend 30.250.25µAV
PP = VPPL, suspend in progress
IPPR VPP Read 215215µAV
PP ≤ VCC
IPPW VPP Write 3 0.05 0.10 0.05 0.10 mA write in progress
IPPE VPP Erase 3 0.05 0.10 0.05 0.10 mA erase in progress
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15.2 DC Voltage Characteristics
Notes:
1. All currents are RMS unless noted. Typical values at typical VCC, TA = +25°C.
2. See Section , “” on page 57 for details.
3. Sampled, not 100% tested.
4. VCC read + write current is the sum of VCC read and VCC write currents.
5. VCC read + erase current is the sum of VCC read and VCC erase currents.
6. ICCES is specified with device deselected. If device is read while in erase suspend, current is ICCES plus ICCR.
7. VPP <= VPPLK inhibits erase and write operations. Don’t use V PP outside the valid range.
8. VIL can undershoot to –1. 0V for dur ations o f 2 ns or less and V IH can over shoot to V CCQ(MAX)+1.0V for durations of 2 ns or
less.
9. If VIN>VCC the inpu t load current increases to 10 µA max.
10. ICCRQ is the output component of read current drawn from VCC, not VCCQ.
11. ICCS is the average current measured over any 5ms time interval 5µs after a CE# deassertion.
12. ICCW, ICCE measured over typical or max times specified in Section 17.0, “Program and Erase
Characteristics” on page 71
Table 27: DC Voltage Characteristics
Sym Parameter Notes
CMOS Inputs
VCCQ
1.7v - 3.6v
TTL Inputs
VCCQ
2.4v - 3.6v Unit Test Condition
Min Max Min Max
VIL Input Low 8 0 0.4 0 0.6 V
VIH Input High 8 VCCQ – 0.4 VCCQ 2.0 VCCQ V
VOL Output Low 0.1 0.1 V VCC = VCCMIN
VCCQ = VCCQMIN
IOL = 100 µA
VOH Output High VCCQ – 0.1 VCCQ – 0.1 V VCC = VCCMIN
VCCQ = VCCQMIN
IOH = –100 µA
VPPLK VPP Lock-Out 7 0.4 0.4 V
VLKO VCC Lock 1.5 1.5 V
VLKOQ VCCQ Lock 0.9 0. 9 V
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16.0 AC Characteristics
16.1 AC Test Conditions
Note: AC test inputs are driven at VCCQ for Logic "1" and 0.0 V for Logic "0." Input/output
timing begins/ends at VCCQ/2. Input rise and fall times (10% to 90%) < 5 ns. Worst
case speed occurs at VCC = VCCMin.
16.2 Capacitance
Figure 19: AC Input/Output Reference Waveform
Figure 20: Transient Equivalent Testing Load Circuit
Table 28: Test configuration component value for wor s t case speed conditions
Test Configuration CL (pF) (includes jig c apa citance)
VCCQMIN 30
Table 29: Capacitance: TA = +25°C, f = 1 MHz (Sampled, not 100% tested)
Symbol Parameter(1) Min Typ Max Unit Condition
CIN Input Capacitance 2 6 8 pF VIN = 0.0 V
COUT Output Capacitance 2 4 7 pF VOUT = 0.0 V
IO_REF.WMF
Input V
CCQ
/2 V
CCQ
/2 Output
V
CCQ
0V
Test Points
Device
Under Test Out
C1
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Notes:
1. See Figure 19 on page 62 for timing measurements and maximum allowable input slew rate.
2. OE# may be delayed by up to tELQV – tGLQV after CE#’s falling edge without impact to tELQV.
3. Sampled, not 100% tested.
4. All specs above apply to all densities.
16.3 AC Read Specifications
Table 30: AC Read Specifications
Num Sym Parameter(1) Temp 0 to +70 C -30 to +85 C Units
Note Min Max Min Max
Asynchronous Specifications
R1 tAVAV Read cycle time 1,4 115 135 ns
R2 tAVQV Address to output valid 1,4 115 135 ns
R3 tELQV CE# low to output valid 1,4 115 135 ns
R4 tGLQV OE# low to output valid 1,2,4 25 25 ns
R5 tPHQV RST# high to output valid 1,4 150 150 ns
R6 tELQX CE# low to output in low-Z 3,4 0 0 ns
R7 tGLQX OE# low to output in low-Z 1,2,3,4 0 0 ns
R8 tEHQZ CE# high to output in high-Z 1,3,4 24 24 ns
R9 tGHQZ OE# high to output in high-Z 1,3,4 24 24 ns
R10 tOH Output hold from first occurring address, CE#, or OE# change 1,3,4 0 0 ns
R11 tEHEL CE# pulse width high 1,4 20 20 ns
R108 tAPA Page address access 25 25 ns
Figure 21: Asynchronous Single-Word Read
R5
R10
R7
R6
R9R4
R8R3
R1
R2 R1
A
ddress [A ]
CE# [ E}
OE# [G]
Data [D/Q]
RST# [P]
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Datasheet July 2010
64 316144-07
Figure 22: Asynchronous Page Mode Read Timing
Q1 Q2 Q3 Q7
R108R108R108
R6
R9R4
R8R3
R10R10R10R10
R1R1
R2
A
[Max:4] [A]
A[3:1]
CE# [E]
OE# [G]
DATA [D/Q]
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16.4 AC Write Specifications
Notes:
1. Write timing characteristics during erase suspend are the same as write-only operations.
2. CE#- or WE#-high terminates a write operation.
3. Sampled, not 100% tested.
4. Write pulse width low (tWLWH or tELEH) is defined from CE# or WE# low (whichever occurs last) to CE# or WE# high
(whichever occurs first). Hence, tWLWH = tELEH = tWLEH = tELWH.
5. Write pulse width high (tWHWL or tEHEL) is defined from CE# or WE# high (whichever is first) to CE# or WE# low
(whichever is last). Hence, tWHWL = tEHEL = tWHEL = tEHWL.
6. VPP and WP# should be at a valid level without changing state until erase or program success is determined.
7. This spec is only applicable when transitioning from a write cycle to an asynchronous read.
8. When doing a read status operation following any command that alters the Status Register contents, W14 is 20ns.
9. Add 10ns if the write operation results in a block lock status chan ge, for subse quent read oper ations to reflect this chang e.
10. Guaranteed by design.
Table 31: AC Write Characteristics
Num Sym Parameter (1, 2) Speed All Speeds Units
Note Min Max
W1 tPHWL RST# high recovery to WE# low 3 150 ns
W2 tELWL CE# setup to WE# low 10 0 ns
W3 tWLWH WE# write pulse width low 4 50 ns
W4 tDVWH Data setup to WE# high 50 ns
W5 tAVWH Address valid setup to WE# high 50 ns
W6 tWHEH CE# hold from WE# high 10 0 ns
W7 tWHDX Data hold from WE# high 0 ns
W8 tWHAX Address hold from WE# high 0 ns
W9 tWHWL WE# pulse width high 20 ns
W10 tVPWH V
PP setup to WE# high 3,6 200 ns
W11 tQVVL VPP hold from valid Status read 3,6 0 ns
W12 tQVBL WP# hold from valid Status read 3,6 0 ns
W13 tBHWH WP# setup to WE# high 3,6 200 ns
W14 tWHGL WE# high to OE# low 8 0 ns
W16 tWHQV WE# high to read valid 3, 5, 9 tAVQV+35 ns
Write to Asynchronous Read Specifications
W18 tWHAV WE# high to Address valid 3, 5, 7 0 ns
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Datasheet July 2010
66 316144-07
Note: See sections 7.6 (AC Read Characteristics) and 7.7 (AC Write Characteristics) for the
values of Rs and Ws.
Figure 23: Single-Word Write Timing
W13
W1
W7
W4
W7
W4
W3W9 W3W9W3W3
W6W2W6W2
W8W18 W5W5
A
ddress [A]
CE# [ E}
WE# [ W ]
OE# [G]
Data [D/Q]
RST# [P]
WP#
Figure 24: Asynchronous Read-to-Write Timing
Q D
R5
W7
W4R10
R7
R6
W6
W3W3
W2
R9R4
R8R3
W8W5
R1
R2 R1
A
ddress [A]
CE# [E}
OE# [G]
WE# [ W]
Data [D/Q]
RST# [P]
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Numonyx® Omneo™ P8P Datasheet
See sections 7.6 (AC Read Characteristics) and 7.7 (AC Write Characteristics) for the
values of Rs and Ws.
Figure 25: Write-to-Asynchronous Read Timing
D Q
W1
R9
R8
R4
R3
R2W7
W4
W14
W18W3W3
R10W6W2
R1R1W8W5
A
ddress [A]
CE # [ E}
WE# [W]
OE# [G]
Data [D/Q]
RST# [P]
Numonyx® Omneo™ P8P Datasheet
Datasheet July 2010
68 316144-07
16.5 SPI AC Specifications
Notes:
1. TCH + TCL must be greater than or equal to 1/FC(max).
2. Sampled, not 100% tested.
3. Expressed as a slew-rate
4. Only applicable as a constraint for a WRSR instruction when SRWD is set to 1.
Sym Parameter Speed -All Spee ds Units
Note Min Max
FCClock Frequency for all instructions except READ (0 to +70) D.C. 50 MHz
FCClock Frequency for all instructions except READ (-30 to +85) D.C. 33 M Hz
FRClock Frequency for READ D.C. 25 MHz
TCH Clock High Time 19 ns
TCL Clock Low Time 19 ns
TCLCH Clock Rise Time (peak to peak) 2, 3 0.1 V/ns
TCHCL Clock Fall Time (peak to peak) 2, 3 0.1 V/ns
TSLCH S# Active Setup Time (relative to C) 5 ns
TCHSL S# Active Hold Time (relative to C) 5 ns
TDVCH Data Input Setup Time 2ns
TCHDX Data Input Hold Time 5ns
TCHSH S# Active Hold Time (relative to C) 5 ns
TSHCH S# Inactive Hold Time (relative to C) 5 ns
TSHSL S# Deselect Time 100 ns
TSHQZ Output Disable Time 2 8 ns
TCLQV Clock Low to Output Valid 9ns
TCLQX Output Hold Time 0ns
THLCH HOLD# Assertion Setup Time (relative to C) 5 ns
TCHHH HOLD# Assertion Hold Time (relative to C) 5 ns
THHCH HOLD# De-assertion Setup Time (relative to C) 5 ns
TCHHL HOLD# De-assertion Hold Time (relative to C) 5 ns
THHQX HOLD# De-assertion to Output Low-Z 2 10 ns
THLQZ HOLD# De-assertion to Output High-Z 2 10 ns
TWHSL W# Setup Time 420 ns
TSHWL W# Hold Time 4 100 ns
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Numonyx® Omneo™ P8P Datasheet
Figure 26: Serial Input Timing
Figure 27: Write Protect Setup and Hold Timing during WRSR when SRWD=1
Figure 28: Hold Timing
MSB LSB
tCHDX
tDVCH
tSHSLtSHSL
tSHCH
tCHSH
tSLCH
tCHSL
C
S#
D
Q
MSB IN LS B I N
tSHWLtWHSL
C
S
W#
D
Q
MSB IN LS B I N
tHHQX
tHHCH
tCHHH
tHLQZ
tHLCH
tCHHL
C
S
D
Q
HOLD#
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Datasheet July 2010
70 316144-07
Figure 29: Output Timing
LSB OUT
A
DDR LSB I N
tSHQZ
tCLQV
tCLQXtCLQV
tCLQX
tCHtCHtCLtCL
C
S
Q
D
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Numonyx® Omneo™ P8P Datasheet
17.0 Program and Erase Characteristics
Notes:
1. Typical values measured at TA = +25 °C, typical voltages and 50% data pattern per word. Excludes system overhead.
Performance numbers are valid for all speed versions. Sampled, but not 100% tested.
2. Averaged over entire device.
3. W602 is the minimum time between an initial block erase or er ase resume command an d the a subsequent eras e suspend
command. Violating the specification repeatedly during any particular b lock erase may cause erase failures in flash
devices. This specification is required if the designer wishes to maintain compatibility with the P33 NOR flash device.
However, it is not required with PCM.
4. These p erformance numbers are valid for all speed versions.
5. Sampled, not 100% tested.
Table 32: Program and Erase Specification
Operation(1) Symbol Parameter Description VPPL(4,5)
Unit
Min Typ Max
Erasing and Suspending
Erase to Suspend W602 3tERS/SUSP Erase or Erase-Resume
command to Erase-suspend
command 500 µs
Erase Time W500 tERS/PB 16-KW Parameter 100 200 ms
W501 tERS/MB 64-KW Main 400 800
Suspend Latency W600 tSUSP/P Write suspend 35 60 µs
W601 tSUSP/E Erase suspend 35 60
Conventional Word Programming
Program Time(6) W200 tPROG/W Single word 60 120 µs
Buffered Programming
Program Time
W200 tPROG/W
Single word
(Legacy Program & Bit-
alterable Write) 5 120 240 µs
W250 tPROG/PB
One Buffer (64 Bytes/32
words)
(Legacy Program & Bit-
alterable Write) 4,5
120 360
µs
One Buffer (64 Bytes/32
words)
(Program on all 1s) 71 280
Numonyx® Omneo™ P8P Datasheet
Datasheet July 2010
72 316144-07
18.0 Ordering Information
This section defines all active line items that can be ordered.
Table 33: Active Line Item Ordering Table (0 to +70 oC)
Part Number Description
NP8P128A13BSM60E P8P 128Mb TSOP 14x20 Bottom Boot
NP8P128A13TSM60E P8P 128Mb TSOP 14x20 Top Boot
NP8P128A13B1760E P8P 128M leadfree 10x8x1.2 easyBGA Bottom Boot
NP8P128A13T1760E P8P 128M leadfree 10x8x1.2 easyBGA Top Boot
Table 34: Active Line Item Ordering Table (-30 to +85 oC)
Part Number Description
NP8P128AE3BSM60E P8P 128Mb TSOP 14x20 Bottom Boot
NP8P128AE3TSM60E P8P 128Mb TSOP 14x20 Top Boot
NP8P128AE3B1760E P8P 128M leadfree 10x8x1.2 ea syBGA Bottom Boot
NP8P128AE3T1760E P8P 128M leadfree 10x8x1.2 easyBGA Top Boot
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Appendix A Supplemental Reference Information
A.1 Flow Charts
Figure 30: Word Programming or Bit Alterable Write Flowchart
Suspend
Write
Loop
Start
Write 40h or 42h
Word Address
Write Dat a
Word Address
Read Status
Register
SR.7 =
Full Status
Check
(if desired)
Write
Complete
FULL WRITE STA TUS CHECK PROCEDURE
Suspend
Write
Read Status
Register
Write
Successful
SR.3 =
SR.1 =
0
0
SR.4 =
0
1
1
1
1
0
No
Yes
VPP Range
Error
Device
Protect Error
Write
Error
WORD PROGRAM or BIT ALTERABLE WORD WRITE PROCEDURE
SR.3 MUST be cleared before the Write State Machine will
allow further write attempts
Only the Clear Staus Register command clears SR.1, 3, 4.
If an error is detected, clear the status register before
attempting a write retry or other error recovery.
Standby
Standby
Bus
Operation Command
Check SR.3
1 = VPP error
Check SR.4
1 = Data write error
Comments
Repeat for subsequent write operations.
Full status register check can be done after each write or after
a sequence of write operations.
Write FFh after the last operati on to enter read array mode.
Comments
Bus
Operation Command
Data = 40h or 42h (Bit Alterable)
Addr = Location to write (WA)
Write Program/
Write
Setup
Data = Data to be written (WD)
Addr = Location to be written (WA)
Write Data
Status register data. Initiate a read
cycle to update status register
Read
Check SR.7
1 = WSM ready
0 = WSM busy
Standby
Standby Check SR.1
1 = Attempted write to locked block
Write aborted
PGM_WRD.WMF
Program Setup
Confirm Data
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Figure 31: Write Suspend/Resume Flowchart
Read Status
Register
SR.7 =
SR.2 =
Read Array
Data
Write
Completed
Done
Reading
Write
Resumed Read Array
Data
0
No
0
Yes
1
1
WRITE SUSPEND / RESUME PROCEDURE
Write Write
Resume Data = D0h
Addr = Suspended block (BA)
Bus
Operation Command Comments
Write Write
Suspend Data = B 0h
Addr = X
Standby Check SR.7
1 = WSM ready
0 = WSM busy
Standby Check SR.2
1 = Program suspended
0 = Program completed
Write Read
Array Data = FFh
Addr = Block address to read (BA)
Read Read array data from block other than
the one being writte
Read
Status register data
Initiate a read cycle to update status
register
Addr = Suspended block (BA)
PGM_SUS.WMF
Start
Write B0h
Any Address
Program Suspend
Read Status
Write 70h
Write FFh
Read Array
Write D0h
Any Address
Write Resume
Write FFh
Read Array
Write Read
Status Data = 70h
Addr = Block to suspend (BA)
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Figure 32: Buffer Program or Bit Alterable Buffer Write Flowchart
Start
Get Next
Target Address
Issue Write to Buf fer
Command E8h or EAh
and Block Address
Read Status Register
(at Block Address)
Is WSM Ready?
SR.7 =
1 = Yes
Device
Supports Buffer
Writes?
Set Timeout or
Loop Counter
Timeout
or Count
Expired?
Write Confir m D0h
and Block Address
Another Buffered
Write?
Yes
No
No
Write Buffer Data,
Start Address
X = 0
Yes
0 = No
No
Yes
Use Single Word Writes
Abort Bufferred
Write?
No
X = N?
Write Buffer Data,
Block Address
X = X + 1
Write to anot her
Block Address
Buffered Write
Aborted
No
YesYes
Write Word Count,
Block Address
1. Word count values on DQ0-DQ7 are loaded into the Count
register. Count ranges for this device are N = 0000h to 0001Fh.
2. The device outputs the status register when read.
3. Write Buffer contents will be written at the device start address or
destination flash address.
4. Align the start address on a Write Buffer boundary for maximum
write performance (i.e., A5–A1 of t he start address = 0).
5. The device aborts the Buffered Program command if the curr ent
address is outside the ori ginal block address.
6. The Status register indicates an "improper command sequence"
if the Buffered Progr am command is aborted. Follow this wit h a
Clear Status Register command.
Full status check can be done aft er all erase and write sequences
complete. Write FFh after the last operation to reset the device to
read array mode.
Bus
Operation
Standby
Read
Command
Write Write to
Buffer
Read
Standby
Comments
Check SR.7
1 = WSM Ready
0 = WSM Busy
Status register Data
CE# and OE# low updates SR
Addr = Block Address
Data = E8H or EAH (Bit Alterable)
Addr = Block Address
SR.7 = Valid
Addr = Block Address
Check SR.7
1 = Device WSM is Busy
0 = Device WSM is Ready
Write Write Confirm Data = D0H
Addr = Block Address
Write
(Notes 1, 2)
Data = N-1 = Word Count
N = 0 corresponds to count = 1
Addr = Block Address
Write
(Notes 3, 4) Data = Write Buffer Data
Addr = Start Address
Write
(Notes 5, 6) Data = Write Buffer Data
Addr = Block Address
Suspend
Write Loop
Read Status Register
SR.7 =?
Full Status
Check if Desired
Write Complete
Suspend
Write
1
0
No
Yes
BUFFER PROGRAM or BIT ALTERABLE BUFFER WRITE PROCEDURE
PGM_BUFFER.WMF
Numonyx® Omneo™ P8P Datasheet
Datasheet July 2010
76 316144-07
Figure 33: Block Erase Flowchart
Start
FULL ERASE STATUS CHE CK PROCEDUR E
Repeat for subsequent block erasures.
Full Status register check can be done after each block erase
or after a sequence of block erasures.
Write FFh after the last operation to enter read array mode.
Only the Clear Staus Register command clears S R.1, 3, 4, 5.
If an error is detected, clear the Status regis ter before
attempting an erase retry or other error recovery.
No
Suspend
Erase
1
0
0
0
1
1
1
1
0Yes
Suspend
Erase
Loop
0
Write 20h
Block Address
Write D0h and
Block Address
Read Status
Register
SR.7 =
Full Erase
Status Check
(if desired)
Block Erase
Complete
Read Status
Register
Block Erase
Successful
SR.1 = Erase of
Locked Block
Aborted
BLOCK ERASE PROCEDURE
Bus
Operation Command Comments
Write Block
Erase
Setup
Data = 20h
Addr = Block to be erased (BA)
Write Erase
Confirm Data = D0h
Addr = Block to be erased (BA)
Read Status register data. Toggle CE# or
OE# to update Status register data
Standby Check SR.7
1 = WSM ready
0 = WSM busy
Bus
Operation Command Comments
SR.3 = VPP Range
Error
SR.4,5 = Command
Sequence Error
SR.5 = Block Erase
Error
Standby Check SR.3
1 = VPP error
Standby Check SR.4,5
Both 1 = Command sequence error
Standby Check SR.5
1 = Block erase error
Standby Check SR.1
1 = Attempted erase of locked block
Erase aborted
ERAS_BLK.WMF
Block Erase
Erase Confirm
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Figure 34: Erase Suspend/R esume Flowchart
Erase
Completed
Read Array
Data
0
0
No
Read
1
Program
Program
Loop
Read Array
Data
1
Yes
Start
Read Status
Register
SR.7 =
SR.6 =
Erase
Resumed
Read or
Program?
Done?
Write
Write
Standby
Standby
Write
Erase
Suspend
Read Array
or Progra m
Program
Resume
Data = B0h
Addr = Same partition address as
above
Data = FFh or 40h
Addr = Block to program or read
Check SR.7
1 = WSM ready
0 = WSM busy
Check SR.6
1 = Erase suspended
0 = Erase completed
Data = D0h
Addr = Any address
Bus
Operation Command Comments
Read Status register data. Toggle CE# or
OE# to update Status register
Addr =X
Read or
Write Read array or program data from/to
block other than the one being erased
ERASE SUSPEND / RESUME PROCEDURE
ERAS_SUS.WMF
Write B0h
Any Address
Erase Suspend
Write 70h
Any Address
Read Status
Write D0h
Any Address
Erase Resume
Write 70h
Any Address
Read Status
Write FFh
Any Addres
Read Array
Write Read
Status Data =70h
Addr = An y device address
Numonyx® Omneo™ P8P Datasheet
Datasheet July 2010
78 316144-07
Figure 35: Locking Operations Flowchart
No
Optional
Start
Write 60h
Block Address
Write 90h
Read Block Lock
Status
Locking
Change?
Lock Change
Complete
Write 01,D0,2Fh
Block Address
Write FFh
Any Address
Yes
Write
Write
Write
(Optional)
Read
(Optional)
Standby
(Optional)
Write
Lock
Setup
Lock,
Unlock, or
Lockdown
Confirm
Read ID
Plane
Block Lock
Status
Read
Array
Data = 60h
Addr = Block to lock/unlock/lock-down (BA)
Data = 01h (Lock block)
D0h (Unlock block)
2Fh (Lockdown block)
Addr = Block to lock/unlock/lock-down (BA)
Data = 90h
Addr = Block address offset +2 (BA+2)
Block Lock status data
Addr = Block address offset +2 (BA+2)
Confirm locking change on DQ1, DQ0.
(See Block Locking State Transitions Table
for valid combinations.)
Data =FFh
Addr = Block address (BA)
Bus
Operation Command Comments
LOCKING OPERATIONS PROCEDURE
LOCK_OP.WMF
Lock Confirm
Lock Setup
Read ID Plane
Read Array
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Numonyx® Omneo™ P8P Datasheet
Figure 36: Protection Register Progra mming Flowchart
FULL STATUS CHECK PROCEDURE
Program Protection Register operation addresses must be
within the Protection Register address space. Addresses
outside this space will return an error.
Repeat for subsequent programming operations.
Full Status Register check can be done after each program, or
after a sequence of program operations.
Write 0xFF after the last operation to set Read Array state.
Only the Clear Staus Register command clears SR[1, 3, 4].
If an error is detected, clear the Status register before
attempting a program retry or other error recovery.
1
0
1
1
1
PROTECTION REGISTER PROGRAMMIN G PROCEDURE
Start
Write 0xC0,
PR Address
Write PR
Address & Data
Read Status
Register
SR[7] =
Full Status
Check
(if desired)
Program
Complete
Read Status
Register Data
Program
Successful
SR[3] =
SR[4] =
SR[1] =
VPP Range Error
Program Error
Register Locked;
Program Aborted
Idle
Idle
Bus
Operation
None
None
Command
Check SR[3]:
1 =VPP Range Error
Check SR[4]:
1 =Programming Error
Comments
Write
Write
Idle
Program
PR Setup
Protection
Program
None
Data = 0xC0
Addr = First Location to Program
Data = Data to Program
Addr = Location to Program
Check SR[7]:
1 = WSM Ready
0 = WSM Busy
Bus
Operation Command Comments
Read None Status Register Data.
Idle None Check SR[1]:
1 =Block locked; operation aborted
(Program Setup)
(Confirm Data)
0
0
0
Numonyx® Omneo™ P8P Datasheet
Datasheet July 2010
80 316144-07
A.2 Write State Machine
Figure 37, “Write State Machine — Next State Table (sheet 1)” on page 80 to Figure 40,
“Write State Machine — Output Next State Table (Sheet 4)” on page 83 shows the
command state transitions based on incoming commands.
Figure 37: Write State Machine — Next State Table (sheet 1)
Erase
Suspend
(Unlock Blk)
Setup SM Entry Busy
Busy SM Ready
Setup SM Exit Busy
Busy Ready
SM Entry SM Entry Busy SM Entry Busy
Ready (Error [Botch] ) Ready (Error [Botch] )
SM Exit SM Exit Busy SM Exit Busy
Ready (Error [Botch] )
Erase Suspend (Lock E rror [Botch])Erase Suspend (Lock E rror [Botch])Lock/CR Setup in Erase Suspend
Ready (Error [Botch] )
Read
Array (2)
Word
Program
(3,4)
Bit Alterable
Word Write
Write to
Buffered
Program
(BP)
Bit Alterable
Write to
Buffer
Streaming
Mode Entry
(SM Entry)
Streaming
Mode Exit
(SM Exit)
Erase Setup
(3,4)
BE Confirm,
P/E Resume,
ULB,
Confirm (7)
BP / Prg / Erase
Suspend Read
Status
Clear
Status
Register (5)
Read
ID/Query
Lock,
Unlock,
Lock-down,
CR setup (4)
(FFH) (10H/40H) (42H) (E8H) (EAH) (4A H) (4FH) (20H) (D0H) (B 0H) (70H) (50H) (90H, 98H) (60H)
Ready SM Entry
Setup SM Exit
Setup Erase Setup Lock/CR
Setup
SM Ready SM Ready SM Exit
Setup Erase Setup Lock/CR
Setup
Ready
(Unlock Block)
Setup
Bus
y
Setup
Busy Word Pgm
Suspend
Suspend Word Pgm
Busy
Setup
BP Load 1 (8)
BP Load 2 (8)
BP Confirm BP Busy
BP Bus
y
BP Sus
p
end
BP Suspend BP Busy
Setup Erase Bus
y
Busy Erase Suspend
Suspend Erase
Suspend Erase
Suspend Erase Busy
Lock/CR
Setup in
Erase
Suspend
Setup
Busy Word Program
Suspend in
Erase Suspend
Suspend Word Pgm
Busy in Erase
Suspend
Setup
BP Load 1 (8)
BP Load 2 (8)
BP Confirm BP Busy in
Erase
Suspend
BP Busy BP Suspend in
Erase Suspend
BP Suspend BP Busy in
Erase
Suspend
Ready Program Setup BP Setup Ready
Word Program Busy
BP Confirm if Dat a load complete; ELSE B P Load 2
BP Confirm if Dat a load complete; ELSE B P Load 2
Word Program SuspendWord Program Suspend
Ready (Error [Botch BP ] in Erase Suspend)Erase Suspend (Error [Botch BP])
Erase Suspend
BP Confirm in E ras e Suspend if Data load complet e; E LS E BP Load 2
Command Input to Chip and resulting Chip Next State
Erase Busy
BP Suspend
BP Busy BP Busy
Word Program Busy
OTP Busy
Ready (Lock Error [Bot ch])
BP SetupProgram Setup
Word Program Busy in Erase Suspend
Erase Busy
BP Busy in Erase Sus pend BP Busy in Erase Sus pend
Word Pro gram Busy in Erase Sus pend
Word Program Busy
Word Program Setup in
Erase Suspend BP Setup in Erase
Suspend
BP Suspend in Erase S us pend BP Sus pend in E rase Suspend
Word Program Suspend in Erase Suspend
BP Suspend
BP in Erase
Suspend
BP
Ready (Error [Botch] ) Ready (Error [B otch])
Ready (Error [Botch] ) Ready (Error [B otch])
Lock/CR Setup
OTP
SM Ready SM Ready
Ready (Lock Error [Bot c h ] )
Erase
Word Program
in Erase
Suspend
BP Confirm in E ras e Suspend if Data load complet e; E LS E BP Load 2
BP Load 1 in Erase Suspend
BP Load 1
Word Program Suspend in Erase Suspend
Word Program Busy in Erase Suspend B usy
Current Chip State (6)
Word Program
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Numonyx® Omneo™ P8P Datasheet
Figure 38: Write State Machine — Next State Table (Sheet 2)
OTP Setup
(4)
Lock
Block
Confirm (7)
Lock-Down
Block
Confirm (7)
Write
RCR/ECR
Confirm (7)
Block
Address
(¹WA0) (9)
Illegal Cmds+U48
(1)
(C0H) (01H) ( 2FH) (03H,04H) (XXXXH) (all othe r codes )
OTP Setup
Ready (Lock
Error [Botch]) Ready
(Lock Block)
Ready
(Lock Down
Blk)
Ready
(Set CR)
Read
y
N/A
Ready
Ready BP Confirm if Data
load complete;
ELSE BP Load 2
Ready
(Error
[Botch])
(Proceed if
unlocked or
Lock error)
Ready (Error
[Botch])
Read
y
Ready
Erase Suspend
Ready
BP Confirm in
Erase Suspend if
Data load
complete; ELSE
BP Load 2
Ready
BP Confirm in
Erase Suspend if
Data load
complete; ELSE
BP Load 2
Ready
(Error
[Botch])
(Proceed if
unlocked or
Lock error)
Ready (Error
[Botch BP] in
Erase Suspend)
Erase Suspend
N/A
Ready
SM Ready
Word Program Busy
N/A
BP Suspend in Erase Suspend
BP Busy in Erase Suspend
Word Program Suspend in Eras e S uspend
BP Load 1 in Erase S uspend
BP Confirm in E rase Suspend if Data load c omplete;
ELSE BP Load 2
N/A
BP Confirm in E rase Suspend if Data load c omplete;
ELSE BP Load 2
Ready (Error [Botch BP] in Erase Suspend)
Ready (Error [Botc h])
BP Confirm if Data load complete; ELSE BP Load 2 N/A
N/A
BP Busy
Ready (Error [Botch] )
BP Confirm if Data load complete; ELSE BP Load 2
BP suspend
BP Load 1
Word Program Busy in Erase Suspend
Word Program Busy in Erase Suspend Busy
Erase Suspend
Erase Busy
N/A
OTP Busy
Ready (Lock Error [Bot ch])
WSM
Operation
Completes
Command Input to Chip and resulting Chip Next State
Word Program Busy
Word Program Suspend
Erase
Suspend
(Error
[Botch])
Erase
Suspend
(Lock Blk)
Erase
Suspend
(Lock Down
Blk)
Erase
Suspend
(Set CR)
Ready
N/A
Ready
N/A
Ready (Error [Botch])
SM Entry Busy
Ready (Error [Botch])
SM Exit Busy
Erase Suspend (Lock Error
[Botch])
Numonyx® Omneo™ P8P Datasheet
Datasheet July 2010
82 316144-07
Figure 39: Write State Machine — Output Next State Table (Sheet 3)
Read
Array (2)
Word
Program
Setup (3,4)
Bit Alterable
Word Write
Write to
Buffered
Program
(BP)
Bit Alterable
Write to
Buffer
Streaming
Mode Entry
(SM Entry)
Streaming
Mode Exit
(SM Exit)
Erase Setup
(3,4)
BE Confirm,
P/E Resume,
ULB Confirm
(7)
Program/
Erase
Suspend
Read
Status
Clear
Status
Register (5)
Read
ID/Query
Lock,
Unlock,
Lock-down,
CR setup (4)
(FFH) (10H/40H) (42H) (E8H) (EAH) (4A H) (4FH) (20H) (D0H) (B 0H) (70H) (50H) (90H, 98H) (60H)
Status Read
BP Busy,
Word Program Busy,
Erase Busy,
BP Busy
BP Busy in Erase Suspend
Word Pgm Suspend,
Word Pgm Busy in Erase Suspend,
Pgm Suspend In Erase Suspend
BP Suspend in Erase Suspend
SM Entry Busy
SM Exit Busy
Ready, SM Ready
Erase Suspend,
BP Suspend
Lock/CR Setup,
Lock/CR Setup in Erase Susp
Erase Setup,
OTP Setup,
BP: Setup, Load 1, Load 2, Confirm,
Word Pgm Setup,
SM Entry Setup, SM Exit Setup
Read Array Status ReadReady Array ID Read
Status
Read
Status Read
OTP Busy
Current chip state
Command Input to Chip and resulti ng Output Mux Next State
Status Read Output m ux does not change.
July 2010
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Numonyx® Omneo™ P8P Datasheet
Figure 40: Write State Machine — Output Next State Table (Sheet 4)
Notes:
1. "Illegal commands" include commands outside of the allowed command set (allowed commands: 40H [pgm], 20H [eras e],
etc.)
2. If a "Read Array" i s attempted while the device is busy writing or er asing, the result will be inval id data. The ID and Query
data are located at different locations in the address map.
3. 1st and 2nd cycles of "2 cycles write commands" must be given to the same device address, or unexpected results will
occur.
4. The 2nd cycle of the following 2 cycle commands will be ignored by the user interface: W ord Program Setup, Er ase Setup,
OTP Setup , and Lock/Unlock/Lock-down/CR setup when issued in an "illegal condition". Illegal conditions are such as "pgm
setup while busy", "erase setup while busy", “Word program s uspend ”, etc. Thus for example t he se cond cy cle of an e r ase
command issued in program suspend will NOT resume the program operation.
5. The Clear St atus command only clears the er ror bits in the Status Register if the device is not in the following modes: 1.
WSM running (Pgm Busy, Erase Busy, Pgm Busy In Erase Suspend, OTP Busy, modes); 2. Suspend states (Pgm Suspend,
Pgm Suspend In Erase Suspend)
6. The "current state" is that of the "devic e"
7. Confirm commands (Lock Block, Unlock Block, Lock-Down Block) perform the operation and then move to the Ready
State.
8. Buffered programming will botch when a different block address (as compared to address given with E8 command) is
written during the BP Load1 and BP Load2 states
9. WA0 refers to the block address latched during the first write cycle of the current operation
OTP Setup
(4)
Lock
Block
Confirm (7)
Lock-Down
Block
Confirm (7)
Write
RCR/ECR
Confirm (7)
Block
Address
(WA0) Illegal Cmds (1)
(C0H) (01H) (2FH) (03H,04H) (FFFFH) (all other codes)
Command Input to Chip and resulting Output Mux Next State
Status Read
Current chip state
BP Busy,
Word Program Busy,
Erase Busy,
BP Busy
BP Busy in Erase Suspen d
Word Pgm Suspend,
Word Pgm Busy in Erase Suspend,
Pgm Suspend In Eras e Suspend
BP Suspend in Erase Suspend
SM Entry Busy
SM Exit Busy
Ready, SM Ready
Erase Suspend,
BP Suspend
Erase Setup ,
OTP Set up,
BP: Setup, Load 1, Load 2, Confirm,
Word Pgm Setup,
SM Entry Setup, SM Exit Setup
Lock/CR Setup,
Lock/CR Setup in Erase Susp
OTP Busy
Status Read
Read ArrayStatus Read Output mux does not change. Ready A rr ay
Status Read Ready
Array
WSM
Operation
Completes
Numonyx® Omneo™ P8P Datasheet
Datasheet July 2010
84 316144-07
A.3 Common Flash Interface
The Numonyx® Omneo™ P8 P PC M de vice borrows from the existing standards
established for flash memory, and supports the use of the Common Flash Interface
(CFI). This appendix defines the data structure or “database” returned by the CFI
Query command. System software should parse this structure to gain critical
information such as block size, density, x16, and electrical specifications. Once this
information has been obtained, the software will know which command sets to use to
enable PCM writes, block erases, and otherwise control the PCM component. The Query
is part of an overall specification for multiple command set and control interface
descriptions called Common Flash Interface, or CFI.
A.3.1 Query Structure Output
The Query database allows system software to obtain information for controlling the
PCM device. This section describes the device’s CFI-compliant interface that allows
access to Query data.
Query data are presented on the lowest-order data outputs (DQ7-0) only. The numerical
offset value is th e address relative to the maximum bus width supported by the device.
On this family of devices, the Query table device starting address is a 10h, which is a
word address for x16 devices.
For a word-wide (x16) device, the first two Query-structure bytes, ASCII “Q” and “R,”
appear on the low byte at word addresses 10h and 11h. This CFI-compliant device
outputs 00h data on upper bytes. The device outputs ASCII “Q” in the low byte (DQ7-0)
and 00h in the high byte (DQ15-8).
At Query addresses containing two or more bytes of information, the least significant
data byte is presented at the lower address, and the most significant data byte is
presented at the higher address.
In all of the following tables, addresses and data are represented in hexadecimal
notation, so the “h” suffix has been dropped. In addition, since the upper byte of word-
wide devices is always “00h,” the leading “00” has been dropped from the table
notation and only the lower byte value is shown. Any x16 device outputs can be
assumed to have 00h on the upper byte in this mode.
Table 35: Summary of Query Structure Output as a Function of Device and Model
Device Hex Offset Hex Code ASCII Value
Device Addresses 00010:
00011:
00012:
51
52
59
“Q”
“R”
“Y”
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Numonyx® Omneo™ P8P Datasheet
Table 36: Example of Query Structure Output of x16- Devices
A.3.2 Query Structure Overview
The Query command causes the PCM component to display the Common Flash
Interface (CFI) Query structure or “database.” The structure sub-sections and address
locations are summarized below.
Notes:
1. Refer to the Query Structure Output section and offset 28h for the detailed definition of offset address as a function of
device bus width and mode.
2. BA = Block Address beginning location (i.e., 08000h is block 1’s beginning location when the block size is 32K-word).
3. Offset 15 defines “P” which points to the Primary Numonyx-specific Extended Query Table.
A.3.3 CFI Query Identification String
The Identification String provides verification that the component supports the
Common Flash Interface specification. It also indicates the specification version and
supported vendor-specified command set(s).
W ord Addressing: Byte Addressing:
Offset Hex Code
V
alue Offset Hex Code
V
alue
A
X
–A
0 D15
–
D0
A
X
–A
0 D7
–
D0
00010h 0051 "Q" 00010h 51 "Q"
00011h 0052 "R" 00011h 52 "R"
00012h 0059 "Y" 00012h 59 "Y"
00013h P_IDLO PrVendor 00013h P_IDLO PrVendor
00014h P_IDHI ID # 00014h P_IDLO ID #
00015h PLO PrVendor 00015h P_IDHI ID #
00016h PHI TblAdr 00016h ... ...
00017h A_IDLO AltVendor 00017h
00018h A_IDHI ID # 00018h
... ... ... ...
Offset Sub-Section Name Description(1)
00000h Manufacturer Code
00001h Device Code
(BA+2)h(2) Bl ock S tatus register Block-specific in formation
00004-Fh Reserved Reserved for vendor-specific information
00010h CFI query ide nti fi cation string Command set ID and vendor data offset
0001Bh System interface information D evice timing & voltage information
00027h Device geometry defini tion F lash device layout
P(3) Vendor-defined ad ditio nal informatio n specific
to the Primary Vendor Algorithm
Primary Intel-specific Extended
Query Table
Numonyx® Omneo™ P8P Datasheet
Datasheet July 2010
86 316144-07
Table 37: Block Status Register
Table 38: CFI Identification
Table 39: System Interf ace Informati on
Offset Length Description Add.
V
alue
(BA+2)h
(1)
1 Block Loc k Status Register BA+2 --00 or --01
BA+2 ( bi t 0): 0 o r 1
BA+2 ( bi t 1): 0 o r 1
BA+2 ( bi t 4): 0 o r 1
BA+2 ( bi t 5): 0 o r 1
BSR 2–3, 6-7: Reserved for future use BA+2 (bit 2–3, 6-7): 0
BSR.0 Block lock status
0 = Unlocked
1 = Locked
BSR.1 Block lock-down status
0 = Not locked down
1 = Locked down
BSR.4 EFA Block lock stat us
0 = Unlocked
1 = Locked
BSR.5 EFA Block lock-down status
0 = Not locked down
1 = Locked down
Offset Length Description Add. Hex
Code Value
10h 3 Qu e r y-u n i q ue ASCII string “QRY“ 1 0: --51 "Q"
11: --52 "R"
12: --59 "Y"
13h 2 Primary vendor command set and control interface ID code. 13: --01
16-bit ID code f o r vend or- speci fied al g orithms 1 4: --00
15h 2 Extended Query Table primary algorithm address 15: --0A
16: --01
17h 2 Alternate vendor command set and control interface ID code. 17: --00
0000h means no second vendor-specified algorithm exists 18: --00
19h 2 Secondary algorithm Extended Query Table address. 19: --00
0000h means none exists 1A: --00
Offset Length Description Add. Hex
Code Value
1Bh 1 1B: --27 2.7V
1Ch 1 1C: --36 3.6V
1Dh 1 1D: --09 0.9V
1Eh 1 1E: --36 3.6V
1Fh 1 “n” such that t
yp
ical sin
g
le word
p
ro
g
ram ti me-out = 2n
µ
-sec 1F: --08 256µs
20h 1 “n” suc h that t
yp
ical full buff er write time-out = 2n
µ
-sec 20: --09 512µs
21h 1 “n” suc h that t
yp
ical block erase t ime-out = 2nm-sec 21: --0A 1s
22h 1 “n” suc h that t
yp
ical full chi
p
erase time-out = 2nm-sec 22: --00 NA
23h 1 “n” suc h that maxim um word
p
ro
g
ram time-out = 2ntimes t
yp
ical 23: --01 512µs
24h 1 “n” such that maximum buffer write time-out = 2ntimes t
yp
ical 24: --01 1024µs
25h 1 “n” such t hat maximum bloc k erase time-out = 2ntimes t
yp
ical 25: --02 4s
26h 1 “n” suc h that maxim um chi
p
erase time-out = 2ntimes t
yp
ical 26: --00 NA
VPP [programming] supply minimum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 HEX volts
VCC logic supply minimum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 BCD volts
VCC logic supply maximum program/erase voltage
bits 0–3 BCD 100 mV
bits 4–7 BCD volts
VPP [programm i ng] s upply maximum program / erase voltage
bits 0–3 BCD 100 mV
bits 4–7 HEX volts
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Numonyx® Omneo™ P8P Datasheet
Table 40: Device Geometry De finition
Offset Length Description Add. Hex
Code Value
27h 1“n” such that device size = 2nin number of bytes 27:
7654321 0
28h 2 ————x64x32x16 x8 28:--01x16
15 14 13 12 11 10 9 8
——————— — 29:--00
2Ah 2“n” such that maximum num ber of bytes in write buffer = 2n2A: --06 64
2B: --00
2Ch 1
2C:
2Dh 4 Erase Block Region 1 Information 2D:
bits 0–15 = y, y+1 = number of identical-size erase blocks 2E:
bits 16–31 = z, region erase block(s) size are z x 256 bytes 2F:
30:
31h 4 Erase Block Region 2 Information 31:
bits 0–15 = y, y+1 = number of identical-size erase blocks 32:
bits 16–31 = z, region erase block(s) size are z x 256 bytes 33:
34:
35h 4 Reserved for future erase block region inform at ion 35:
36:
37:
38:
See table below
See table below
See table below
See table below
Number of erase block regions (x) within device:
1. x = 0 means no erase blocking; the device erases in bulk
2. x specifies the number of device regions with one or
more contiguous same-size erase blocks.
3. Symmet rically blocked partitions have one blocking region
See table below
Flash device interface code assignment:
"n" such that n+1 specifies the bit f ield that represents the fl ash device width
capabilities as described in the table:
Address 128 Mbit
–B –T
27: --18 --18
28: 01: 01:
29: 00: 00:
2A: 06: 06:
2B: 00: 00:
2C: --02 --02
2D: --03 --7E
2E: --00 --00
2F: --80 --00
30: --00 --02
31: --7E --03
32: --00 --00
33: --00 --80
34: --02 --00
35: --00 --00
36: --00 --00
37: --00 --00
38: --00 --00
Device Geom etry Definiti on
Numonyx® Omneo™ P8P Datasheet
Datasheet July 2010
88 316144-07
A.3.4 Numonyx-Specific Extended Query Table
Table 41: Primary Ve ndor-S pe cifi c Extended Query
Offset(1) Length Description Hex
P = 10Ah (Optional flash features and commands) Add. Code
V
alue
(P+0)h 3 Primary extended query table 10A --50 "P"
(P+1)h Unique ASCII st ring “PRI “ 10B: --52 "R"
(P+2)h 10C: --49 "I"
(P+3)h 1 Major version number, ASCII 10D: --31 "1"
(P+4)h 1 Minor version number, ASCII 10E: --34 "4"
(P+5)h 4 Optional feature and command support (1=yes, 0=no) 10F: --E6
(P+6)h bits 10–31 are reserved; undefined bits are “0.” If bit 31 is 110: --00
(P+7)h “1” then another 31 bit field of Optional features follows at 111: --00
(P+8)h the end of the bit–30 field. 112: --00
bit 0 Chip erase supported bit 0 = 0 No
bit 1 Suspend erase supported bit 1 = 1 Yes
bit 2 Suspend program supported bit 2 = 1 Yes
bit 3 Legacy lock/unlock supported bit 3 = 0 No
bit 4 Queued erase supported bit 4 = 0 No
bit 5 Instant individual block locking supported bit 5 = 1 Yes
bit 6 Protection bits s upported bit 6 = 1 Yes
bit 7 Pagemode read supported bit 7 = 1 Yes
bit 8 Synchronous read supported bit 8 = 0 No
bit 9 Simultaneous operations supported bit 9 = 0 No
bit 10 Extended Flash Array Blocks supported bit 10 = 0 No
bit 30 CFI Link(s) to follow bit 30 = 0 No
bit 31 Another "Optional Features" field to follow bit 31 = 0 No
(P+9)h 1 113: --01
bit 0 Program supported after erase suspend bit 0 = 1 Yes
(P+A)h 2 Block status register mask 114: --03
(P+B)h bits 2–15 are Reserved; undefined bits are “0
”
115: --00
bit 0 Block Lock-Bit Status register active bit 0 = 1 Yes
bit 1 B lock Lo ck-D o wn B it St a tus active bit 1 = 1 Yes
bit 4 EFA Block Lock-Bit St atus regis t er active bit 4 = 0 No
bit 5 EFA Block Lock-Down Bit Status active bit 5 = 0 No
(P+C)h 1 116: --33 3.3V
(P+D)h 1 117: --33 3.3V
Supported functions after suspend: read Array, Status , Query
Other supported operations are:
bits 1–7 reserved; undefined bits are “0”
VPP optimum program /erase supply volt age
bits 0–3 BCD value in 100 mV
bits 4–7 HEX value in volts
VCC logic supply highest performance program/erase voltage
bits 0–3 BCD value in 100 mV
bits 4–7 BCD value in volts
July 2010
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Numonyx® Omneo™ P8P Datasheet
Table 42: Protection Register Information
Table 43: Read Information
Offset(1) Length Description Hex
P = 10Ah (Optional flash features and commands) Add. Code
V
alue
(P+E)h 1 118: --02 2
(P+F)h 4 Protection Field 1: Protection Description 119: --80 80h
(P+10)h This field describes user-available One Time Programm able 11A: --00 00h
(P+11)h (OTP) Protection register bytes. Some are pre-programmed 11B: --03 8 byte
(P+12)h 11C: --03 8 b yt e
(P+13)h 10 Protection Field 2: Protection Description 11D: --89 89h
(P+14)h 11E: --00 00h
(P+15)h 11F: --00 00h
(P+16)h 120: --00 00h
(P+17)h 121: --00 0
(P+18)h bits 40–47 = “n” ∪n = factory pgm'd groups (high byte) 122: --00 0
(P+19)h 123: --00 0
(P+1A)h 124: --10 16
(P+1B)h 125: --00 0
(P+1C)h 126: --04 16
with device-unique serial numbers. Others are user programmable. Bits 0–15
point to the Protec tion register Lock byte, the section’s first byte. The following
bytes are factory pre-programm ed and user-programmable.
bits 0–7 = Lock/bytes Jedec -plane physical low address
bits 8–15 = Lock/bytes Jedec-plane physical high address
bits 16–23 = “n” such that 2n = factory pre-programm ed bytes
bits 24–31 = “n” such that 2n = user programmable bytes
Bits 0–31 point to the Protection register physical Lock-word address in the
Jedec-plane.
Following bytes are factory or user-programmable.
bits 32–39 = “n”
¬
n = factory pgm'd groups (low byte)
Number of Protection register fields in JEDEC ID space.
“00h,” indicates that 256 protection fields are available
bits 48–55 = “n” \ 2n = factory programmable bytes/group
bits 56–63 = “n”
¬
n = user pgm'd groups (low byte)
bits 64–71 = “n” ¬ n = us er pgm 'd groups (high byte)
bits 72–79 = “n” ¬ 2n = user programm able bytes /group
Offset(1) Length Description Hex
P = 10Ah (Optional flash features and commands) Add. Code
V
alue
(P+1D)h 1 127: --04 16 byte
(P+1E)h 1 128: --00 0
Page Mode Re ad c a pa b i l i ty
bits 0–7 = “n” such that 2n HEX value represents the number of
read-page bytes. See offset 28h for device word width to
determine page-mode data output width. 00h indicates no
read
p
a
g
e buffer.
Number of synchronous mode read configuration fields that follow. 00h indicates
no burst capability.
Numonyx® Omneo™ P8P Datasheet
Datasheet July 2010
90 316144-07
Table 44: Partition and Erase-block Region Information
Offset
(1) See table b el o w
P = 10Ah Descri
p
tion Address
Bottom To
p
(
O
p
tional flash features and commands
)
Len Bot Top
(P+1F)h (P+1F)h
1 129: 129:
Partition Region 1 Information
(P+20)h (P+20)h Data size of this Parition Region I nformati on f i el d 212A: 12A
(P+21)h (P+21)h (# addressable locat i ons, includi ng t hi s f i el d) 12B 12B
(P+22)h (P+22)h Number of ident i cal partitions within the partiti on regi on 2 12C: 12C:
(P+23)h (P+23)h 12D: 12D:
(P+24)h (P+24)h 1 12E: 12E:
(P+25)h (P+25)h 1 12F: 12F:
(P+26)h (P+26)h 1 130: 130:
(P+27)h (P+27)h 1 131: 131:
(P+28)h (P+28)h Partition Region 1 E rase Block Type 1 Inf ormation 4 132: 132:
(P+29)h (P+29)h bits 0–15 = y, y+1 = # i denti cal-size eras e bl ks in a partition 133: 133:
(P+2A)h (P+ 2A )h bit s 16–31 = z, region erase bl ock(s) si ze are z x 256 bytes 134: 134:
(P+2B)h (P+2B)h 135: 135:
(P+2C)h (P+2C)h Partiti on 1 (E rase Block T ype 1) 2 136: 136:
(P+2D)h (P+2D)h Block erase cycles x 1000 137: 137:
(P+2E)h (P+2E)h 1 138: 138:
(P+2F)h (P+2F)h 1 139: 139:
Simul taneous program or erase operations all owed in other partitions while a
partition in this region is i n E rase mode
bits 0–3 = number of simultaneous P rogram operations
bits 4–7 = number of simultaneous E rase operations
Number of device hardware-partition regions withi n t he devi c e.
x = 0: a single hardware partition device (no f iel ds follow).
x specifies t he number of device parti tion regions cont ai ni ng
one or more contiguous erase bloc k regi ons.
Types of erase block regions i n t hi s Partiti on Regi on.
x = 0 = no erase blocking; t he P artition Region eras es in bulk
x = number of erase bloc k regions w/ conti guous s ame-si ze
erase blocks. Symmetrically blocked partitions have one
blocking regi on. Partiti on size = (Type 1 blocks)x(Type 1
block s i zes) + (Type 2 blocks)x(Type 2 block sizes) + … +
(Type n blocks)x(Type n block sizes)
Partition 1 (erase bloc k Type 1) page mode and synchronous mode capabilit ies
defined in Table 10.
bit 0 = page-mode host reads permitted (1=yes , 0=no)
bit 1 = synchronous host reads permitted (1= yes , 0=no)
bit 2 = synchronous host writes permitted (1=yes , 0=no)
bits 3–7 = res erved for future use
Partition 1 (erase block Type 1) bit s per cell; internal EDAC
bits 0–3 = bit s per cell in eras e regi on
bit 4 = internal E DA C used (1= yes , 0=no)
bits 5–7 = res erve for future use
Number of program or erase operations al l owed in a partit ion
bits 0–3 = number of simultaneous P rogram operations
bits 4–7 = number of simultaneous E rase operations
Simul taneous program or erase operations all owed in other partitions while a
partition in this region is i n P rogram mode
bits 0–3 = number of simultaneous P rogram operations
bits 4–7 = number of simultaneous E rase operations
July 2010
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Numonyx® Omneo™ P8P Datasheet
Table 45: Partition and Erase-block Region Information
Parti t ion Region 1 (Erase Block Type 1) Programming Region In formation 6
(P+30)h (P+30)h bits 0–7 = x, 2^x = Programming Regi on aligned si ze (bytes)13A: 13A:
(P+31)h (P+3 1)h bits 8 –14 = Reserved; bit 15 = Legacy flash operation (i g nor e 0:7) 1 3B: 13B:
(P+32)h (P+32)h bits 16–23 = y = Cont r ol Mod e valid size in bytes 13C: 13C:
(P+33)h (P+3 3)h bits 24-31 = Reserve d 13D: 13D:
(P+34)h (P+34)h bits 32-39 = z = Control Mode invalid size in bytes 13E: 13E:
(P+35)h (P+3 5)h bits 40-46 = Reserve d; bit 47 = Le gacy flas h operation (ignore 23:16 & 39:32) 13F: 13F:
(P+36)h (P+3 6)h Part ition Reg ion 1 Erase B lock T ype 2 Information 4 140: 140:
(P+37)h (P+3 7)h bits 0 –15 = y, y+1 = # iden tical-size erase bl ks in a pa rtition 141: 141:
(P+38)h (P+3 8)h bits 1 6–31 = z, region erase block(s) size are z x 256 byt es 142: 142:
(P+39)h (P+39)h 143: 143:
(P+3A)h (P+3A)h Partition 1 (Erase Block Type 2) 2 144: 144:
(P+3B)h (P+3B)h Block erase c ycles x 1000 145: 145:
(P+3C)h (P+3C)h 1 146: 146:
(P+3D)h (P+3D)h 1 147: 147:
Parti t ion Region 1 (Erase Block Type 2) Programming Region In formation 6
(P+3E)h (P+3E)h bits 0 –7 = x, 2^x = Program ming Regi on aligned si ze (bytes)148: 148:
(P+3F)h (P+3F)h bits 8 –14 = Reserved; bit 15 = Legacy flash oper ation (ignore 0:7) 149: 149:
(P+40)h (P+40)h bits 16–23 = y = Cont r ol Mod e valid size in bytes 14A: 14A:
(P+41)h (P+41)h bits 24-31 = Reserved 14B: 14B:
(P+42)h (P+42)h bits 32-39 = z = Control Mode invalid size in bytes 14C: 14C:
(P+43)h (P+4 3)h bits 40-46 = Reserve d; bit 47 = Le gacy flas h op eration (ignore 23:16 & 39:32) 14D: 14D:
Partition 1 (e rase bloc k Type 2) bits per cell; int e r nal EDAC
bits 0 –3 = b its per cell in erase r egion
bit 4 = internal EDAC us ed (1=yes, 0=no)
bits 5–7 = reserve for future use
Parti t i o n 1 (erase block Type 2) pa ge mode and s ync hronous m ode capabil ities
defined i n Ta ble 10.
bit 0 = page- mode host reads permitted (1=yes , 0=no)
bit 1 = s ync hronous hos t reads per mitt ed ( 1= yes, 0=no)
bit 2 = s ync hronous hos t writes permitt ed ( 1= yes , 0=no)
bits 3–7 = reserved for future use
Numonyx® Omneo™ P8P Datasheet
Datasheet July 2010
92 316144-07
Table 46: Partition and Erase-block Region Information
Parti t i on and Erase-bloc k Regi o n I nf ormation
Addres
s
–B –T
129: --01 --01
12A: --24 --24
12B: --00 --00
12C: --01 --01
12D: --00 --00
12E: --11 --11
12F: --00 --00
130: --00 --00
131: --02 --02
132: --03 --7E
133: --00 --00
134: --80 --00
135: --00 --02
136: --64 --64
137: --00 --00
138: --01 --01
139: --01 --01
13A: --00 --00
13B: --80 --80
13C: --00 --00
13D: --00 --00
13E: --00 --00
13F: --80 --80
140: --7E --03
141: --00 --00
142: --00 --80
143: --02 --00
144: --64 --64
145: --00 --00
146: --01 --01
147: --01 --01
148: --00 --00
149: --80 --80
14A: --00 --00
14B: --00 --00
14C: --00 --00
14D: --80 --80
128 Mbit
