GT93C46A Advanced GT93C46A 1K-bit Microwire Serial EEPROM www.giantec-semi.com a0 1/19 GT93C46A Table of Content 1 FEATURES ...................................................................................................................... 3 2 DESCRIPTION................................................................................................................. 4 3 PIN CONFIGURATION .................................................................................................. 5 4 BLOCK DIAGRAM ......................................................................................................... 6 5 DEVICE OPERATION .................................................................................................... 7 6 TIMING DIAGRAMS ...................................................................................................... 9 7 ABSOLUTE MAXIMUM RATINGS ............................................................................ 12 8 DC ELECTRICAL CHARACTERISTICS .................................................................... 13 9 AC ELECTRICAL CHARACTERISTICS .................................................................... 14 10 ORDERING INFORMATION ..................................................................................... 15 11 PACKAGE INFORMATION....................................................................................... 16 12 REVISION HISTORY.................................................................................................. 19 www.giantec-semi.com a0 2/19 GT93C46A 1 FEATURES * * * * * * * * Industry-standard Microwire Interface Wide-voltage Operation - Vcc = 1.8V to 5.5V Speed - 1 MHz (1.8V), 2 MHz (2.5V), 3 MHz (5.5V) Standby current - 1uA (max.) 1.8V Operating current - 1mA (max.) 1.8V User Configured Memory Organization - 64x16-bit (ORG = Vcc or Floating) or 128x8-bit (ORG = 0V) Self timed write cycle: 5 ms (max.) Hardware and software write protection - - * * CMOS technology Versatile, easy-to-use interface - - - - * * * * Defaults to write-disabled state at power-up Software instructions for write-enable/disable Automatic erase-before-write Programming status indicator Byte, Word and chip single erasable Chip select enables power savings Noise immunity on inputs, besides Schmitt trigger High-reliability - Endurance: 1 million cycles - Data retention: 100 years Packages: SOIC/SOP, TSSOP, and UDFN Lead-free, RoHS, Halogen free, Green Copyright (c) 2010 Giantec Semiconductor Inc. (Giantec) All rights reserved. Giantec reserves the right to make changes to this specification and its products at any time without notice. Giantec products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for critical medical or surgical equipment, aerospace or military, or other applications planned to support or sustain life. It is the customer's obligation to optimize the design in their own products for the best performance and optimization on the functionality and etc. Giantec assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on any published information and prior placing orders for products. www.giantec-semi.com a0 3/19 GT93C46A 2 DESCRIPTION The GT93C46A is 1kb non-volatile serial EEPROM with memory array of 1,024 bits. The array can be organized as either 128 bytes of 8 bits or 64 words of 16 bits via the ORG control. Utilizing the CMOS design and process, these products provide low standby current and low power operations. The devices can operate in a wide supply voltage range from 1.8V to 5.5V, with frequency up to 3MHz. When the ORG pin is connected to Vcc or floating, x16 is selected. Conversely, when it is connected to ground, x8 is chosen. An instruction Op-code defines the various operations of the devices, including read, write, and mode-enable functions. To protect against inadvertent data modification, all write and erase instructions are merely accepted while the device is in write enable mode. A selected x8 byte or x16 word can be modified with a single WRITE or ERASE instruction. Additionally, the WRITE ALL or ERASE ALL instruction can program or erase the entire array, respectively. Once a device begins its self-timed program procedure, the data out pin (Dout) can indicate the READY/BUSY status by raising chip select (CS). The devices can output any number of consecutive bytes/words using a single READ instruction. www.giantec-semi.com a0 4/19 GT93C46A 3 PIN CONFIGURATION 8-Pin SOIC/SOP, TSSOP 8-pad UDFN CS SK DIN DOUT VCC NC ORG GND Table 3.1: Pin Descriptions Pin Name Descriptions Chip Select CS Serial Data Clock SK Serial Data Input DIN Serial Data Output DOUT Ground GND Organization Select ORG Not Connect NC Supply Voltage VCC www.giantec-semi.com a0 5/19 GT93C46A 4 BLOCK DIAGRAM 128x8 64x16 www.giantec-semi.com a0 6/19 GT93C46A 5 DEVICE OPERATION Device Operations The GT93C46A is controlled by a set of instructions which are clocked-in serially on the Din pin. Before each low-to-high transition of the clock (SK), the CS pin must have already been raised to HIGH, and the Din value must be stable at either LOW or HIGH. Each instruction begins with a start bit of the logical "1" or HIGH. Following this are the Op-code, address field, and data, if appropriate. The clock signal may be held stable at any moment to suspend the device at its last state, allowing clock speed flexibility. Upon completion of bus communication, CS would be pulled LOW. The device then would enter Standby mode if no internal programming is underway. Read (READ) The READ instruction is the only instruction that outputs serial data on the DOUT pin. After the read instruction and address have been decoded, data is transferred from the selected memory array into a serial shift register. (Please note that one logical "0" bit precedes the actual 8 or 16-bit output data string.) The output on DOUT changes during the low-to-high transitions of SK (see Figure 3). The GT93C46A is designed to output a continuous stream of memory content in response to a single read operation instruction. To utilize this function, the system asserts a read instruction specifying a start location address. Once the 8 or 16 bits of the addressed register have been clocked out, the data in consecutively higher address locations is output. The address will wrap around continuously with CS HIGH until the chip select (CS) control pin is brought LOW. This allows for single instruction data dumps to be executed with a minimum of firmware overhead. Write Enable (WEN) The write enable (WEN) instruction must be executed before any device programming (WRITE, WRALL, ERASE, and ERAL) can be done. When Vcc is applied, this device powers up in the write disabled state. The device then remains in a write disabled state until a WEN instruction is executed. Thereafter, the device remains enabled until a WDS instruction is executed or until Vcc is removed. (See Figure 4.) (Note: Chip select must remain LOW until Vcc reaches its operational value.) Write Disable (WDS) The write disable (WDS) instruction disables all programming capabilities. This protects the entire device against accidental modification of data until a WEN instruction is executed. (When Vcc is applied, this part powers up in the write disabled state.) To protect data, a WDS instruction should be executed upon completion of each programming operation. Write (WRITE) The WRITE instruction writes 8 or 16 bits of data into the specified memory location. After the last data bit has been applied to DIN, and before the next rising edge of SK, CS must be brought LOW. If the device is write-enabled, then the falling edge of CS initiates the self-timed programming cycle (see WEN). If CS is brought HIGH, after a minimum wait of 200 ns after the falling edge of CS (tCS) DOUT will indicate the READY/BUSY status of the chip. Logical "0" means programming is still in progress; logical "1" means the selected memory array has been written, and the part is ready for another instruction (see Figure 5). The READY/BUSY status will not be available if the CS input goes HIGH after the end of the self-timed programming cycle (tWP). Write All Memory (WRAL) The write all (WRALL) instruction programs entire memory with the data pattern specified in the instruction. As with the WRITE instruction, the falling edge of CS must occur to initiate the self-timed programming cycle. If CS is then brought HIGH after a minimum wait of 200 ns (tCS), the DOUT pin indicates the READY/BUSY status of the chip (see Figure 6). Erase (ERASE) After the erase instruction is entered, CS must be brought LOW. The falling edge of CS initiates the selftimed internal programming cycle. Bringing CS HIGH after a minimum of tCS, will cause DOUT to indicate the READ/BUSY status of the chip: a logical "0" indicates programming is still in progress; a logical "1" indicates the erase cycle is complete and the part is ready for another instruction (see Figure 8). www.giantec-semi.com a0 7/19 GT93C46A Erase All Memory (ERAL) Full chip erase is provided for ease of programming. Erasing the entire chip involves setting all bits in the entire memory array to a logical "1" (see Figure 9). Power-On Reset (POR) The device incorporates a Power-On Reset (POR) circuitry which protects the internal logic against powering up into a wrong state. The device will power up into Standby mode after VCC exceeds the POR trigger level and will power down into Reset mode when VCC drops below the POR trigger level. This POR feature protects the device being `brown-out' due to a sudden power loss or power cycling. In order to refrain the state machine entering into a wrong state during power-up sequence or a power toggle off-on condition, a power on reset (POR) circuit is embedded. During power-up, the device does not respond to any instruction until VCC has reached a minimum stable level above the reset threshold voltage. Once VCC passes the POR threshold, the device is reset and enters in Standby mode. This can also avoid any inadvertent Write operations during power-up stage. During power-down process, the device must enter into standby mode, once VCC drops below the power on reset threshold voltage. In addition, the device will enter standby mode after current operation completes, provided that no internal write operation is in progress. INSTRUCTION SET - GT93C46A (1Kb) Instruction [2] Start Bit OP Code 8-bit Organization (ORG = GND) Address[1] Data[1] Required Clock Cycles 00x xxxx -- 10 WDS (Write 1 00 Disable) WEN (Write Enable) 1 00 11x xxxx -- ERAL (Erase All 1 00 10x xxxx -- Memory) WRAL (Write All 1 00 01x xxxx (D7-D0) Memory) WRITE 1 01 (A6-A0) (D7-D0) READ 1 10 (A6-A0) -- ERASE 1 11 (A6-A0) -- Notes: 1. x = Don't care bit. 2. Exact number of clock cycles is required for each Op-code instruction. www.giantec-semi.com a0 16-bit Organization (ORG = Vcc or Floating) Address[1] Data[1] Required Clock Cycles 00 xxxx -- 9 10 10 11 xxxx 10 xxxx -- -- 9 9 18 01 xxxx (D15-D0) 25 18 (A5-A0) (A5-A0) (A5-A0) (D15-D0) -- -- 25 10 8/19 9 GT93C46A 6 TIMING DIAGRAMS Fig. 2: Synchronous Data Timing Fig. 3: Read Cycle Timing Fig. 4: Write Enable (WEN) Cycle Timing (Hi-Z) www.giantec-semi.com a0 9/19 GT93C46A Fig. 5: Write (Write) Cycle Timing Notes: 1. After the completion of the instruction (DOUT is in READY status) then it may perform another instruction. If device is in BUSY status (DOUT indicates BUSY status) then attempting to perform another instruction could cause device malfunction. 2. To determine address bits An-A0 and data bits Dm-D0, see Instruction Set for the specific device. Fig. 6: Write All (WRALL) Cycle Timing Notes: 1. After the completion of the instruction (DOUT is in READY status) then it may perform another instruction. If device is in BUSY status (DOUT indicates BUSY status) then attempting to perform another instruction could cause device malfunction. 2. To determine data bits Dm-D0, see Instruction Set for the appropriate device. www.giantec-semi.com a0 10/19 GT93C46A Fig. 7: Write Disable (WDS) Timing (Hi-Z) Fig. 8: Erase (Erase) Cycle Timing Fig. 9: Erase All (ERAL) Cycle Timing Note for Figures 8 and 9: 1. After the completion of the instruction (DOUT is in READY status) then it may perform another instruction. If device is in BUSY status (DOUT indicates BUSY status) then attempting to perform another instruction could cause device malfunction. 2. To determine data bits An - A0, see Instruction Set for the appropriate device. www.giantec-semi.com a0 11/19 GT93C46A 7 ABSOLUTE MAXIMUM RATINGS Table 7.1. Absolute Maximum Ratings [1] Symbol VCC VP TBIAS TSTG IOUT [1] Parameter Supply Voltage Voltage on Any Pin Temperature Under Bias Storage Temperature Output Current Value -0.5 to +6.5 -0.5 to Vcc + 0.5 -55 to +125 -65 to +150 5 Unit V V C C mA Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING RANGE Table 7.2. Industrial Operation VCC 1.8V to 5.5V Ambient Temperature (TA) -40C to +85C Grade Industrial (I) Note: Giantec offers Industrial grade for Commercial applications (0C to +70C). CAPACITANCE[1,2] Symbol CIN COUT Parameter Input Capacitance Input /Output Capacitance Conditions VIN = 0V VOUT = 0V Max. Unit 6 pF 8 pF Notes: 1. Tested initially and after any design or process changes that may affect these parameters and not 100% tested. 2. Test conditions: TA = 25C, f = 1 MHz, Vcc = 5.0V. www.giantec-semi.com a0 12/19 GT93C46A 8 DC ELECTRICAL CHARACTERISTICS Table 8.1. DC Characteristics TA = -40C to +85C for Industrial Symbol VOL1 VOL2 VOH1 Parameter Output LOW Voltage Output LOW Voltage Output HIGH Voltage Test Conditions VCC = 1.8V~5.5V, IOL = 100 uA VCC = 2.5V~5.5V, IOL = 2.1 mA VCC = 1.8V~5.5V, IOH = -0.1mA VOH2 VIH1 VIH2 VIL1 VIL2 ILI ILO Output HIGH Voltage Input HIGH Voltage Input HIGH Voltage Input LOW Voltage Input LOW Voltage Input Leakage Current Output Leakage Current VCC = 2.5V~5.5V, IOH = -0.4mA 1.8V to 5.5V 2.5V to 5.5V 1.8V to 5.5V 2.5V to 5.5V VIN = 0V to VCC (CS, SK,DIN,ORG) VOUT = 0V to VCC, CS = 0V Min. -- -- VCC - 0.2 Max. 0.2 0.4 -- Unit V V V 2.4 0.7*VCC 2 -0.3 -0.3 0 0 -- VCC +1 VCC +1 0.3*VCC 0.8 2.5 2.5 V V V V V A A POWER SUPPLY CHARACTERISTICS Table 8.2. Power Supply Characteristics (TA = -40C to +85C for Industrial) Symbol Vcc ISB1 Parameter Supply Voltage Standby current Vcc Test Conditions 1.8 CS = GND, SK = GND, ORG = Vcc or Floating (x16), DIN = Vcc or GND 2.5 5.5 ISB2 Standby current 1.8 2.5 CS = GND, SK = GND, ORG = GND (x8), DIN = Vcc or GND 5.5 ICC-Read ICC-Write Read current Write current www.giantec-semi.com Min. 1.8 -- Typ. 0.1 Max. 5.5 1 Unit V A -- 0.3 1 A -- 0.5 1 A -- 0.4 1 A -- 6 10 A -- 10 15 A 1.8 CS = VIH, SK = 1 MHz -- 0.5 mA 2.5 CS = VIH, SK = 2 MHz -- 0.5 mA 5.5 1.8 2.5 5.5 CS = VIH, SK = 3 MHz -- -- -- -- 1 1 1 2 mA mA mA mA CS = VIH, SK = 1 MHz CS = VIH, SK = 2 MHz CS = VIH, SK = 3 MHz a0 13/19 GT93C46A 9 AC ELECTRICAL CHARACTERISTICS AC Characteristics - Industrial Table 9.1: AC Characteristics - Industrial (TA = -40C to +85C, Supply voltage = 1.8V to 5.5V) Symbol Parameter [1] 1.8V Vcc < 2.5V Min. Max. 0 1 -- 10 -- 10 250 -- 250 -- 250 -- 200 -- 0 -- 100 -- 50 -- 2.5V Vcc < 4.5V Min. Max. 0 2 -- 10 -- 10 200 -- 200 -- 200 -- 100 -- 0 -- 50 -- 50 -- 4.5V Vcc < 5.5V Min. Max. 0 3 -- 10 -- 10 200 -- 100 -- 200 -- 50 -- 0 -- 50 -- 50 -- Unit fSCK tR tF tSKH tSKL tCS tCSS tCSH tDIS tDIH SCK Clock Frequency Input Rise Time Input Fall Time SK High Time SK Low Time Minimum CS LOW Time CS Setup Time CS Hold Time DIN Setup Time DIN Hold Time tPD1 Output Delay to "1" -- 400 -- 200 -- 100 ns tPD0 tSV tDF tWP Output Delay to "0" CS to Status Valid CS to Dout in 3-state Write Cycle Time -- -- -- -- 400 400 200 10 -- -- -- -- 200 200 100 5 -- -- -- -- 100 200 100 5 ns ns ns ms Notes: 1. The parameters are characterized but not 100% tested. 2. AC measurement conditions: CL = 100 pF Input pulse voltages: per VIL and VIH spec Input rise and fall times: 10 ns Timing reference voltages: half VCC level www.giantec-semi.com a0 14/19 MHz ns ns ns ns ns ns ns ns ns GT93C46A 10 ORDERING INFORMATION Industrial Grade: 1.8V to 5.5V, -40C to +85C, Lead-free Product Voltage Range Part Number* GT93C46A 1.8V to 5.5V GT93C46A-2GLI-TR GT93C46A-2ZLI-TR GT93C46A-2UDLI-TR Package (8-pin)* 150-mil SOIC/SOP JEDEC 3 x 4.4 mm TSSOP 2 x 3 x 0.55 mm UDFN * 1. Contact Giantec Sales Representatives for availability and other package information. 2. The listed part numbers are packed in tape and reel "-TR" (4K per reel). UDFN is 5K per reel. 3. For tube/bulk packaging, remove "-TR" at the end of the P/N. 4. Refer to Giantec website for related declaration document on lead free, RoHS, halogen free, or Green, whichever is applicable. 5. Giantec offers Industrial grade for Commercial applications (0C to +70C). www.giantec-semi.com a0 15/19 GT93C46A 11 PACKAGE INFORMATION SOIC/SOP (JEDEC) www.giantec-semi.com a0 16/19 GT93C46A TSSOP www.giantec-semi.com a0 17/19 GT93C46A UDFN: Ultra-thin DFN www.giantec-semi.com a0 18/19 GT93C46A 12 REVISION HISTORY Revision a0 Date 3/23/2010 www.giantec-semi.com Page All Descriptions Initial version a0 19/19