4-3
File Number
2281.3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
http://www.intersil.com or 407-727-9207 |Copyright © Intersil Corporation 1999
IRF9520
6A, 100V, 0.600 Ohm, P-Channel Power
MOSFET
This advanced power MOSFET is designed, tested, and
guaranteed to withstand a specified level of energy in the
breakdown avalanche mode of operation. These are
P-Channel enhancement mode silicon gate power field
effect transistors designed for applications such as switching
regulators, switching converters, motor drivers, relay drivers
and drivers for high power bipolar switching transistors
requiring high speed and low gate drive power. These types
can be operated directly from integrated circuits.
Formerly developmental type TA17501.
Features
6A, 100V
•r
DS(ON) = 0.600
Single Pulse Avalanche Energy Rated
SOA is Power Dissipation Limited
Nanosecond Switching Speeds
Linear Transfer Characteristics
High Input Impedance
Symbol
Packaging
JEDEC TO-220AB
Ordering Information
PART NUMBER PACKAGE BRAND
IRF9520 TO-220AB IRF9520
NOTE: When ordering, use the entire part number.
G
D
S
DRAIN (FLANGE)
GATE
SOURCE
DRAIN
Data Sheet July 1999
4-4
Absolute Maximum Ratings TC = 25oC, Unless Otherwise Specified IRF9520 UNITS
Drain to Source Breakdown Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDS -100 V
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR -100 V
Continuous Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
TC =100oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID-6
-4 A
A
Pulsed Drain Current (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM -24 A
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS ±20 V
Maximum Power Dissipation (Figure 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .P
D40 W
Linear Derating Factor (Figure 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.32 W/oC
Single Pulse Avalanche Energy Rating (Note 4). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . EAS 370 mJ
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TJ, TSTG -55 to 150 oC
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL
Package Body for 10s, See Techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg 300
260
oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operationofthe
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
1. TJ = 25oC to TJ = 125oC.
Electrical Specifications TC = 25oC, Unless Otherwise Specified
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Drain to Source Breakdown Voltage BVDSS ID = -250µA, VGS = 0V (Figure 10) -100 - - V
Gate Threshold Voltage VGS(TH) VGS = VDS, ID = -250µA -2 - -4 V
Zero Gate Voltage Drain Current IDSS VDS = Rated BVDSS, VGS = 0V - - -25 µA
VDS = 0.8 x Rated BVDSS, VGS = 0V
TC = 125oC- - -250 µA
On-State Drain Current (Note 2) ID(ON) VDS > ID(ON) x rDS(ON) MAX, VGS = -10V -6 - - A
Gate to Source Leakage Current IGSS VGS = ±20V - - ±100 nA
Drain to Source On Resistance (Note 2) rDS(ON) ID = -3.5A, VGS = -10V (Figures 8, 9) - 0.500 0.600
Forward Transconductance (Note 2) gfs VDS > ID(ON) x rDS(ON)MAX, ID = -3.5A
( Figure 12) 0.9 2 - S
Turn-On Delay Time td(ON) VDD = 0.5 x Rated BVDSS, ID -6.0A,
RG = 50 , RL = 7.7 for VDSS = 50
MOSFET Switching Times are Essentially
Independent of Operating Temperature
-2550ns
Rise Time tr- 50 100 ns
Turn-Off Delay Time td(OFF) - 50 100 ns
Fall Time tf- 50 100 ns
Total Gate Charge
(Gate to Source + Gate to Drain) Qg(TOT) VGS = -10V, ID = -6A, VDS = 0.8 x Rated BVDSS
(Figure 14) Gate Charge is Essentially
Independent of Operating Temperature
-1622nC
Gate to Source Charge Qgs -9-nC
Gate to Drain “Miller” Charge Qgd -7-nC
Input Capacitance CISS VDS = -25V, VGS = 0V, f = 1MHz
(Figure 11) - 300 - pF
Output Capacitance COSS - 200 - pF
Reverse Transfer Capacitance CRSS -50- pF
Internal Drain Inductance LDMeasured From the
Contact Screw on Tab To
Center of Die
Modified MOSFET
Symbol Showing the
Internal Devices
Inductances
- 3.5 - nH
Measured From the Drain
Lead, 6mm (0.25in) from
Package to Center of Die
- 4.5 - nH
Internal Source Inductance LSMeasured From the
Source Lead, 6mm
(0.25in) From Header to
Source Bonding Pad
- 7.5 - nH
Thermal Resistance Junction-to-Case RθJC - - 3.12 oC/W
Thermal Resistance Junction-to-Ambient RθJA Typical Socket Mount - - 62.5 oC/W
LS
LD
G
D
S
IRF9520
4-5
Source to Drain Diode Specifications
PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
Continuous Source to Drain Current ISD Modified MOSFET Sym-
bol Showing the Integral
Reverse P-N Junction
Diode
- - -6.0 A
Pulse Source to Drain Current
(Note 3) ISDM - - -24 A
Source to Drain Diode Voltage
(Note 2) VSD TC = 25oC, ISD = -6.0A, VGS = 0V
(Figure 13) - - -1.5 V
Reverse Recovery Time trr TJ = 150oC, ISD = -6.0A, dISD/dt = 100A/µs - 230 - ns
Reverse Recovery Charge QRR TJ = 150oC, ISD = -6.0A, dISD/dt = 100A/µs - 1.3 - µC
NOTES:
2. Pulse test: pulse width 300µs, duty cycle 2%.
3. Repetitive rating: pulse width limited by maximum junction temperature. See Transient Thermal Impedance curve (Figure 3).
4. VDD = 25V, starting TJ= 25oC, L = 15.4mH, RG= 25Ω, peak IAS = 6.0A.
Typical Performance Curves
Unless Otherwise Specified
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
FIGURE 3. NORMALIZED TRANSIENT THERMAL IMPEDANCE
G
D
S
TA, CASE TEMPERATURE (oC)
POWER DISSIPATION MULTIPLIER
0.0 0 25 50 75 100 150
0.2
0.4
0.6
0.8
1.0
1.2
125 050 100
ID, DRAIN CURRENT (A)
TC, CASE TEMPERATURE (oC)
150
25 75 125
6.0
4.8
3.6
2.4
1.2
t1, RECTANGULAR PULSE DURATION (s)
ZθJC, NORMALIZED TRANSIENT
THERMAL IMPEDANCE
10-3 10-2
1
10-5 10-4
0.01
0.1
SINGLE PULSE
PDM
10
10-1 1
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC xR
θJC + TC
t1
t2
0.1
0.02
0.2
0.5
0.01
0.05
IRF9520
4-6
FIGURE 4. FORWARD BIAS SAFE OPERATING AREA FIGURE 5. OUTPUT CHARACTERISTICS
FIGURE 6. SATURATION CHARACTERISTICS FIGURE 7. TRANSFER CHARACTERISTICS
FIGURE 8. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT FIGURE 9. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
Typical Performance Curves
Unless Otherwise Specified (Continued)
VDS, DRAIN TO SOURCE VOLTAGE (V)
1
ID, DRAIN CURRENT (A)
10
0.1 101
10µs
100µs
1ms
10ms
DC
OPERATION IN THIS AREA
IS LIMITED BY rDS(ON)
100
TJ = MAX RATED
TC = 25oC
100ms
ID, DRAIN CURRENT (A)
0 -10 -20 -30 -40
-2
-4
-6
-8
-10
-50
VGS = -9V
VGS = -7V
VGS = -6V
VGS = -5V
VDS, DRAIN TO SOURCE VOLTAGE (V)
VGS = -4V
PULSE DURATION = 80µs
0
VGS = -8V
VGS = -10V
DUTY CYCLE = 0.5% MAX.
0
-1
0-1 -2 -3 -5
-2
-3
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
-4
-4
-5
VGS = -7V
VGS = -10V
VGS = -9V
VGS = -4V
VGS = -5V
VGS = -6V
VGS = -8V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX.
-10
-8
-6
-4
-2
00 -2-4 -6-8-10
VGS, GATE TO SOURCE VOLTAGE (V)
ID(ON), ON-STATE DRAIN CURRENT (A)
TJ = -55oC
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX.
VDS ID(ON) x rDS(ON) MAX
TJ = 125oC
TJ = 25oC
ID, DRAIN CURRENT (A)
rDS(ON), DRAIN TO SOURCE
2.0
1.6
1.2
0.8
0.4
00 -5 -10 -15 -20 -25
VGS = -20V
VGS = -10V
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX.
ON RESISTANCE ()
NORMALIZED DRAIN TO SOURCE
2.2
1.4
1.0
0.6
0.2 -40 0 40
TJ, JUNCTION TEMPERATURE (oC)
120
1.8
80
ON RESISTANCE
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX.
VGS = -10V, ID = -4A
IRF9520
4-7
FIGURE 10. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE FIGURE 11. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 12. TRANSCONDUCTANCE vs DRAIN CURRENT FIGURE 13. SOURCE TO DRAIN DIODE VOLTAGE
FIGURE 14. GATE TO SOURCE VOLTAGE vs GATE CHARGE
Typical Performance Curves
Unless Otherwise Specified (Continued)
1.25
0.95
0.85
0.75
-40 0 40
TJ, JUNCTION TEMPERATURE (oC)
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
80 120 160
1.05
1.15
ID = 250µA500
100
00-20 -50
C, CAPACITANCE (pF)
300
VDS, DRAIN TO SOURCE VOLTAGE (V)
400
200
CISS
COSS
CRSS
-10 -30 -40
CISS = CGS + CGD
CRSS = CGD
COSS CDS + CGD
VGS = 0V, f = 1MHz
3
2
1
00-2-4-6-8-10
TJ = -55oC
TJ = 25oC
TJ = 125oC
gfs, TRANSCONDUCTANCE (S)
ID, DRAIN CURRENT (A)
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX.
-0.4 -1.0 -1.2 -1.6 -1.8-0.6 VSD, SOURCE TO DRAIN VOLTAGE (V)
-0.8 -1.4
-0.1
-1.0
-10
ISD, DRAIN CURRENT (A)
-100
TJ = 25oC
TJ = 150oC
0
-5
-10
0481216
VDS = -50V
VDS = -20V
Qg(TOT), TOTAL GATE CHARGE (nC)
VGS, GATE TO SOURCE (V)
ID = -6A
20
VDS = -80V
IRF9520
4-8
Test Circuits and Waveforms
FIGURE 15. UNCLAMPED ENERGY TEST CIRCUIT FIGURE 16. UNCLAMPED ENERGY WAVEFORMS
FIGURE 17. SWITCHING TIME TEST CIRCUIT FIGURE 18. RESISTIVE SWITCHING WAVEFORMS
FIGURE 19. GATE CHARGE TEST CIRCUIT FIGURE 20. GATE CHARGE WAVEFORMS
tP
0.01
L
IAS
+
-
VDS
VDD
RG
DUT
VARY tP TO OBTAIN
REQUIRED PEAK IAS
0V
VGS
VDD
VDS
BVDSS
tP
IAS
tAV
0
VGS
RL
RG
DUT
+
-VDD
td(ON)
tr
90%
10%
VDS 90%
tf
td(OFF)
tOFF
90%
50%
50%
10%
PULSE WIDTH
VGS
tON
10%
0
0
0.3µF
12V
BATTERY 50k
+VDS
S
DUT
D
G
IG(REF)
0
(ISOLATED
-VDS
0.2µF
CURRENT
REGULATOR
ID CURRENT
SAMPLING
IG CURRENT
SAMPLING
SUPPLY)
RESISTOR RESISTOR
DUT
Qg(TOT)
Qgd
Qgs
VDS
0
VGS
VDD
0
IG(REF)
IRF9520
4-9
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time with-
out notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is gr anted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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IRF9520