MX25L5121E MX25L1021E MX25L5121E, MX25L1021E DATASHEET P/N: PM1573 1 REV. 1.1, DEC. 29, 2011 MX25L5121E MX25L1021E Contents FEATURES................................................................................................................................................................... 4 GENERAL............................................................................................................................................................. 4 PERFORMANCE.................................................................................................................................................. 4 SOFTWARE FEATURES...................................................................................................................................... 4 HARDWARE FEATURES...................................................................................................................................... 4 GENERAL DESCRIPTION.......................................................................................................................................... 5 PIN CONFIGURATIONS .............................................................................................................................................. 6 PIN DESCRIPTION....................................................................................................................................................... 6 BLOCK DIAGRAM........................................................................................................................................................ 7 MEMORY ORGANIZATION.......................................................................................................................................... 8 Table 1-1. Memory Organization (512Kb)............................................................................................................ 8 Table 1-2. Memory Organization (1Mb)................................................................................................................ 8 DEVICE OPERATION................................................................................................................................................... 9 Figure 1. Serial Modes Supported......................................................................................................................... 9 DATA PROTECTION................................................................................................................................................... 10 Table 2. Protected Area Sizes............................................................................................................................. 10 COMMAND DESCRIPTION........................................................................................................................................ 11 Table 3. Command Set........................................................................................................................................ 11 (1) Write Enable (WREN).................................................................................................................................... 12 (2) Write Disable (WRDI)..................................................................................................................................... 12 (3) Read Identification (RDID)............................................................................................................................. 12 Table 4. ID Definitions ........................................................................................................................................ 12 (4) Read Status Register (RDSR)....................................................................................................................... 13 Table 5. Status Register...................................................................................................................................... 13 (5) Write Status Register (WRSR)....................................................................................................................... 14 Table 6. Protection Modes................................................................................................................................... 14 (6) Read Data Bytes (READ).............................................................................................................................. 15 (7) Read Data Bytes at Higher Speed (FAST_READ)........................................................................................ 15 (8) Sector Erase (SE).......................................................................................................................................... 15 (9) Block Erase (BE)............................................................................................................................................ 15 (10) Chip Erase (CE)........................................................................................................................................... 16 (11) Page Program (PP)...................................................................................................................................... 16 (12) Deep Power-Down (DP).............................................................................................................................. 16 (13) Release from Deep Power-Down (RDP)..................................................................................................... 17 POWER-ON STATE.................................................................................................................................................... 18 Program/ Erase flow with read array data........................................................................................................... 19 ELECTRICAL SPECIFICATIONS............................................................................................................................... 20 P/N: PM1573 2 REV. 1.1, DEC. 29, 2011 MX25L5121E MX25L1021E ABSOLUTE MAXIMUM RATINGS...................................................................................................................... 20 Figure 2. Maximum Negative Overshoot Waveform........................................................................................... 20 CAPACITANCE TA = 25C, f = 1.0 MHz.............................................................................................................. 20 Figure 3. Maximum Positive Overshoot Waveform............................................................................................. 20 Figure 4. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL............................................................... 21 Figure 5. OUTPUT LOADING............................................................................................................................ 21 Table 7. DC CHARACTERISTICS (Temperature = 0C to 70C for Commercial grade, VCC = 2.7V ~ 3.6V) .. 22 Table 8. AC CHARACTERISTICS (Temperature = 0C to 70C for Commercial grade, VCC = 2.7V ~ 3.6V) .. 23 Timing Analysis......................................................................................................................................................... 24 Figure 6. Serial Input Timing............................................................................................................................... 24 Figure 7. Output Timing....................................................................................................................................... 24 Figure 8. WP# Disable Setup and Hold Timing during WRSR when SRWD=1.................................................. 25 Figure 9. Write Enable (WREN) Sequence (Command 06)................................................................................ 25 Figure 10. Write Disable (WRDI) Sequence (Command 04)............................................................................... 25 Figure 11. Read Identification (RDID) Sequence (Command 9F)....................................................................... 26 Figure 12-1. Read Status Register (RDSR) Sequence (Command 05).............................................................. 27 Figure 12-2. Read Status Register (RDSR) Sequence (Command 05).............................................................. 27 Figure 13. Write Status Register (WRSR) Sequence (Command 01)................................................................ 28 Figure 14. Read Data Bytes (READ) Sequence (Command 03)....................................................................... 28 Figure 15. Read at Higher Speed (FAST_READ) Sequence (Command 0B).................................................... 29 Figure 16. Sector Erase (SE) Sequence (Command 20)................................................................................... 29 Figure 17. Block Erase (BE) Sequence (Command D8 or 52)........................................................................... 30 Figure 18. Chip Erase (CE) Sequence (Command 60 or C7)............................................................................ 30 Figure 19. Page Program (PP) Sequence (Command 02)................................................................................. 30 Figure 20. Deep Power Down (DP) Sequence (Command B9)......................................................................... 31 Figure 21. Release from Deep Power Down (RDP) Sequence (Command AB)................................................ 31 Figure 23. Power-Up Timing................................................................................................................................ 32 Table 9. Power-Up Timing................................................................................................................................... 32 INITIAL DELIVERY STATE.................................................................................................................................. 32 OPERATING CONDITIONS........................................................................................................................................ 33 Figure 24. AC Timing at Device Power-Up.......................................................................................................... 33 Figure 25. Power-Down Sequence..................................................................................................................... 34 ERASE AND PROGRAMMING PERFORMANCE..................................................................................................... 35 DATA RETENTION .................................................................................................................................................... 35 LATCH-UP CHARACTERISTICS............................................................................................................................... 35 ORDERING INFORMATION....................................................................................................................................... 36 PART NAME DESCRIPTION...................................................................................................................................... 37 PACKAGE INFORMATION......................................................................................................................................... 38 REVISION HISTORY ................................................................................................................................................. 40 P/N: PM1573 3 REV. 1.1, DEC. 29, 2011 MX25L5121E MX25L1021E 512K-BIT [x 1] CMOS SERIAL FLASH MEMORY 1M-BIT [x 1] CMOS SERIAL FLASH MEMORY FEATURES GENERAL * Serial Peripheral Interface compatible -- Mode 0 and Mode 3 * 512K: 524,288 x 1 bit structure 1M: 1,048,576 x 1 bit structure * 16 Equal Sectors with 4K bytes each (512Kb) 32 Equal Sectors with 4K bytes each (1Mb) - Any Sector can be erased individually * 1 Equal Blocks with 64K byte each (512Kb) 2 Equal Blocks with 64K byte each (1Mb) - Any Block can be erased individually * Program Capability - Byte base - Page base (32 bytes) * Single Power Supply Operation - 2.7 to 3.6 volt for read, erase, and program operations * Latch-up protected to 100mA from -1V to Vcc +1V PERFORMANCE * Performance - Fast Read: 45MHz serial clock - Fast program time: 180us(typ.) and 650us(max.)/page - Fast erase time: 90ms (typ.)/sector ; 1s (typ.)/block * Low Power Consumption - Low active read current: 5mA(max.) at 25MHz, 10mA(max.) at 45MHz - Low active programming current: 12mA (max.) - Low active erase current: 15mA (max.) - Low standby current: 20uA (typ.) - Deep power down current: 2uA (typ.) * Typical 100,000 erase/program cycles * 20 years data retention SOFTWARE FEATURES * Input Data Format - 1-byte Command code * Block Lock protection - The BP0~BP1 status bits defines the size of the area to be software protected against Program and Erase instructions * Auto Erase and Auto Program Algorithm - Automatically erases and verifies data at selected sector - Automatically programs and verifies data at selected page by an internal algorithm that automatically times the program pulse widths (Any page to be programed should have page in the erased state first) * Status Register Feature * Electronic Identification - JEDEC 1-byte manufacturer ID and 2-bytes device ID HARDWARE FEATURES * SCLK Input - Serial clock input * SI Input P/N: PM1573 4 REV. 1.1, DEC. 29, 2011 MX25L5121E MX25L1021E - Serial Data Input * SO Output - Serial Data Output * WP# pin - Hardware write protection * PACKAGE - 8-pin SOP (150mil) - 8-pin TSSOP (173mil) - 8-USON (2x3mm) - All devices are RoHS Compliant GENERAL DESCRIPTION The device feature a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. The three bus signals are a clock input (SCLK), a serial data input (SI), and a serial data output (SO). Serial access to the device is enabled by CS# input. The device provides sequential read operation on whole chip. After program/erase command is issued, auto program/erase algorithms which program/erase and verify the specified page or sector locations will be executed. Program command is executed on page (32 bytes) basis, and erase command is executes on sector, or block, or whole chip. To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit. When the device is not in operation and CS# is high, it is put in Standby Mode and draws less than 30uA (typical:20uA) DC current. The device utilizes Macronix proprietary memory cell, which reliably stores memory contents even after typical 100,000 program and erase cycles. P/N: PM1573 5 REV. 1.1, DEC. 29, 2011 MX25L5121E MX25L1021E PIN CONFIGURATIONS PIN DESCRIPTION 8-PIN SOP (150mil) CS# SO WP# GND SYMBOL 1 2 3 4 8 7 6 5 CS# VCC NC SCLK SI Serial Data Input (for 1 x I/O) SO Serial Data Output (for 1 x I/O) NC CS# SO WP# GND 1 2 3 4 8 7 6 5 VCC NC SCLK SI Chip Select SI SCLK 8-PIN TSSOP (173mil) DESCRIPTION Clock Input NC pin (Not connect) WP# Write Protection VCC 2.7V to 3.6V Power Supply GND Ground 8-LAND USON (2x3mm) CS# SO WP# GND P/N: PM1573 1 2 3 4 8 7 6 5 VCC NC SCLK SI 6 REV. 1.1, DEC. 29, 2011 MX25L5121E MX25L1021E BLOCK DIAGRAM X-Decoder Address Generator Memory Array Page Buffer SI Data Register Y-Decoder SRAM Buffer CS# SCLK Mode Logic State Machine HV Generator Clock Generator Output Buffer SO P/N: PM1573 Sense Amplifier 7 REV. 1.1, DEC. 29, 2011 MX25L5121E MX25L1021E MEMORY ORGANIZATION Table 1-1. Memory Organization (512Kb) Block Sector 15 0 P/N: PM1573 Table 1-2. Memory Organization (1Mb) Block Address Range 00F000h 00FFFFh 1 Sector Address Range 31 01F000h 01FFFFh : : : : : : 3 003000h 003FFFh 16 010000h 010FFFh 2 002000h 002FFFh 15 00F000h 00FFFFh 1 001000h 001FFFh : : : 0 000000h 000FFFh 3 003000h 003FFFh 2 002000h 002FFFh 1 001000h 001FFFh 0 000000h 000FFFh 0 8 REV. 1.1, DEC. 29, 2011 MX25L5121E MX25L1021E DEVICE OPERATION 1. Before a command is issued, status register should be checked to ensure device is ready for the intended operation. 2. When incorrect command is inputted to this LSI, this LSI becomes Standby Mode and keeps the Standby Mode until next CS# falling edge. In Standby Mode, all SO pins of this LSI should be High-Z. 3. When correct command is inputted to this LSI, this LSI becomes active mode and keeps the active mode until next CS# rising edge. 4. Input data is latched on the rising edge of Serial Clock(SCLK) and data shifts out on the falling edge of SCLK. The difference of Serial mode 0 and mode 3 is shown as Figure 1. 5. For the following instructions: RDID, RDSR, READ and FAST_READ the shifted-in instruction sequence is followed by a data-out sequence. After any bit of data being shifted out, the CS# can be high. For the following instructions: WREN, WRDI, WRSR, SE, PP, RDP, and DP the CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. 6. During the progress of Program, Erase operation, to access the memory array is neglected and not affect the current operation of Program and Erase. Figure 1. Serial Modes Supported CPOL CPHA shift in (Serial mode 0) 0 0 SCLK (Serial mode 3) 1 1 SCLK SI shift out MSB SO MSB Note: CPOL indicates clock polarity of Serial master, CPOL=1 for SCLK high while idle, CPOL=0 for SCLK low while not transmitting. CPHA indicates clock phase. The combination of CPOL bit and CPHA bit decides which Serial mode is supported. P/N: PM1573 9 REV. 1.1, DEC. 29, 2011 MX25L5121E MX25L1021E DATA PROTECTION The device is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transition. During power up the device automatically resets the state machine in the Standby Mode. In addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. The device also incorporates several features to prevent inadvertent write cycles resulting from VCC power-up and power-down transition or system noise. * Valid command length checking: The command length will be checked whether it is at byte base and completed on byte boundary. * Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before other command to change data. The WEL bit will return to reset stage under following situation: - Power-up - Write Disable (WRDI) command completion - Write Status Register (WRSR) command completion - Page Program (PP) command completion - Sector Erase (SE) command completion - Block Erase (BE) command completion - Chip Erase (CE) command completion * Software Protection Mode (SPM): by using BP0-BP1 bits to set the part of Flash protected from data change. * Hardware Protection Mode (HPM): by using WP# going low to protect the BP0-BP1 bits and SRWD bit from data change. * Deep Power Down Mode: By entering Deep Power Down Mode, the flash device also is under protected from writing all commands except Release from Deep Power Down Mode command (RDP). Table 2. Protected Area Sizes BP1 0 0 1 1 P/N: PM1573 Status bit BP0 0 1 0 1 MX25L5121E 0 (none) 1 (All) 2 (All) 3 (All) 10 Protect level MX25L1021E 0 (none) 1 (1 block) 2 (All) 3 (All) REV. 1.1, DEC. 29, 2011 MX25L5121E MX25L1021E COMMAND DESCRIPTION Table 3. Command Set Command WREN (write WRDI (write (byte) enable) disable) 1st byte 06 (hex) 04 (hex) WRSR RDID RDSR (write status (read identific- (read status register) ation) register) 01 (hex) 9F (hex) 05 (hex) 2nd byte 3rd byte 4th byte 5th byte Action Command (byte) 1st byte 2nd byte 3rd byte 4th byte Action READ (read data) 03 (hex) AD1 (A23-A16) AD2 (A15-A8) AD3 (A7-A0) FAST READ (fast read data) 0B (hex) AD1 AD2 AD3 Dummy sets the (WEL) resets the to write new outputs to read out n bytes read n bytes read write enable (WEL) write values of the JEDEC the values out until CS# out until CS# latch bit enable latch status register ID: 1-byte of the status goes high goes high bit Manufacturer register ID & 2-bytes Device ID SE (sector erase) BE (block erase) CE (chip erase) PP (page program) DP (Deep power down) RDP (Release from deep power down) AB (hex) 20 (hex) 52 or D8 (hex) 60 or C7 (hex) 02 (hex) B9 (hex) AD1 AD1 AD1 AD2 AD2 AD2 AD3 AD3 AD3 to erase the to erase the to erase to program enters Deep release from selected selected whole chip the selected Power Down Deep Power sector block page Mode Down Mode Note 1: It is not recommended to adopt any other code not in the command definition table, which will potentially enter the hidden mode. Note 2: Value "1" should be input to the un-used significant bits of address bits by user (e.g. A17~A23(MSB) in MX25L1021E ; A16-A23(MSB) in MX25L5121E) P/N: PM1573 11 REV. 1.1, DEC. 29, 2011 MX25L5121E MX25L1021E (1) Write Enable (WREN) The Write Enable (WREN) instruction is for setting Write Enable Latch (WEL) bit. For those instructions like PP, SE, BE, CE and WRSR which are intended to change the device content, should be set every time after the WREN instruction setting the WEL bit. The sequence of issuing WREN instruction is: CS# goes low sending WREN instruction codeCS# goes high. (Please refer to Figure 9) (2) Write Disable (WRDI) The Write Disable (WRDI) instruction is for resetting Write Enable Latch (WEL) bit. The sequence of issuing WRDI instruction is: CS# goes lowsending WRDI instruction codeCS# goes high. (Please refer to Figure 10) The WEL bit is reset by following situations: - Power-up - Write Disable (WRDI) instruction completion - Write Status Register (WRSR) instruction completion - Page Program (PP) instruction completion - Sector Erase (SE) instruction completion - Block Erase (BE) instruction completion - Chip Erase (CE) instruction completion (3) Read Identification (RDID) The RDID instruction is for reading the manufacturer ID of 1-byte and followed by Device ID of 2-bytes. The MXIC Manufacturer ID is C2(hex), the memory type ID is 22(hex) as the first-byte device ID, and the individual device ID of second-byte ID are listed as table of "ID Definitions". (Please refer to table 4) The sequence of issuing RDID instruction is: CS# goes lowsending RDID instruction code24-bits ID data out on SO to end RDID operation can use CS# to high at any time during data out. (Please refer to Figure 11) While Program/Erase operation is in progress, it will not decode the RDID instruction, so there's no effect on the cycle of program/erase operation which is currently in progress. When CS# goes high, the device is at Standby Mode. Table 4. ID Definitions RDID Command P/N: PM1573 manufacturer ID C2 MX25L5121E memory type 22 memory density 10 12 manufacturer ID C2 MX25L1021E memory type 22 memory density 11 REV. 1.1, DEC. 29, 2011 MX25L5121E MX25L1021E (4) Read Status Register (RDSR) The RDSR instruction is for reading Status Register Bits. The Read Status Register can be read at any time (even in program/erase condition) and continuously. It is recommended to check the Write in Progress (WIP) bit before sending a new instruction when a program or erase operation is in progress. The sequence of issuing RDSR instruction is: CS# goes lowsending RDSR instruction codeStatus Register data out on SO (Please refer to Figure 12-1, Figure 12-2) The definition of the status register bits is as below: WIP bit. The Write in Progress (WIP) bit, a volatile bit, indicates whether the device is busy in program/erase progress. When WIP bit sets to 1, which means the device is busy in program/erase progress. When WIP bit sets to 0, which means the device is not in progress of program/erase register cycle. WEL bit. The Write Enable Latch (WEL) bit, a volatile bit, indicates whether the device is set to internal write enable latch. When WEL bit sets to 1, which means the internal write enable latch is set, the device can accept program/ erase instruction. When WEL bit sets to 0, which means no internal write enable latch; the device will not accept program/erase instruction. BP1, BP0 bits. The Block Protect (BP1, BP0) bits, volatile bits, indicate the protected area(as defined in table 1) of the device to against the program/erase instruction without hardware protection mode being set. To write the Block Protect (BP1, BP0) bits requires the Write Status Register (WRSR) instruction to be executed. Those bits define the protected area of the memory to against Page Program (PP), Sector Erase (SE), Block Erase (BE) and Chip Erase(CE) instructions (only if all Block Protect bits set to 0, the CE instruction can be executed) SRWD bit. The Status Register Write Disable (SRWD) bit, volatile bit, is operated together with Write Protection (WP#) pin for providing hardware protection mode. The hardware protection mode requires SRWD sets to 1 and WP# pin signal is low stage. In the hardware protection mode, the Write Status Register (WRSR) instruction is no longer accepted for execution and the SRWD bit and Block Protect bits (BP1, BP0) are read only. Table 5. Status Register bit7 bit6 bit5 bit4 SRWD (status register write protect) Reserved Reserved Reserved 1=status register write disable 0 0 0 bit3 BP1 (level of protected block) bit2 BP0 (level of protected block) (note 1) (note 1) bit1 bit0 WEL WIP (write enable (write in latch) progress bit) 1=write 1=write enable operation 0=not write 0=not in write enable operation Note: 1. See the table "Protected Area Sizes". The default BP0-BP2 values are "1" (protected). 2. The SRWD default value is "0" P/N: PM1573 13 REV. 1.1, DEC. 29, 2011 MX25L5121E MX25L1021E (5) Write Status Register (WRSR) The WRSR instruction is for changing the values of Status Register Bits. Before sending WRSR instruction, the Write Enable (WREN) instruction must be decoded and executed to set the Write Enable Latch (WEL) bit in advance. The WRSR instruction can change the value of Block Protect (BP1, BP0) bits to define the protected area of memory (as shown in table 1). The WRSR also can set or reset the Status Register Write Disable (SRWD) bit in accordance with Write Protection (WP#) pin signal. The WRSR instruction cannot be executed once the Hardware Protected Mode (HPM) is entered. The sequence of issuing WRSR instruction is: CS# goes low sending WRSR instruction code Status Register data on SI CS# goes high. (see Figure 13) The WRSR instruction has no effect on b6, b5, b4, b1, b0 of the status register. The CS# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. The self-timed Write Status Register cycle time (tW) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Write Status Register cycle is in progress. The WIP sets 1 during the tW timing, and sets 0 when Write Status Register Cycle is completed, and the Write Enable Latch (WEL) bit is reset. Table 6. Protection Modes Mode Software protection mode (SPM) Hardware protection mode (HPM) Status register condition WP# and SRWD bit status Memory Status register can be written in (WEL bit is set to "1") and the SRWD, BP0-BP1 bits can be changed WP#=1 and SRWD bit=0, or WP#=0 and SRWD bit=0, or WP#=1 and SRWD=1 The protected area cannot be program or erase. The SRWD, BP0-BP1 of status register bits cannot be changed WP#=0, SRWD bit=1 The protected area cannot be program or erase. Note: 1. As defined by the values in the Block Protect (BP1, BP0) bits of the Status Register, as shown in Table 1. As the table above showing, the summary of the Software Protected Mode (SPM) and Hardware Protected Mode (HPM). Software Protected Mode (SPM): - When SRWD bit=0, no matter WP# is low or high, the WREN instruction may set the WEL bit and can change the values of SRWD, BP1, BP0. The protected area, which is defined by BP1, BP0, is at software protected mode (SPM). - When SRWD bit=1 and WP# is high, the WREN instruction may set the WEL bit can change the values of SRWD, BP1, BP0. The protected area, which is defined by BP1, BP0, is at software protected mode (SPM) Note: If SRWD bit=1 but WP# is low, it is impossible to write the Status Register even if the WEL bit has previously been set. It is rejected to write the Status Register and not be executed. Hardware Protected Mode (HPM): - When SRWD bit=1, and then WP# is low (or WP# is low before SRWD bit=1), it enters the hardware protected mode (HPM). The data of the protected area is protected by software protected mode by BP1, BP0 and hardware protected mode by the WP# to against data modification. Note: to exit the hardware protected mode requires WP# driving high once the hardware protected mode is entered. If the WP# pin is permanently connected to high, the hardware protected mode can never be entered; only can use software protected mode via BP1, BP0. P/N: PM1573 14 REV. 1.1, DEC. 29, 2011 MX25L5121E MX25L1021E (6) Read Data Bytes (READ) The read instruction is for reading data out. The address is latched on rising edge of SCLK, and data shifts out on the falling edge of SCLK at a maximum frequency fC. The first address can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single READ instruction. This product does not provide the function of read around. After reading through density 512Kb or 1Mb, CS# must go high. Otherwise, the data correctness will not be guaranteed. If the device needs to read data again, it must issue read command once more. The sequence of issuing READ instruction is: CS# goes low sending READ instruction code 3-bytes address on SIdata out on SOto end READ operation can use CS# to high at any time during data out. (Please refer to Figure 14) (7) Read Data Bytes at Higher Speed (FAST_READ) The FAST_READ instruction is for quickly reading data out. The address is latched on rising edge of SCLK, and data of each bit shifts out on the falling edge of SCLK at a maximum frequency fC. The first address byte can be at any location. The address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single FAST_READ instruction. The address counter rolls over to 0 when the highest address has been reached. The sequence of issuing FAST_READ instruction is: CS# goes low sending FAST_READ instruction code 3-byte address on SI 1-dummy byte address on SIdata out on SO to end FAST_READ operation can use CS# to high at any time during data out. (Please refer to Figure 15) While Program/Erase/Write Status Register cycle is in progress, FAST_READ instruction is rejected without any impact on the Program/Erase/Write Status Register current cycle. (8) Sector Erase (SE) The Sector Erase (SE) instruction is for erasing the data of the chosen sector to be "1". The instruction is used for any 4K-bytes sector. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Sector Erase (SE). Any address of the sector (Please refer to table 1) is a valid address for Sector Erase (SE) instruction. The CS# must go high exactly at the byte boundary (the eighth bit of last address byte been latched-in); otherwise, the instruction will be rejected and not executed. Address bits [Am-A12] (Am is the most significant address) select the sector address. The sequence of issuing SE instruction is: CS# goes lowsending SE instruction code3-bytes address on SI CS# goes high. (Please refer to Figure 16) The self-timed Sector Erase Cycle time (tSE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tSE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. (9) Block Erase (BE) The Block Erase (BE) instruction is for erasing the data of the chosen block to be "1". The instruction is used for 64K-byte sector erase operation. A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) P/N: PM1573 15 REV. 1.1, DEC. 29, 2011 MX25L5121E MX25L1021E bit before sending the Block Erase (BE). Any address of the block (see table 2) is a valid address for Block Erase (BE) instruction. The CS# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. The sequence is shown as Figure 17. The self-timed Block Erase Cycle time (tBE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Sector Erase cycle is in progress. The WIP sets 1 during the tBE timing, and sets 0 when Sector Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. (10) Chip Erase (CE) The Chip Erase (CE) instruction is for erasing the data of the whole chip to be "1". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Chip Erase (CE). Any address of the sector (see table 1) is a valid address for Chip Erase (CE) instruction. The CS# must go high exactly at the byte boundary( the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. The sequence is shown as Figure 18. The self-timed Chip Erase Cycle time (tCE) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Chip Erase cycle is in progress. The WIP sets 1 during the tCE timing, and sets 0 when Chip Erase Cycle is completed, and the Write Enable Latch (WEL) bit is reset. (11) Page Program (PP) The Page Program (PP) instruction is for programming the memory to be "0". A Write Enable (WREN) instruction must execute to set the Write Enable Latch (WEL) bit before sending the Page Program (PP). After the instruction and address input, data to be programmed is input sequentially. The internal sequence controller will sequentially program the data from the initial address. If the transmitted data goes beyond the page boundary, the internal sequence controller may not function properly and the content of the device will not be guaranteed. Therefore, If the initial A4-A0 (The five least significant address bits) are set to all 0, maximum 32 bytes of data can be input sequentially. If the initial address A4-A0 (The five least significant address bits) are not set to all 0, maximum bytes of data input will be the subtraction of the initial address A4-A0 from 32bytes. The data exceeding 32bytes data is not sent to device. In this case, data is not guaranteed. The sequence of issuing PP instruction is: CS# goes low sending PP instruction code 3-bytes address on SI at least 1-byte on data on SI CS# goes high. (Please refer to Figure 19) The CS# must be kept to low during the whole Page Program cycle; The CS# must go high exactly at the byte boundary( the eighth bit of data being latched in), otherwise the instruction will be rejected and will not be executed. The self-timed Page Program Cycle time (tPP) is initiated as soon as Chip Select (CS#) goes high. The Write in Progress (WIP) bit still can be check out during the Page Program cycle is in progress. The WIP sets 1 during the tPP timing, and sets 0 when Page Program Cycle is completed, and the Write Enable Latch (WEL) bit is reset. (12) Deep Power-Down (DP) The Deep Power Down (DP) instruction is for setting the device on the minimizing the power consumption (to entering the Deep Power Down Mode), the standby current is reduced from ISB1 to ISB2. The Deep Power Down Mode requires the Deep Power Down (DP) instruction to enter, during the Deep Power Down Mode, the device is not acP/N: PM1573 16 REV. 1.1, DEC. 29, 2011 MX25L5121E MX25L1021E tive and all Read/Write/Program/Erase instruction are ignored. The sequence of issuing DP instruction is: CS# goes lowsending DP instruction code CS# goes high. (Please refer to Figure 20) Once the DP instruction is set, all instruction will be ignored except the Release from Deep Power Down Mode (RDP) instruction. When Power-down, the Deep Power Down Mode automatically stops, and when power-up, the device automatically is in Standby Mode. For RDP instruction the CS# must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not executed. As soon as Chip Select (CS#) goes high, a delay of tDP is required before entering the Deep Power Down Mode. (13) Release from Deep Power-Down (RDP) The Release from Deep Power Down (RDP) instruction is terminated by driving Chip Select (CS#) High. When Chip Select (CS#) is driven High, the device is put in the Standby Mode. If the device was not previously in the Deep Power Down Mode, the transition to the Standby Mode is immediate. If the device was previously in the Deep Power Down Mode, though, the transition to the Standby Mode is delayed by tRES1, and Chip Select (CS#) must remain High for at least tRES1(max), as specified in Table 8. AC Characteristics. Once in the Standby Mode, the device waits to be selected, so that it can receive, decode and execute instructions. The RDP instruction is only for releasing from Deep Power Down Mode. The sequence is shown as Figure 21. Even in Deep Power Down Mode, the RDP is also allowed to be executed, only except the device is in progress of program/erase cycle; there's no effect on the current program/erase cycle in progress. P/N: PM1573 17 REV. 1.1, DEC. 29, 2011 MX25L5121E MX25L1021E POWER-ON STATE The device is at below states when power-up: - Standby Mode ( please note it is not Deep Power Down Mode) - Write Enable Latch (WEL) bit is reset The device must not be selected during power-up and power-down stage unless the VCC achieves below correct level: - VCC minimum at power-up stage and then after a delay of tVSL - GND at power-down Please note that a pull-up resistor on CS# may ensure a safe and proper power-up/down level. An internal power-on reset (POR) circuit may protect the device from data corruption and inadvertent data change during power up state. For further protection on the device, if the VCC does not reach the VCC minimum level, the correct operation is not guaranteed. The read, write, erase, and program command should be sent after the below time delay: - tVSL after VCC reached VCC minimum level Note: - To stabilize the VCC level, the VCC rail decoupled by a suitable capacitor close to package pins is recommended. (generally around 0.1uF) P/N: PM1573 18 REV. 1.1, DEC. 29, 2011 MX25L5121E MX25L1021E Program/ Erase flow with read array data start WREN command RDSR command* WEL=1? No Yes Program/erase command Write program data/address (Write erase address) RDSR command WIP=0? No Yes RDSR command Read WEL=0 Read array data (same address of PGM/ERS) Verify OK? No Yes Program/erase fail Program/erase successfully Program/erase another block? Yes No Program/erase completed P/N: PM1573 19 REV. 1.1, DEC. 29, 2011 MX25L5121E MX25L1021E ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS RATING VALUE Ambient Operating Temperature Commercial grade 0C to 70C Storage Temperature -65C to 150C Applied Input Voltage -0.5V to 4.6V Applied Output Voltage -0.5V to 4.6V VCC to Ground Potential -0.5V to 4.6V Notes: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is stress rating only and functional operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended period may affect reliability. 2. Specifications contained within the following tables are subject to change. 3. During voltage transitions, all pins may overshoot Vss to -2.0V and Vcc to +2.0V for periods up to 20ns, please refer to Figure 2, 3. Figure 3. Maximum Positive Overshoot Waveform Figure 2. Maximum Negative Overshoot Waveform 20ns 20ns 20ns Vss Vcc + 2.0V Vss-2.0V Vcc 20ns 20ns 20ns CAPACITANCE TA = 25C, f = 1.0 MHz Symbol Parameter CIN COUT P/N: PM1573 Min. Typ. Max. Unit Input Capacitance 6 pF VIN = 0V Output Capacitance 8 pF VOUT = 0V 20 Conditions REV. 1.1, DEC. 29, 2011 MX25L5121E MX25L1021E Figure 4. INPUT TEST WAVEFORMS AND MEASUREMENT LEVEL Input timing reference level 0.8VCC 0.7VCC 0.3VCC 0.2VCC Output timing reference level 0.7VCC AC Measurement Level 0.3VCC Note: Input pulse rise and fall time are <8ns Notes: Rise time means 0.2VCC to 0.8VCC; Fall time means 0.8VCC to 0.2VCC. Figure 5. OUTPUT LOADING DEVICE UNDER TEST 2.7K ohm CL 6.2K ohm +3.3V DIODES=IN3064 OR EQUIVALENT CL=30pF Including jig capacitance P/N: PM1573 21 REV. 1.1, DEC. 29, 2011 MX25L5121E MX25L1021E Table 7. DC CHARACTERISTICS (Temperature = 0C to 70C for Commercial grade, VCC = 2.7V ~ 3.6V) Symbol Parameter Notes Min. Typ. Max. Units Test Conditions ILI Input Load Current 1 2 uA VCC = VCC Max, VIN = VCC or GND ILO Output Leakage Current 1 2 uA VCC = VCC Max, VOUT = VCC or GND ISB1 VCC Standby Current 1 20 30 uA VIN = VCC or GND, CS# = VCC ISB2 Deep Power Down Current 2 8 uA 10 mA 5 mA ICC1 VCC Read 1 VIN = VCC or GND, CS# = VCC f=45MHz, SCLK=0.1VCC/0.9VCC, SO=Open f=25MHz, SCLK=0.1VCC/0.9VCC, SO=Open Program in Progress, CS# = VCC ICC2 VCC Program Current (PP) 1 12 mA ICC3 VCC Write Register (WRSR) Current 1 15 mA Program Status Register in Progress, CS#=VCC ICC4 VCC Sector Erase Current (SE) 1 15 mA Erase in Progress, CS#=VCC VIL Input Low Voltage -0.5 0.2VCC V VIH Input High Voltage 0.8VCC VCC+0.4 V VOL Output Low Voltage 0.4 V IOL = 1.6mA VOH Output High Voltage V IOH = -100uA VWI Low VCC Write Inhibit Voltage VCC-0.2 3 2.1 2.3 2.5 V Notes : 1. Typical values at VCC = 3.3V, T = 25C. These currents are valid for all product versions (package and speeds). 2. Typical value is calculated by simulation. 3. Not 100% tested. P/N: PM1573 22 REV. 1.1, DEC. 29, 2011 MX25L5121E MX25L1021E Table 8. AC CHARACTERISTICS (Temperature = 0C to 70C for Commercial grade, VCC = 2.7V ~ 3.6V) Symbol fSCLK fRSCLK tCH(1) tCL(1) tCLCH(2) tRISE(2) tCHCL(2) tFALL(2) tSLCH tCHSL tDVCH tCHDX tCHSH tSHCH tSHSL(3) tSHQZ(2) tCLQV tCLQX tWHSL(4) tSHWL(4) tW tDP(2) tRES1(2) tPP tSE tRPD1 tBE tCE Alt. Parameter fC Clock Frequency for FAST_READ Clock Frequency for the following instructions: fR READ, PP, SE, BE, CE, DP, RDP, WREN, RDID, RDSR, WRSR @ 25 MHz tCLH Clock High Time @ 45 MHz @ 25 MHz tCLL Clock Low Time @ 45 MHz Clock Rise Time (3) (peak to peak) Clock Rise Time (3) Clock Fall Time (3) (peak to peak) Clock Fall Time (3) tCSS CS# Active Setup Time (relative to SCLK) CS# Not Active Hold Time (relative to SCLK) tDSU Data In Setup Time tDH Data In Hold Time CS# Active Hold Time (relative to SCLK) CS# Not Active Setup Time (relative to SCLK) Read tCSH CS# Deselect Time Write/Erase/Program tDIS Output Disable Time @ 25 MHz tV Clock Low to Output Valid @ 45 MHz tHO Output Hold Time Write Protect Setup Time Write Protect Hold Time Write Status Register Cycle Time CS# High to Deep Power Down Mode CS# High to Standby Mode without Electronic Signature Read Page Program Cycle Time (32 Bytes) Sector Erase Cycle Time (4K Bytes) CS# High to Power-Down Block Erase Cycle Time 512Kb Chip Erase Cycle Time 1Mb Min. 1KHz Typ. 1KHz Max. 45 Unit MHz 25 MHz 18 10 18 10 0.1 10 0.1 10 20 20 4 6 20 20 50 50 20 18 18 0 20 100 5 180 90 15 20 20 650 300 1 1 1.5 2 2 3 100 ns ns ns ns V/ns ns/V V/ns ns/V ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms us us us ms ns s s s Notes: 1. tCH + tCL must be greater than or equal to 1/ f (fC). 2. Value guaranteed by characterization, not 100% tested in production. 3. Test condition is shown as Figure 4, 5. 4. Only applicable as a constraint for a WRSR instruction when SRWD is set at 1. P/N: PM1573 23 REV. 1.1, DEC. 29, 2011 MX25L5121E MX25L1021E Timing Analysis Figure 6. Serial Input Timing tSHSL CS# tSLCH tCHSL tSHCH tCHSH SCLK tCHCL tDVCH tCLCH tCHDX LSB MSB SI High-Z SO Figure 7. Output Timing CS# tCH SCLK tCLQV tCLQV tCLQX tCLQX LSB SO SI P/N: PM1573 tSHQZ tCL ADDR.LSB IN 24 REV. 1.1, DEC. 29, 2011 MX25L5121E MX25L1021E Figure 8. WP# Disable Setup and Hold Timing during WRSR when SRWD=1 WP# tSHWL tWHSL CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK 01 SI High-Z SO Figure 9. Write Enable (WREN) Sequence (Command 06) CS# 0 1 2 3 4 5 6 7 6 7 SCLK Command SI 06 High-Z SO Figure 10. Write Disable (WRDI) Sequence (Command 04) CS# 0 1 2 3 4 5 SCLK Command SI SO P/N: PM1573 04 High-Z 25 REV. 1.1, DEC. 29, 2011 MX25L5121E MX25L1021E Figure 11. Read Identification (RDID) Sequence (Command 9F) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 28 29 30 31 SCLK Command SI 9F Manufacturer ID SO High-Z 7 6 5 3 MSB P/N: PM1573 2 Device ID 1 0 15 14 13 3 2 1 0 MSB 26 REV. 1.1, DEC. 29, 2011 MX25L5121E MX25L1021E Figure 12-1. Read Status Register (RDSR) Sequence (Command 05) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK command 05 SI Status Register Out High-Z SO 7 6 5 4 3 2 Status Register Out 1 0 7 6 5 4 3 2 1 0 7 MSB MSB Figure 12-2. Read Status Register (RDSR) Sequence (Command 05) CS# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK Command SI 05 Status Register Out High-Z SO 7 6 5 4 3 2 1 0 MSB CS# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK Command SI 05 Status Register Out High-Z SO 7 6 5 4 3 2 1 0 MSB CS# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK Command SI 05 Status Register Out SO High-Z 7 6 5 4 3 2 1 0 MSB P/N: PM1573 27 REV. 1.1, DEC. 29, 2011 MX25L5121E MX25L1021E Figure 13. Write Status Register (WRSR) Sequence (Command 01) CS# 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 SCLK command SI Status Register In 01 7 5 4 3 2 0 1 MSB High-Z SO 6 Figure 14. Read Data Bytes (READ) Sequence (Command 03) CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 SCLK command SI 03 24-Bit Address 23 22 21 3 2 1 0 MSB SO Data Out 1 High-Z 7 6 5 4 3 2 Data Out 2 1 0 7 MSB P/N: PM1573 28 REV. 1.1, DEC. 29, 2011 MX25L5121E MX25L1021E Figure 15. Read at Higher Speed (FAST_READ) Sequence (Command 0B) CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 SCLK Command SI 24 BIT ADDRESS 23 22 21 0B 3 2 1 0 High-Z SO CS# 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCLK Dummy Byte 7 SI 6 5 4 3 2 1 0 DATA OUT 2 DATA OUT 1 7 SO 6 5 4 3 2 1 0 7 6 5 4 MSB MSB 3 2 1 0 7 MSB Figure 16. Sector Erase (SE) Sequence (Command 20) CS# 0 1 2 3 4 5 6 7 8 9 29 30 31 SCLK 24 Bit Address Command SI 23 22 20 2 1 0 MSB P/N: PM1573 29 REV. 1.1, DEC. 29, 2011 MX25L5121E MX25L1021E Figure 17. Block Erase (BE) Sequence (Command D8 or 52) CS# 0 1 2 3 4 5 6 7 8 9 29 30 31 SCLK Command SI 24 Bit Address 23 22 D8 2 0 1 MSB Note: BE command is D8(hex). Figure 18. Chip Erase (CE) Sequence (Command 60 or C7) CS# 0 1 2 3 4 5 6 7 SCLK Command SI 60 or C7 Note: CE command is 60(hex) or C7(hex). Figure 19. Page Program (PP) Sequence (Command 02) CS# 0 1 2 3 4 5 6 7 8 9 10 28 29 30 31 32 33 34 35 36 37 38 39 SCLK 1 0 7 6 5 3 2 1 0 287 2 286 3 285 23 22 21 02 SI Data Byte 1 284 24-Bit Address 283 Command 4 1 0 MSB MSB 282 281 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 280 CS# SCLK Data Byte 2 SI 7 6 MSB P/N: PM1573 5 4 3 2 Data Byte 32 Data Byte 3 1 0 7 6 5 4 MSB 3 2 1 0 7 6 5 4 3 2 MSB 30 REV. 1.1, DEC. 29, 2011 MX25L5121E MX25L1021E Figure 20. Deep Power Down (DP) Sequence (Command B9) CS# 0 1 2 3 4 5 6 tDP 7 SCLK Command B9 SI Deep Power Down Mode Standby Mode Figure 21. Release from Deep Power Down (RDP) Sequence (Command AB) CS# 0 1 2 3 4 5 6 tRES1 7 SCLK Command SI SO AB High-Z Deep Power Down Mode P/N: PM1573 31 Standby Mode REV. 1.1, DEC. 29, 2011 MX25L5121E MX25L1021E Figure 23. Power-Up Timing VCC VCC(max) Chip Selection is Not Allowed VCC(min) tVSL Device is fully accessible time Note: VCC (max.) is 3.6V and VCC (min.) is 3.0V. Table 9. Power-Up Timing Symbol tVSL(1) Parameter VCC(min) to CS# low Min. 300 Max. Unit us Note: 1. The parameter is characterized only. INITIAL DELIVERY STATE The device is delivered with the memory array erased: all bits are set to 1 (each byte contains FFh). The Status Register contains 00h (all Status Register bits are 0). P/N: PM1573 32 REV. 1.1, DEC. 29, 2011 MX25L5121E MX25L1021E OPERATING CONDITIONS At Device Power-Up and Power-Down AC timing illustrated in Figure 24 and Figure 25 are for the supply voltages and the control signals at device powerup and power-down. If the timing in the figures is ignored, the device will not operate correctly. During power-up and power-down, CS# needs to follow the voltage applied on VCC to keep the device not to be selected. The CS# can be driven low when VCC reach Vcc(min.) and wait a period of tVSL. Figure 24. AC Timing at Device Power-Up VCC VCC(min) GND tVR tSHSL CS# tSLCH tCHSL tSHCH tCHSH SCLK tDVCH tCHCL tCHDX LSB IN MSB IN SI High Impedance SO Symbol tVR tRH tCLCH Parameter VCC Rise Time Reset High Time Before Read Notes 1 Min. 10 5 Max. 500000 Unit us/V ms Notes : 1. Sampled, not 100% tested. 2. For AC spec tSLCH, tDVCH, tCHDX, tCHSH in the figure, please refer to "AC CHARACTERISTICS" table. P/N: PM1573 33 REV. 1.1, DEC. 29, 2011 MX25L5121E MX25L1021E Figure 25. Power-Down Sequence During power-down, CS# needs to follow the voltage drop on VCC to avoid mis-operation. VCC CS# SCLK P/N: PM1573 34 REV. 1.1, DEC. 29, 2011 MX25L5121E MX25L1021E ERASE AND PROGRAMMING PERFORMANCE Parameter Min. Typ. (1) Max. (2) Unit Sector Erase Time 90 300 ms Block Erase Time 1 2 s 1 2 s 1.5 3 s 180 650 us Chip Erase Time 512Kb 1Mb Page Program Time Erase/Program Cycle 100,000 cycles Note: 1. Typical program and erase time assumes the following conditions: 25C, 3.3V, and checker board pattern. 2. Under worst conditions of 70C and 2.7V. 3. System-level overhead is the time required to execute the first-bus-cycle sequence for the programming command. 4. Erase/Program cycles comply with JEDEC JESD-47E & A117A standard. DATA RETENTION Parameter Condition Min. Data retention 70C 20 Max. Unit years LATCH-UP CHARACTERISTICS Min. Max. Input Voltage with respect to GND on all power pins, SI, CS# -1.0V 2 VCCmax Input Voltage with respect to GND on SO -1.0V VCC + 1.0V -100mA +100mA Current Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time. P/N: PM1573 35 REV. 1.1, DEC. 29, 2011 MX25L5121E MX25L1021E ORDERING INFORMATION 512Kb CLOCK (MHz) TEMPERATURE PACKAGE MX25L5121EMC-20G 45 0C~70C 8-SOP (150mil) MX25L5121EOC-20G 45 0C~70C 8-TSSOP (173mil) MX25L5121EZUC-20G 45 0C~70C 8-USON (2x3mm) CLOCK (MHz) TEMPERATURE PACKAGE 45 0C~70C 8-SOP (150mil) PART NO. Remark 1Mb PART NO. MX25L1021EMC-20G P/N: PM1573 36 Remark REV. 1.1, DEC. 29, 2011 MX25L5121E MX25L1021E PART NAME DESCRIPTION MX 25 L 1021E M C 20 G OPTION: G: RoHS Compliant SPEED: 20: 45MHz TEMPERATURE RANGE: C: Commercial (0C to 70C) PACKAGE: M: 150mil 8-SOP O: 173mil 8-TSSOP ZU: 2x3mm 8-USON DENSITY & MODE: 5121E: 512Kb 1021E: 1Mb TYPE: L: 3V DEVICE: 25: Serial Flash P/N: PM1573 37 REV. 1.1, DEC. 29, 2011 MX25L5121E MX25L1021E PACKAGE INFORMATION P/N: PM1573 38 REV. 1.1, DEC. 29, 2011 MX25L5121E MX25L1021E P/N: PM1573 39 REV. 1.1, DEC. 29, 2011 MX25L5121E MX25L1021E P/N: PM1573 40 REV. 1.1, DEC. 29, 2011 MX25L5121E MX25L1021E REVISION HISTORY Revision No. Description 0.01 1. Corrected 25L5121 ID code 2. Added VWI into table 7 3. Modified ISB1, ISB2, ICC1, ICC2 & ICC4 4. Modified tDVCH, tCHDX & tCLQV 5. Modified EPN Page P12 P22 P4,22,36 P23 P36,37 1.0 1. Removed "Advanced Information" 2. Modified Chip Erase time (1Mb) 3. Modified "At Device Power-Up and Power-Down" description 4. Modified ILO test conditions from VIN to VOUT 5. Added 8-USON package information P4 NOV/02/2011 P23,35 P33 P22 P5,6,36,37,40 1.1 Removed "Advanced Information". Modified Storage Temperature to "-65C to 150C" P5,6,36,37 P20 P/N: PM1573 41 Date APR/07/2010 DEC/29/2011 REV. 1.1, DEC. 29, 2011 MX25L5121E MX25L1021E Except for customized products which has been expressly identified in the applicable agreement, Macronix's products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only, and not for use in any applications which may, directly or indirectly, cause death, personal injury, or severe property damages. In the event Macronix products are used in contradicted to their target usage above, the buyer shall take any and all actions to ensure said Macronix's product qualified for its actual use in accordance with the applicable laws and regulations; and Macronix as well as it's suppliers and/or distributors shall be released from any and all liability arisen therefrom. Copyright(c) Macronix International Co., Ltd. 2010~2011. All rights reserved. Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, NBit, NBiit, Macronix NBit, eLiteFlash, XtraROM, Phines, BE-SONOS, KSMC, Kingtech, MXSMIO, Macronix vEE are trademarks or registered trademarks of Macronix International Co., Ltd. The names and brands of other companies are for identification purposes only and may be claimed as the property of the respective companies. For the contact and order information, please visit Macronix's Web site at: http://www.macronix.com MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. 42