www.power.com September 2015
Energy-Efcient, Accurate Primary-Side Regulation
CC/CV Switcher for LED Lighting Applications
LYT2002-2005
LYTSwitch-2 Family
This Product is Covered by Patents and/or Pending Patent Applications.
Output Power Table2
Product5
90-308 VAC
Enclosed Bulb3Ballast Driver4
LYT2002D 5 W 6 W
LY T20 03 D 6 W 7 W
LY T20 04 D 7 W 8 W
LY T20 04 E/K 9 W 10 W
LYT2005E/K 10 W 12 W
Table 1. Output Power Table.
Notes:
1. Nominal input and bias supply applied to BYPASS pin.
2. Performance for typical design.
3. Maximum continuous power in a typical non-ventilated bulb measured at +50
°C ambient, device TJ ≤ 100 °C.
4. Maximum practical continuous power in an open frame design with adequate
heat sinking, measured at +50 °C.
5. Packages: D: SO-8C, E: eSIP-7C, K: eSOP-12B.
Product Highlights
Accurate CC Regulation, Meets ±3% in a Typical
Design1
Controller Automatically Compensates For:
• Transformer inductance variation
• External component changes with temperature
• Input line voltage variations
This enhances production yield
Cost-Effective, Small Size Designs
• Eliminates the optocoupler and secondary CC control circuitry
• Eliminates control loop compensation circuitry
• Frequency-jitter greatly reduces EMI lter cost
• Programmable switching frequency reduces transformer size
• 725 V switching power MOSFET enables clampless yback designs
Advanced Protection/Safety Features
• Auto-restart protection reduces power delivered by >90% for output
short-circuit and control loop faults (open and short-circuit components)
• Hysteretic thermal shutdown – with automatic recovery
• Meets high-voltage creepage requirements between DRAIN and all
other pins both on the PCB and at the package
EcoSmart™– Energy Efcient
• No-load consumption <30 mW1
• No current sense resistors – maximizes efciency
Green Package
• All parts are halogen free and RoHS compliant
Applications
• LED bulbs, down lights, luminaires, ballasts and T8 tubes
Description
The LYTSwitch™-2 family of ICs dramatically simplies low power CC
LED drivers by eliminating the optocoupler and secondary control
circuitry. The family introduces a revolutionary control technique which
provides accurate output current regulation, compensating for
transformer and external component variations, and device parameter
tolerances as well as input voltage variations.
The device incorporates a high-voltage switching MOSFET, an ON/OFF
control state-machine, a high-voltage switched current source for
self-biasing, frequency jitter to reduce EMI, cycle-by-cycle current limit
and hysteretic thermal shutdown circuitry into a monolithic IC. This high
level of integration enables cost-effective designs with very few
external components, reducing solution cost and driver size.
LYTSwitch-2 parts minimize energy consumption when the output is
unloaded. Practical designs can easily achieve less than 30 mW
no-load consumption.
The 725 V power MOSFET used in LYTSwitch-2 devices increases the
circuits’ ability to withstand input surge. In addition, each package is
designed to maximize the creepage distance between high-voltage pins
and logic level inputs. This increased pin spacing increases driver
lifetime and reliability in polluted environments. These in-built protec-
tion features also protect the entire circuit from excess temperature
operation, increasing lifetime in thermally challenging environments.
Figure 1. Typical Flyback Implementation – Not a Simplied Circuit.
LYTSwitch-2
PI-7037a-051914
D
S
FB
BP
AC
IN
Rev. B 09/15
2
LYT2002-2005
www.power.com
Pin Functional Description
DRAIN (D) Pin:
Power MOSFET drain connection. It also provides internal
operating current during start-up and in steady-state operation.
BYPASS (BP) Pin:
Connection point for the external 1 mF bypass capacitor connected to
the internally generated 6 V supply.
FEEDBACK (FB) Pin:
Controls switching of the power MOSFET during normal opera-
tion. This pin senses the AC voltage on the bias winding.
Input is used to regulate both the output voltage in CV mode
and output current in CC mode based on voltage across the
bias winding in the yback portion of the switching cycle. The
internal inductance correction circuit uses voltage on the bias
winding during forward part of the switching cycle to sense the
bulk capacitor voltage.
SOURCE (S) Pin:
Connected to the MOSFET source and is used for high-voltage
power and control circuit common returns.
Figure 2. Functional Block Diagram.
Figure 3. Pin Conguration.
PI-7302-061214
SOURCE
(S)
LEADING
EDGE
BLANKING
+
-
+
-
+
-
DRAIN
(D)
REGULATOR
6 V
BYPASS
(BP)
FEEDBACK
(FB)
SOURCE
(S)
FB
OUT Reset
6 V
5 V
tSAMPLE-OUT
tSAMPLE-INPUT
VILIMIT
ILIM
VTH
tSAMPLE-INPUT
tSAMPLE-OUT
VILIMIT
6.5 V
Drive
ILIM
DCMAX
DCMAX
FB
Current Limit
Comparator
STATE
MACHINE
SAMPLE
DELAY
THERMAL
SHUTDOWN
OSCILLATOR
FAULT
AUTO-RESTART
OPEN-LOOP
INDUCTANCE
CORRECTION
CONSTANT
CURRENT
D Q
12 S
11 S
10 S
9 S
8 S
7 S
FB 1
BP 2
NC 3
NC 4
D 6
PI-6906-051614
Exposed Pad
(On Back Side)
Internally
Connected to
SOURCE Pin
1
E Package
(eSIP-7C)
K Package
(eSOP-12B)
Exposed Pad (On Bottom)
Internally Connected to
SOURCE Pin
2
BP
FB
3
NC
4
NC
5
S
7
D
D Package (SO-8C)
FB 1
BP 2
D 4
8 S
7 S
6 S
5 S
Rev. B 09/15
3
LYT2002-2005
www.power.com
LYTSwitch-2 Functional Description
The LYTSwitch-2 IC combines a high-voltage power MOSFET switch
with a power supply controller in one device. Similar to the
LinkSwitch™-LP and TinySwitch™-III ICs it uses an ON/OFF control to
regulate the output voltage. In addition, the switching frequency is
modulated to regulate the output current to provide a constant current
characteristic. The LYTSwitch-2 controller consists of an oscillator,
feedback (sense and logic) circuit, 6 V regulator, over-temperature
protection, frequency jittering, current limit circuit, leading-edge
blanking, inductance correction circuitry, frequency control for
constant current regulation and ON/OFF state-machine for CV control.
Inductance Correction Circuitry
If the primary magnetizing inductance is either too high or low the
converter will automatically compensate for this by adjusting the
oscillator frequency. Since this controller is designed to operate in
discontinuous-conduction mode the output power is directly propor-
tional to the set primary inductance and its tolerance can be completely
compensated with adjustments to the switching frequency.
Constant Current (CC) Operation
As the output voltage and therefore the yback voltage across the
bias winding ramps up, the FEEDBACK pin voltage increases. The
switching frequency is adjusted as the FEEDBACK pin voltage increases
to provide a constant output current regulation. The constant current
circuit and the inductance correction circuit are designed to operate
concurrently in the CC region.
Constant Voltage (CV) Operation
As the FEEDBACK pin approaches 2 V from the constant current
regulation mode, the power supply transitions into CV operation.
The switching frequency at this point is at its maximum value,
corresponding to the peak power point of the CV/CC characteristic.
The controller regulates the FEEDBACK pin voltage to remain at
FEEDBACK pin threshold (VFBTH) using an ON/OFF state-machine.
The FEEDBACK pin voltage is sampled 2.5 ms after the turn-off of the
high-voltage switch. At light loads the current limit is also reduced to
decrease the transformer ux density and the FEEDBACK pin
sampling is done earlier.
Auto-Restart and Open-Loop Protection
In the event of a fault condition such as an output short or an
open-loop condition the LYTSwitch-2 IC enters into an appropriate
protection mode.
In the event the FEEDBACK pin voltage during the yback period falls
below 0.7 V before the FEEDBACK pin sampling delay (~2.5 ms) for a
duration in excess of ~450 ms (auto-restart on-time (tAR-ON) the
converter enters into auto-restart, wherein the power MOSFET is
disabled for 1.2 seconds. The auto-restart alternately enables and
disables the switching of the power MOSFET until the fault condition
is removed.
In addition to the conditions for auto-restart described above, if the
sensed FEEDBACK pin current during the forward period of the
conduction cycle (switch “on” time) falls below 120 mA, the converter
annunciates this as an open-loop condition (top resistor in potential
divider is open or missing) and reduces the auto-restart time from
450 ms to approximately 6 clock cycles (90 ms), whilst keeping the
disable period of 2 seconds.
Over-Temperature Protection
The thermal shutdown circuitry senses the die temperature. The
threshold is set at 142 °C typical with a 60 °C hysteresis. When the
die temperature rises above this threshold (142 °C) the power
MOSFET is disabled and remains disabled until the die temperature
falls by 60 °C, at which point the MOSFET is re-enabled.
Current Limit
The current limit circuit senses the current in the power MOSFET.
When this current exceeds the internal threshold (ILIMIT), the power
MOSFET is turned off for the remainder of that cycle. The leading
edge blanking circuit inhibits the current limit comparator for a short
time (tLEB) after the power MOSFET is turned on. This leading edge
blanking time has been set so that current spikes caused by capaci-
tance and rectier reverse recovery time will not cause premature
termination of the MOSFET conduction. The LYTSwitch-2 IC also
contains a “di/dt” correction feature to minimize CC variation across the
input line range.
6 V Regulator
The 6 V regulator charges the bypass capacitor connected to the
BYPASS pin to 6 V by drawing a current from the voltage on the
DRAIN pin, whenever the MOSFET is off. The BYPASS pin is the
internal supply voltage node. When the MOSFET is on, the device
runs off of the energy stored in the bypass capacitor. Extremely low
power consumption of the internal circuitry allows the LYTSwitch-2 IC
to operate continuously from the current drawn from the DRAIN pin.
A bypass capacitor value of 1 mF is sufcient for both high frequency
decoupling and energy storage.
Rev. B 09/15
4
LYT2002-2005
www.power.com
Applications Example
Circuit Description
This circuit shown in Figure 4 is congured as a primary-side
regulated yback power supply utilizing the LYT2004E from the
LYTSwitch-2 family of ICs. This type of LED driver design is typical
for an external ballast application where safety isolation is required
while power factor correction is not. The output can drive an LED
load from 48 V to 22 V with a constant output current of 180 mA ±5%
across input range of 90 VAC to 265 VAC and ambient temperature
range of 0 ºC to 60 ºC. It has an average efciency of >86% and
<30 mW no-load input power measured at nominal input voltages
(i.e. 115 VAC and 230 VAC). This design easily meets the most
stringent current energy efciency requirements.
Input Filter
AC input power is rectied by bridge diode BR1. The rectied DC is
ltered by the bulk storage capacitors C1 and C2. Inductor L1, L2,
C1 and C2 form a pi (π) lter, which attenuates conducted differen-
tial-mode EMI. Resistors R1 and R2 placed across the inductors
damp the Q to improve frequency noise ltering without reducing low
frequency noise attenuation. A small value Y capacitor (C7) across
the transformer was used to reducer common-mode noise currents.
The fuse F1 provides protection against catastrophic failure. This
can be replaced by a fusible resistor for cost reduction but should be
suitably rated (and typically a wire wound type) to withstand the
instantaneous dissipation experienced during input capacitor charging
when rst connected to the AC line.
LYT2004 Primary
The LYTSwitch-2 family (U1) incorporates the power switching device,
oscillator, CC/CV control engine, start-up, and protection functions.
The integrated 725 V power MOSFET provides a large drain voltage
margin in universal input AC applications, increasing reliability and
also reducing the output diode voltage stress by permitting the use of
higher transformer turns ratios. The device is completely self-
powered from the BYPASS pin and decoupling capacitor C4.
The optional bias supply formed by D2 and C5 and R6 provides
operating current to U1 via resistor R9. This reduces the no-load
consumption from 200 mW to less than 30 mW. The bias supply also
increases light load efciency.
The rectied and ltered input voltage is applied to one side of the
primary winding of T1. The other side of the transformer’s primary
winding is driven by the integrated power MOSFET in U1. The
leakage inductance drain voltage spike is limited by an RCD-R clamp
consisting of D1, R3, R4, R5, and C3.
Output Rectication
The output from the transformer is rectied by D3, a 1 A, 400 V
ultrafast recovery type diode (for higher efciency), and ltered by
C6. In this application C6 was sized to meet a (typical) ripple
requirement of less than 10% without the need for an additional LC
post lter.
PI-7280-051414
D
S
FB
BP
L1
3.9 mH
C1
12 µF
400 V
C4
1 µF
50 V
C5
1 µF
50 V
C2
12 µF
400 V
C6
100 µF
63 V
C7
1 nF
500 V
U1
LYT2004E
LYTSwitch-2
C3
470 pF
1 kV
R2
3.9 kΩ
1/8 W
R5
560 Ω
R4
560 Ω
R8
6.98 kΩ
1%
1/8 W
R9
12 kΩ
1/8 W
R7
60.4 kΩ
1%
1/8 W
R6
2 Ω
1/8 W
T1
EE19
9
5
10
1
2
R10
1.2 MΩ
D1
S1ML
D2
BAV21W-7-F
4
D3
US1G
R3
220 kΩ
L2
3.9 mH
22 V - 48 V,
180 mA
TP3
RTN
TP4
R1
3.9 kΩ
1/8 W
F1
2 A
90 - 265
VAC
L
TP1
N
TP2
BR1
B10S-G
1000 V
Figure 4. Energy Efcient 8.6 W LED Power Supply (>86 % Average Efciency, <30 mW No-load Input Power).
Rev. B 09/15
5
LYT2002-2005
www.power.com
A pre-load resistor R10 was employed to discharge the output
capacitor and extinguish the LED light immediately after turn-off. The
resistor will also keep the output from rising higher than the permitted
maximum output voltage (usually determined by the output capacitor
voltage rating) when the load is disconnected.
Output Regulation
The LYTSwitch-2 family regulates the output using ON/OFF control in
the constant voltage (CV) regulation region of the output characteris-
tic and frequency control for the constant current (CC) region. The
feedback resistors (R7 and R8) were selected using standard 1%
resistors to center both the nominal output voltage and constant
current regulation thresholds. Resistor R6 acts as lter to limit the
voltage spike (caused by the coupling of the bias winding to the
primary winding), improving regulation.
Key Application Considerations
Output Power Table
The data sheet maximum output power table (Table 1) represents the
maximum practical continuous output power that can be obtained
under the following assumed conditions:
1. The minimum DC bus voltage is 100 V at 90 VAC input. The value
of the input capacitance should be made large enough to meet
this requirement for AC input designs – typically 2-3 mF/W for
low-line or universal input designs and 1-2 mF/W for high-line input
designs.
2. The secondary output rectier diode should withstand peak
inverse voltage (PIV) for 55 V output voltage for open load
condition.
3. Assume efciency of >80%.
4. Discontinuous mode operation (KP >1.3).
5. The LYTSwitch-2 part is either board mounted with SOURCE pins
soldered to a sufcient area of copper to keep the SOURCE pin
temperature at or below 100 °C, or (in the case of the E package)
attached to a sufciently sized heat sink to limit device tempera-
ture to below 110 °C.
6. Ambient temperature of less than 50 °C for open frame designs
and an internal enclosure temperature of 60 °C for enclosed
ballast-type designs.
Note: Higher output powers are achievable if an output CC tolerance
> ±10% is acceptable, and allowing the device to be operated at a
higher SOURCE pin temperature.
Output Tolerance
LYTSwitch-2 K and E package parts provides an overall CC mode
output current tolerance of ±5% including line voltage, normal
board-to-board component variation and across a temperature range
of 0 °C to 110 °C. For the D package (SO-8) additional CC variance
may occur due to stress caused by manufacturing (i.e. solder-wave
immersion or IR reow).
A sample power supply build is recommended to verify production
tolerances for each design.
BYPASS Pin Capacitor Selection
A 1 mF BYPASS pin capacitor is recommended. The capacitor voltage
rating should be greater than 7 V. The capacitor can be ceramic or
electrolytic but tolerance of capacitor should be ≤ ±50%. The
capacitor must be physically located close to the LYTSwitch-2 BYPASS
pin for effective noise decoupling.
LYTSwitch-2 Layout Considerations
Circuit Board Layout
The LYTSwitch-2 family of ICs present a highly integrated power
supply solution that integrates, both, the controller and the high-
voltage power MOSFET onto a single die. The presence of high
switching currents and voltages together with analog signals makes
it especially important to follow good PCB design practice to ensure
stable and trouble free operation of the power supply. See Figures 5
and 6 for a recommended circuit board layout for LYTSwitch-2.
When designing a printed circuit board layout for the LYTSwitch-2 based
power supply, it is important to follow these guidelines:
Single Point Grounding
Use a single point (Kelvin) connection at the negative terminal of the
input lter capacitor for the LYTSwitch-2 SOURCE pin and bias
winding return. This improves surge capabilities by returning surge
currents from the bias winding directly to the input lter capacitor.
Bypass Capacitor
The BYPASS pin capacitor should be located as close as possible to
the SOURCE and BYPASS pins for effective noise decoupling.
Feedback Resistors
Place the feedback resistors (R7 and R8) very close to the FEEDBACK
pin of the LYTSwitch-2 device. This minimizes noise coupling.
Thermal Considerations (D and K Package)
The copper area connected to the SOURCE pins provides heat sinking.
A good estimate of expected power dissipation is to assume is that
the LYTSwitch-2 will dissipate 5% of the output power. Provide
enough copper area to keep the SOURCE pin temperature below
100 °C. Higher temperatures are allowable but output current (CC)
tolerance will increase. In this case a maximum SOURCE pin tempera-
ture below 100 °C is recommended to provide margin for part-to-part
RDS(ON) variation.
Secondary Loop Area
To minimize leakage inductance and EMI the area of the loop
contained within the connections between the secondary winding
(T1), the output diode (D3) and the output lter capacitor (C6) should
be minimized. In addition, sufcient copper area should be to the
rectier diode for heat sinking preferably connected to the quiet
cathode terminal. A large anode area can increase high frequency
radiated EMI.
Electrostatic Discharge Spark Gap
A trace is placed at one of the AC line inputs to form one electrode of
a spark gap. The other electrode on the secondary is formed by the
output return node. The spark gap directs most ESD energy from the
secondary back to the AC input during a surge event. The trace from
the AC input to the spark gap electrode should be spaced away from
other traces to prevent unwanted arcing occurring and possible circuit
damage. If R1 and R2 are removed additional spark gaps across the
EMI lter inductors (L1 and L2) to prevent excessive build-up of
voltage across them during surge.
Rev. B 09/15
6
LYT2002-2005
www.power.com
Figure 5. PCB Layout Example using SO-8C Package. Figure 6. PCB Layout Example using eSIP Package.
Drain Clamp Optimization
LYTSwitch-2 ICs use primary-side sensing to regulate the output.
The voltage that appears on the primary winding is a reection of the
secondary winding voltage while the internal is off. Leakage inductance
induced ringing can affect output regulation. Optimizing the drain
clamp to minimize high frequency ringing will give the best regulation.
Figure 7 shows the desired drain voltage waveform; while Figure 8
shows a large undershoot due to a leakage inductance induced ring.
Ringing can be reduced (and hence regulation improved) by adjusting
the value of the resistor in series with the primary clamp diode.
Addition of a Bias Circuit for Higher Light Load Efciency and
Lower No-load Input Power Consumption
The addition of a bias circuit can decrease the no-load input power
from ~200 mW to less than 30 mW at 230 VAC input.
The power supply schematic shown in Figure 4 has the bias circuit
incorporated. Diode D2, C5 and R9 form the bias circuit.
Diode D2 recties the output and C5 is the lter capacitor. A 1 mF
capacitor is recommended to maintain the minimum bias voltage at
low switching frequencies.
The recommended current into the BYPASS pin is equal to IC supply
current (~0.5 mA) at the minimum bias winding voltage. The BYPASS
pin current should not exceed 3 mA at the maximum bias winding
voltage. The value of R9 is calculated according to (VBIAS-VBP)/IS2,
where VBIAS (10 V typical) is the voltage across C5, IS2 (0.5 mA typ.) is
the IC supply current and VBP (6.2 V typ.) is the BYPASS pin voltage.
The parameters IS2 and VBP are provided in the parameter table of the
LYTSwitch-2 data sheet. Diode D2 can be a low-cost type such as
FR102, 1N4148 or BAV19/20/21.
Quick Design Checklist
As with any power supply design, all LYTSwitch-2 family designs should
be veried on the bench to make sure that component specications
are not exceeded under worst-case conditions. The following set of
tests is strongly recommended:
1. Maximum drain voltage – Verify that the peak VDS does not
exceed 680 V at the highest input voltage and maximum output
power.
2. Drain current – At maximum ambient temperature, maximum and
minimum input voltage and maximum output load, review drain
current waveforms at start-up for any signs of transformer
saturation or excessive leading edge current spikes. LYTSwitch-2
devices have a leading edge blanking time to prevent premature
termination of the ON-cycle, but limit leading edge spikes to less
than the maximum time as specied in the data sheet.
3. Thermal check – At maximum output power, for both minimum
and maximum input voltage and maximum ambient temperature;
verify that temperature limits are not exceeded for LYTSwitch-2,
transformer, output diodes and output capacitors. Thermal
margin should be provided to allow for part-to-part variation in the
RDS(ON) of the LYTSwitch-2 device. For optimum regulation, a
SOURCE pin temperature of 90 ºC is recommended.
Design Tools
Up-to-date information on design tools can be found at the Power
Integrations web site: www.power.com
Rev. B 09/15
7
LYT2002-2005
www.power.com
Figure 9. Example Schematic of LYTSwitch-2 Flyback Power Supply without Bias Supply.
Figure 7. Desired Drain Voltage Waveform with Minimal Leakage Ringing
Undershoot.
Figure 8. Undesirable Drain Voltage Waveform with Large Leakage Ring
Undershoot.
PI-7284-043014
D
S
FB
BP
L1
470 µH
C1
4.7 µF
400 V
C4
1 µF
50 V
C2
33 µF
400 V
C6
100 µF
100 V
C7
1 nF
500 VAC
U1
LYT2005E
LYTSwitch-2
C3
1000 pF
630 V
R4
100 Ω
R8
8.06 kΩ
1%
1/8 W
R7
140 kΩ
1%
1/8 W
T1
EE19
9
5
10
NC
1
2
R10
130 kΩ
D1
S1ML
4
D3
UF5404
R2
220 kΩ48 V
J5
RTN
J6
R1
10 kΩ
1/8 W
F1
2 A
90 - 265
VAC
L
J2
N
J1
BR1
B10S-G
1000 V
Negative ring may increase
output ripple and/or degrade
output regulation
An overshoot is acceptable
Rev. B 09/15
8
LYT2002-2005
www.power.com
Parameter Symbol
Conditions
SOURCE = 0 V; TJ = 0 to 100 °C
(Unless Otherwise Specied)
Min Typ Max Units
Control Functions
Programmable
Maximum Frequency fOSC
TJ = 25 °C
tON × IFB = 1.4 mA-ms
See Note A
VFB = VFBth 85 kHz
Minimum Operation
Frequency fOSC(MIN)
TJ = 25 °C
VFB = VFBth
LYT2002-2003 300 330 365
HzLYT2004 775 850 930
LYT2005 510 580 645
Frequency Ratio
(Constant Current) fRAT IO(CC)
TJ = 25 °C
Between VFB = 1.0 V and VFB = 1.6 V 1.550 1.593 1.635
Frequency Ratio
(Inductance
Correction)
fRATIO(IC)
Between tON × IFB = 1.4 mA and
tON × IFB = 2 mA-ms 1.160 1.210 1.260
Frequency Jitter Peak-to-Peak Jitter Compared to Average
Frequency, TJ = 25 °C ±7 %
Absolute Maximum Ratings(1,6)
DRAIN Voltage .........................................................-0.3 V to 725 V
DRAIN Pin Peak Current(5): LYT2002 ......................... 504 (750) mA(2)
LYT2003 ......................... 654 (980) mA(2)
LYT2004 ........................ 686 (1029) mA(2)
LYT2005 ........................ 784 (1176) mA(2)
Peak Negative Pulsed Drain Current .................................. -100 mA(3)
FEEDBACK Pin Voltage ................................................... -0.3 to 9 V
FEEDBACK Pin Current .........................................................100 mA
BYPASS Pin Voltage ........................................................ -0.3 to 9 V
Storage Temperature ................................................. -65 to 150 °C
Operating Junction Temperature(4) ............................... -40 to 150 °C
Lead Temperature(5) .............................................................. 260 °C
Notes:
1. All voltages referenced to SOURCE, TA = 25 °C.
2. Higher peak Drain current allowed while Drain to Source
voltage does not exceed 400 V.
3. Duration not to exceed 2 ms.
4. Normally limited by internal circuitry.
5. 1/16 in. from case for 5 seconds.
6. Absolute Maximum Ratings specied may be applied, one
at a time without causing permanent damage to the
product. Exposure to Absolute Maximum Ratings for
extended periods of time may affect product reliability.
Thermal Resistance
Thermal Resistance: D Package:
(qJA) ......................................100 °C/W(2), 80 °C/W(3)
(qJC)(1) .........................................................30 °C/W
E Package
(qJA) .............................................. 105 °C/W(4)
(qJC) ..................................................2 °C/W(5)
K Package
(qJA) .............................. 45 °C/W(6), 38 °C/W(7)
(qJC) ..................................................2 °C/W(5)
Notes:
1. Measured on pin 8 (SOURCE) close to plastic interface.
2. Soldered to 0.36 sq. in. (232 mm2), 2 oz. (610 g/m2) copper clad.
3. Soldered to 1 sq. in. (645 mm2), 2 oz. (610 g/m2) copper clad.
4. Free standing with no heat sink.
5. Measured at the back surface of tab.
6. Soldered (including exposed pad for K package) to typical
application PCB with a heat sinking area of 0.36 sq. in.
(232 mm2), 2 oz. (610 g/m2) copper clad.
7. Soldered (including exposed pad for K package) to typical
application PCB with a heat sinking area of 1 sq. in. (645 mm2),
2 oz. (610 g/m2) copper clad.
Rev. B 09/15
9
LYT2002-2005
www.power.com
Parameter Symbol
Conditions
SOURCE = 0 V; TJ = 0 to 100 °C
(Unless Otherwise Specied)
Min Typ Max Units
Control Functions (cont.)
Maximum Duty Cycle DCMAX See Notes D, E 55 %
FEEDBACK Pin Voltage VFB(TH) CBP = 1 mF
TJ = 25 °C1.915 1.940 1.965
V
TJ = 100 °C
See Note E 1.90 1.94 1.98
FEEDBACK Pin Voltage at
Turn-Off Threshold VFB(AR) 0.69 0.75 0.81 V
Minimum Switch
ON-Time tON(MIN) See Note E 700 ns
FEEDBACK Pin
Sampling Delay tFB TJ = 25 °C2.35 2.55 2.75 ms
DRAIN Pin
Supply Current
IS1
FB Voltage > VFBth
(MOSFET Not Switching) 320 370 mA
IS2
FB Voltage = VFBth
-0.1 V,
Switch ON-Time =
tON (MOSFET
Switching at fOSC)
LYT2002 500 560
mA
LYT2003 550 600
LYT2004 600 680
LYT2005 700 800
BYPASS Pin
Charge Current
ICH1 VBP = 0 V
LYT2002 -7.0 -4.8 -2.5
mA
LYT2003 -7. 2 -5.8 -3.2
LYT2004 -8.5 -6.3 -3.2
LYT2005 -8.5 -6.3 -3.2
ICH2 VBP = 4 V
LYT2002 -5.6 -3.2 -1.4
LYT2003 -5.6 -4.0 -2.0
LYT2004 -6.0 -4.4 -2.0
LYT2005 -6.0 -4.4 -2.0
BYPASS Pin
Voltage VBP 5.65 5.9 6.25 V
BYPASS Pin
Voltage Hysteresis VBPH 0.70 0.95 1.20 V
BYPASS Pin
Shunt Voltage VSHUNT 6.2 6.4 6.8 V
Rev. B 09/15
10
LYT2002-2005
www.power.com
Parameter Symbol
Conditions
SOURCE = 0 V; TJ = 0 to 100 °C
(Unless Otherwise Specied)
Min Typ Max Units
Circuit Protection
Current Limit ILIMIT
VBP = 5.9 V
TJ = 25 °C
LYT2002D
di/dt = 80 mA/ms293 315 337
mA
LYT2003D
di/dt = 100 mA/ms363 390 417
LYT2004D
di/dt = 105 mA/ms390 420 450
LYT2004E/K
di/dt = 125 mA/ms460 495 530
LYT2005E/K
di/dt = 135 mA/ms511 550 589
Minimum Current Limit
Scale Factor ILIMIT(MIN) TJ = 25 °C0.28 0.32 0.39
Normalized Output
Current IOTJ = 25 °C0.975 1.000 1.025
Leading Edge
Blanking Time tLED
TJ = 25 °C
See Note E 170 215 ns
Thermal Shutdown
Temperature TSD See Note E 135 142 150 °C
Thermal Shutdown
Hysteresis TSDH See Note E 60 °C
Output
ON-State
Resistance RDS(ON)
LYT2002D
ID = 63 mA
TJ = 25 °C13 15.5
W
TJ = 100 °C20 23.5
LYT2003D
ID = 78 mA
TJ = 25 °C 8 9.2
TJ = 100 °C12 14
LYT2004D
ID = 84 mA
TJ = 25 °C 5 5.9
TJ = 100 °C7. 5 8.60
LYT2004E/K
ID = 99 mA
TJ = 25 °C 5 5.9
TJ = 100 °C7. 5 8.60
LYT2005E/K
ID = 110 mA
TJ = 25 °C3.2 3.8
TJ = 100 °C4.6 5.40
Rev. B 09/15
11
LYT2002-2005
www.power.com
NOTES:
A. Auto-restart on-time is a function of switching frequency programmed by tonx IFB and minimum frequency in CC mode.
B. The current limit threshold is compensated to cancel the effect of current limit delay. As a result the output current stays constant across
the input line range.
C. IDSS1 is the worst-case off-state leakage specication at 80% of BVDSS and maximum operating junction temperature. IDSS2 is a typical
specication under worst-case application conditions (rectied 265 VAC) for no-load consumption calculations.
D. When the duty cycle exceeds DCMAX the LYTSwitch-2 operates in on-time extension mode.
E. This parameter is derived from characterization.
Parameter Symbol
Conditions
SOURCE = 0 V; TJ = 0 to 100 °C
(Unless Otherwise Specied)
Min Typ Max Units
Output (cont.)
OFF-State
Leakage
IDSS1
VDS = 560 V
TJ = 125 °C, See Note C 50
mA
IDSS2
V DS = 375 V
TJ = 50 °C15
Breakdown
Voltage BVDSS TJ = 25 °C725 V
DRAIN Pin
Supply Voltage 50 V
Auto-Restart
ON-Time tAR-ON
tON × IFB = 1.4 mAms
fOSC = 12 kHz
VFB = 0
See Notes A, E
100 ms
Auto-Restart
OFF-Time tAR-OFF See Note E 0.32 s
Open-Loop
FEEDBACK Pin
Current Threshold
IOL See Note E -45 mA
Open-Loop
ON-Time See Note E 1.4 ms
Rev. B 09/15
12
LYT2002-2005
www.power.com
1.200
0.600
0.800
1.000
0.200
0.400
0.000
-40 -15 10 35 60 85 110 13
5
Temperature (°C)
Frequency Ratio
(Normalized to 25 °C)
PI-5087-040508
1.200
0.600
0.800
1.000
0.200
0.400
0.000
-40 -15 10 35 60 85 1101
35
Temperature (°C)
Frequency Ratio
(Normalized to 25 °C)
PI-5088-040508
1.200
0.600
0.800
1.000
0.200
0.400
0.000
-40 -15 10 35 60 85 110 135
Temperature (°C)
Feedback Voltage
(Normalized to 25 °C)
PI-5089-040508
Figure 10. Current Limit vs. Temperature. Figure 11. Output Frequency vs. Temperature.
Figure 12. Frequency Ratio vs. Temperature (Constant Current). Figure 13. Frequency Ratio vs. Temperature (Inductor Current).
Figure 14. Feedback Voltage vs. Temperature. Figure 15. Normalized Output Current vs. Temperature.
Typical Performance Characteristics
1.200
0.600
0.800
1.000
0.200
0.400
0.85
-40 -15 10 35 60 85 135110
Temperature (°C)
Current Limit
(Normalized to 25 °C)
PI-7290-050114
1.200
0.600
0.800
1.000
0.200
0.400
0.85
-40 -15 10 35 60 85 135110
Temperature (°C)
Output Frequency
(Normalized to 25 °C)
PI-7291-050214
1.200
0.600
0.800
1.000
0.200
0.400
0.000
-40 -15 10 35 60 85 110 135
Temperature (°C)
Normalized Output Current
(Normalized to 25 °C)
PI-7289-050114
Rev. B 09/15
13
LYT2002-2005
www.power.com
Figure 16. Breakdown vs. Temperature.
Typical Performance Characteristics
1.1
1.0
0.9
-50 -25 0255075 100 125 150
Junction Temperature (°C)
Breakdown Voltage
(Normalized to 25
°C)
PI-2213-012301
Figure 17. Output Characteristic.
Figure 18. COSS vs. Drain Voltage. Figure 19. Drain Capacitance Power.
DRAIN Voltage (V)
Drain Current (mA)
300
250
200
100
50
150
0
0 2 4 6 8 10
TCASE=25 °C
TCASE=100 °C
PI-7285-091715
LYT2002 1.5
LYT2003 2.6
LYT2004 4.1
LYT2005 6.7
Scaling Factors:
30
15
20
25
5
10
0
0 200 300100 400 500 600
DRAIN Voltage (V)
Power (mW)
PI-7286-091715
LYT2002 1.5
LYT2003 2.6
LYT2004 4.1
LYT2005 6.7
Scaling Factors:
Drain Voltage (V)
Drain Capacitance (pF)
PI-7287-091715
0 100 200 300 400 500 600
1
10
100
1000
LYT2002 1.5
LYT2003 2.6
LYT2004 4.1
LYT2005 6.7
Scaling Factors:
Rev. B 09/15
14
LYT2002-2005
www.power.com
PI-4526-040110
D07C
3.90 (0.154) BSC
Notes:
1. JEDEC reference: MS-012.
2. Package outline exclusive of mold flash and metal burr.
3. Package outline inclusive of plating thickness.
4. Datums A and B to be determined at datum plane H.
5. Controlling dimensions are in millimeters. Inch dimensions
are shown in parenthesis. Angles in degrees.
0.20 (0.008) C
2X
14
5
8
26.00 (0.236) BSC
D
4
A
4.90 (0.193) BSC
2
0.10 (0.004) C
2X
D
0.10 (0.004) C2X
A-B
1.27 (0.050) BSC
7X 0.31 - 0.51 (0.012 - 0.020)
0.25 (0.010) MC A-B D
0.25 (0.010)
0.10 (0.004)
(0.049 - 0.065)
1.25 - 1.65
1.75 (0.069)
1.35 (0.053)
0.10 (0.004) C
7X
C
H
o
1.27 (0.050)
0.40 (0.016)
GAUGE
PLANE
0 - 8
1.04 (0.041) REF 0.25 (0.010)
BSC
SEATING
PLANE
0.25 (0.010)
0.17 (0.007)
DETAIL A
DETAIL A
C
SEATING PLANE
Pin 1 ID
B
4
+
++
4.90 (0.193)
1.27 (0.050) 0.60 (0.024)
2.00 (0.079)
Reference
Solder Pad
Dimensions
+
SO-8C (D Package)
Rev. B 09/15
15
LYT2002-2005
www.power.com
PI-4917-061510
MOUNTING HOLE PATTERN
(not to scale)
PIN 7
PIN 1
0.100 (2.54) 0.100 (2.54)
0.059 (1.50)
0.059 (1.50)
0.050 (1.27)
0.050 (1.27)
0.100 (2.54)
0.155 (3.93)
0.020 (0.50)
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimensions noted are determined at the outermost
extremes of the plastic body exclusive of mold flash,
tie bar burrs, gate burrs, and interlead flash, but including
any mismatch between the top and bottom of the plastic
body. Maximum mold protrusion is 0.007 [0.18] per side.
3. Dimensions noted are inclusive of plating thickness.
4. Does not include inter-lead flash or protrusions.
5. Controlling dimensions in inches (mm).
0.403 (10.24)
0.397 (10.08)
0.325 (8.25)
0.320 (8.13)
0.050 (1.27)
FRONT VIEW
2
2
B
A
0.070 (1.78) Ref.
Pin #1
I.D.
3
C
0.016 (0.41)
Ref.
0.290 (7.37)
Ref.
0.047 (1.19)
0.100 (2.54)
0.519 (13.18)
Ref.
0.198 (5.04) Ref.
0.264 (6.70)
Ref.
0.118 (3.00)
6×
6×
3
0.140 (3.56)
0.120 (3.05)
0.021 (0.53)
0.019 (0.48)
0.378 (9.60)
Ref. 0.019 (0.48) Ref.
0.060 (1.52)
Ref.
0.048 (1.22)
0.046 (1.17)
0.081 (2.06)
0.077 (1.96)
0.207 (5.26)
0.187 (4.75)
0.033 (0.84)
0.028 (0.71)
0.016 (0.41)
0.011 (0.28)
eSIP-7C (E Package)
10° Ref.
All Around
0.020 M 0.51 M C
0.010 M 0.25 M C A B
SIDE VIEW
END VIEW
BACK VIEW
4
0.023 (0.58)
0.027 (0.70)
DETAIL A
Detail A
Rev. B 09/15
16
LYT2002-2005
www.power.com
SIDE VIEW END VIEW
11×
2
7
7
PI-5748a-100311
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimensions noted are determined at the outermost
extremes of the plastic body exclusive of mold flash,
tie bar burrs, gate burrs, and interlead flash, but
including any mismatch between the top and bottom of
the plastic body. Maximum mold protrusion is 0.007
[0.18] per side.
3. Dimensions noted are inclusive of plating thickness.
4. Does not include interlead flash or protrusions.
5. Controlling dimensions in inches [mm].
6. Datums A and B to be determined at Datum H.
7. Exposed pad is nominally located at the centerline of
Datums A and B. “Max” dimensions noted include both
size and positional tolerances.
eSOP-12B (K Package)
B
C
C
H
TOP VIEW BOTTOM VIEW
Pin #1 I.D.
(Laser Marked)
0.023 [0.58]
0.018 [0.46]
0.006 [0.15]
0.000 [0.00]
0.098 [2.49]
0.086 [2.18]
0.092 [2.34]
0.086 [2.18]
0.032 [0.80]
0.029 [0.72]
Seating
Plane
Detail A
Seating plane to
package bottom
standoff
0.034 [0.85]
0.026 [0.65]
0.049 [1.23]
0.046 [1.16]
3 4
0.460 [11.68]
0.400 [10.16]
0.070 [1.78]
0.306 [7.77]
Ref.
2
0.350 [8.89]
0.010 [0.25]
Ref.
Gauge Plane
Seating Plane
0.055 [1.40] Ref.
0.010 [0.25]
0.059 [1.50]
Ref, Typ 0.225 [5.72]
Max.
0.019 [0.48]
Ref.
0.022 [0.56]
Ref.
0.020 [0.51]
Ref.
0.028 [0.71]
Ref.
0.325 [8.26]
Max.
0.356 [9.04]
Ref.
0.059 [1.50]
Ref, Typ
0.120 [3.05] Ref
0.010 (0.25) M C A B
11×
0.016 [0.41]
0.011 [0.28]
3
DETAIL A (Scale = 9X)
0.008 [0.20] C
2X, 5/6 Lead Tips
0.004 [0.10] C
0.004 [0.10] C A 2X
0.004 [0.10] C B
0 -
° 8°
123 4 6 6 1
7 12
2X
0.217 [5.51]
0.321 [8.15]
0.429 [10.90]
0.028 [0.71]
0.067 [1.70] Land Pattern
Dimensions
11
12
10
9
8
7
2
1
3
4
6
Revision Notes Date
A Code A. 05/19/14
A Updated Figure 2. 06/12/14
A Updated VFB(TH) parameter table information. 12/08/14
B Removed LYT2001D part number from data sheet. 09/15
For the latest updates, visit our website: www.power.com
Power Integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. Power Integrations
does not assume any liability arising from the use of any device or circuit described herein. POWER INTEGRATIONS MAKES NO WARRANTY
HEREIN AND SPECIFICALLY DISCLAIMS ALL WARRANTIES INCLUDING, WITHOUT LIMITATION, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE, AND NON-INFRINGEMENT OF THIRD PARTY RIGHTS.
Patent Information
The products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one
or more U.S. and foreign patents, or potentially by pending U.S. and foreign patent applications assigned to Power Integrations. A complete list of
Power Integrations patents may be found at www.power.com. Power Integrations grants its customers a license under certain patent rights as set
forth at http://www.power.com/ip.htm.
Life Support Policy
POWER INTEGRATIONS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS
WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF POWER INTEGRATIONS. As used herein:
1. A Life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose
failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in signicant injury or
death to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the
failure of the life support device or system, or to affect its safety or effectiveness.
The PI logo, TOPSwitch, TinySwitch, LinkSwitch, LYTSwitch, InnoSwitch, DPA-Switch, PeakSwitch, CAPZero, SENZero, LinkZero, HiperPFS,
HiperTFS, HiperLCS, Qspeed, EcoSmart, Clampless, E-Shield, Filterfuse, FluxLink, StakFET, PI Expert and PI FACTS are trademarks of Power
Integrations, Inc. Other trademarks are property of their respective companies. ©2015, Power Integrations, Inc.
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