September 2006
Advance Information
Copyright © Alliance Memory All rights reserved.
AS7C1024C
5V 128K X 8 CMOS SRAM
12/5/06, v. 1.0 Alliance Memory P. 1 of 9
®
Features
• Industrial (-40o to 85oC) temperature
• Organization: 131,072 x 8 bits
• High speed
- 12 ns address access time
- 6 ns output enable access time
• Low power consumption via chip deselect
• Easy memory expansion with CE1, CE2, OE inputs
• TTL/LVTTL-compatible, three-state I/O
• 32-pin JEDEC standard packages
-300 mil SOJ
-400 mil SOJ
• ESD protection ≥ 2000 volts
Logic block diagram
Pin arrangement
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
VCC
A15
CE2
WE
A13
A8
A9
A11
OE
A10
CE1
I/O7
I/O6
I/O5
I/O4
I/O3
NC
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
GND
AS7C1024C
32-pin SOJ (300 mil)
32-pin SOJ (400 mil)
131,702 x 8
Array
(1,048,576)
Sense amp
Input buffer
A10
A11
A12
A13
A14
A15
A16
I/O0
I/O7
OE
CE1
WE
Address decoder
Address decoder
Control
circuit
A9
A0
A1
A2
A3
A4
A5
A6
A7
V
CC
GND
A8
CE2
AS7C1024C
12/5/06, v. 1.0 Alliance Memory P. 2 of 9
®
Functional description
The AS7C1024C is a 5V high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) device organized
as 131,072 words x 8 bits. It is designed for memory applications where fast data access, low power, and simple interfacing
are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 12 ns with output enable access times (tOE) of 6 ns are ideal for high
performance applications. Active high and low chip enables (CE1, CE2) permit easy mem ory expansion with multiple-ban k
systems.
When CE1 is high or CE2 is low, the devices enter standby mode. If inputs are still toggling, the device will consume ISB
power. If the bus is static, then full standby power is reached (ISB1).
A write cycle is accomplished by asserting write enable (WE) and both chip e nables (C E1 , CE2). Data on the input pins I/O0
through I/O7 is written on the rising edge of WE (write cycle 1) or the active-to-inactive edge of CE1 or CE2 (write cycle 2).
To avoid bus contention, extern al devices shoul d drive I/O pin s onl y after ou tputs have been dis abled with output enable ( OE)
or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and both chip enables (CE1, CE2), with write enable (WE) high.
The chips drive I/O p ins with the data w ord referenced by th e in put address. When either chip en able is inactive, output enable
is inactive, or write enable is active, output drivers stay in high-impedance mode.
Note:
Stresses greater than those listed under Absolute Maximum Rating s may cause permanent damage to the device. This is a stress rating only and functi onal
operation of the devic e at these or any other conditions outside th ose indicated in the operational sections of this sp ecification is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect reliability.
Key: X = don’t care, L = low, H = high.
Absolute maximum ratings
Parameter Symbol Min Max Unit
Voltage on VCC relative to GND Vt1 –0.50 +7.0 V
Voltage on any pin relative to GND Vt2 –0.50 VCC +0.50 V
Power dissipation PD–1.25W
Storage temperature (plastic) Tstg –55 +125 °C
Ambient temperature with VCC applied Tbias –55 +125 °C
DC current into outputs (low) IOUT –50mA
Truth table
CE1
CE2
WE OE
Data Mode
H X X X High Z Standby (ISB, ISB1)
X L X X High Z Standby (ISB, ISB1)
L H H H High Z Output disable (ICC)
LHHL D
OUT Read (ICC)
LHLX D
IN Write (ICC)
AS7C1024C
12/5/06, v. 1.0 Alliance Memory P. 3 of 9
®
Note:
1 VIL min = -1.5V for pulse width less than 10ns, once per cycle.
Recommended operating conditions
Parameter Symbol Min Nominal Max Unit
Supply Voltage VCC 4.5 5.0 5.5 V
Input Voltage VIH 2.2 - VCC + 0.5 V
VIL(1) –0.5(1) –0.8V
Ambient operating temperature (Industrial) TA–40 – 85 °C
DC operating characteristics (over the operating range)1
Parameter Symbol Test conditions
AS7C1024C-12
UnitMin Max
Input leakage current |ILI|V
CC = Max, VIN = GND to VCC –5μA
Output leaka g e cu rr e nt |ILO|VCC = Max, CE1 = VIH or
CE2 = VIL, VOUT = GND to VCC –5μA
Operating power supply current ICC
VCC = Max, CE1 ≤ VIL,
CE2 ≥ VIH, f = fMax,
IOUT = 0 mA – 160 mA
Standby power supply current1
ISB VCC = Max, CE1 ≥ VIH and/or
CE2 ≤ VIL, f = fMax –40
mA
ISB1
VCC = Max, CE1 ≥ VCC–0.2V
and/or CE2 ≤ 0.2V
VIN ≤ 0.2V or
VIN ≥ VCC – 0.2V, f = 0
–10
mA
Output voltage VOL IOL = 8 mA, VCC = Min – 0.4 V
VOH IOH = –4 mA, VCC = Min 2.4 – V
Capacitance (f = 1 MHz, Ta = 25o C, VCC = NOMINAL)2
Parameter Symbol Signals Test conditions Max Unit
Input capacitance CIN A, CE1, CE2, WE, OE VIN = 3dV 7 pF
I/O capacitance CI/O I/O VOUT = 3dV 8 pF
Note:
This parameter is guaranteed by device characte rization, but is not production tested.
AS7C1024C
12/5/06, v. 1.0 Alliance Memory P. 4 of 9
®
Key to switching waveforms
Read waveform 1 (address controlled)3,6,7,9
Read waveform 2 (CE1, CE2, and OE controlled)3,6,8,9,12
Read cycle (over the operating range)3,9
Parameter Symbol
AS7C1024C-12
Unit NotesMin Max
Read cycle time tRC 12 – ns
Address access time tAA –12ns3
Chip enable (CE1) access time tACE1 –12ns3, 12
Chip enable (CE2) access time tACE2 –12ns3, 12
Output enable (OE) access time tOE –6ns
Output hold from address change tOH 4–ns5
CE1 Low to output in low Z tCLZ1 3 – ns 4, 5, 12
CE2 High to output in lo w Z tCLZ2 3 – ns 4, 5, 12
CE1 Low to output in high Z tCHZ1 0 6 ns 4, 5, 12
CE2 Low to out pu t in hi gh Z tCHZ2 – 5 ns 4, 5, 12
OE Low to output in low Z tOLZ 0 – ns 4, 5
OE High to output in high Z tOHZ – 5 ns 4, 5
Power up time tPU 0 – ns 4, 5, 12
Power down time tPD – 12 ns 4, 5, 12
Undefined/don’t careFalling inputRising input
A
ddress
D
OUT
Data valid
t
OH
t
AA
t
RC
supply
Current
CE2
OE
D
OUT
t
OE
t
OLZ
t
ACE1
,
tACE2
t
CHZ1
, t
CHZ2
t
CLZ1
, t
CLZ2
t
PU
t
PD
I
CC
I
SB
50% 50%
Data valid
t
RC1
CE1
t
OHZ
AS7C1024C
12/5/06, v. 1.0 Alliance Memory P. 5 of 9
®
Write waveform 1 (WE controlled)10,11
Write waveform 2 (CE1 and CE2 controlled)10,11,12
Write cycle (over the operating range)11
Parameter Symbol
AS7C1024C-12
Unit NotesMin Max
Write cycle time tWC 12 – ns
Chip enable (CE1) to write end tCW1 10 – ns 12
Chip enable (CE2) to write end tCW2 10 – ns 12
Address setup to write end tAW 10 – ns
Address setup time tAS 0–ns12
Write pulse wi dth tWP 8–ns
Write recovery time tWR 0–ns
Address hold from end of write tAH 0–ns
Data valid to write end tDW 7–ns
Data hold time tDH 0 – ns 4, 5
Write enable to output in high Z tWZ 0 5 ns 4, 5
Output active from write end tOW 3 – ns 4, 5
t
AW
t
AH
t
WC
Address
WE
D
OUT
t
DH
t
OW
t
DW
t
WZ
t
WP
t
AS
Data valid
D
IN
t
WR
t
AW
Address
CE1
WE
D
OUT
t
CW1
, t
CW2
t
WP
t
DW
t
DH
t
AH
t
wz
t
WC
t
AS
CE2
Data valid
D
IN
t
WR
AS7C1024C
12/5/06, v. 1.0 Alliance Memory P. 6 of 9
®
AC test conditions
Notes
1 During VCC power-up, a pull-up resistor to VCC on
CE
is required to meet ISB specification.
2 This parameter is sampled, but not 100% teste d.
3 For test conditions, see AC Test Conditions, Figures A and B.
4t
CLZ and tCHZ are specified with CL = 5 pF, as in Figure B. Transition is measured ±200 mV from steady-state voltage.
5 This parameter is guarante ed, but not 100% tested.
6
WE
is high for read cycle.
7
CE
and
OE
are low for read cycle.
8 Address is valid prior to or coincident with
CE
transition low.
9 All read cycle timings are reference d from the last valid addre ss to the first transitioning address.
10 N/A
11 All write cycle timings are referenced fro m the last valid addre ss to the first transitioning addre ss.
12 N/A.
13 C = 30 pF, ex cept all high Z and low Z parameters where C = 5 pF.
– Output load: see Figure B.
– Input pulse level: GND to 3.0 V. See Figure A.
– Input rise and fall times: 3 ns. See Figure A.
– Input and output timin g reference levels: 1.5 V.
168
Ω
Thevenin equivalent:
D
OUT
+1.728 V
255
Ω
C
13
480
Ω
D
OUT
GND
+5 V
Figure B: 5 V Output load
10%
90%
10%
90%
GND
+3.0V
Figure A: Input pulse
3 ns
AS7C1024C
12/5/06, v. 1.0 Alliance Memory P. 7 of 9
®
Package dimensions
eD
E1
Pin 1
b
B
A1
A2 c
E
Seating
plane
E2
A
32-pin SOJ
300/400 mil
32-pin SOJ 300
mil 32-pin SOJ 400
mil
Min Max Min Max
A 0.128 0.145 0.132 0.146
A1 0.025 - 0.025 -
A2 0.095 0.105 0.105 0.115
B 0.026 0.032 0.026 0.032
b 0.016 0.020 0.015 0.020
c 0.007 0.010 0.007 0.013
D 0.820 0.830 0.820 0.830
E 0.255 0.275 0.354 0.378
E1 0.295 0.305 0.395 0.405
E2 0.330 0.340 0.435 0.445
e 0.050 BSC 0.050 BSC
Note: This part is compatible with both pin numbering
conventions used by various manufacturers.
AS7C1024C
12/5/06, v. 1.0 Alliance Memory P. 8 of 9
®
Ordering Codes
Package Volt/Temp 12 ns
Plastic SOJ, 300 mil 5V industrial AS7C1024C-12TJIN
Plastic SOJ, 400 mil 5V industrial AS7C1024C-12JIN
Part numbering system
AS7C 1024C –XX X X X
SRAM prefix Device
number Access time
Package:
J = SOJ 400 mil
TJ = SOJ 300 mil
Temperature range
I = industrial, -40°
C to 85° C
N = LEAD FREE
PART
Alliance Memory, Inc.
1116 South Amphlett
San Mateo, CA 94402
Tel: 650-525-3737
Fax: 650-525-0449
www.alliancememory.com
Copyright © Alliance Memory
All Rights Reserved
Part Number: AS7C1024C
Document Version: v. 1.0
© Copyright 2003 Alliance Mem ory, Inc. All rights reserved. Our three-point lo go, our name and Intelliwatt are trademarks or registered trademarks of
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document and its products at any time without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data
contained herein repres ents Alli ance's b est data a nd/or e stimat es at th e time of issuan ce. Allianc e reserve s the right t o cha nge or correct this data at any
time, without n otice. If the produ ct described h erein is under develop ment, significant c hanges to the se specifications are p ossible. The information in
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claims arising from such use.
AS7C1024C
®
®
