W956D6KBKX
64Mb Async./Burst/Sync./A/D MUX
Publication Release Date: Mar. 02, 2017
Revision: A01-001
- 1 -
TABLE OF CONTENTS
1. GENERAL DESCRIPTION .......................................................................................................... 3
2. FEATURES.................................................................................................................................. 3
3. ORDERING INFORMATION ....................................................................................................... 3
4. BALL CONFIGURATION ............................................................................................................ 4
5. BALL DESCRIPTION .................................................................................................................. 5
6. BLOCK DIAGRAM ...................................................................................................................... 6
7. INSTRUCTION SET .................................................................................................................... 7
8. FUNCTIONAL DESCRIPTION .................................................................................................... 8
8.1 Power Up Initialization ..................................................................................................................... 8
8.2 Bus Operating Modes ...................................................................................................................... 8
8.3 Asynchronous Modes ...................................................................................................................... 8
8.3.1 READ Operation (ADV# LOW) .................................................................................................................. 9
8.3.2 WRITE Operation (ADV# LOW) ................................................................................................................ 9
8.4 Burst Mode Operation .................................................................................................................... 10
8.4.1 Burst Mode READ (4-word burst) ............................................................................................................ 10
8.4.2 Burst Mode WRITE (4-word burst) .......................................................................................................... 11
8.4.3 Refresh Collision During Variable-Latency READ Operation .................................................................. 12
8.5 Mixed-Mode Operation .................................................................................................................. 13
8.5.1 WAIT Operation ....................................................................................................................................... 13
8.5.2 Wired-OR WAIT Configuration ................................................................................................................ 13
8.5.3 LB#/ UB# Operation ................................................................................................................................. 14
8.6 Low Power Operation .................................................................................................................... 14
8.6.1 Standby Mode Operation ......................................................................................................................... 14
8.6.2 Temperature Compensated Refresh ....................................................................................................... 14
8.6.3 Partial-Array Refresh ............................................................................................................................... 14
8.6.4 Deep Power-Down Operation .................................................................................................................. 14
8.7 Registers ....................................................................................................................................... 15
8.7.1 Access Using CRE .................................................................................................................................. 15
8.7.2 Configuration Register WRITE Asynchronous Mode Followed by READ Operation .............................. 15
8.7.3 Configuration Register WRITE Synchronous Mode Followed by READ Operation ................................ 16
8.7.4 Configuration Register READ Asynchronous Mode Followed by READ ARRAY Operation .................. 17
8.7.5 Configuration Register READ Synchronous Mode Followed by READ ARRAY Operation .................... 18
8.7.6 Software Access ...................................................................................................................................... 19
8.7.7 Load Configuration Register .................................................................................................................... 19
8.7.8 Read Configuration Register ................................................................................................................... 20
8.8 Bus Configuration Register ............................................................................................................ 20
8.8.1 Bus Configuration Register Definition ...................................................................................................... 21
8.8.2 Burst Length (BCR[2:0]) Default = Continuous Burst .............................................................................. 22
8.8.3 Burst Wrap (BCR[3]) Default = No Wrap ................................................................................................. 22
8.8.4 Sequence and Burst Length .................................................................................................................... 23
8.8.5 Drive Strength (BCR[5:4]) Default = Outputs Use Half-Drive Strength ................................................... 24
8.8.6 Drive Strength .......................................................................................................................................... 24
8.8.7 WAIT Configuration. (BCR[8]) Default =WAIT Transitions 1 Clock Before Data Valid/ Invalid ............... 24
8.8.8 WAIT Polarity (BCR[10]) Default = WAIT Active HIGH ........................................................................... 24
8.8.9 WAIT Configuration During Burst Operation ........................................................................................... 25
8.8.10 Latency Counter (BCR[13:11]) Default = Three Clock Latency ............................................................ 25
8.8.11 Initial Access Latency (BCR[14]) Default = Variable ............................................................................. 25
8.8.12 Allowed Latency Counter Settings in Variable Latency Mode ............................................................... 25
8.8.13 Latency Counter (Variable Initial Latency, No Refresh Collision) ......................................................... 26
8.8.14 Allowed Latency Counter Settings in Fixed Latency Mode ................................................................... 26
8.8.15 Latency Counter (Fixed Latency) .......................................................................................................... 27
8.8.16 Operating Mode (BCR[15]) Default is Asynchronous Operation ........................................................... 27
W956D6KBKX
Publication Release Date: Mar. 02, 2017
Revision: A01-001
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8.9 Refresh Configuration Register ...................................................................................................... 28
8.9.1 Refresh Configuration Register Mapping ................................................................................................ 28
8.9.2 Partial Array Refresh (RCR[2:0]) Default = Full Array Refresh ............................................................... 28
8.9.3 Address Patterns for PAR (RCR [4] = 1) ................................................................................................. 29
8.9.4 Deep Power-Down (RCR[4]) Default = DPD Disabled ............................................................................ 29
8.10 Device Identification Register ....................................................................................................... 29
9. ELECTRICAL CHARACTERISTIC ........................................................................................... 30
9.1 Absolute Maximum DC, AC Ratings .............................................................................................. 30
9.2 Electrical Characteristics and Operating Conditions ....................................................................... 30
9.3 Deep Power-Down Specifications .................................................................................................. 31
9.4 Partial Array Self Refresh Standby Current .................................................................................... 31
9.5 Capacitance ................................................................................................................................... 31
9.6 AC Input-Output Reference Waveform ........................................................................................... 31
9.7 AC Output Load Circuit .................................................................................................................. 31
10. TIMING REQUIREMENTS....................................................................................................... 32
10.1 Read, Write Timing Requirements ............................................................................................... 32
10.1.1 Asynchronous READ Cycle Timing Requirements ............................................................................... 32
10.1.2 Burst READ Cycle Timing Requirements .............................................................................................. 33
10.1.3 Asynchronous WRITE Cycle Timing Requirements .............................................................................. 34
10.1.4 Burst WRITE Cycle Timing Requirements ............................................................................................ 35
10.2 TIMING DIAGRAMS .................................................................................................................... 36
10.2.1 Initialization Period ................................................................................................................................. 36
10.2.2 DPD Entry and Exit Timing Parameters ................................................................................................ 36
10.2.3 Initialization Timing Parameters ............................................................................................................ 36
10.2.4 Initialization and DPD Timing Parameters ............................................................................................. 36
10.2.5 Asynchronous READ ............................................................................................................................. 37
10.2.6 Single Access Burst READ Operation - Variable Latency..................................................................... 38
10.2.7 Four Word Burst READ Operation-Variable Latency ............................................................................ 39
10.2.8 Single-Access Burst READ Operation-Fixed Latency ........................................................................... 40
10.2.9 Four Word Burst READ Operation-Fixed Latency ................................................................................. 41
10.2.10 Burst READ Terminate at End-of-Row (Wrap Off) .............................................................................. 42
10.2.11 Burst READ Row Boundary Crossing ................................................................................................. 43
10.2.12 Asynchronous WRITE ......................................................................................................................... 44
10.2.13 Burst WRITE Operation-Variable Latency Mode ................................................................................. 45
10.2.14 Burst WRITE Operation-Fixed Latency Mode ..................................................................................... 46
10.2.15 Burst WRITE Terminate at End of Row (Wrap Off) ............................................................................. 47
10.2.16 Burst WRITE Row Boundary Crossing ................................................................................................ 48
10.2.17 Burst WRITE Followed by Burst READ ............................................................................................... 49
10.2.18 Asynchronous WRITE Followed by Burst READ ................................................................................ 50
10.2.19 Burst READ Followed by Asynchronous WRITE ................................................................................ 51
10.2.20 Asynchronous WRITE Followed by Asynchronous READ .................................................................. 52
11. PACKAGE SPECIFICATION .................................................................................................. 53
12. REVISION HISTORY ............................................................................................................... 54
W956D6KBKX
Publication Release Date: Mar. 02, 2017
Revision: A01-001
- 3 -
1. GENERAL DESCRIPTION
Winbond x16 ADMUX products are high-speed, CMOS pseudo-static random access memory developed for low-
power, portable applications. The 64Mb device has a DRAM core organized as 4 Meg x 16 bits. These devices are a
variation of the industry-standard Flash control interface, with a multiplexed address/data bus. The multiplexed
address and data functionality dramatically reduce the required signal count, and increase READ/WRITE bandwidth.
For seamless operation on a burst Flash bus, Winbond x16 ADMUX products incorporate a transparent self-refresh
mechanism. The hidden refresh requires no additional support from the system memory controller and has no
significant impact on device READ/WRITE performance.
Two user-accessible control registers define device operation. The bus configuration register (BCR) defines how the
Winbond x16 ADMUX device interacts with the system memory bus and is nearly identical to its counterpart on burst
mode Flash devices. The refresh configuration register (RCR) is used to control how refresh is performed on the
DRAM array. These registers are automatically loaded with default settings during power-up and can be updated
anytime during normal operation.
Special attention has been focused on standby current consumption during self refresh. Winbond x16 ADMUX
products include two mechanisms to minimize standby current. Partial-array refresh (PAR) enables the system to limit
refresh to only that part of the DRAM array that contains essential data. Temperature-compensated refresh (TCR)
uses an on-chip sensor to adjust the refresh rate to match the device temperature —the refresh rate decreases at
lower temperatures to minimize current consumption during standby. The system-configurable refresh mechanisms
are accessed through the RCR.
Winbond x16 ADMUX device is programmable into the 1st operation mode (called as CRAM 1.5 mode) in which it is
compliant with the industry-standard CellularRAM 1.5 x16 A/D MUX. Winbond x16 ADMUX device is also
programmable into the 2nd operation mode in which the data rate is double to the 1st operation.
2. FEATURES
• Supports asynchronous, page, and burst operations
• VCC, VCCQ Voltages:
1.7V–1.95V VCC
1.7V–1.95V VCCQ
• Random access time: 70ns
• Burst mode READ and WRITE access:
4, 8, 16, or 32 words, or continuous burst
Burst wrap or sequential
Max clock rate:
133 MHz (tCLK = 7.5ns)
• Low power consumption:
Asynchronous random READ/WRITE: <25 mA
Continuous burst READ: <35 mA
Standby current: <250 μA
• Low-power features
On-chip temperature compensated refresh (TCR)
Partial array refresh (PAR)
Deep Power-Down (DPD) mode
• Configuration: 64Mb (4M x 16)
• 16-bit multiplexed address/data bus
• Support package:
49 balls WFBGA (x16)
• Operating temperature range:
-40°C ≤ TCASE ≤ 85°C
3. ORDERING INFORMATION
Part Number
VCC/VCCQ
I/O Width
Package
Description
W956D6KBKX7I
1.8V/1.8V
16
49 balls WFBGA
CRAM ADMux, 133MHz, -40°C~85°C, DPD Mode
W956D6KBKX
Publication Release Date: Mar. 02, 2017
Revision: A01-001
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4. BALL CONFIGURATION
1 2 65 743
AVDDQ
TOP VIEW (Ball Down)
B
C
D
E
F
G
VDDQ VDDQ VDDQVSS
VSSVSS
WAIT ADQ5 ADQ0
ADQ9VDDADQ14
ADQ3 ADQ8ADQ2
OE#ADQ6
ADQ15
ADQ10
ADQ13
ADQ1VSS
ADQ4VSS ADQ12
ADQ7 ADQ11
A20 VSS VSS A19UB#
VSSADV#
A21 NC NC A18LB#
CREWE#
A16 VDD VDD A17CE#
VSSCLK
W956D6KBKX
Publication Release Date: Mar. 02, 2017
Revision: A01-001
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5. BALL DESCRIPTION
Symbol
Type
Description
A[max:16]
Input
Address inputs: Inputs for addresses during READ and WRITE operations. Addresses are
internally latched during READ and WRITE cycles. The address lines are also used to
define the value to be loaded into the BCR or the RCR. A[max:16]=A[21:16] (64Mb).
CLK
(Note 1)
Input
Clock: CLK input synchronizes the memory to the system operating frequency during
synchronous operations. When configured for synchronous operation, the address is latched
on the first rising CLK edge when ADV# is active. CLK must be static (HIGH or LOW) during
asynchronous access READ and WRITE operations when burst mode is enabled.
ADV#
(Note 1)
Input
Address valid: Indicates that a valid address is present on the address inputs. Addresses
are latched on the rising edge of ADV# during asynchronous READ and WRITE operations.
CRE
Input
Control register enable: When CRE is HIGH, WRITE operations load the RCR or BCR,
and READ operations access the RCR, BCR, or DIDR.
CE#
Input
Chip enable: Activates the device when LOW. When CE# is HIGH, the device is disabled
and goes into standby mode.
OE#
Input
Output enable: Enables the output buffers when LOW. When OE# is HIGH, the output
buffers are disabled.
WE#
Input
Write enable: Determines if a given cycle is a WRITE cycle. If WE# is LOW, the cycle is a
WRITE to either a configuration register or to the memory array.
LB#
Input
Lower byte enable: DQ[7:0].
UB#
Input
Upper byte enable: DQ[15:8].
A/DQ[15:0]
Input/Output
Address/data I/Os: These pins are a multiplexed address/data bus. As inputs for
addresses, these pins behave as A[15:0]. A[0] is the LSB of the 16-bit word address within
the CellularRAM device. Address, RCR, and BCR values are loaded with ADV# LOW. Data
is input or output when ADV# is HIGH.
WAIT
(Note 1)
Output
WAIT: Provides data-valid feedback during burst READ and WRITE operations. WAIT is
used to arbitrate collisions between refresh and READ/WRITE operations. WAIT is also
asserted at the end of a row unless wrapping within the burst length. WAIT should be
ignored during asynchronous operations. WAIT is High-Z when CE# is HIGH.
NC
—
Reserved for future use.
VCC
Supply
Device power supply: Power supply for device core operation.
VCCQ
Supply
I/O power supply: Power supply for input/output buffers.
VSS
Supply
VSS must be connected to ground.
VSSQ
Supply
VSSQ must be connected to ground.
Note:
1. When using asynchronous mode exclusively, CLK can be tied to VSSQ or VCCQ. WAIT should be ignored during asynchronous
mode operations.
W956D6KBKX
Publication Release Date: Mar. 02, 2017
Revision: A01-001
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6. BLOCK DIAGRAM
Address Decode
Logic
Refresh Configuration
Register (RCR)
Device ID Register
(DIDR)
Bus Configuration
Register (BCR)
DRAM
Memory
Array
Input /
Output
MUX
and
Buffers
Control
Logic
CE#
A/DQ [7:0]
A[max:16]
Internal External
A/DQ [15:8]
WE#
OE#
CLK
ADV#
CRE
WAIT
LB#/UB#
W956D6KBKX
Publication Release Date: Mar. 02, 2017
Revision: A01-001
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7. INSTRUCTION SET
Bus Operation
Asynchronous
Mode BCR[15] =
1 (default)
Power
CLK
ADV#
CE#
OE#
WE#
CRE
LB#/
UB#
WAIT*2
A/DQ[15:0]*3
Notes
Read
Active
X
L
L
H
L
L
Low-Z
Data out
4
Write
Active
X
L
X
L
L
L
High-Z
Data in
4
Standby
Standby
H or L
X
H
X
X
L
X
High-Z
High-Z
5, 6
No operation
Idle
X
X
L
X
X
L
X
Low-Z
X
4, 6
Configuration
register WRITE
Active
X
L
H
L
H
X
Low-Z
High-Z
Configuration
register READ
Active
x
L
L
H
H
L
Low-Z
Config. reg. out
DPD
Deep power-
down
L
X
H
X
X
X
X
High-Z
High-Z
10
Burst Mode
BCR[15] = 0
Power
CLK*1
ADV#
CE#
OE#
WE#
CRE
LB#/
UB#
WAIT*2
A/DQ[15:0]*3
Notes
Read
Active
H or L
L
L
H
L
L
Low-Z
Data out
4, 7
Write
Active
H or L
L
X
L
L
L
High-Z
Data in
4
Standby
Standby
H or L
X
H
X
X
L
X
High-Z
High-Z
5, 6
No operation
Idle
H or L
X
L
X
X
L
X
Low-Z
X
4, 6
Initial burst READ
Active
L
L
X
H
L
L
Low-Z
Address
4, 8
Initial burst WRITE
Active
L
L
H
L
L
X
Low-Z
Address
4, 8
Burst continue
Active
H
L
X
X
X
L
Low-Z
Data in or Data
out
4, 8
Configuration
register WRITE
Active
L
L
H
L
H
X
Low-Z
High-Z
8, 9
Configuration
register READ
Active
L
L
L
H
H
L
Low-Z
Config. reg. out
8, 9
DPD
Deep power-
down
L
X
H
X
X
X
X
High-Z
High-Z
10
Notes:
1. With burst mode enabled, CLK must be static (LOW) during asynchronous READs and asynchronous WRITEs and to achieve standby
power during standby and DPD modes.
2. The WAIT polarity is configured through the bus configuration register (BCR[10]).
3. When LB# and UB# are in select mode (LOW), DQ[15:0] are enabled. When only LB# is in select mode, DQ[7:0] are enabled. When only
UB# is in the select mode, DQ[15:8] are enabled.
4. The device will consume active power in this mode whenever addresses are changed.
5. When the device is in standby mode, address inputs and data inputs/outputs are internally isolated from any external influence.
6. VIN = VCCQ or 0V; all device balls must be static (unswitched) in order to achieve standby current.
7. When the BCR is configured for synchronous mode, synchronous READ and WRITE and asynchronous WRITE and READ are supported.
8. Burst mode operation is initialized through the bus configuration register (BCR[15])
9. Initial cycle. Following cycles are the same as BURST CONTINUE. CE# must stay LOW for the equivalent of a single-word burst (as
indicated by WAIT).
10. DPD is initiated when CE# transitions from LOW to HIGH after writing RCR[4] to 0. DPD is maintained until CE# transitions from HIGH to
LOW.
W956D6KBKX
Publication Release Date: Mar. 02, 2017
Revision: A01-001
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8. FUNCTIONAL DESCRIPTION
In general, ADMUX PSRAM devices are high-density alternatives to SRAM and Pseudo SRAM products, popular in
low-power, portable applications. The 64Mb device contains a 67,108,864 bit DRAM core, organized as 4,194,304
addresses by 16 bits. Both devices implement a multiplexed address/data bus. This multiplexed configuration supports
greater bandwidth through the x16 data bus, yet still reduces the required signal count. The ADMUX PSRAM bus
interface supports both asynchronous and burst mode transfers.
8.1 Power Up Initialization
ADMUX PRAM products include an on-chip voltage sensor used to launch the power-up initialization process.
Initialization will configure the BCR and the RCR with their default settings. VCC and VCCQ must be applied
simultaneously. When they reach a stable level at or above 1.7V, the device will require 150μs to complete its self-
initialization process. During the initialization period, CE# should remain HIGH. When initialization is complete, the
device is ready for normal operation.
Power-Up Initialization Timing
Device Initialization
Device ready for
normal operation
tPU
VCC=1.7V
VCC
VCCQ
8.2 Bus Operating Modes
This asynchronous/burst ADMUX PSRAM products incorporate a burst mode interface found on Flash products
targeting low-power, wireless applications. This bus interface supports asynchronous, and burst mode read and write
transfers. The specific interface supported is defined by the value loaded into the BCR.
8.3 Asynchronous Modes
Using industry-standard SRAM control signals (CE#, ADV#, OE#, WE#, and LB#/UB#). READ operations are initiated
by bringing CE#, ADV#, and LB#/UB# LOW while keeping OE# and WE# HIGH, and driving the address onto the
A/DQ bus. ADV# is taken HIGH to capture the address, and OE# is taken LOW. Valid data will be driven out of the
I/Os after the specified access time has elapsed.
WRITE operations occur when CE#, ADV#, WE#, and LB#/UB# are driven LOW with the address on the A/DQ bus.
ADV# is taken HIGH to capture the address, then the WRITE data is driven onto the bus. During asynchronous
WRITE operations, the OE# level is a “Don't Care,” and WE# will override OE#; however, OE# must be HIGH while
the address is driven onto the A/DQ bus. The data to be written is latched on the rising edge of CE#, WE#, UB#, or
LB# (whichever occurs first).
During asynchronous operation with burst mode enabled, the CLK input must be held static (LOW). WAIT will be
driven during asynchronous READs, and its state should be ignored. WE# LOW time must be limited to tCEM.
W956D6KBKX
Publication Release Date: Mar. 02, 2017
Revision: A01-001
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8.3.1 READ Operation (ADV# LOW)
Address
Address DATA
A[max:16]
CE#
OE#
WE#
A/DQ[15:0]
LB#/UB#
ADV#
DON’T CARE
High - Z
8.3.2 WRITE Operation (ADV# LOW)
Address
A[max:16]
CE#
Address DATA
A/DQ[15:0]
LB#/UB#
ADV#
OE#
WE#
<tCEM
DON’T CARE Undefined
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Publication Release Date: Mar. 02, 2017
Revision: A01-001
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8.4 Burst Mode Operation
Burst mode operations enable high-speed synchronous READ and WRITE operations. Burst operations consist of a
multi-clock sequence that must be performed in an ordered fashion. .After CE# goes LOW, the address to access is
latched on the first CLK edge after ADV# LOW. During this first clock rising edge, WE# indicates whether the
operation is going to be a READ (WE# = HIGH) or WRITE (WE# =LOW).
8.4.1 Burst Mode READ (4-word burst)
A[max:16]
CE#
A/DQ[15:0]
LB#/UB#
ADV#
OE#
WE#
WAIT
CLK
Latency Code 2(3 clocks)
READ burst identified
(WE# = HIGH)
Valid
Address
Valid
Address D0 D1 D2 D3
Invalid Don’t Care Undefined
Note:
Non-default BCR settings for burst mode READ (4-word burst): fixed or variable latency, Latency code 2 (3 clocks),
WAIT active Low, WAIT asserted during delay. Diagram is representative of variable latency with no refresh collision or
fixed-latency access.
W956D6KBKX
Publication Release Date: Mar. 02, 2017
Revision: A01-001
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8.4.2 Burst Mode WRITE (4-word burst)
A[max:16]
CE#
A/DQ[15:0]
LB#/UB#
ADV#
OE#
WE#
WAIT
CLK
Latency Code 2(3 clocks)
WRITE burst identified
(WE# = LOW)
Valid
Address
Valid
Address D0 D1 D2 D3
Don’t Care
Note:
Non-default BCR settings for burst mode WRITE (4-word burst): fixed or variable latency, latency code 2 (3 clocks),
WAIT active LOW, WAIT asserted during delay.
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The size of a burst can be specified in the BCR either as a fixed length or continuous. Fixed-length bursts consist of 4,
8, 16, or 32 words. Continuous bursts have the ability to start at a specified address and burst to the end of the
address. It goes back to the first address and continues to burst when continuous bursts meet the end of address.
The latency count stored in the BCR defines the number of clock cycles that elapse before the initial data value is
transferred between the processor and ADMUX PSRAM device. The initial latency for READ operations can be
configured as fixed or variable (WRITE operations always use fixed latency). Variable latency allows the ADMUX
PSRAM to be configured for minimum latency at high clock frequencies, but the controller must monitor WAIT to
detect any conflict with refresh cycles.
Fixed latency outputs the first data word after the worst-case access delay, including allowance for refresh collisions.
The initial latency time and clock speed determine the latency count setting. Fixed latency is used when the controller
cannot monitor WAIT. Fixed latency also provides improved performance at lower clock frequencies.
In CRAM 1.5 mode, the WAIT output asserts when a burst is initiated, and de-asserts to indicate when data is to be
transferred into (or out of) the memory. WAIT will again be asserted at the boundary of the row, unless wrapping within
the burst length. With wrap off, the ADMUX PSRAM device will restore the previous row’s data and access the next
row, WAIT will be de-asserted, and the burst can continue across the row boundary. If the burst is to terminate at the
row boundary, CE# must go HIGH within 2 clocks of the last data. CE# must go HIGH before any clock edge following
the last word of a defined-length burst WRITE.
The CE# LOW time is limited by refresh considerations. CE# must not stay LOW longer than tCEM. If a burst
suspension will cause CE# to remain LOW for longer than tCEM, CE# should be taken HIGH and the burst restarted
with a new CE# LOW/ADV# LOW cycle.
8.4.3 Refresh Collision During Variable-Latency READ Operation
D0
Additional WAIT satates inserted to allow refresh completion
High-Z
CLK
Undefined
A[max:16]
CE#
A/DQ[15:0]
LB#/UB#
ADV#
OE#
WE#
WAIT
VOH D1 D2 D3
Don’t Care
Valid
Address
Valid
Address
VOL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
Note:
Non-default BCR settings for refresh collision during variable-latency READ operation: latency code 2 (3 clocks),
WAIT active LOW, WAIT asserted during delay.
W956D6KBKX
Publication Release Date: Mar. 02, 2017
Revision: A01-001
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8.5 Mixed-Mode Operation
The device supports a combination of synchronous WRITE / READ and asynchronous WRITE / READ operations
when the BCR is configured for synchronous operation. The asynchronous WRITE operations require that the clock
(CLK) remain static (HIGH or LOW) during the entire sequence. The ADV# signal can be used to latch the target
address, or it can remain LOW during the entire WRITE operation. CE# can remain LOW when transitioning between
mixed-mode operations with fixed latency enabled; however, the CE# LOW time must not exceed tCEM. Mixed-mode
operation facilitates a seamless interface to legacy burst mode Flash memory controllers.
8.5.1 WAIT Operation
The WAIT output on an ADMUX PSRAM device is typically connected to a shared, system level WAIT signal. The
shared WAIT signal is used by the processor to coordinate transactions with multiple memories on the synchronous
bus.
8.5.2 Wired-OR WAIT Configuration
CellularRAM
WAIT
WAIT
Other
Device
WAIT
Other
Device
External
Pull-Up/
Pull-Down
Resistor
READY
Processor
When a burst READ or WRITE operation has been initiated, WAIT goes active to indicate that the ADMUX PSRAM
device requires additional time before data can be transferred. For READ operations, WAIT will remain active until
valid data is output from the device. For WRITE operations, WAIT will indicate to the memory controller when data will
be accepted into the ADMUX PSRAM device. When WAIT transitions to an inactive state, the data burst will progress
on successive clock edges.
During a burst cycle, CE# must remain asserted until the first data is valid. Bringing CE# HIGH during this initial
latency may cause data corruption.
When using variable initial access latency (BCR[14] = 0), the WAIT output performs an arbitration role for burst READ
operations launched while an on-chip refresh is in progress. If a collision occurs, WAIT is asserted for additional clock
cycles until the refresh has completed. When the refresh operation has completed, the burst READ operation will
continue normally.
In CRAM 1.5 mode WAIT is also asserted when a continuous READ or WRITE burst crosses a row boundary. The
WAIT assertion allows time for the new row to be accessed.
WAIT will be asserted after OE# goes LOW during asynchronous READ operations. WAIT will be High-Z during
asynchronous WRITE operations. WAIT should be ignored during all asynchronous operations. By using fixed initial
latency (BCR[14] = 1), this ADMUX PSRAM device can be used in burst mode without monitoring the WAIT signal.
However, WAIT can still be used to determine when valid data is available at the start of the burst and at the end of
the row. If WAIT is not monitored, the controller must stop burst accesses at row boundaries on its own.
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8.5.3 LB#/ UB# Operation
The LB# enable and UB# enable signals support byte-wide data WRITEs. During WRITE operations, any disabled
bytes will not be transferred to the RAM array and the internal value will remain unchanged. During an asynchronous
WRITE cycle, the data to be written is latched on the rising edge of CE#, WE#, LB#, or UB#, whichever occurs first.
LB# and UB# must be LOW during READ cycles.
When both the LB# and UB# are disabled (HIGH) during an operation, the device will disable the data bus from
receiving or transmitting data. Although the device will seem to be deselected, it remains in an active mode as long as
CE# remains LOW.
8.6 Low Power Operation
8.6.1 Standby Mode Operation
During standby, the device current consumption is reduced to the level necessary to perform the DRAM refresh
operation. Standby operation occurs when CE# is HIGH. The device will enter a reduced power state upon completion
of a READ or WRITE operation, or when the address and control inputs remain static for an extended period of time.
This mode will continue until a change occurs to the address or control inputs.
8.6.2 Temperature Compensated Refresh
Temperature-compensated refresh (TCR) allows for adequate refresh at different temperatures. This ADMUX
PSRAM device includes an on-chip temperature sensor that automatically adjusts the refresh rate according to the
operating temperature. The device continually monitors the temperature to select an appropriate self-refresh rate.
8.6.3 Partial-Array Refresh
Partial-array refresh (PAR) restricts refresh operation to a portion of the total memory array. This feature enables the
device to reduce standby current by refreshing only that part of the memory array required by the host system. The
refresh options are full array, one-half array, one-quarter array, one-eighth array, or none of the array. The mapping of
these partitions can start at either the beginning or the end of the address map. READ and WRITE operations to
address ranges receiving refresh will not be affected. Data stored in addresses not receiving refresh will become
corrupted. When re-enabling additional portions of the array, the new portions are available immediately upon writing
to the RCR.
8.6.4 Deep Power-Down Operation
Deep power-down (DPD) operation disables all refresh-related activity. This mode is used if the system does not
require the storage provided by the AD MUX PSRAM device. Any stored data will become corrupted when DPD is
enabled. When refresh activity has been re-enabled, the AD MUX PSRAM device will require 150μs to perform an
initialization procedure before normal operations can resume. During this 150μs period, the current consumption will
be higher than the specified standby levels, but considerably lower than the active current specification.
DPD can be enabled by writing to the RCR using CRE or the software access sequence; DPD starts when CE# goes
HIGH. DPD is disabled the next time CE# goes LOW and stays LOW for at least 10μs.
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8.7 Registers
Two user-accessible configuration registers define the device operation. The bus configuration register (BCR) defines
how the ADMUX PSRAM interacts with the system memory bus and is nearly identical to its counterpart on burst
mode Flash devices. The refresh configuration register (RCR) is used to control how refresh is performed on the
DRAM array. These registers are automatically loaded with default settings during power-up, and can be updated any
time the devices are operating in a standby state.
A DIDR provides information on the device manufacturer, CellularRAM generation, and the specific device
configuration. The DIDR is read-only.
8.7.1 Access Using CRE
The registers can be accessed using either a synchronous or an asynchronous operation when the control register
enable (CRE) input is HIGH. When CRE is LOW, a READ or WRITE operation will access the memory array. The
configuration register values are written via addresses A[max:16] and ADQ[15:0]. In an asynchronous WRITE, the
values are latched into the configuration register on the rising edge of CE#, or WE#, whichever occurs first; LB# and
UB# are “Don’t Care.” The BCR is accessed when A[19:18] are 10b; the RCR is accessed when A[19:18] are 00b. The
DIDR is read when A[19:18] are 01b. For reads, address inputs other than A[19:18] are “Don’t Care,” and register bits
15:0 are output on DQ[15:0]. Immediately after performing a configuration register READ or WRITE operation, reading
the memory array is highly recommended.
8.7.2 Configuration Register WRITE Asynchronous Mode Followed by READ Operation
OPCODE Address
r
Select control register
OPCODE Address
Initiate control register access
Write address bus value
to control register
(except A[19:18])
A[max:16]
CE#
ADV#
OE#
WE#
CRE
LB#/UB#
A/DQ[15:0]
A[19:18]1Address
tAVS
tAVS
tAVH
tAVH
tVP
tCW
tWP
tCPH
Valid
Data
Don’t Care
Note:
1. A[19:18] = 00b to load RCR, and 10b to load BCR.
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8.7.3 Configuration Register WRITE Synchronous Mode Followed by READ Operation
High-Z
Address
Address
High-Z
Notes 3
tSP
tSP
tHD
tKHTL
tCBPH
(except A[19:18])
A[max:16]
CE#
ADV#
OE#
WE#
CRE
LB#/UB#
A/DQ[15:0]
A[19:18]2
CLK
WAIT
Don’t Care
Valid
Data
tHD
tHD
tSP
tCSP
tSP
tHD
Latch control register value
Latch control register address
OPCODE
Address
OPCODE
Notes:
1. Non-default BCR settings for synchronous mode configuration register WRITE followed by READ ARRAY operation:
latency code 2 (3 clocks), WAIT active LOW, WAIT asserted during delay.
2. A[19:18] = 00b to load RCR, and 10b to load BCR.
3. CE# must remain LOW to complete a burst-of-one WRITE. WAIT must be monitored—additional WAIT cycles
caused by refresh collisions require a corresponding number of additional CE# LOW cycles.
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8.7.4 Configuration Register READ Asynchronous Mode Followed by READ ARRAY Operation
Address
Valid CR Valid Data
Undefined
Address
(except A[19:18])
A[max:16]
CE#
ADV#
OE#
WE#
CRE
LB#/UB#
A/DQ[15:0]
A[19:18]1
Don’t Care
tAVS
tAVS
tAVH
tAVH
tCPH
tVP
tAA
tCO
tOE
tBA tOLZ tBHZ
tOHZ
tAA
tHZ
tCPH
tAAVD
Select control register
Initiate control register access
Address
Note:
A[19:18] = 00b to read RCR, 10b to read BCR , and 01b to read DIDR.
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8.7.5 Configuration Register READ Synchronous Mode Followed by READ ARRAY Operation
Valid
Data
High-Z
Valid CR Address
Note 3
Undefined
Don’t Care
(except A[19:18])
A[max:16]
CE#
ADV#
OE#
WE#
CRE
LB#/UB#
A/DQ[15:0]
A[19:18]2
CLK
WAIT High-Z
tSP
tSP
tSP
tHD
tHD
tHD
tCSP
tSP
tACLK
tBOE
tOLZ tKOH
tOHZ
tCBPH
tABA
tHZ
tHD
tKHTL
Latch control register value
Latch control register address
Address
Address
Notes:
1. Non-default BCR settings for synchronous mode register READ followed by READ ARRAY operation: Latency code
2 (3 clocks) : WAIT active LOW;WAIT asserted during delay.
2. A[19:18]=00b to read RCR,10b to read BCR, and 01b to read DIDR.
3. CE# must remain LOW to complete a burst-of-one READ. WAIT must be monitored—additional WAIT cycles
caused by refresh collisions require a corresponding number of additional CE# LOW cycles.
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8.7.6 Software Access
Software access of the registers uses a sequence of asynchronous READ and asynchronous WRITE operations. The
contents of the configuration registers can be modified and all registers can be read using the software sequence. The
configuration registers are loaded using a four-step sequence consisting of two asynchronous READ operations
followed by two asynchronous WRITE operations.
The read sequence is virtually identical except that an asynchronous READ is performed during the fourth operation.
The address used during all READ and WRITE operations is the highest address of the ADMUX PSRAM device being
accessed; the contents of this address are not changed by using this sequence.
The data value presented during the third operation (WRITE) in the sequence defines whether the BCR, RCR, is to be
accessed. If the data is 0000h, the sequence will access the RCR; if the data is 0001h, the sequence will access the
BCR. During the fourth operation, ADQ[15:0] transfer data in to or out of bits 15:0 of the registers.
The use of the software sequence does not affect the ability to perform the standard (CRE-controlled) method of
loading the configuration registers. However, the software nature of this access mechanism eliminates the need for
CRE. If the software mechanism is used, CRE can simply be tied to VSS. The port line often used for CRE control
purposes is no longer required.
8.7.7 Load Configuration Register
WRITEWRITEREAD
CR Value
In
0ns (min)
RCR:0000h
BCR:0001h
CE#
ADV#
OE#
WE#
LB#/UB#
A/DQ[15:0]
A[max:16]
Don’t Care
READ
Address
(MAX) Address
(MAX) Address
(MAX) Address
(MAX)
Address
(MAX) XXXX Address
(MAX) XXXX Address
(MAX) Address
(MAX)
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8.7.8 Read Configuration Register
READWRITEREAD
CR Value
Out
0ns (min)
CE#
ADV#
OE#
WE#
LB#/UB#
A/DQ[15:0]
A[max:16]
Don’t Care
READ
Address
(MAX) Address
(MAX) Address
(MAX) Address
(MAX)
Address
(MAX) XXXX Address
(MAX) XXXX Address
(MAX) Address
(MAX)
RCR:0000h
BCR:0001h
DIDR:0002h
8.8 Bus Configuration Register
The BCR defines how the ADMUX PSRAM device interacts with the system memory bus. At power-up, the BCR is set
to 9D1Fh. The BCR is accessed with CRE HIGH and A[19:18] = 10b, or through the register access software
sequence with A/DQ = 0001h on the third cycle.
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8.8.1 Bus Configuration Register Definition
Reserved Register
Select Reserved Operating
Mode Initial
Latency Latency
Counter WAIT
Polarity Reserved WAIT Reserved Reserved Drive Strength Burst Burst
15 10 9 8 7 6 5 4 3
WAIT Polarity
0
1
Active Low
Active HIGH (default)
0
1
Operating Mode
Synchronous burst access mode
Asynchronous access mode (default)
Register Select
0 0
0
0
1
1
Select RCR
Select BCR
Select DIDR
0
1
Burst wraps within the burst length
0
1
0
0
1
1
Drive Strength
Full
Reserved
0
1
0
1
WAIT Configuration
Asserted one data cycle before delay (default)
Asserted during delay
0 0 1
0 1 0
0 1 1
1 0 0
1 1 1
Others Reserved
Continuous burst (default)
32 words
Burst Length (Note1)
0
1
0
0
0
1
1
1
0
1
1
1
1
0
0
1
0
All others
0
0
0
1
1
VariableFixed
0
0
1
0
1
1
0
1
1
All others
11 0
Latency
Reserved
Reserved
1 00 0
A[max:20] A[19:18] A[17:16] A/DQ15 A/DQ14 A/DQ10 A/DQ9 A/DQ8 A/DQ7 A/DQ6 A/DQ5 A/DQ4 A/DQ3 A/DQ[2:0]A/DQ[13:11]
All must be set to “0”Must be set to “0”Must be set to “0”Must be set to “0”Must be set to “0”
Configuration (WC) Wrap(BW)* Length(BL)*
17-1619-18 14-11 2-0
max-20
Burst no wraps (default)
Burst Wraps (Note1)
BCR[3]
BCR[5] BCR[4]
BCR[8]
16 words
8 words
4 words
1/2 (default)
1/4
BCR[10]
BCR[15]
BCR[19] BCR[18]
BCR[14] BCR[13] BCR[12] BCR[11]
BCR[2] BCR[1] BCR[0]
Code 3 (default)
Code 2
Code 4
Code 2
Code 3
Code 4
Code 5
Code 6
Code 8
Notes:
1. Burst wrap and length apply to both READ and WRITE operations.
2. Reserved bits must be set to zero. Reserved bits not set to zero will affect device functionality.
3. BCR[15:0] will be read back as written.
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8.8.2 Burst Length (BCR[2:0]) Default = Continuous Burst
Burst lengths define the number of words the device outputs during burst READ and WRITE operations. The device
supports a burst length of 4, 8, 16, or 32 words.
In CRAM 1.5 mode, the device can also be set in continuous burst mode where data is output sequentially without
regard to address boundaries; the internal address wraps to 000000h if the device is read past the last address.
8.8.3 Burst Wrap (BCR[3]) Default = No Wrap
The burst-wrap option determines if a 4-, 8-, 16-, or 32-word READ or WRITE burst wraps within the burst length, or
steps through sequential addresses.
In CRAM 1.5 mode, if the wrap option is not enabled, the device accesses data from sequential addresses without
regard to address boundaries; the internal address wraps to 000000h if the device is read past the last address.
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8.8.4 Sequence and Burst Length
Burst Wrap
Start
Addr
4-Word
Burst
Length
8-Word
Burst Length
16-Word
Burst Length
32-Word
Burst Length
Continuous Burst
BCR[3]
Wrap
Deci-
mal
Linear
Linear
Linear
Linear
Linear
0
Yes
0
0-1-2-3
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15
0-1-2-...-29-30-31
0-1-2-3-4-5-6-…
1
1-2-3-0
1-2-3-4-5-6-7-0
1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-0
1-2-3-...-30-31-0
1-2-3-4-5-6-7-…
2
2-3-0-1
2-3-4-5-6-7-0-1
2-3-4-5-6-7-8-9-10-11-12-13-14-15-0-1
2-3-4-...-31-0-1
2-3-4-5-6-7-8-…
3
3-0-1-2
3-4-5-6-7-0-1-2
3-4-5-6-7-8-9-10-11-12-13-14-15-0-1-2
3-4-5-...-0-1-2
3-4-5-6-7-8-9-…
4
4-5-6-7-0-1-2-3
4-5-6-7-8-9-10-11-12-13-14-15-0-1-2-3
4-5-6-...-1-2-3
4-5-6-7-8-9-10-…
5
5-6-7-0-1-2-3-4
5-6-7-8-9-10-11-12-13-14-15-0-1-2-3-4
5-6-7-...-2-3-4
5-6-7-8-9-10-11-…
6
6-7-0-1-2-3-4-5
6-7-8-9-10-11-12-13-14-15-0-1-2-3-4-5
6-7-8-...-3-4-5
6-7-8-9-10-11-12-
7
7-0-1-2-3-4-5-6
7-8-9-10-11-12-13-14-15-0-1-2-3-4-5-6
7-8-9-...-4-5-6
7-8-9-10-11-12-13-…
...
...
...
...
14
14-15-0-1-2-3-4-5-6-7-8-9-10-11-12-13
14-15-16-...-11-12-13
14-15-16-17-18-19-20-...
15
15-0-1-2-3-4-5-6-7-8-9-10-11-12-13-14
15-16-17-...-12-13-14
15-16-17-18-19-20-21-...
...
...
...
30
30-31-0-...-27-28-29
30-31-32-33-34-...
31
31-0-1-...-28-29-30
31-32-33-34-35-...
1
No
0
0-1-2-3
0-1-2-3-4-5-6-7
0-1-2-3-4-5-6-7-8-9-10-11-12-13-14-15
0-1-2...--29-30-31
0-1-2-3-4-5-6-…
1
1-2-3-4
1-2-3-4-5-6-7-8
1-2-3-4-5-6-7-8-9-10-11-12-13-14-15-16
1-2-3-...-30-31-32
1-2-3-4-5-6-7-…
2
2-3-4-5
2-3-4-5-6-7-8-9
2-3-4-5-6-7-8-9-10-11-12-13-14-15-16-17
2-3-4-...-31-32-33
2-3-4-5-6-7-8-…
3
3-4-5-6
3-4-5-6-7-8-9-10
3-4-5-6-7-8-9-10-11-12-13-14-15-16-17-18
3-4-5-...-32-33-34
3-4-5-6-7-8-9-…
4
4-5-6-7-8-9-10-
11
4-5-6-7-8-9-10-11-12-13-14-15-16-17-18-19
4-5-6-...-33-34-35
4-5-6-7-8-9-10-…
5
5-6-7-8-9-10-11-
12
5-6-7-8-9-10-11-12-13-...-15-16-17-18-19-20
5-6-7-...-34-35-36
5-6-7-8-9-10-11…
6
6-7-8-9-10-11-
12-13
6-7-8-9-10-11-12-13-14-...-16-17-18-19-20-21
6-7-8-...-35-36-37
6-7-8-9-10-11-12…
7
7-8-9-10-11-12-
13-14
7-8-9-10-11-12-13-14-...-17-18-19-20-21-22
7-8-9-...-36-37-38
7-8-9-10-11-12-13…
...
...
...
...
14
14-15-16-17-18-19-...-23-24-25-26-27-28-29
14-15-16-...-43-44-45
14-15-16-17-18-19-20-…
15
15-16-17-18-19-20-...-24-25-26-27-28-29-30
15-16-17-...-44-45-46
15-16-17-18-19-20-21-…
...
...
...
30
30-31-32-...-59-60-61
30-31-32-33-34-35-36-...
31
31-32-33-...-60-61-62
31-32-33-34-35-36-37-...
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8.8.5 Drive Strength (BCR[5:4]) Default = Outputs Use Half-Drive Strength
The output driver strength can be altered to full, one-half, or one-quarter strength to adjust for different data bus
loading scenarios. The reduced-strength options are intended for stacked chip (Flash + ADMUX PSRAM)
environments when there is a dedicated memory bus. The reduced-drive-strength option minimizes the noise
generated on the data bus during READ operations. Full output drive strength should be selected when using a
discrete ADMUX PSRAM device in a more heavily loaded data bus environment. Outputs are configured at half-drive
strength during testing.
8.8.6 Drive Strength
BCR[5]
BCR[4]
Drive Strength
0
0
Full
0
1
1/2 (default)
1
0
1/4
1
1
Reserved
8.8.7 WAIT Configuration. (BCR[8]) Default =WAIT Transitions 1 Clock Before Data Valid/ Invalid
The WAIT configuration bit is used to determine when WAIT transitions between the asserted and the de-asserted
state with respect to valid data presented on the data bus. The memory controller will use the WAIT signal to
coordinate data transfer during synchronous READ and WRITE operations. When BCR[8] = 0, data will be valid or
invalid on the clock edge immediately after WAIT transitions to the de-asserted or asserted state, respectively. When
BCR[8] = 1, the WAIT signal transitions one clock period prior to the data bus going valid or invalid.
8.8.8 WAIT Polarity (BCR[10]) Default = WAIT Active HIGH
The WAIT polarity bit indicates whether an asserted WAIT output should be HIGH or LOW. This bit will determine
whether the WAIT signal requires a pull-up or pull-down resistor to maintain the de-asserted state.
The default value is BCR[10]=1, indicating WAIT active HIGH.
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8.8.9 WAIT Configuration During Burst Operation
D0
End of row
Initial latency
Don’t Care
A/DQ[15:0]
BCR[8]=0
Data valid in current cycle
BCR[8]=1
Data valid in next cycle
D1 D2 D3
WAIT
WAIT
CLK
Note:
Signals shown are for WAIT active LOW, no wrap.
8.8.10 Latency Counter (BCR[13:11]) Default = Three Clock Latency
The latency counter bits determine how many clocks occur between the beginning of a READ or WRITE operation and
the first data value transferred. For allowable latency codes, see the following tables and figures.
8.8.11 Initial Access Latency (BCR[14]) Default = Variable
Variable initial access latency outputs data after the number of clocks set by the latency counter. However, WAIT must
be monitored to detect delays caused by collisions with refresh operations.
Fixed initial access latency outputs the first data at a consistent time that allows for worst-case refresh collisions. The
latency counter must be configured to match the initial latency and the clock frequency. It is not necessary to monitor
WAIT with fixed initial latency. The burst begins after the number of clock cycles configured by the latency counter.
8.8.12 Allowed Latency Counter Settings in Variable Latency Mode
BCR[13:11]
Latency
Configuration
Code
Latency *1
Max Input CLK Frequency (MHz)
Normal
133
104
010
2 (3 clocks)
2
66 (15ns)
66 (15ns)
011
3 (4clocks)—default
3
104 (9.62ns)
104 (9.62ns)
100
4 (5 clocks)
4
133 (7.5ns)
—
Others
Reserved
—
—
—
Note:
1. Latency is the number of clock cycles from the initiation of a burst operation until data appears. Data is transferred on
the next clock cycle.
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8.8.13 Latency Counter (Variable Initial Latency, No Refresh Collision)
Valid
Address
Code 2
Code 3 (Default)
Code 4
A[max:16]
ADV#
A/DQ[15:0]
CLK
A/DQ[15:0]
A/DQ[15:0]
Undefined
Don’t Care
Valid
Address
Valid
Address
Valid
Address
Valid
Output Valid
Output Valid
Output Valid
Output
Valid
Output Valid
Output
Valid
Output
Valid
Output Valid
Output Valid
Output Valid
Output
Valid
Output
8.8.14 Allowed Latency Counter Settings in Fixed Latency Mode
BCR[13:11]
Latency Configuration Code
Latency Count (N)
Max Input CLK Frequency (MHz)
133
104
010
2 (3 clocks)
2
33 (30ns)
33 (30ns)
011
3 (4 clocks)—default
3
52 (19.2ns)
52 (19.2ns)
100
4 (5 clocks)
4
66 (15ns)
66 (15ns)
101
5 (6 clocks)
5
75 (13.3ns)
75 (13.3ns)
110
6 (7 clocks)
6
104 (9.62ns)
104 (9.62ns)
000
8 (9 clocks)
8
133 (7.5ns)
—
Others
Reserved
—
—
—
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8.8.15 Latency Counter (Fixed Latency)
Valid
Address
Cycle N
Burst Identified
(READ)
A[max:16]
CE#
ADV#
A/DQ[15:0]
CLK
(WRITE)
A/DQ[15:0]
Undefined
Don’t Care
ADV# = LOW
N-1
Cycles
Valid
Output
Valid
Input
Valid
Output Valid
Output Valid
Output Valid
Output
Valid
Input Valid
Input Valid
Input Valid
Input
tAA
tAADV
tACLK
tCO
tSP tHD
Valid
Address
8.8.16 Operating Mode (BCR[15]) Default is Asynchronous Operation
The operating mode bit selects either synchronous burst operation or the default asynchronous mode of operation.
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8.9 Refresh Configuration Register
The refresh configuration register (RCR) defines how the ADMUX PSRAM device performs its transparent self refresh.
Altering the refresh parameters can dramatically reduce current consumption during standby mode. At power-up, the
RCR is set to 0010h. The RCR is accessed with CRE HIGH and A[19:18] = 00b; or through the register access
software sequence with A/DQ = 0000h on the third cycle.
8.9.1 Refresh Configuration Register Mapping
Reserved
6 5 4 3 2 01
Reserved Register
Select Reserved PAR
Refersh Coverage
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
0
1
0
0
0 1
Register Select
Selsect RCR
Selsect BCR
Selsect DIDR
Setting is ignored
Deep Power-Down
0
1
DPD Enable
DPD Disable (default)
Ignored DPD
All must be set to “0” All must be set to “0”Must be set to “0”
RCR[19] RCR[18] RCR[1] RCR[0]RCR[2]
RCR[4]
A[max:20] A[19:18] A/DQ6
A[17:16], ADQ[15: 7] A/DQ5 A/DQ4 A/DQ3 A/DQ2 A/DQ1 A/DQ0
Full array (default)
None of array
Bottom 1/2 array
Bottom 1/4 array
Bottom 1/8 array
Top 1/2 array
Top 1/4 array
Top 1/8 array
max-20 19-18 17-7
Note:
Reserved bits must be set to zero. Reserved bits not set to zero will affect device functionality. RCR[15:0] will be read back as
written.
8.9.2 Partial Array Refresh (RCR[2:0]) Default = Full Array Refresh
The PAR bits restrict refresh operation to a portion of the total memory array. This feature allows the device to reduce
standby current by refreshing only that part of the memory array required by the host system. The refresh options are
full array, one-half array, one-quarter array, one-eighth array, or none of the array. The mapping of these partitions can
start at either the beginning or the end of the address map.
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8.9.3 Address Patterns for PAR (RCR [4] = 1)
RCR[2]
RCR[1]
RCR[0]
Active Section
Address Space
Size
Density
0
0
0
Full die
000000h–3FFFFFh
4 Meg x 16
64Mb
0
0
1
One-half of die
000000h–1FFFFFh
2 Meg x 16
32Mb
0
1
0
One-quarter of die
000000h–0FFFFFh
1 Meg x 16
16Mb
0
1
1
One-eighth of die
000000h–07FFFFh
0.5 Meg x 16
8Mb
1
0
0
None of die
0
0 Meg x 16
0Mb
1
0
1
One-half of die
200000h–3FFFFFh
2 Meg x 16
32Mb
1
1
0
One-quarter of die
300000h–3FFFFFh
1 Meg x 16
16Mb
1
1
1
One-eighth of die
380000h–3FFFFFh
0.5 Meg x 16
8Mb
8.9.4 Deep Power-Down (RCR[4]) Default = DPD Disabled
The deep power-down bit enables and disables all refresh-related activity. This mode is used if the system does not
require the storage provided by the ADMUX PSRAM device. Any stored data will become corrupted when DPD is
enabled. When refresh activity has been re-enabled, the ADMUX PSRAM device will require 150μs to perform an
initialization procedure before normal operations can resume.
Deep power-down is enabled by setting RCR[4] = 0 and taking CE# HIGH. DPD can be enabled using CRE or the
software sequence to access the RCR. Taking CE# LOW for at least 10μs disables DPD and sets RCR[4] = 1; it is not
necessary to write to the RCR to disable DPD. BCR and RCR values (other than RCR[4]) are preserved during DPD.
8.10 Device Identification Register
The DIDR provides information on the device manufacturer, CellularRAM generation, and the specific device
configuration. This register is read-only.
The DIDR is accessed with CRE HIGH and A[19:18] = 01b, or through the register access software sequence with
ADQ = 0002h on the third cycle.
Device Identification Register Mapping
Bit Field
DIDR[15]
DIDR[14:11]
DIDR[10:8]
DIDR[7:5]
DIDR[4:0]
Field name
Row length
Device version
Device density
CellularRAM generation
Vendor ID
Options
Length
Bit Setting
Version
Bit Setting
Density
Bit Setting
Generation
Bit Setting
Vendor
Bit Setting
256
1b
1st
0000b
64Mb
010b
CR1.5
010b
Winbond
00110b
2nd
0001b
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9. ELECTRICAL CHARACTERISTIC
9.1 Absolute Maximum DC, AC Ratings
Parameter
Min
Max
Unit
Operating temperature (case) Wireless
-40
+85
°C
Storage temperature (plastic)
-55
+150
°C
Soldering temperature and time 10s (solder ball only)
+260
°C
Voltage to any ball except VCC, VCCQ relative to VSS
-0.3
VCCQ +0.3
V
Voltage on VCC supply relative to VSS
-0.20
+2.45
V
Voltage on VCCQ supply relative to VSS
-0.20
+2.45
V
Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at
these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
9.2 Electrical Characteristics and Operating Conditions
Description
Conditions
Symbol
Typical
Min
Max
Unit
Note
Supply voltage
VCC
1.7
1.95
V
I/O supply voltage
VCCQ
1.7
1.95
V
Input high voltage
VIH
VCCQ–0.4
VCCQ+0.2
V
1
Input low voltage
VIL
–0.20
0.4
V
2
Output high voltage
IOH=–0.2mA
VOH
0.8xVCCQ
V
3
Output low voltage
IOL=+0.2mA
VOL
0.2xVCCQ
V
3
Input leakage current
VIN=0 to VCCQ
ILI
1
μA
Output leakage current
OE#=VIH or chip disabled
ILO
1
μA
Operating Current
Description
Conditions
Symbol
Typical
Max
Unit
Note
Asynchronous random
READ/WRITE
VIN = VCCQ or 0V,
Chip enabled,
IOUT=0
ICC1
RC/WC=70ns
-
25
mA
4
Initial access,
burst READ/WRITE
ICC2
133MHz
-
40
mA
4
104MHz
-
35
Continuous burst READ
ICC3R
133MHz
-
35
mA
4
104MHz
-
30
Continuous burst WRITE
ICC3W
133MHz
-
40
mA
4
104MHz
-
35
Standby Current
VIN = VCCQ or 0V,
CE# = VCCQ
ISB
Standard
-
250
μA
5, 6
Notes:
1. Input signals may overshoot to VCCQ + 1.0V for periods less than 2ns during transitions.
2. Input signals may undershoot to VSS – 1.0V for periods less than 2ns during transitions.
3. BCR[5:4] = 01b.
4. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add the current required to
drive output capacitance expected in the actual system.
5. ISB (max) values measured with PAR set to FULL ARRAY and at 85°C. In order to achieve low standby current, all inputs must
be driven to either VCCQ or VSS. ISB might be slightly higher for up to 500ms after power-up, or when entering standby mode.
6. ISB (typ) is the average ISB at 25°C and VCC = VCCQ = 1.8V. This parameter is verified during characterization, and is not 100%
tested.
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9.3 Deep Power-Down Specifications
Description
Conditions
Symbol
Max
Unit
Deep Power-Down
VIN = VCCQ or 0V;
VCC, VCCQ = 1.95V; +85°C
IZZ
10
μA
Note: Typical (TYP) IZZ value applies across all operating temperatures and voltages.
9.4 Partial Array Self Refresh Standby Current
Description
Conditions
Symbol
Array
Partition
Max
Unit
Partial-array refresh
Standby current
VIN = VCCQ or 0V,
CE# = VCCQ
IPAR
Standard power
(no designation)
Full
250
µA
1 / 2
240
1 / 4
235
1 / 8
230
Note:
IPAR (MAX) values measured at 85°C. IPAR might be slightly higher for up to 500ms after changes to the PAR array partition or
when entering standby mode.
9.5 Capacitance
Description
Conditions
Symbol
Min
Max
Unit
Note
Input Capacitance
TC = +25°C; f = 1 MHz;
VIN = 0V
CIN
2.0
6
pF
1
Input/Output Capacitance (A/DQ)
CIO
3.0
6.5
pF
1
Note 1: These parameters are verified in device characterization and are not 100% tested.
9.6 AC Input-Output Reference Waveform
Test Points VCCQ/23
VCCQ/22 Output
Intput
VCCQ
VSSQ
1
Notes:
1. AC test inputs are driven at VCCQ for a logic 1 and VSSQ for a logic 0. Input rise and fall times (10% to 90%) <1.6ns.
2. Input timing begins at VCCQ/2.
3. Output timing ends at VCCQ/2.
9.7 AC Output Load Circuit
DUT
30pF
VCCQ/2
50 Ohm
Test Point
Note:
All tests are performed with the outputs configured for default setting of half drive strength (BCR[5:4] = 01b).
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10. TIMING REQUIREMENTS
10.1 Read, Write Timing Requirements
10.1.1 Asynchronous READ Cycle Timing Requirements
All tests performed with outputs configured for default setting of half drive strength, (BCR[5:4] = 01b).
Parameter
Symbol
Min
Max
Unit
Note
Address access time
tAA
70
ns
ADV# access time
tAADV
70
ns
Address hold from ADV# HIGH
tAVH
2
ns
Address setup to ADV# HIGH
tAVS
5
ns
LB#/UB# access time
tBA
70
ns
LB#/UB# disable to DQ High-Z Output
tBHZ
7
ns
1
Chip select access time
tCO
70
ns
CE# LOW to ADV# HIGH
tCVS
7
ns
Chip disable to DQ and WAIT High-Z output
tHZ
7
ns
1
Output enable to valid output
tOE
20
ns
OE# LOW to WAIT valid
tOEW
1
7.5
ns
Output disable to DQ High-Z output
tOHZ
7
ns
1
Output enable to Low-Z output
tOLZ
3
ns
2
ADV# pulse width
tVP
5
ns
Notes:
1. Low-Z to High-Z timings are tested with AC Output Load Circuit. The High-Z timings measure a 100mV transition from
either VOH or VOL toward VCCQ/2.
2. High-Z to Low-Z timings are tested with the circuit. The Low-Z timings measure a 100mV transition away from the High-Z
(VCCQ/2) level toward either VOH or VOL.
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10.1.2 Burst READ Cycle Timing Requirements
All tests performed with outputs configured for default setting of half drive strength, (BCR[5:4] = 01b).
Parameter
Symbol
133 MHz
104 MHz
Unit
Notes
Min
Max
Min
Max
Address access time (fixed latency)
tAA
70
70
ns
ADV# access time (fixed latency)
tAADV
70
70
ns
Burst to READ access time (variable latency)
tABA
35.5
35.9
ns
CLK to output delay
tACLK
5.5
7
ns
Address hold from ADV# HIGH (fixed latency)
tAVH
2
2
ns
Burst OE# LOW to output delay
tBOE
20
20
ns
CE# HIGH between subsequent burst or mixed-mode operations
tCBPH
5
5
ns
1
Maximum CE# pulse width
tCEM
4
4
µs
1
CLK period
tCLK
7.5
9.62
ns
Chip select access time (fixed latency)
tCO
70
70
ns
CE# setup time to active CLK edge
tCSP
2.5
3
ns
Hold time from active CLK edge
tHD
1.5
2
ns
Chip disable to DQ and WAIT High-Z output
tHZ
7
7
ns
2
CLK rise or fall time
tKHKL
1.2
1.6
ns
CLK to WAIT valid
tKHTL
5.5
7
ns
Output HOLD from CLK
tKOH
2
2
ns
CLK HIGH or LOW time
tKP
3
3
ns
Output disable to DQ High-Z output
tOHZ
7
7
ns
2
Output enable to Low-Z output
tOLZ
3
3
ns
3
Setup time to active CLK edge
tSP
2
3
ns
Notes:
1. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two
conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than 15ns.
2. Low-Z to High-Z timings are tested with the circuit. The High-Z timings measure a 100mV transition from either VOH or VOL
toward VCCQ/2.
3. High-Z to Low-Z timings are tested with the circuit. The Low-Z timings measure a 100mV transition away from the High-Z
(VCCQ/2) level toward either VOH or VOL.
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10.1.3 Asynchronous WRITE Cycle Timing Requirements
Parameter
Symbol
Min
Max
Unit
Note
Address and ADV# LOW setup time
tAS
0
ns
Address HOLD from ADV# going HIGH
tAVH
2
ns
Address setup to ADV# going HIGH
tAVS
5
ns
Address valid to end of WRITE
tAW
70
ns
LB#/UB# select to end of WRITE
tBW
70
ns
CE# HIGH between subsequent asynchronous operations
tCPH
5
ns
CE# LOW to ADV# HIGH
tCVS
7
ns
Chip enable to end of WRITE
tCW
70
ns
Data HOLD from WRITE time
tDH
0
ns
Data WRITE setup time
tDW
20
ns
Chip disable to WAIT High-Z output
tHZ
7
ns
1
ADV# pulse width
tVP
5
ns
ADV# setup to end of WRITE
tVS
70
ns
WRITE pulse width
tWP
45
ns
2
WRITE recovery time
tWR
0
ns
Notes:
1. Low-Z to High-Z timings are tested with AC Output Load Circuit. The High-Z timings measure a 100mV transition from
either VOH or VOL toward VCCQ/2.
2. WE# LOW time must be limited to tCEM (4μs).
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10.1.4 Burst WRITE Cycle Timing Requirements
Parameter
Symbol
133 MHz
104 MHz
Unit
Notes
Min
Max
Min
Max
Address and ADV# LOW setup time
tAS
0
0
ns
1
Address HOLD from ADV# HIGH (fixed latency)
tAVH
2
2
ns
CE# HIGH between subsequent burst or mixed-mode
operations
tCBPH
5
5
ns
2
Maximum CE# pulse width
tCEM
4
4
µs
2
Clock period
tCLK
7.5
9.62
ns
CE# setup to CLK active edge
tCSP
2.5
3
ns
Hold time from active CLK edge
tHD
1.5
2
ns
Chip disable to WAIT High-Z output
tHZ
7
7
ns
3
CLK rise or fall time
tKHKL
1.2
1.6
ns
Clock to WAIT valid
tKHTL
5.5
7
ns
Output HOLD from CLK
tKOH
2
2
ns
CLK HIGH or LOW time
tKP
3
3
ns
Setup time to activate CLK edge
tSP
2
3
ns
Notes:
1. tAS required if tCSP > 20ns.
2. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two conditions:
a) clocked CE# HIGH, or b) CE# HIGH for longer than 15ns.
3. Low-Z to High-Z timings are tested with the circuit. The High-Z timings measure a 100mV transition from either VOH or VOL
toward VCCQ/2.
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10.2 TIMING DIAGRAMS
10.2.1 Initialization Period
Device ready for normal
operation
tPU
VCC, VCCQ=1.7V
VCC (MIN)
10.2.2 DPD Entry and Exit Timing Parameters
CE#
Write
RCR [4] = 0 DPD Enabled
tDPD tPU
DPD Exit Device Initialization Device ready for
normal operation
tDPDX
10.2.3 Initialization Timing Parameters
Description
Symbol
Min
Max
Unit
Initialization period (required before normal operations)
tPU
-
150
μs
10.2.4 Initialization and DPD Timing Parameters
Description
Symbol
Min
Max
Unit
CE# HIGH after Write RCR[4]=0
tDPD
150
-
μs
CE# LOW between DPD Enable and Device Initialization
tDPDX
10
-
μs
DPD Exit to next Operation Command
tPU
-
150
μs
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10.2.5 Asynchronous READ
Valid Output
Valid Address
Valid Address
High-z High-z
High-z
A[max:16]
CE#
A/DQ[15:0]
LB#/UB#
ADV#
OE#
WE#
WAIT
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
Undefined
Don’t Care
tAA
tVP
tCO
tBA
tOE
tAA
tHZ
VOL
VOH
tAVHtAVS
tCVS
tAVS tAVH
tOLZ
tOEW
tBHZ
tOHZ
tHZ
tAADV
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10.2.6 Single Access Burst READ Operation - Variable Latency
Valid Address Valid Output
Valid Address
Undefined
HIGH-Z
READ burst identified
(WE# = HIGH)
HIGH-Z
HIGH-Z
Don't Care
A[max:16]
CE#
A/DQ[15:0]
LB#/UB#
ADV#
OE#
WE#
WAIT
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
CLK VIH
VIL
tSP
tSP
tSP
tSP
tSP tHD
tHD
tHD
tHD
tKP tKP
tHD
tHD
tHZ
tCSP
tCLK
tCEM
tABA
tBOE
tOLZ
tOHZ
tKOH
tKOH
tACLK
tKHTL
tKHTL
tKHKL
VOH
VOL
Note:
Non-default BCR settings: latency code 2 (3 clocks), WAIT active LOW, WAIT asserted during delay.
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10.2.7 Four Word Burst READ Operation-Variable Latency
A[max:16]
CE#
A/DQ[15:0]
LB#/UB#
ADV#
OE#
WE#
WAIT
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
CLK VIH
VIL
HIGH-Z
Valid
Address
Note 2
Note 3
HIGH-Z
HIGH-Z
Undefined
Don't Care
READ burst identified
(WE# = HIGH)
Valid
Address Valid
Output Valid
Output Valid
Output Valid
Output
tSP
tSP
tSP
tSP
tSP
tKP tKP
tHD
tHD
tHD
tHD
tHD
tHD
tHZ
tCSP tABA
tCEM
tBOE
tOLZ
tKOH
tKOH
tKHTL
tKHTL
tOHZ
tCBPH
tACLK
tKHKL tCLK
VOH
VOL
Notes:
1. Non-default BCR settings: latency code 2 (3 clocks), WAIT active LOW, WAIT asserted during delay.
2. WAIT will remain de-asserted even if CE# remains LOW past the end of the defined burst length.
3. A/DQ[15:0] will output undefined data if CE# remains LOW past the end of the defined burst length.
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10.2.8 Single-Access Burst READ Operation-Fixed Latency
A[max:16]
CE#
A/DQ[15:0]
LB#/UB#
ADV#
OE#
WE#
WAIT
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
CLK VIH
VIL
Undefined
READ burst identified
(WE# = HIGH) Don't Care
VOH
VOL
tSP
tSP
tSP
tSP
tSP
tHD
tHD
tCLK
tAVH
tCSP
tAVH
tKHTL tKHTL
tKOH
tKOH
tHD
tOHZ
tOLZ
tBOE
tCEM
tAADV
tCO
tAA
tKHKL
tKP tKP
tHZ
tHD
tACLK
HIGH-Z
HIGH-Z
Valid
Output
Valid
Address
Valid
Address
HIGH-Z
Note:
Non-default BCR settings: fixed latency, latency code 4 (5 clocks), WAIT active LOW, WAIT asserted during delay.
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10.2.9 Four Word Burst READ Operation-Fixed Latency
A[max:16]
CE#
A/DQ[15:0]
LB#/UB#
ADV#
OE#
WE#
WAIT
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
CLK VIH
VIL
UndefinedDon't Care
READ burst identified
(WE# = HIGH)
tAA
tSP
tSP
tSP
tSP
tSP
tHD
tHD
tHD
tHZ
tHD
tKPtKPtCLK
tKHKL
tKHTL
tKHTL
tCSP
tAVH
tAVH
tAADV
tCO
tBOE
tCEM
tOLZ
tKOH
tKOH
tACLK
tCBPH
tOHZ
VOH
VOL
Valid
Output Valid
Output Valid
Output Valid
Output
Note 2
Note 3
HIGH-Z
HIGH-Z
Valid
Address
Valid
Address
HIGH-Z
Notes:
1. Non-default BCR settings: fixed latency, latency code 2 (3 clocks), WAIT active LOW, WAIT asserted during delay.
2. WAIT will remain de-asserted even if CE# remains LOW past the end of the defined burst length.
3. A/DQ[15:0] will output undefined data if CE# remains LOW past the end of the defined burst length.
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10.2.10 Burst READ Terminate at End-of-Row (Wrap Off)
Undefined
Don't Care
A[max:16]
CE#
A/DQ[15:0]
LB#/UB#
ADV#
OE#
WE#
WAIT
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
CLK VIH
VIL
End of Row
Note 2
Valid
Output Valid
Output
tCLK
tHD
tHZ
tHZ
tKHTL
tKOH
HIGH-Z
tCSP
Notes:
1. Non-default BCR settings for burst READ at end of row: fixed or variable latency, WAIT active LOW, WAIT asserted
during delay (shown as solid line).
2. For burst READs, CE# must go HIGH before the second CLK after the WAIT period begins (before the second CLK after
WAIT asserts with BCR[8] = 0, or before the third CLK after WAIT asserts with BCR[8] = 1).
W956D6KBKX
Publication Release Date: Mar. 02, 2017
Revision: A01-001
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10.2.11 Burst READ Row Boundary Crossing
Undefined Don’t Care
End of Row
Valid
Output
Note 2
Valid
Output Valid
Output
Valid
Output
A[max:16]
CE#
A/DQ[15:0]
LB#/UB#
ADV#
OE#
WE#
WAIT
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
VOH
VOL
CLK VIH
VIL
tKHTL
tKOH tKOH
tKHTL
tCLK
Notes:
1. Non-default BCR settings for burst READ at end of row: fixed or variable latency, WAIT active LOW, WAIT asserted
during delay (shown as solid line).
2. WAIT will be asserted LC+1 cycles for variable latency or fixed latency.
W956D6KBKX
Publication Release Date: Mar. 02, 2017
Revision: A01-001
- 44 -
10.2.12 Asynchronous WRITE
A[max:16]
CE#
A/DQ[15:0]
LB#/UB#
ADV#
OE#
WE#
WAIT
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL Don’t Care
HIGH-Z
tAVS tAVH
tCVS
tAVS tAVH
tAW
tDW tDH
tWP
tAS
tBW
tCW
tAS
tAS
tVP
tVS tAW
Valid
Address
Valid
Address Valid
Input
W956D6KBKX
Publication Release Date: Mar. 02, 2017
Revision: A01-001
- 45 -
10.2.13 Burst WRITE Operation-Variable Latency Mode
Undefined
WRITE burst identified
(WE# = LOW) Don't Care
A[max:16]
CE#
A/DQ[15:0]
LB#/UB#
ADV#
OE#
WE#
WAIT
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
CLK VIH
VIL
3
D1
Note 4
Valid
Address
Valid
Address D2 D3 D4
tSP tHD
tSP tHD
tSP tHD
tSP tHD
tAS
3
tAS
3
tAS
tCSP
tSP tHD
tKHKL
tCEM tHD tCBPH
tSP tHD
tKP tKP
tCLK
HIGH-Z
HIGH-Z
Note 2
tKHTL
tKHTL
tKOH
tHZ
Notes:
1. Non-default BCR settings for burst WRITE operation in variable latency mode: latency code 2 (3 clocks), WAIT active
LOW, WAIT asserted during delay, burst length 4, burst wrap enabled.
2. WAIT asserts for LC cycles for both fixed and variable latency. LC = latency code (BCR[13:11]).
3. tAS is required if tCSP > 20ns.
4. CE# must go HIGH before any clock edge following the last word of a defined-length burst.
W956D6KBKX
Publication Release Date: Mar. 02, 2017
Revision: A01-001
- 46 -
10.2.14 Burst WRITE Operation-Fixed Latency Mode
Undefined
WRITE burst identified
(WE# = LOW) Don't Care
A[max:16]
CE#
A/DQ[15:0]
LB#/UB#
ADV#
OE#
WE#
WAIT
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
CLK VIH
VIL
HIGH-Z Note 2
Note 4
HIGH-Z
Valid
Address D2 D3 D0
D1
tCLK tKHKL
tKP tKP
tKHTL tKHTL
tSP tHD
tSP tHD
tSP
tSP
3
tAS
3
tAS
3
tAS
tCSP
tSP tHD
tSP tHD
tCEM tHD tCBPH
tHZ
tKOH
tAVH
tAVH
Valid
Address
Notes:
1. Non-default BCR settings for burst WRITE operation in fixed latency mode: fixed latency, latency code 2 (3 clocks),
WAIT active LOW, WAIT asserted during delay, burst length 4, burst wrap enabled.
2. WAIT asserts for LC cycles for both fixed and variable latency. LC = latency code (BCR[13:11]).
3. tAS is required if tCSP > 20ns.
4. CE# must go HIGH before any clock edge following the last word of a defined-length burst.
W956D6KBKX
Publication Release Date: Mar. 02, 2017
Revision: A01-001
- 47 -
10.2.15 Burst WRITE Terminate at End of Row (Wrap Off)
Undefined
Don't Care
A[max:16]
CE#
A/DQ[15:0]
LB#/UB#
ADV#
OE#
WE#
WAIT
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
CLK VIH
VIL
HIGH-Z
Note 2
END OF ROW
Valid
Input Valid
Input Valid
Input
tCLK
tSP tHD
tKHTL
tKOH
tHZ
tHD tCSP
tHZ
Notes:
1. Non-default BCR settings for burst WRITE at end of row: fixed or variable latency, WAIT active LOW, WAIT asserted
during delay (shown as solid line).
2. For burst WRITEs, CE# must go HIGH before the second CLK after the WAIT period begins (before the second CLK
after WAIT asserts with BCR[8] = 0, or before the third CLK after WAIT asserts with BCR[8] = 1).
W956D6KBKX
Publication Release Date: Mar. 02, 2017
Revision: A01-001
- 48 -
10.2.16 Burst WRITE Row Boundary Crossing
Undefined
Don't Care
A[max:16]
CE#
A/DQ[15:0]
LB#/UB#
ADV#
OE#
WE#
WAIT
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
CLK VIH
VIL
End of row
Note 2
tCLK
tKHTL tKHTL
tKOH
tKOH
Valid
Input Valid
Input Valid
Input Valid
Input Valid
Input
tSP tHD
Notes:
1. Non-default BCR settings for burst WRITE at end of row: fixed or variable latency, WAIT active LOW, WAIT asserted
during delay (shown as solid line).
2. WAIT will be asserted LC cycles for variable latency or fixed latency.
W956D6KBKX
Publication Release Date: Mar. 02, 2017
Revision: A01-001
- 49 -
10.2.17 Burst WRITE Followed by Burst READ
Undefined
Don't Care
A[max:16]
CE#
A/DQ[15:0]
IN/OUT
LB#/UB#
ADV#
OE#
WE#
WAIT
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
CLK VIH
VIL
D2
Valid
Address
Valid
output
Note 2
HIGH-Z HIGH-Z
tCLK
tSP tHD
tSP tHD
tSP
tHD
tSP
tHD
tSP tHD
tSP
tHD
tSP
tHD
tSP tHD
tSP tHD
tHD tCBPH
tCSP tOHZ
tCSP
tKOH
tBOE
tACLK
VOH
VOL
Valid
Address Valid
Output
Valid
Output Valid
Output
Valid
Output
D3
D0 D1
Valid
Address
Valid
Address
tSP tHD
Notes:
1. Non-default BCR settings for burst WRITE followed by burst READ: fixed or variable latency, latency code 2 (3 clocks),
WAIT active LOW, WAIT asserted during delay.
2. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of the following two
conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than 15ns.
W956D6KBKX
Publication Release Date: Mar. 02, 2017
Revision: A01-001
- 50 -
10.2.18 Asynchronous WRITE Followed by Burst READ
Undefined
Don't Care
A[max:16]
CE#
A/DQ[15:0]
LB#/UB#
ADV#
OE#
WE#
WAIT
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
CLK VIH
VIL
Valid
Address Valid
Address
Note 2
HIGH-Z
Valid
Address Valid
Output Valid
Output Valid
Output Valid
Output
Valid
Address VOH
VOL
tAVS tAVH
tCSP
tSP tHD
tSP tHD
tSP tHD
tSP tHD
tSP tHD
tCBPH
tKHTL tACLK
tCLK
tOHZ
tBOE
tAStVP
tAS tBW
tAS
tWC
tWP
tAVS tAVH tDW tDH tKOH
tCW
Data
Notes:
1. Non-default BCR settings for asynchronous WRITE, with ADV# LOW, followed by burst READ: fixed or variable latency,
latency code 2 (3 clocks), WAIT active LOW, WAIT asserted during delay.
2. When the device is transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. CE#
can stay LOW when the device is transitioning to fixed-latency burst READs. A refresh opportunity must be provided
every tCEM. A refresh opportunity is satisfied by either of the following two conditions: a) clocked CE# HIGH, or b) CE#
HIGH for longer than 15ns.
W956D6KBKX
Publication Release Date: Mar. 02, 2017
Revision: A01-001
- 51 -
10.2.19 Burst READ Followed by Asynchronous WRITE
Undefined
Don't Care
A[max:16]
CE#
A/DQ[15:0]
LB#/UB#
ADV#
OE#
WE#
WAIT
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
CLK VIH
VIL
HIGH-Z HIGH-Z
READ burst identified
(WE# = HIGH)
VOH
VOL
VIH
VIL
Note 2
tCLK
tCSP
tBOE
tOLZ
tKOH
tKOH
tACLK
tKHTL
tKHTL
tSP tHD
tSP tHD
tSP tHD
tSP tHD
tSP
tHD tHZ tAStCBPH
tOHZ
tHD
tAS
tAVS
tAS tVS
tVP
tAW
tCW
tBW
tWP tWPH
tAVHtAVS tDW tDH
tAVH
Valid
Address Valid
Address Valid
Input
Valid
Output
Valid
Address Valid
Address
Notes:
1. Non-default BCR settings for burst READ followed by asynchronous WRITE using ADV#: fixed or variable latency,
latency code 2 (3 clocks), WAIT active LOW, WAIT asserted during delay.
2. When the device is transitioning between asynchronous and variable-latency burst operations, CE# must go HIGH. CE#
can stay LOW when the device is transitioning from fixed-latency burst READs; asynchronous operation begins at the
falling edge of ADV#. A refresh opportunity must be provided every tCEM. A refresh opportunity is satisfied by either of
the following two conditions: a) clocked CE# HIGH, or b) CE# HIGH for longer than 15ns.
W956D6KBKX
Publication Release Date: Mar. 02, 2017
Revision: A01-001
- 52 -
10.2.20 Asynchronous WRITE Followed by Asynchronous READ
A[max:16]
CE#
A/DQ[15:0]
LB#/UB#
ADV#
OE#
WE#
WAIT
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VOH
VOL
Valid
Address
Valid
Output
Valid
Address
Valid
Address
Valid
Address
Valid
Input
HIGH-Z
Note 1
Undefined
Don't Care
tAVS tAVH
tCVS
tAVS tAVH
tAVS tAVH
tCVS
tCPH
tOLZ tOHZ
tOEW
tAVS tAVH
tAS tAW
tVS
tVP
tAS
tBW
tCW
tWP
tAS
tDW tDH
tAW tAA
VOH
VOL
tHZ
tOE
tHZ
tCO
tBA
tAADV
tAA
tWR tVP
tBHZ
Note:
1. When configured for synchronous mode (BCR[15] = 0), CE# must remain HIGH for at least 5ns (tCPH) to schedule the
appropriate refresh interval. Otherwise, tCPH is only required after CE#-controlled WRITEs.
W956D6KBKX
Publication Release Date: Mar. 02, 2017
Revision: A01-001
- 53 -
11. PACKAGE SPECIFICATION
Package Outline WFBGA 49 Balls (4x4 mm2, Ball pitch: 0.5mm)
Note:
1. Ball land:0.34mm, Ball opening:0.24mm,
PCB Ball land suggested 0.24mm
W956D6KBKX
Publication Release Date: Mar. 02, 2017
Revision: A01-001
- 54 -
12. REVISION HISTORY
Versio
n
Date
Page
Description
A01-001
Mar. 02, 2017
All
Initial formally datasheet
