ADC088S052CIMTX/NOPB - NATIONAL SEMICONDUCTOR

8 9

CS SCLK

VADOUT

AGND DIN

IN0 VD

IN1 DGND

IN2 IN7

IN3 IN6

IN4 IN5

ADC088S052

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ADC088S052 8-Channel, 200 ksps to 500 ksps, 8-Bit A/D Converter

Check for Samples: ADC088S052

1FEATURES DESCRIPTION

The ADC088S052 is a low-power, eight-channel

23• Eight Input Channels CMOS 8-bit analog-to-digital converter specified for

• Variable Power Management conversion throughput rates of 200 ksps to 500 ksps.

• Independent Analog and Digital Supplies The converter is based on a successive-

approximation register architecture with an internal

• SPI™/ QSPI™/MICROWIRE/DSP Compatible track-and-hold circuit. It can be configured to accept

• Packaged in 16-Lead TSSOP up to eight input signals at inputs IN0 through IN7.

The output serial data is straight binary and is

APPLICATIONS compatible with several standards, such as SPI™,

• Automotive Navigation QSPI™, MICROWIRE, and many common DSP

• Portable Systems serial interfaces.

• Medical Instruments The ADC088S052 may be operated with independent

• Mobile Communications analog and digital supplies. The analog supply (VA)

can range from +2.7V to +5.25V, and the digital

• Instrumentation and Control Systems supply (VD) can range from +2.7V to VA. Normal

power consumption using a +3V or +5V supply is 1.2

KEY SPECIFICATIONS mW and 6.5 mW, respectively. The power-down

• Conversion Rate: 200 ksps to 500 ksps feature reduces the power consumption to 0.03 µW

using a +3V supply and 0.15 µW using a +5V supply.

• DNL (VA= VD= 2.7V to 5.0V): ±0.2 LSB (Max) The ADC088S052 is packaged in a 16-lead TSSOP

• INL (VA= VD= 2.7V to 5.0V): ±0.2 LSB (Max) package. Operation over the extended industrial

• Power Consumption temperature range of −40°C to +105°C is ensured.

– 3V Supply: 1.2 mW (Typ)

– 5V Supply: 6.5 mW (Typ)

Connection Diagram

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2SPI, QSPI are trademarks of Motorola, Inc..

3All other trademarks are the property of their respective owners.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

IN0

IN7

MUX T/H

ADC088S052 SCLK

AGND

DGND

DIN

DOUT

CONTROL

LOGIC

8-BIT

SUCCESSIVE

APPROXIMATION

ADC

AGND

ADC088S052

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Block Diagram

PIN DESCRIPTIONS AND EQUIVALENT CIRCUITS

Pin No. Symbol Equivalent Circuit Description

ANALOG I/O

4 - 11 IN0 to IN7 Analog inputs. These signals can range from 0V to VREF.

DIGITAL I/O

Digital clock input. The specified performance range of frequencies

16 SCLK for this input is 3.2 MHz to 8 MHz. This clock directly controls the

conversion and readout processes.

Digital data output. The output samples are clocked out of this pin on

15 DOUT the falling edges of the SCLK pin.

Digital data input. The ADC088S052's Control Register is loaded

14 DIN through this pin on rising edges of the SCLK pin.

Chip select. On the falling edge of CS, a conversion process begins.

1 CS Conversions continue as long as CS is held low.

POWER SUPPLY

Positive analog supply pin. This voltage is also used as the

reference voltage. This pin should be connected to a quiet +2.7V to

2 VA+5.25V source and bypassed to GND with 1 µF and 0.1 µF

monolithic ceramic capacitors located within 1 cm of the power pin.

Positive digital supply pin. This pin should be connected to a +2.7V

13 VDto VAsupply, and bypassed to GND with a 0.1 µF monolithic ceramic

capacitor located within 1 cm of the power pin.

3 AGND The ground return for the analog supply and signals.

12 DGND The ground return for the digital supply and signals.

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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

Absolute Maximum Ratings(1)(2)

Analog Supply Voltage VA−0.3V to 6.5V

Digital Supply Voltage VD−0.3V to VA+ 0.3V, max 6.5V

Voltage on Any Pin to GND −0.3V to VA+0.3V

Input Current at Any Pin(3) ±10 mA

Package Input Current(3) ±20 mA

Power Dissipation at TA= 25°C See(4)

Human Body Model 2500V

ESD Susceptibility(5) Machine Model 250V

For soldering specifications see SNOA549

Junction Temperature +150°C

Storage Temperature −65°C to +150°C

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the

Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may

degrade when the device is not operated under the listed test conditions.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and

specifications.

(3) When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND or VIN > VAor VD), the current at that pin should be

limited to 10 mA. The 20 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies

with an input current of 10 mA to two.

(4) The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by

TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula

PDMAX = (TJmax −TA)/θJA. In the 16-pin TSSOP, θJA is 96°C/W, so PDMAX = 1,200 mW at 25°C and 625 mW at the maximum

operating ambient temperature of 105°C. Note that the power consumption of this device under normal operation is a maximum of 12

mW. The values for maximum power dissipation listed above will be reached only when the ADC088S052 is operated in a severe fault

condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is reversed).

Obviously, such conditions should always be avoided.

(5) Human body model is 100 pF capacitor discharged through a 1.5 kΩresistor. Machine model is 220 pF discharged through ZERO ohms

Operating Ratings(1)(2)

Operating Temperature −40°C ≤TA≤+105°C

VASupply Voltage +2.7V to +5.25V

VDSupply Voltage +2.7V to VA

Digital Input Voltage 0V to VA

Analog Input Voltage 0V to VA

Clock Frequency 50 kHz to 16 MHz

(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for

which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the

Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may

degrade when the device is not operated under the listed test conditions.

(2) All voltages are measured with respect to GND = 0V, unless otherwise specified.

Package Thermal Resistance

Package θJA

16-lead TSSOP on 4-layer, 2 oz. PCB 96°C / W

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ADC088S052 Converter Electrical Characteristics(1)

The following specifications apply for VA= VD= +2.7V to +5.25V, AGND = DGND = 0V, fSCLK = 3.2 MHz to 8 MHz, fSAMPLE =

200 ksps to 500 ksps, and CL= 50pF, unless otherwise noted. Boldface limits apply for TA= TMIN to TMAX: all other limits TA

= 25°C.

Symbol Parameter Conditions Typical Limits(2) Units

STATIC CONVERTER CHARACTERISTICS

Resolution with No Missing Codes 8Bits

Integral Non-Linearity

INL ±0.05 ±0.2 LSB (max)

(End Point Method)

DNL Differential Non-Linearity ±0.06 ±0.2 LSB (min)

VOFF Offset Error +0.6 ±0.7 LSB (max)

OEM Offset Error Match ±0.02 ±0.2 LSB (max)

FSE Full Scale Error +0.5 ±0.6 LSB (max)

FSEM Full Scale Error Match ±0.01 ±0.2 LSB (max)

DYNAMIC CONVERTER CHARACTERISTICS

FPBW Full Power Bandwidth (−3dB) 8 MHz

SINAD Signal-to-Noise Plus Distortion Ratio fIN = 40.2 kHz, −0.02 dBFS 49.6 49.2 dB (min)

SNR Signal-to-Noise Ratio fIN = 40.2 kHz, −0.02 dBFS 49.6 49.3 dB (min)

THD Total Harmonic Distortion fIN = 40.2 kHz, −0.02 dBFS −70.6 −63.1 dB (max)

SFDR Spurious-Free Dynamic Range fIN = 40.2 kHz, −0.02 dBFS 68.1 64.8 dB (min)

ENOB Effective Number of Bits fIN = 40.2 kHz 7.95 7.88 Bits (min)

ISO Channel-to-Channel Isolation fIN = 20 kHz 67.3 dB

Intermodulation Distortion, Second fa= 19.5 kHz, fb= 20.5 kHz −75.0 dB

Order Terms

IMD Intermodulation Distortion, Third Order fa= 19.5 kHz, fb= 20.5 kHz −69.4 dB

Terms

ANALOG INPUT CHARACTERISTICS

VIN Input Range 0 to VAV

IDCL DC Leakage Current ±1 µA (max)

Track Mode 33 pF

CINA Input Capacitance Hold Mode 3 pF

DIGITAL INPUT CHARACTERISTICS

VA= VD= +2.7V to +3.6V 2.1 V (min)

VIH Input High Voltage VA= VD= +4.75V to +5.25V 2.4 V (min)

VIL Input Low Voltage 0.8 V (max)

IIN Input Current VIN = 0V or VD±0.01 ±1 µA (max)

CIND Digital Input Capacitance 2 4pF (max)

DIGITAL OUTPUT CHARACTERISTICS

VOH Output High Voltage ISOURCE = 200 µA, VD−0.5 V (min)

VOL Output Low Voltage ISINK = 200 µA to 1.0 mA, 0.4 V (max)

IOZH, IOZL Hi-Impedance Output Leakage Current ±1 µA (max)

COUT Hi-Impedance Output Capacitance(1) 24pF (max)

Output Coding Straight (Natural) Binary

(1) The min/max specification limits are specified by design, test, or statistical analysis.

(2) Tested limits are ensured to TI's AOQL (Average Outgoing Quality Level).

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ADC088S052 Converter Electrical Characteristics(1) (continued)

The following specifications apply for VA= VD= +2.7V to +5.25V, AGND = DGND = 0V, fSCLK = 3.2 MHz to 8 MHz, fSAMPLE =

200 ksps to 500 ksps, and CL= 50pF, unless otherwise noted. Boldface limits apply for TA= TMIN to TMAX: all other limits TA

= 25°C.

Symbol Parameter Conditions Typical Limits(2) Units

POWER SUPPLY CHARACTERISTICS (CL= 10 pF)

2.7 V (min)

VA, VDAnalog and Digital Supply Voltages VA≥VD5.25 V (max)

VA= VD= +2.7V to +3.6V, 0.4 1.0 mA (max)

fSAMPLE = 500 kSPS, fIN = 40 kHz

Total Supply Current

Normal Mode ( CS low) VA= VD= +4.75V to +5.25V, 1.3 1.7 mA (max)

fSAMPLE = 500 kSPS, fIN = 40 kHz

IA+ IDVA= VD= +2.7V to +3.6V, 10 nA

fSCLK = 0 ksps

Total Supply Current

Shutdown Mode (CS high) VA= VD= +4.75V to +5.25V, 30 nA

fSCLK = 0 ksps

VA= VD= +3.0V 1.2 3.0 mW (max)

fSAMPLE = 500 kSPS, fIN = 40 kHz

Power Consumption

Normal Mode ( CS low) VA= VD= +5.0V 6.5 8.5 mW (max)

fSAMPLE = 500 kSPS, fIN = 40 kHz

PCVA= VD= +3.0V 0.03 µW

fSCLK = 0 ksps

Power Consumption

Shutdown Mode (CS high) VA= VD= +5.0V 0.15 µW

fSCLK = 0 ksps

AC ELECTRICAL CHARACTERISTICS

fSCLKMIN Minimum Clock Frequency 0.8 3.2 MHz (min)

fSCLK Maximum Clock Frequency 16 8MHz (max)

50 200 ksps (min)

Sample Rate

fSContinuous Mode 1000 500 ksps (max)

tCONVERT Conversion (Hold) Time 13 SCLK cycles

30 40 % (min)

DC SCLK Duty Cycle 70 60 % (max)

tACQ Acquisition (Track) Time 3SCLK cycles

Throughput Time Acquisition Time + Conversion Time 16 SCLK cycles

tAD Aperture Delay 4 ns

ADC088S052 Timing Specifications

The following specifications apply for VA= VD= +2.7V to +5.25V, AGND = DGND = 0V, fSCLK = 3.2 MHz to 8 MHz, fSAMPLE =

200 ksps to 500 ksps, and CL= 50pF. Boldface limits apply for TA= TMIN to TMAX: all other limits TA= 25°C.

Symbol Parameter Conditions Typical Limits(1) Units

tCSH CS Hold Time after SCLK Rising Edge 0 10 ns (min)

CS Setup Time prior to SCLK Rising

tCSS 510 ns (min)

Edge

tEN CS Falling Edge to DOUT enabled 5 30 ns (max)

DOUT Access Time after SCLK Falling

tDACC 17 27 ns (max)

Edge

DOUT Hold Time after SCLK Falling

tDHLD 4 ns (typ)

Edge

DIN Setup Time prior to SCLK Rising

tDS 310 ns (min)

Edge

tDH DIN Hold Time after SCLK Rising Edge 3 10 ns (min)

tCH SCLK High Time 0.4 x tSCLK ns (min)

tCL SCLK Low Time 0.4 x tSCLK ns (min)

(1) Tested limits are ensured to TI's AOQL (Average Outgoing Quality Level).

Product Folder Links: ADC088S052

tCSH

SCLK

tCSS

tCONVERT

tACQ tCH

tCL

tEN

tDH

tDS

FOUR ZEROS DB6

DONTC DONTC ADD2 ADD1 ADD0 DONTC DONTC DONTC

DB7 DB5 DB4 B1

87654321

DB0

DIN

DOUT

SCLK

tDIS

13 14

tDACC

tDHLD

FOUR ZEROS

15 16

8 9 10 11 12 13 14 15 16

Track Hold

Power Up

ADD2 ADD1 ADD0

DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0

DIN

DOUT

SCLK

Control register

1 2 3 4 5 6 7

ADD2 ADD1 ADD0

DB7 DB6 DB5

Power

Down

Power Up

Track Hold

ADC088S052

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ADC088S052 Timing Specifications (continued)

The following specifications apply for VA= VD= +2.7V to +5.25V, AGND = DGND = 0V, fSCLK = 3.2 MHz to 8 MHz, fSAMPLE =

200 ksps to 500 ksps, and CL= 50pF. Boldface limits apply for TA= TMIN to TMAX: all other limits TA= 25°C.

Symbol Parameter Conditions Typical Limits(1) Units

DOUT falling 2.4 20 ns (max)

CS Rising Edge to DOUT High-

tDIS Impedance DOUT rising 0.9 20 ns (max)

Timing Diagrams

Figure 1. ADC088S052 Operational Timing Diagram

Figure 2. ADC088S052 Serial Timing Diagram

Figure 3. SCLK and CS Timing Parameters

Specification Definitions

ACQUISITION TIME is the time required for the ADC to acquire the input voltage. During this time, the hold

capacitor is charged by the input voltage.

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APERTURE DELAY is the time between the fourth falling edge of SCLK and the time when the input signal is

internally acquired or held for conversion.

CONVERSION TIME is the time required, after the input voltage is acquired, for the ADC to convert the input

voltage to a digital word.

CHANNEL-TO-CHANNEL ISOLATION is resistance to coupling of energy from one channel into another

channel.

CROSSTALK is the coupling of energy from one channel into another channel. This is similar to Channel-to-

Channel Isolation, except for the sign of the data.

DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1

LSB.

DUTY CYCLE is the ratio of the time that a repetitive digital waveform is high to the total time of one period. The

specification here refers to the SCLK.

EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise

and Distortion or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02 and says that the converter is equivalent to a

perfect ADC of this (ENOB) number of bits.

FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental

drops 3 dB below its low frequency value for a full scale input.

FULL SCALE ERROR (FSE) is a measure of how far the last code transition is from the ideal 1½ LSB below

VREF+and is defined as:

VFSE = Vmax + 1.5 LSB – VREF+(1)

where Vmax is the voltage at which the transition to the maximum code occurs. FSE can be expressed in Volts,

LSB or percent of full scale range.

GAIN ERROR is the deviation of the last code transition (111...110) to (111...111) from the ideal (VREF - 1.5

LSB), after adjusting for offset error.

INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from

negative full scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last code

transition). The deviation of any given code from this straight line is measured from the center of that code value.

INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two

sinusoidal frequencies being applied to an individual ADC input at the same time. It is defined as the ratio of the

power in the second and third order intermodulation products to the power in one of the original frequencies.

Second order products are fa± fb, where faand fbare the two sine wave input frequencies. Third order products

are (2fa± fb) and (fa± 2fb). IMD is usually expressed in dB.

MISSING CODES are those output codes that will never appear at the ADC outputs. These codes cannot be

reached with any input value. The ADC088S052 is specified not to have any missing codes.

OFFSET ERROR is the deviation of the first code transition (000...000) to (000...001) from the ideal (i.e. GND +

0.5 LSB).

SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms

value of the sum of all other spectral components below one-half the sampling frequency, not including

harmonics or d.c.

SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the

input signal to the rms value of all of the other spectral components below half the clock frequency, including

harmonics but excluding d.c.

SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the rms values of the

input signal and the peak spurious signal where a spurious signal is any signal present in the output spectrum

that is not present at the input, including harmonics but excluding d.c.

TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dBc, of the rms total of the first five harmonic

components at the output to the rms level of the input signal frequency as seen at the output. THD is calculated

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‡A

A++A

logTHD = 20 

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(2)

where Af1 is the RMS power of the input frequency at the output and Af2 through Af6 are the RMS power in the

first 5 harmonic frequencies.

THROUGHPUT TIME is the minimum time required between the start of two successive conversions. It is the

acquisition time plus the conversion and read out times. In the case of the ADC088S052, this is 16 SCLK

periods.

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Typical Performance Characteristics

VA= VD= +5.0V, TA= +25°C, fSAMPLE = 500 ksps, fSCLK = 8 MHz, fIN = 40.2 kHz unless otherwise stated.

DNL DNL

Figure 4. Figure 5.

INL INL

Figure 6. Figure 7.

DNL vs. Supply INL vs. Supply

Figure 8. Figure 9.

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Typical Performance Characteristics (continued)

VA= VD= +5.0V, TA= +25°C, fSAMPLE = 500 ksps, fSCLK = 8 MHz, fIN = 40.2 kHz unless otherwise stated.

SNR vs. Supply THD vs. Supply

Figure 10. Figure 11.

ENOB vs. Supply DNL vs. VDwith VA= 5.0 V

Figure 12. Figure 13.

INL vs. VDwith VA= 5.0 V DNL vs. SCLK Duty Cycle

Figure 14. Figure 15.

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Typical Performance Characteristics (continued)

VA= VD= +5.0V, TA= +25°C, fSAMPLE = 500 ksps, fSCLK = 8 MHz, fIN = 40.2 kHz unless otherwise stated.

INL vs. SCLK Duty Cycle SNR vs. SCLK Duty Cycle

Figure 16. Figure 17.

THD vs. SCLK Duty Cycle ENOB vs. SCLK Duty Cycle

Figure 18. Figure 19.

DNL vs. SCLK INL vs. SCLK

Figure 20. Figure 21.

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Typical Performance Characteristics (continued)

VA= VD= +5.0V, TA= +25°C, fSAMPLE = 500 ksps, fSCLK = 8 MHz, fIN = 40.2 kHz unless otherwise stated.

SNR vs. SCLK THD vs. SCLK

Figure 22. Figure 23.

ENOB vs. SCLK DNL vs. Temperature

Figure 24. Figure 25.

INL vs. Temperature SNR vs. Temperature

Figure 26. Figure 27.

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Typical Performance Characteristics (continued)

VA= VD= +5.0V, TA= +25°C, fSAMPLE = 500 ksps, fSCLK = 8 MHz, fIN = 40.2 kHz unless otherwise stated.

THD vs. Temperature ENOB vs. Temperature

Figure 28. Figure 29.

SNR vs. Input Frequency THD vs. Input Frequency

Figure 30. Figure 31.

ENOB vs. Input Frequency Power Consumption vs. SCLK

Figure 32. Figure 33.

Product Folder Links: ADC088S052

IN0

MUX

AGND

SAMPLING

CAPACITOR

SW1

+CONTROL

LOGIC

CHARGE

REDISTRIBUTION

DAC

SW2

IN7

VA/2

IN0

MUX

AGND

SAMPLING

CAPACITOR

SW1

+CONTRO

LOGI

CHARGE

REDISTRIBUTION

DAC

VA/2

SW2

IN7

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Functional Description

The ADC088S052 is a successive-approximation analog-to-digital converter designed around a charge-

redistribution digital-to-analog converter.

ADC088S052 OPERATION

Simplified block diagrams of the ADC088S052 in both track and hold operation are shown in Figure 34 and

Figure 35 respectively. In Figure 34, the ADC088S052 is in track mode: switch SW1 connects the sampling

capacitor to one of eight analog input channels through the multiplexer, and SW2 balances the comparator

inputs. The ADC088S052 is in this state for the first three SCLK cycles after CS is brought low.

Figure 35 shows the ADC088S052 in hold mode: switch SW1 connects the sampling capacitor to ground,

maintaining the sampled voltage, and switch SW2 unbalances the comparator. The control logic then instructs

the charge-redistribution DAC to add or subtract fixed amounts of charge to or from the sampling capacitor until

the comparator is balanced. When the comparator is balanced, the digital word supplied to the DAC is the digital

representation of the analog input voltage. The ADC088S052 is in this state for the last thirteen SCLK cycles

after CS is brought low.

Figure 34. ADC088S052 in Track Mode

Figure 35. ADC088S052 in Hold Mode

SERIAL INTERFACE

An operational timing diagram and a serial interface timing diagram for the ADC088S052 are shown in Timing

Diagrams section. CS, chip select, initiates conversions and frames the serial data transfers. SCLK (serial clock)

controls both the conversion process and the timing of serial data. DOUT is the serial data output pin, where a

conversion result is sent as a serial data stream, MSB first. Data to be written to the ADC088S052's Control

A serial frame is initiated on the falling edge of CS and ends on the rising edge of CS. Each frame must contain

an integer multiple of 16 rising SCLK edges. The ADC's DOUT pin is in a high impedance state when CS is high

and is active when CS is low. Thus, CS acts as an output enable. Similarly, SCLK is internally gated off when CS

is brought high.

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During the first 3 cycles of SCLK, the ADC is in the track mode, acquiring the input voltage. For the next 13

SCLK cycles the conversion is accomplished and the data is clocked out. SCLK falling edges 1 through 4 clock

out leading zeros, falling edges 5 through 12 clock out the conversion result, MSB first, and falling edges 13

through 16 clock out trailing zeros. If there is more than one conversion in a frame (continuous conversion

mode), the ADC will re-enter the track mode on the falling edge of SCLK after the N*16th rising edge of SCLK

and re-enter the hold/convert mode on the N*16+4th falling edge of SCLK. "N" is an integer value.

The ADC088S052 enters track mode under three different conditions. In Figure 1, CS goes low with SCLK high

and the ADC enters track mode on the first falling edge of SCLK. In the second condition, CS goes low with

SCLK low. Under this condition, the ADC automatically enters track mode and the falling edge of CS is seen as

the first falling edge of SCLK. In the third condition, CS and SCLK go low within the times defined by tCSU and

tCLH. While there is no timing restriction with respect to the rising edges of CS and SCLK, it is best to strictly

observe the minimum tCSU and TCLH times given in the Timing Specifications to prevent uncertainty as to when

date begins clocking in at DIN.

While a conversion is in progress, the address of the next input for conversion is clocked into a control register

through the DIN pin on the first 8 rising edges of SCLK after the fall of CS. See Table 1 Table 2 Table 3. That is,

the address for the NEXT conversion to be run is loaded at the beginning of the current conversion.

There is no need to incorporate a power-up delay or dummy conversion as the ADC088S052 is able to acquire

the input signal to full resolution in the first conversion immediately following power-up. The first conversion result

after power-up will be that of IN0.

Table 1. Control Register Bits

Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

DONTC DONTC ADD2 ADD1 ADD0 DONTC DONTC DONTC

Table 2. Control Register Bit Descriptions

Bit #: Symbol: Description

7, 6, 2, 1, 0 DONTC Don't care. The values of these bits do not affect the device.

5 ADD2 These three bits determine which input channel will be sampled and converted at the next

conversion cycle. The mapping between codes and channels is shown in Table 3.

4 ADD1

3 ADD0

Table 3. Input Channel Selection

ADD2 ADD1 ADD0 Input Channel

0 0 0 IN0 (Default)

0 0 1 IN1

0 1 0 IN2

0 1 1 IN3

1 0 0 IN4

1 0 1 IN5

1 1 0 IN6

1 1 1 IN7

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VIN

30 pF

3 pF

Conversion Phase - Switch Open

Track Phase - Switch Closed

0V +VA - 1.5 LSB

0.5 LSB ANALOG INPUT

1 LSB = VA/256

ADC CODE

111...111

111...110

111...000

011...111

000...010

000...001

000...000

ADC088S052

SNAS340F –SEPTEMBER 2005–REVISED MARCH 2013

www.ti.com

ADC088S052 TRANSFER FUNCTION

The output format of the ADC088S052 is straight binary. Code transitions occur midway between successive

integer LSB values. The LSB width for the ADC088S052 is VA/ 256. The ideal transfer characteristic is shown in

Figure 36. The transition from an output code of 0000 0000 to a code of 0000 0001 is at 1/2 LSB, or a voltage of

VA/ 512. Other code transitions occur at steps of one LSB.

Figure 36. Ideal Transfer Characteristic

ANALOG INPUTS

An equivalent circuit for one of the ADC088S052's input channels is shown in Figure 37. Diodes D1 and D2

provide ESD protection for the analog inputs. The operating range for the analog inputs is 0 V to VA. Going

beyond this range will cause the ESD diodes to conduct and result in erratic operation. For this reason, these

ESD diodes should NOT be used to clamp the input signal.

The capacitor C1 in Figure 37 has a typical value of 3 pF and is mainly the package pin capacitance. Resistor R1

is the on resistance of the multiplexer and track / hold switch and is typically 500 ohms. Capacitor C2 is the

ADC088S052 sampling capacitor, and is typically 30 pF. The ADC088S052 will deliver best performance when

driven by a low-impedance source (less than 100 ohms). This is especially important when using the

ADC088S052 to sample dynamic signals. Also important when sampling dynamic signals is a band-pass or low-

pass filter which reduces harmonics and noise in the input.

Figure 37. Equivalent Input Circuit

DIGITAL INPUTS AND OUTPUTS

The ADC088S052's digital inputs (SCLK, CS, and DIN) have an operating range of 0 V to VA. They are not prone

to latch-up and may be asserted before the digital supply (VD) without any risk. The digital output (DOUT)

operating range is controlled by VD. The output high voltage is VD- 0.5V (min) while the output low voltage is

0.4V (max).

Product Folder Links: ADC088S052

IN0

IN7

.MICROPROCESSOR

DSP

SCLK

DIN

DOUT

AGND

ADC088S052

LP2950 5V

0.1 PF1.0 PF0.1 PF1 PF0.1 PF

DGND

1.0 PF

51:

22:

INPUT

1 nF

ADC088S052

www.ti.com

SNAS340F –SEPTEMBER 2005–REVISED MARCH 2013

APPLICATIONS INFORMATION

TYPICAL APPLICATION CIRCUIT

A typical application is shown in Figure 38. The split analog and digital supply pins are both powered, in this

example, by the TI LP2950 low-dropout voltage regulator. The analog supply is bypassed with a capacitor

network located close to the ADC088S052. The digital supply is separated from the analog supply by an isolation

resistor and bypassed with additional capacitors. The ADC088S052 uses the analog supply (VA) as its reference

voltage, so it is very important that VAbe kept as clean as possible. Due to the low power requirements of the

ADC088S052, it is also possible to use a precision reference as a power supply.

To minimize the error caused by the changing input capacitance of the ADC088S052, a capacitor is connected

from each input pin to ground. The capacitor, which is much larger than the input capacitance of the

ADC088S052 when in track mode, provides the current to quickly charge the sampling capacitor of the

ADC088S052. An isolation resistor is added to isolate the load capacitance from the input source.

Figure 38. Typical Application Circuit

POWER SUPPLY CONSIDERATIONS

There are three major power supply concerns with this product: power supply sequencing, power management,

and the effect of digital supply noise on the analog supply.

Power Supply Sequence

The ADC088S052 is a dual-supply device. The two supply pins share ESD resources, so care must be exercised

to ensure that the power is applied in the correct sequence. To avoid turning on the ESD diodes, the digital

supply (VD) cannot exceed the analog supply (VA) by more than 300 mV, not even on a transient basis.

Therefore, VAmust ramp up before or concurrently with VD.

Power Management

The ADC088S052 is fully powered-up whenever CS is low and fully powered-down whenever CS is high, with

one exception. If operating in continuous conversion mode, the ADC088S052 automatically enters power-down

mode between SCLK's 16th falling edge of a conversion and the SCLK's 1st falling edge of the subsequent

conversion (see Figure 1).

In continuous conversion mode, the ADC088S052 can perform multiple conversions back to back. Each

conversion requires 16 SCLK cycles and the ADC088S052 will perform conversions continuously as long as CS

is held low. Continuous mode offers maximum throughput.

Product Folder Links: ADC088S052

uPN +

tN + tS

tN + tSuPS

PC =

ADC088S052

SNAS340F –SEPTEMBER 2005–REVISED MARCH 2013

www.ti.com

In burst mode, the user may trade off throughput for power consumption by performing fewer conversions per

unit time. This means spending more time in power-down mode and less time in normal mode. By utilizing this

technique, the user can achieve very low sample rates while still utilizing an SCLK frequency within the electrical

specifications. The Power Consumption vs. SCLK curve in the Typical Performance Characteristics section

shows the typical power consumption of the ADC088S022 in the continuous conversion mode. Burst mode

power is calculated as shown below:

Power Consumption Equation

where

• PCis average power consumption

• (tN) is the time in the normal (continuous conversion) mode

• tSis the time in shut down mode

• PNis the power consumption in the normal mode

• PSis the power consumption in the shutdown mode

Power Supply Noise Considerations

The charging of any output load capacitance requires current from the digital supply, VD. The current pulses

required from the supply to charge the output capacitance will cause voltage variations on the digital supply. If

these variations are large enough, they could degrade SNR and SINAD performance of the ADC. Furthermore, if

the analog and digital supplies are tied directly together, the noise in the on-chip digital supply will be coupled

directly into the analog supply, causing greater performance degradation than would noise on the digital supply

alone. Similarly, discharging the output capacitance when the digital output goes from a logic high to a logic low

will dump current into the die substrate. Load discharge currents will cause "ground bounce" noise in the

substrate that will degrade noise performance if that current is large enough. The larger the output capacitance,

the more current flows through the die substrate and the greater the noise coupled into the analog channel.

The first solution to keeping digital noise out of the analog supply is to decouple the analog and digital supplies

from each other or use separate supplies for them. To keep noise out of the digital supply, keep the output load

capacitance as small as practical. If the load capacitance is greater than 50 pF, use a 100 Ωseries resistor at

the ADC output, located as close to the ADC output pin as practical. This will limit the charge and discharge

current of the output capacitance and maintain noise performance. Since the series resistor and the load

capacitance form a low frequency pole, verify signal integrity once the series resistor has been added.

LAYOUT AND GROUNDING

Capacitive coupling between the noisy digital circuitry and the sensitive analog circuitry can lead to poor

performance. The solution is to keep the analog circuitry separated from the digital circuitry and keep the clock

line as short as possible.

Digital circuits create substantial supply and ground current transients. The logic noise generated could have

significant impact upon system noise performance. To avoid performance degradation of the ADC088S052 due

to supply noise, do not use the same supply for the ADC088S052 that is used for digital logic.

Generally, analog and digital lines should cross each other at 90° to avoid crosstalk. However, to maximize

accuracy in mixed signal systems, avoid crossing analog and digital lines altogether. It is important to keep clock

lines as short as possible and isolated from ALL other lines, including other digital lines. In addition, the clock line

should also be treated as a transmission line and be properly terminated.

The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input.

Any external component (e.g., a filter capacitor) connected between the converter's input pins and ground or to

the reference input pin and ground should be connected to a very clean point in the ground plane.

We recommend the use of a single, uniform ground plane and the use of split power planes. The power planes

should be located within the same board layer. All analog circuitry (input amplifiers, filters, reference

components, etc.) should be placed over the analog power plane. All digital circuitry and I/O lines should be

placed over the digital power plane. Furthermore, all components in the reference circuitry and the input signal

chain that are connected to ground should be connected together with short traces and enter the analog ground

plane at a single, quiet point.

Product Folder Links: ADC088S052

ADC088S052

www.ti.com

SNAS340F –SEPTEMBER 2005–REVISED MARCH 2013

REVISION HISTORY

Changes from Revision E (March 2013) to Revision F Page

• Changed layout of National Data Sheet to TI format .......................................................................................................... 18

Product Folder Links: ADC088S052

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

ADC088S052CIMT/NOPB ACTIVE TSSOP PW 16 92 RoHS & Green SN Level-1-260C-UNLIM -40 to 105 088S052

CIMT

ADC088S052CIMTX/NOPB ACTIVE TSSOP PW 16 2500 RoHS & Green SN Level-1-260C-UNLIM -40 to 105 088S052

CIMT

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

ADC088S052CIMTX/NOP

BTSSOP PW 16 2500 330.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 6-Nov-2015

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

ADC088S052CIMTX/NOP

BTSSOP PW 16 2500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 6-Nov-2015

Pack Materials-Page 2

www.ti.com

PACKAGE OUTLINE

14X 0.65

4.55

16X 0.30

0.19

TYP

6.6

6.2

1.2 MAX

0.15

0.05

0.25

GAGE PLANE

-80

BNOTE 4

4.5

4.3

NOTE 3

5.1

4.9

0.75

0.50

(0.15) TYP

TSSOP - 1.2 mm max heightPW0016A

SMALL OUTLINE PACKAGE

4220204/A 02/2017

0.1 C A B

PIN 1 INDEX AREA

SEE DETAIL A

0.1 C

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing

per ASME Y14.5M.

2. This drawing is subject to change without notice.

3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not

exceed 0.15 mm per side.

4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.

5. Reference JEDEC registration MO-153.

SEATING

PLANE

A 20

DETAIL A

TYPICAL

SCALE 2.500

www.ti.com

EXAMPLE BOARD LAYOUT

0.05 MAX

ALL AROUND 0.05 MIN

ALL AROUND

16X (1.5)

16X (0.45)

14X (0.65)

(5.8)

(R0.05) TYP

TSSOP - 1.2 mm max heightPW0016A

SMALL OUTLINE PACKAGE

4220204/A 02/2017

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN

SCALE: 10X

SYMM

15.000

METAL

SOLDER MASK

OPENING METAL UNDER

SOLDER MASK SOLDER MASK

OPENING

EXPOSED METAL

SOLDER MASK DETAILS

NON-SOLDER MASK

DEFINED

(PREFERRED)

SOLDER MASK

DEFINED

www.ti.com

EXAMPLE STENCIL DESIGN

16X (1.5)

16X (0.45)

14X (0.65)

(5.8)

(R0.05) TYP

TSSOP - 1.2 mm max heightPW0016A

SMALL OUTLINE PACKAGE

4220204/A 02/2017

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate

design recommendations.

9. Board assembly site may have different recommendations for stencil design.

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

SCALE: 10X

SYMM

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