SA306
SA306U 1
P r o d u c t I n n o v a t i o n F r o m
DESCRIPTION
designed primarily to drive three-phase Brushless
DC (BLDC) motors. Three independent half bridges
provide over 15 amperes peak output current under
microcontroller or DSC control. Thermal and short cir-
cuit monitoring is provided, which generates fault sig-
nals for the microcontroller to take appropriate action.
A block diagram is provided in Figure 1.
Additionally, cycle-by-cycle current limit offers user
programmable hardware protection independent of the
microcontroller. Output current is measured using an
innovative low loss technique. The SA306 is built using
a multi-technology process allowing CMOS logic con-
trol and complementary DMOS output power devices
on the same IC. Use of P-channel high side FETs en-
ables 60V operation without bootstrap or charge pump
circuitry.
The Power Quad surface mount package balances ex-
cellent thermal performance with the advantages of a
FEATURES
-
controllers and Digital Signal Controllers
generation and shoot-through prevention
limit protection
signals
APPLICATIONS
3 Phase Switching Amplifier
SA306
P r o d u c t I n n o v a t i o n F r o m
FIGURE 1. BLOCK DIAGRAM
Copyright © Cirrus Logic, Inc. 2008
(All Rights Reserved)
http://www.cirrus.com
DEC 2008
SA306 Switching Amplifier
V s (p ha se A )
P G N D ( A & B )
Gate
Control
PWM
Signals
A
B
C
O u t A
O u t B
O u t C
P G N D ( C )
T E M P
GND
V s (p ha se B & C )
V
S
+
I
LIM
/D IS 1
S C
D IS 2
S G N D
P h as e A
P h as e C
P h as e B
Control
Logic
V
DD
Ia' Ib' Ic'
Ia'
Ib'
Ic'
Fault
Logic
Ia
Ic
Ib
A t
A b
B t
B b
C t
C b
V
DD
V
DD
V
DD
SA306
2 SA306U
P r o d u c t I n n o v a t i o n F r o m
1. CHARACTERISTICS AND SPECIFICATIONS
NOTES:
-
at typical supply voltages and TC = 25°C).
ABSOLUTE MAXIMUM RATINGS
Parameter Symbol Min Max Units
VS60 V
VDD 5.5 V
(-0.5) (VDD+0.5) V
OUTPUT CURRENT, peak, 10ms2IOUT 17 A
2PD100
TEMPERATURE, junction3TJ150 °C
T 125 °C
TA 125 °C
2. Long term operation at elevated temperature will result in reduced product life. De-rate internal power
dissipation to achieve high MTBF.
3. Output current rating may be limited by duty cycle, ambient temperature, and heat sinking. Under any
Parameter Test Conditions2SA306 SA306A Units
Min Typ Max Min Typ Max
LOGIC
1 * V
* V
0.3 * V
3.7 * V
OUTPUT CURRENT
(SC, Temp, ILIM/DIS1) 50 * mA
POWER SUPPLY
VSUVLO 50 60 55 V
VS
LOCKOUT, (UVLO) 9 * * V
VDD 5.5 * * V
SUPPLY CURRENT, VS
20 kHz (One phase
switching at 50% duty
cycle) , VS=50V, VDD=5V
25 30 * * mA
SUPPLY CURRENT, VDD
20 kHz (One phase
switching at 50% duty
cycle) , VS=50V, VDD=5V
5 6 * * mA
SPECIFICATIONS
SA306
SA306U 3
P r o d u c t I n n o v a t i o n F r o m
Parameter Test Conditions2SA306 SA306A Units
Min Typ Max Min Typ Max
CURRENT LIMIT
CURRENT LIMIT
THRESHOLD (Vth) 3.95 * V
Vth HYSTERESIS 100 * mV
OUTPUT
CURRENT, CONTINUOUS 5A
See Figure 10 270 * ns
See Figure 10 270 * ns
DISABLE DELAY, TD(DIS) See Figure 10 200 * ns
ENABLE DELAY, TD(DIS) See Figure 10 200 * ns
RISE TIME, T(RISE) See Figure 11 50 * ns
FALL TIME, T(FALL) See Figure 11 50 * ns
ON RESISTANCE
5A Load 300 750 300 600
ON RESISTANCE
5A Load 250 750 250 600
THERMAL
135 *
HYSTERESIS *
RESISTANCE, junction to
case Full temperature range 1.25 1.5 * *
case -25 125
FIGURE 2. 64-PIN QFP, PACKAGE STYLE HQ
SPECIFICATIONS, continued
SA306
4 SA306U
P r o d u c t I n n o v a t i o n F r o m
DIODE FORWARD VOLTAGE - TOP FET
(P-Channel)
0
1
2
3
4
5
FORWARD VOLTAGE (V)
CURRENT (A)
0.5 1.51.31.10.90.7
DIODE FORWARD VOLTAGE - BOTTOM FET
(N-Channel)
0
1
2
3
4
5
FORWARD VOLTAGE (V)
CURRENT (A)
0.5 1.51.31.10.90.7
ON RESISTANCE - TOP FET
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0.55
0.6
0.65
0.7
0.75
0.8
IOUT,(A)
RDS(on),(Ω)
VS=11
VS=13
VS=15
VS>17
100 987654321
(P-Channel)
ON RESISTANCE - BOTTOM FET
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
0.55
0.6
0.65
0.7
0.75
0.8
10
IOUT,(A)
RDS(on),(Ω)
VS=11
VS=13
VS=15
VS=17
VS>22
0 987654321
(N-Channel)
POWER DERATING
0
20
40
60
80
100
120
CASE TEMPERATURE, TC
POWER DISSIPATION, PD
SA306
SA306A
-40 12080400
VDD SUPPLY CURRENT
4.5
4.6
4.7
4.8
4.9
5
0 50 100 150 200 250 300
FREQUENCY (kHz)
VDD SUPPLY CURRENT (mA)
ONE PHASE SWITCHING @
50% DUTY CYCLE; VS=50V
VDD SUPPLY CURRENT
4
4.5
5
5.5
6
6.5
7
7.5
8
10 20 30 40 50 60
VS SUPPLY VOLTAGE (V)
VDD SUPPLY CURRENT (mA)
ONE PHASE SWITCHING
FREQUENCY = 20kHz
50% DUTY CYCLE
25°C
125°C
CURRENT SENSE
0.1
1
10
0.01 0.1 1 10
SENSE CURRENT (mA)
LOAD CURRENT (A)
VS SUPPLY CURRENT
20
40
60
80
100
120
140
160
180
0 50 100 150 200 250 300
FREQUENCY (kHz)
V
S
SUPPLY CURRENT (mA)
ONE PHASE SWITCHING @
50% DUTY CYCLE; VS=50V
0
V
S
SUPPLY CURRENT
0
5
10
15
20
25
V
S
SUPPLY VOLTAGE (V)
V
S
SUPPLY CURRENT (mA)
125°C
25°C
ONE PHASE SWITCHING
FREQUENCY = 20kHz
50% DUTY CYCLE
10 20 30 40 50 60
SA306
SA306U 5
P r o d u c t I n n o v a t i o n F r o m
FIGURE 3. EXTERNAL CONNECTIONS
53
54
55
56
57
58
59
60
61
62
63
64
32
31
30
29
28
27
26
25
24
23
22
21
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
OUT C
OUT C
NC
VS B & C
VS B & C
VS B & C
VS B & C
NC
OUT B
OUT B
OUT B
NC
PGND A & B
PGND A & B
PGND A & B
PGND A & B
NC
OUT A
OUT A
OUT A
Ic
NC
SC
NC
Ib
NC
ILIM/DIS1
NC
SGND
NC
Bt
NC
Bb
NC
Ab
NC
At
NC
VDD
NC
OUT C
NC
PGND C
PGND C
PGND C
HS
HS
NC
Cb
NC
Ct
NC
NC
VS A
VS A
VS A
NC
HS
HS
TEMP
NC
DIS2
NC
Ia
TABLE 1. PIN DESCRIPTIONS
Pin # Pin Name Signal Type
29,30,31 VS (phase A) Power
51,52,53 OUT C Power Output Half Bridge C Power Output
55,56,57 Power
3 SC Logic Output
61 Cb Logic Input Logic high commands C phase lower FET to turn on
63 Ct Logic Input Logic high commands C phase upper FET to turn on
1 Ic Analog Output Phase C current sense output
5 Ib Analog Output Phase B current sense output
7 ILIM/DIS1 Logic Input/Output
As an output, logic high indicates cycle-by-cycle current limit, and
logic low indicates normal operation. As an input, logic high places
all outputs in a high impedance state and logic low disables the
cycle-by-cycle current limit function.
SA306
6 SA306U
P r o d u c t I n n o v a t i o n F r o m
TABLE 1. PIN DESCRIPTIONS
Pin # Pin Name Signal Type
9 Power
11 Bt Logic Input Logic high commands B phase upper FET to turn on
13 Bb Logic Input Logic high commands B phase lower FET to turn on
15 Ab Logic Input Logic high commands A phase lower FET to turn on
17 At Logic Input Logic high commands A phase upper FET to turn on
19 VDD Power Logic Supply (5V)
21 Ia Analog Output Phase A current sense output
23 DIS2 Logic Input Logic high places all outputs in a high impedance state
25 TEMP Logic Output
OUT B Power Output Half Bridge B Power Output
VS (phase B&C) Power High Voltage Supply phase B&C
OUT A Power Output Half Bridge A Power Output
Power
HS Mechanical Pins connected to the package heat slug
NC --- Do Not Connect
1.2 Pin Descriptions
S:
S
S pins to handle load current peaks and
potential motor regeneration. Refer to the applications section of this datasheet for additional discussion regarding
current for phases B & C. Phase A may be operated at a different supply voltage from phases B & C. Only the B &
OUT A, OUT B, OUT C:
load, it is recommended that two Schottky diodes with good switching characteristics (fast tRR specs) be connected
to each pin so that they are in parallel with the parasitic back-body diodes of the output FETs. (See Section 2.6)
PGND:
this datasheet for more details.
SC: Short Circuit output. If a condition is detected on any output which is not in accordance with the input com-
mands, this indicates a short circuit condition and the SC pin goes high. The SC signal is blanked for approximately
200ns during switching transitions but in high current applications, short glitches may appear on the SC pin. A high
-
tor.
Ab, Bb, Cb: These Schmitt triggered logic level inputs are responsible for turning the associated bottom, or lower
N-channel output FETs on and off. Logic high turns the bottom N-channel FET on, and a logic low turns the low side
N-channel FET off. If Ab, Bb, or Cb is high at the same time that a corresponding At, Bt, or Ct input is high, protection
circuitry will turn off both FETs in order to prevent shoot-through current on that output phase. Protection circuitry
SA306
SA306U 7
P r o d u c t I n n o v a t i o n F r o m
also includes a dead-time generator, which inserts dead time in the outputs in the case of simultaneous switching
of the top and bottom input signals.
At, Bt, Ct: These Schmitt triggered logic level inputs are responsible for turning the associated top side, or upper
P-channel FET outputs on and off. Logic high turns the top P-channel FET on, and a logic low turns the top P-chan-
nel FET off.
Ia, Ib, Ic: Current sense pins. The SA306 supplies a positive current to these pins which is proportional to the cur-
body diode of the P-channel FET or through external Schottky diodes are not registered on the current sense pins.
that can be monitored with ADC inputs of a processor or external circuitry.
The current sense pins are also internally compared with the current limit threshold voltage reference, Vth. If the
voltage on any current sense pin exceeds Vth, the cycle by cycle current limit circuit engages. Details of this func-
tionality are described in the applications section of this datasheet.
ILIM/DIS1: This pin is directly connected to the disable circuitry of the SA306. Pulling this pin to logic high places OUT
A, OUT B, and OUT C in a high impedance state. This pin is also connected internally to the output of the current
feature. Pulling this pin to a logic low effectively disables the cycle-by-cycle current limit feature.
SGND: This is the ground return connection for the VDD logic power supply pin. All internal analog and logic circuitry
do to this may result in oscillations on the output pins during rising or falling edges.
DD: This is the connection for the 5V power supply, and provides power for the logic and analog circuitry in the
SA306. This pin requires decoupling (at least 0.1µF capacitor with good high frequency characteristics is recom-
DIS2: The DIS2 pin is a Schmitt triggered logic level input that places OUT A, OUT B, and OUT C in a high im-
-
nected.
TEMP:
HS: These pins are internally connected to the thermal slug on the reverse of the package. They should be con-
NC: These “no-connect” pins should be left unconnected.
SA306
8 SA306U
P r o d u c t I n n o v a t i o n F r o m
2. SA306 OPERATION
The SA306 is designed primarily to drive three phase motors. However, it can be used for any application requir-
Current Limit fault signals provide important feedback to the system controller which can safely disable the output
drivers in the presence of a fault condition. High side current monitors for all three phases provide performance
information which can be used to regulate or limit torque.
FIGURE 4. SYSTEM DIAGRAM
SA306 Switching Amplifier
BRUSHLESS
MOTOR
Vs (phase A)
PGND (A&B)
Current
monitor
Signals
Sensor – Hall Sensors
or
Sensorless – Input from Stator leads
A
B
C
OUT A
OUT B
OUT C
PGND (C)
GND
Vs (phase B&C)
Vs +
Sensing
circuits
GND
SGND
Gate
Control
Control
Logic
Fault
Logic
T E M P
I
LIM
/D IS 1
S C
Ia
Ic
Ib
V
DD
PWM
Signals
D IS 2
S G N D
A t
A b
B t
B b
C t
C b
M icro contro ller
or DSC
SA306
SA306U 9
P r o d u c t I n n o v a t i o n F r o m
SGND
Gate
Control
Vs
OUT A
PGND
At
Ab
SC
TEMP
SC
Logic
Temp
Sense
Ref
Ia
DIS2
ILIM/DIS1
UVLO
Ia'
+
_
Lim b
Lim c
+
_
Vdd
Lim a
Current
Sense
12k
12k
12k
12k
Vth
The block diagram in Figure 5 illustrates the features of the input and output structures of the SA306. For simplicity,
a single phase is shown.
FIGURE 5. INPUT AND OUTPUT STRUCTURES FOR A SINGLE PHASE
TABLE 2. TRUTH TABLE
At, Bt, Ct
Ab, Bb, Cb
Ia, Ib, Ic
ILIM/DIS1
DIS2
OUT A,
OUT B,
OUT C
Comments
0 0 X X X High-Z Top and Bottom output FETs for that phase are turned off.
0 1 <Vth 0 0 Bottom output FET for that phase is turned on.
1 0 <Vth 0 0 VS Top output FET for that phase is turned on.
1 1 X X X High-Z Both output FETs for that phase are turned off.
X X >Vth 1 X High-Z Voltage on Ia, Ib, or Ic has exceeded Vth, which causes ILIM/DIS1 to go high.
This internally disables Top and Bottom output FETs for ALL phases.
X X X X 1 High-Z DIS2 pin pulled high, which disables all outputs.
X X X Pulled
High X High-Z Pulling the ILIM/DIS1 pin high externally acts as a second disable input,
which disables ALL output FETs.
X X X Pulled
Low 0
Determined
inputs
Pulling the DIS2 pin low externally disables the cycle-by-cycle current limit
X X X X X High-Z If VS is below the UVLO threshold all output FETs will be disabled.
SA306
10 SA306U
P r o d u c t I n n o v a t i o n F r o m
2.1 LAYOUT CONSIDERATIONS
Output traces carry signals with very high dV/dt and dI/dt. Proper routing and adequate power supply bypassing
ringing at the outputs.
The VS supply should be bypassed with a surface mount ceramic capacitor mounted as close as possible to the VS
pins. Total inductance of the routing from the capacitor to the VS-
current should be placed near the SA306 as well. Capacitor types rated for switching applications are the only types
that should be considered. Note that phases B & C share a VS connection and the bypass recommendation should
The bypassing requirements of the VDD
mount ceramic capacitor (X7R or NPO) connected directly to the VDD
plane may be separated into power and logic sections connected by a pair of back to back Schottky diodes. This
isolates noise between signal and power ground traces and prevents high currents from passing between the plane
sections.
2.2 FAULT INDICATIONS
In the case of either an over-temperature or short circuit fault, the SA306 will take no action to disable the outputs.
Instead, the SC and TEMP signals are provided to an external controller, where a determination can be made re-
garding the appropriate course of action. In most cases, the SC pin would be connected to a FAULT input on the
the processor would recognize the condition as an external interrupt, which could be processed in software via an
Interrupt Service Routine. The processor could optionally bring all inputs low, or assert a high level to either of the
disable inputs on the SA306.
-
vides a hard wired shutdown of all outputs in re-
sponse to a fault indication. An SC or TEMP fault sets
the latch, pulling the disable pin high. The processor
can be used in safety critical applications to remove
software from the fault-shutdown loop, or simply to
reduce processor overhead.
the TEMP pin may be externally connected to the
adjacent DIS1 pin. If the device temperature reaches
motor. The SA306 will re-energize the motor when
of thermal oscillations which can greatly reduce the life of the device.
The undervoltage lockout condition results in the SA306 unilaterally disabling all output FETs until VS is above
the UVLO threshold indicated in the spec table. There is no external signal indicating that an undervoltage lock-
FIGURE 6. EXTERNAL FAULT LATCH
CIRCUIT
SA306
PROCESSOR
INTERRUPT
GPIO
PWM
SC
DIS2 TEMP
LATCHED FAULT
FAULT RESET
SA306
SA306U 11
P r o d u c t I n n o v a t i o n F r o m
out condition is in progress. The SA306 has two
VS connections: one for phase A, and another for
phases B & C. The supply voltages on these pins
need not be the same, but the UVLO will engage
if either is below the threshold. Hysteresis on the
UVLO circuit prevents oscillations with typical
power supply variations.
2.4 CURRENT SENSE
External power shunt resistors are not required
with the SA306. Forward current in each top, P-
channel output FET is measured and mirrored to
the respective current sense output pin, Ia, Ib and
Ic. By connecting a resistor between each cur-
rent sense pin and a reference, such as ground,
a voltage develops across the resistor that is pro-
portional to the output current for that phase. An
ADC can monitor the voltages on these resistors
for protection or for closed loop torque control
sense pins source current from the VDD supply.
Headroom required for the current sense circuit
is approximately 0.5V. The nominal scale factor for each proportional output current is shown in the typical perfor-
2.5 CYCLE-BY-CYCLE CURRENT LIMIT
In applications where the current in the motor is not directly controlled, both the average current rating of the motor
up.
Because the output current of each upper output FET is measured, the SA306 is able to provide a very robust cur-
rent limit scheme. This enables the SA306 to safely and easily drive virtually any brushless motor through a start-
shows starting current and back EMF with and without current limit enabled.
If the voltage of any of the three current sense pins exceeds the current limit threshold voltage (Vth), all outputs are
disabled. After all current sense pins fall below the Vth threshold voltage AND the offending phase’s top side input
goes low, the output stage will return to an active state on the rising edge of ANY top side input command signal (At,
cycle. This scheme regulates the
peak current in each phase during each cycle as illustrated in the timing diagram below. The ratio of average
to peak current depends on the inductance of the motor winding, the back EMF developed in the motor, and the
width of the pulse.
LIM/DIS1 goes high when
any current sense pin exceeds Vth. Notice that the moment at which the current sense signal exceeds the Vth
motor winding L/R time constant will often result in an audible beat frequency sometimes called a sub-cycle oscilla-
tion. This oscillation can be seen on the ILIM
Input signals commanding 0% or 100% duty cycle may be incompatible with the current limit feature due to the
absence of rising edges of At, Bt, and Ct except when commutating phases. At high RPM, this may result in poor
performance. At low RPM, the motor may stall if the current limit trips and the motor current reaches zero without a
commutation edge which will typically reset the current limit latch.
TIME
NON-LIMITED BACK EMF
LIMITED BACK EMF
LIMITED MOTOR CURRENT
NON-LIMITED MOTOR CURRENT
CURRENT
SA306
12 SA306U
P r o d u c t I n n o v a t i o n F r o m
The current limit feature may be disabled
by tying the ILIM/DIS
current sense pins will continue to provide
top FET output current information.
Typically, the current sense pins source
current into grounded resistors which pro-
vide voltages to the current limit compara-
tors. If instead the current limit resistors
are connected to a voltage output DAC,
the current limit can be controlled dynami-
cally from the system controller. This tech-
nique essentially reduces the current limit
threshold voltage to (Vth-VDAC). During
expected conditions of high torque de-
mand, such as start-up or reversal, the
DAC can adjust the current limit dynami-
cally to allow periods of high current. In
normal operation when low current is ex-
pected, the DAC output voltage can in-
crease, reducing the current limit setting
to provide more conservative fault protec-
tion.
2.6 EXTERNAL FLYBACK
DIODES
-
istics and lower forward voltage drop than the internal back-body di-
power dissipation and heating during commutation of the motor current.
Reverse recovery time and capacitance are the most important param-
better reverse recovery time and Schottky diodes typically have low
capacitance. Individual application requirements will be the guide when
determining the need for these diodes and for selecting the component
which is most suitable.
At INPUT
OUTA
Ia
Vth
ILIM/DIS1
FIGURE 9. SCHOTTKY
DIODES
OUTA
OUTC
OUTB
VSVSVS
SA306
SA306
SA306U 13
P r o d u c t I n n o v a t i o n F r o m
FIGURE 10. TIMING DIAGRAMS
3. POWER DISSIPATION
The thermally enhanced package of the SA306 al-
lows several options for managing the power dissi-
pated in the three output stages. Power dissipation
of output power dissipation and switching losses.
Output power dissipation depends on the quadrant
are used to carry the reverse or commutating cur-
rents. Switching losses are dependent on the fre-
-
cal performance graphs.
The size and orientation of the heatsink must be
selected to manage the average power dissipation
of the SA306. Applications vary widely and various
thermal techniques are available to match the re-
quired performance. The patent pending mounting
technique shown in Figure 12, with the SA306 in-
verted and suspended through a cutout in the PCB
the HS33, a 1.5 inch long aluminum extrusion with
JAD). Mounting the PCB parallel
JAD). In applica-
tions in which higher power dissipation is expected or lower junction or case temperatures are required, a larger
4. ORDERING AND PRODUCT STATUS INFORMATION
MODEL TEMPERATURE PRODUCTION STATUS
SA306-IHZ Samples Available
SA306A-FHZ Samples Available
TOP INPUT
BOTTOM INPUT
DELAY TIMING
OUTPUT
DISABLE
td(fall) td(dis)td(rise) td(dis)
td(dis)
td(dis)
TOP INPUT
BOTTOM INPUT
OUTPUT
t(fall)
t(rise)
20%
80%
FIGURE 11. OUTPUT RESPONSE
SA306
14 SA306U
P r o d u c t I n n o v a t i o n F r o m
FIGURE 12. HEATSINK TECHNIQUE
PATENT PENDING
CONTACTING CIRRUS LOGIC SUPPORT
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International customers can also request support by contacting their local Cirrus Logic Sales Representative.
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