"AMI's 0.8m Gate Array family is simply the best 0.8m on the market . . . one of the highest performance, yet lowest cost array products available today . . ." Designed for 3V, 5V, or 3V/5V mixed supplies 210 ps gate delays (fanout = 2) 5,000 to 663,000 available gate densities Complete package lineup quad flatpack (QFP), LCC, DIP, grid array . . . Usable megafunctions Families of single port RAMs, microprocessors, controllers, datapath functions . . . "Made in America" engineering, manufacturing, and support No `overseas' delays to your important questions; we're right here, ready to help. Table of Contents Features....................................................................................... 1 AMI8Gx Gate Array Family ............................................................ 1 Architectural Overview .................................................................. 2 Product Applications ..................................................................... 3 ASIC Design Tools and Methodology ............................................. 3 The Design Library ........................................................................ 5 DC Specifications ........................................................................ 6 Library Cell Selection Guide ................................................... 8 - 21 Delay Derating Information ............................................................ 22 Packaging .................................................................................... 23 0.8 micron CMOS Gate Arrays Digital ASICs Products and Services August 1993 AMI's "AMI8Gx" series of 0.8m gate arrays exploits a proprietary power grid and track routing architecture on a compact, channelless, sea-of-gates design to provide one of the highest performance, cost effective array products available today. * JTAG Boundary Scan macro support * Cost driven architecture: - Offers both 2 and 3 level metal interconnect to provide the lowest user cost for the number of gates and pads required. - Provides 6 extra power pads per corner to preserve more I/O cells for signal use. - Contains extra I/O cells to provide extra drive without wasting bond pads. Features * 3V, 5V, and combined 3V/5V operation: Each individual pad cell can be driven independently by a 3V or 5V supply. 3V to 5V and 5V to 3V level shift is available in all I/O cells. Core can be either 3V for low power or 5V for high speed. * Extensive library for quick design: - Complete primary cell and I/O library. - Synchronous single port RAM compilers with over 2000 compiled RAM sizes from 32x1 to 1Kx32 bits. - MG65C02, MG29C01, MG29C10, MG80C85, MG82Cxx, MGMC51 megacells. - Various datapath logic synthesizers (FIFOs, multipliers, adders, barrel shifters). * Operating Temp equals -55 to 125 oC: Few competing products allow this range. * Excellent performance: - 260 MHz maximum toggle rate on clocked flip-flops (TJ = 135 oC). - 200 ps delay (FO=2) for a 2-input NAND gate. Clock tree generation: 400 ps clock skew (fan out = 3500 at 80 MHz). * 1 to 16 mA drive per single I/O cell: Selectable I/O drive with controllable slew rate. Extra I/O cells allow combined I/O drive up to 96mA without reducing pad count. * Wide range of packaging: Full QFP and LCC line, DIPs and PGAs, individual die, (ball grid array package under study). Burn-in capability as needed. * Automatic Test Program Generation: Includes scan macros (NETSCAN) for high fault coverage. * Power equals 3.2 W/MHz/cell * Full operating voltage range from 2.7V to 5.5V * ESD protection > 2kV; latchup > 100mA AMI8Gx Gate Array Family Part Number Raw Gates Usable Gates1 Triple Metal Double Metal Available I/O Cells Available Bond Pads2 AMI8G663 663,350 464,350 331,700 732 528 AMI8G392 392,160 274,500 196,100 564 424 AMI8G247 246,790 172,750 123,400 448 336 AMI8G201 200,740 140,500 100,400 404 304 AMI8G142 141,590 99,100 70,800 340 256 AMI8G93 92,740 64,900 46,400 276 208 AMI8G65 65,420 45,800 32,700 232 176 AMI8G55 54,700 38,300 27,400 212 160 AMI8G44 44,460 31,100 22,200 192 144 AMI8G34 33,860 23,700 16,900 168 128 AMI8G21 20,800 14,550 10,400 132 100 AMI8G15 14,960 10,470 7,480 112 84 AMI8G9 8,900 6,230 4,450 88 68 AMI8G5 5,250 3,670 2,630 68 52 Note1:Exactusablegatecountwillvarydependingondesigninterconnectandmacroselection. Note2:24optionalfixedpowerpins(6ineachcorner)arenotincludedinthisnumber. 1 0.8 micron CMOS Gate Arrays Digital ASICs Products and Services August 1993 FIGURE 1: GATE ARRAY ARCHITECTURE Selectable 2 or 3 metal interconnect [note 1] Large I/O driver with prebuffer [note 5] Core cell sites with 4 transistors [note 2] 2 P-channel 2 N-channel Extra corner power pads [note 4] Separately configured power busses for I/O and core [note 3] Architectural Overview Some important elements of the AMI8Gx gate array family are: * [Note 1] Drawn gate length of 0.8 micron; 2 or 3 level metal interconnect selectable. * [Note 4] Twenty-four (six per corner) fixed power pads (not included in Bond Pad count in Table 1) available on each array for customer use. * Each I/O cell can be configured as 5V VDD, 3V VDD, VSS, or signal I/O. * [Note 2] Two p-channel and two n-channel transistors per site (or cell). Sites are arrayed in a sea-of-gates structure that can allow interconnect routing over active sites. Also, p-channel transistors are sized larger than the stronger n-channel transistors in each cell to provide better matched rise times and fall times. * [Note 5] Each I/O cell has selectable drive from 1mA to 16mA. All I/O cell logic can be built in the I/O cell prebuffer. Level shifting (3V to 5V or 5V to 3V) may require the use of a few core gates. * [Note 3] Four separate power busses for I/O cells to allow separate supplies for output buffers, input buffers, and mixed VDD levels all on an individual I/O cell basis. Two separate power busses for core logic (not shown). 2 0.8 micron CMOS Gate Arrays Digital ASICs Products and Services August 1993 Product Applications known layouts are used. Once actual layout is completed by AMI, a post-layout interconnect capacitance table will be supplied for final validation of device timing. The family's extended temperature and voltage operation range make it well suited for telecom, industrial, and military applications. The low cost structure also makes it ideal in computer and office automation ASIC requirements. Figure 2 shows a typical design flow for a new design. FPGA OR PAL CONVERSION: AMI can convert netlists from most FPGA and PAL devices to a more cost and performance effective AMI8Gx gate array design for volume production. 2ND SOURCE EXISTING PRODUCTS: Netlist conversion capabilities from AMI allow a competitive alternate supply with AMI8Gx for current high volume designs. NEW DESIGN CAPTURE: AMI8Gx design is supported by many popular third party software platforms, as well as AMI's Enhanced Design Utilities (EDU) environment. PROCESS UPGRADE: Designs done in AMI's 1.25m and 1.0m gate array families can easily be upgraded to the AMI8Gx family. The AMI ASIC Standard Library provides a common netlist design base. ASIC Design Tools and Methodology AMI8Gx and other AMI ASIC families are supported on popular third party products: * * * * * * * Cadence Mentor Graphics Synopsys Viewlogic Valid Verilog simulation IKOS simulation accelerator (AMI's sign-off simulator) AMI has maintained critical proprietary software tools to ensure a tight, well coupled design to our silicon process. This methodology includes our expert-system design analysis tools, AMI's Enhanced Design Utilities (EDU), a software support methodology that covers the complete set of wafer processing possibilities, and a dedicated, experienced engineering staff that can assist at any level of the design process. AMI Design Flow AMI will supply an AMI8Gx design kit which includes a cell library containing symbols, simulation models and software for design verification, timing calculations, and netlist generation. For pre-layout timing simulations, capacitance values derived from statistical averages of 3 0.8 micron CMOS Gate Arrays Digital ASICs Products and Services August 1993 AMI Design Flow (cont.) Working with an AMI design center, the customer is responsible for capturing and verifying the design using the AMI ASIC Standard Library. He is also responsible for creating the test vectors that will eventually serve as the logical part of the manufacturing test. Software aids such as logic synthesis, megacells, automatic test program generation, netlist rule checkers, etc. can greatly speed up this process. (A fault coverage check of the test vector set is optional and can be done as an additional service.) After layout has been completed the interconnect data is extracted from the physical layout to be fed back to the sign-off simulator for final circuit verification. This post layout interconnect data can be sent to the customer for final validation on his simulator. When the post-layout simulation has been completed and approved by the customer the design is then released for mask and wafer fabrication. The test program is developed in parallel using internal automatic test program generation software. Prototypes can then be tested before they are shipped. When the design is received by the factory, the "Design Start Package" is reviewed by AMI engineers. This start package, which is completed by the customer, contains the device specification, netlist, critical timing paths, and test vectors. The design is pre-screened on the Enhanced Design Utilities (EDU) and then resimulated on IKOS, AMI's sign-off simulator. The results are compared to the customer's simulation from the third-party CAE tool. Figure 3 outlines a typical software environment when using third party tools. AMI uses EDIF to speed ports between various software products. AMI's Enhanced Design Utilities tools are intended to be used interactively at each stage of the design. EDU software is a set of design analysis tools that check both the design and test vectors for correctness and compatibility with in-house ASIC testers, and analyze the design for inefficiencies and possible flaws that could cause problems in manufacturing the device. Once the design has passed the initial screening it is then ready for placement and routing. The layout proceeds by first placing memory and megacells, assigning priority to critical paths, and designing the distribution and buffering of clocks. Next, the layout is completed with automatic place-and-route on the balance of the circuit. FIGURE 3: DESIGN ENVIRONMENT WITH THIRD PARTY SOFTWARE AMI Environment ** AMI ASIC Std. Library Logic Synthesis Memory Compiler HDL Optional Synthesis Tool ** AMI ASIC Stnd. Library Schematic Translation Physical Data Schematic Entry ** Design Database Netlist Translation Third Party Environment ** Enhanced Design Utilities supplied ** Elements in AMI Design Kit Vector Generation Estimated Delays ** Models & Symbols VHDL Timing Simulation Design Verification Place and Route Post Route Verification ATPG 4 0.8 micron CMOS Gate Arrays Digital ASICs Products and Services August 1993 Memory Compiler Library Size Memory Compiler SRAM (single-port, synchronous) min. max. 32 x 1 1K x 32 Increment 16 words, 1 bit Comments 9 ns typical access time on 1Kx16 NOTE:OtherSRAMandROMcompilersareavailableforstandardcellorembeddedarraydesignapproaches. ContactanAMIDesignCenterfordetailsabouttheseotherproductofferings. The Design Library Memory Compilers AMI provides a robust collection of building blocks for the AMI8Gx gate array family. A broad range of primary cells is complemented with memory cell compilers and useful megacells. With such broad, US-based design talent, AMI can quickly design specific cells that customers need to add an edge in customization. The AMI8Gx family offers the memory compiler shown above. Each of the thousands of possible memory blocks created by this compiler is optimized precisely to the customers' parameters rather than built from a presized leaf cell that covers a range of sizes. This yields a better size and performance match for each application. The AMI ASIC Standard Library Upon supplying the cell specification to AMI, the customer can receive an accurate simulation timing specification overnight by facsimile and a full simulation model for any AMI supported software environment within five working days. The AMI ASIC Standard Library contains a rich set of core and pad cells which allow great flexibility in building competitive devices for customer applications. The library is portable across all AMI's gate array and standard cell families. The ASIC Standard Library is listed in detail on pages 9 to 21. Datapath Synthesizers AMI8Gx also supports the complex datapath logic functions listed here. These functions are synthesized from an input set of design parameters, and can be optimized for either minimum delay, minimum area or a compromise between the two. Contact AMI for the size range and parameter set for any desired functions. Soft Datapath Library (xx by yy) Name Function MGAxxyyDv Adder MGAxxyyEv Adder-subtracter MGBxxyyAv Arithmetic/barrel shifter MGBxxBv Barrel shifter These logic synthesizers produce soft megacell schematics in the ASIC Standard Library, and a schematic symbol for incorporation and simulation with the design netlist. MGBxxCv Arithmetic shifter Megacells MGCxxAv 2-function binary comparator MGCxxBv 6-function binary comparator MGDxxAv Decrementer MGFxxyyC1 Latch-based FIFO MGIxxAv Incrementer MGIxxBv Incrementer/decrementer MGMxxyyDv Signed/unsigned multiplier MGMxxyyEv Multiplier-accumulator MGSxxyyAv Signed/unsigned subtracter The AMI8Gx gate array family supports soft megacell versions that are compatible with many popular architectures. These products are listed on the following page. Soft megacells are functionally and logically compatible with the stand alone products, but since the function is captured in a gate array, each instance of the megacell will differ slightly depending on its physical placement on the array. Soft megacells become part of the design netlist, requiring backannotation of interconnect capacitance after place-and-route for final verification. AMI supplies an actual gate level netlist and schematic of the soft megacell allowing the user to make design changes or remove unneeded features. Test vectors are provided and can be used directly or incorporated into the overall design test. All soft megacells are static designs and use AMI's ASIC Standard Library to ensure portability. 5 0.8 micron CMOS Gate Arrays Digital ASICs Products and Services August 1993 Soft Megacell Library Name Function Name Function MG1468C18 Real-time clock MG82C50A Asynchronous comm. element MG29C01 4-bit microprocessor slice MG82C54 Programmable interval timer MG29C10 Microprogram controller/sequencer MG82C55A Programmable peripheral interface MG65C02 8-bit microprocessor MG82C59A Programmable interrupt controller MG80C85 8-bit microprocessor MGMC51 8-bit microcontroller, 8051 compatible MG82C37A Programmable DMA controller MGMC51FB 8-bit microcontroller, 8051 compatible DC Specifications Operating Specifications Parameter Minimum VDD, Supply Voltage Ambient Temperature - Military - Commercial CMOS Input Specifications Maximum Units 2.7 5.5 Volts -55 125 C 0 70 C (4.5V<VDD<5.5V; -55oC<T<125oC) Vil Low Level Input Voltage Vih High Level Input Voltage Iil Low Level Input Current -1.0 A Iih High Level Input Current 1.0 A Iil Input Pull-Up Current -30 -140 A Iih Input Pull-Down Current 30 185 A Vt- Schmitt Negative Threshold Vt+ Schmitt Positive Threshold Vh Schmitt Hysteresis TTL Input Specifications 0.3*VDD 0.7*VDD Volts Volts 0.2*VDD Volts 0.8*VDD 1.0 Volts Volts (4.5V<VDD<5.5V; -55oC<T<125oC) Vil Low Level Input Voltage 0.8 Vih High Level Input Voltage Iil Low Level Input Current -1.0 A Iih High Level Input Current 1.0 A Iil Input Pull-Up Current -30 -140 A Iih Input Pull-Down Current 30 185 A Vt- Schmitt Negative Threshold 0.7 Vt+ Schmitt Positive Threshold Vh Schmitt Hysteresis 2.0 Volts Volts 2.1 0.4 6 Volts Volts Volts 0.8 micron CMOS Gate Arrays Digital ASICs Products and Services August 1993 7 0.8 micron CMOS Gate Arrays Digital ASICs Products and Services August 1993 Library Cell Selection Guide This selection guide outlines the basic performance of each cell in the AMI ASIC Standard Library. Other custom cells can be created for specific needs. For detailed design analysis please contact an AMI ASIC Design Center for a software design kit and more detailed data sheets. An explanation of the information contained in the selection guide is listed below: Eq. Gates This column lists the equivalent gates of each core cell. It is a measure of the cell transistor count but is normalized to the transistor count of a 2-input NAND gate. A 2-input NAND gate (NA21) requires four transistors, hence, one equivalent gate equals four transistors. I/O Cells This column lists the number of I/O sites (or pad sites) required to implement the listed I/O cell. Parameters The parameters column lists the mnemonics for the propagation delay or timing parameter whose values are given under "Propagation Delay": tPLH Input to output propagation delay for a rising edge on the output tPHL Input to output propagation delay for a falling edge on the output tZH High impedance to high level delay tZL High impedance to low level delay tsu Input setup time with respect to clock th Input hold time tPZ Valid to high impedance state on the output Propagation Delay This column shows the values of the delay parameter for three different loads. For output pad cells, 25pf, 50pf, and 75pf loads are used. For core cells and input pad cells, fanouts of two, four, and eight gates are used. A fanout consists of that number of NA21 input capacitive loads and an average interconnect capacitance based on past layout experience. Delays are in nanoseconds. Description This final column gives a short textual description of the cell. 8 0.8 micron CMOS Gate Arrays Digital ASICs Products and Services August 1993 Simple Gates Name AA21 AA22 AA31 AA32 AA41 AA42 EN21 EO21 NA21 NA22 NA31 NA32 NA41 NA42 NA51 NA52 NA61 NA81 NO21 NO22 NO31 NO32 NO41 Eq Gates 2 2 2 3 3 3 3 3 1 2 2 3 2 4 3 5 5 6 1 2 2 3 2 Parameters Propagation Delay (ns) Description 2 FO 4 FO 8 FO tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL 0.47 0.43 0.46 0.43 0.67 0.52 0.70 0.53 0.89 0.58 0.92 0.56 0.56 0.52 0.72 0.61 0.28 0.24 0.22 0.18 0.36 0.40 0.28 0.29 0.39 0.53 0.32 0.43 0.45 0.76 0.36 0.61 0.75 1.01 0.77 1.12 0.44 0.20 0.33 0.15 0.81 0.22 0.59 0.16 0.60 0.52 0.53 0.49 0.80 0.61 0.78 0.59 1.03 0.68 1.01 0.63 0.72 0.64 0.94 0.70 0.41 0.36 0.28 0.24 0.48 0.56 0.34 0.38 0.52 0.73 0.39 0.54 0.58 1.01 0.43 0.74 0.81 1.08 0.83 1.19 0.67 0.27 0.44 0.19 1.15 0.30 0.77 0.21 0.84 0.67 0.66 0.59 1.06 0.78 0.92 0.69 1.30 0.85 1.16 0.74 1.18 0.88 1.40 0.86 0.65 0.59 0.41 0.36 0.73 0.88 0.47 0.54 0.77 1.14 0.52 0.75 0.84 1.50 0.57 0.99 0.94 1.18 0.96 1.29 1.12 0.43 0.68 0.27 1.83 0.46 1.12 0.29 2-input AND gate tPLH tPHL 1.21 0.23 1.66 0.31 2.55 0.48 4-input NOR gate 9 2-input AND gate 3-input AND gate 3-input AND gate 4-input AND gate 4-input AND gate Exclusive NOR Exclusive OR 2-input NAND gate 2-input NAND gate 3-input NAND gate 3-input NAND gate 4-input NAND gate 4-input NAND gate 5-input NAND gate 5-input NAND gate 6-input NAND gate 8-input NAND gate 2-input NOR gate 2-input NOR gate 3-input NOR gate 3-input NOR gate 0.8 micron CMOS Gate Arrays Digital ASICs Products and Services August 1993 Simple Gates (Continued) Name NO42 NO51 NO52 OR21 OR22 OR31 OR32 OR41 OR42 Eq Gates 4 3 5 2 2 2 3 3 5 Parameters Propagation Delay (ns) Description 2 FO 4 FO 8 FO tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL 0.93 0.17 1.76 0.24 1.40 0.18 0.39 0.53 1.16 0.21 2.32 0.33 1.69 0.22 0.52 0.63 1.63 0.30 3.44 0.49 2.27 0.31 0.76 0.80 4-input NOR gate tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL 0.37 0.58 0.44 0.88 0.42 0.97 0.43 1.36 0.34 1.07 0.43 0.64 0.57 1.00 0.49 1.05 0.49 1.45 0.41 1.15 0.56 0.75 0.82 1.20 0.62 1.18 0.63 1.60 0.54 1.29 2-input OR gate 5-input NOR gate 5-input NOR gate 2-input OR gate 3-input OR gate 3-input OR gate 4-input OR gate 4-input OR gate Complex Gates Name AN11 AN31 Eq Gates 2 2 7 Parameters tPLH tPHL tPLH tPHL A to S B to S AU11 CI to S ON11 ON31 2 2 tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Propagation Delay (ns) 2 FO 4 FO 8 FO 0.72 0.37 1.06 0.31 1.45 1.11 1.47 1.13 1.25 1.11 0.72 0.42 0.51 0.49 0.95 0.49 1.40 0.42 1.58 1.24 1.60 1.24 1.37 1.23 0.95 0.54 0.74 0.65 1.41 0.73 2.08 0.65 1.83 1.46 1.85 1.43 1.63 1.42 1.41 0.79 1.20 0.98 10 Description Two 2-input ANDs into 2-input NOR 2-input AND into 3-input NOR One-bit full adder Two 2-input ORs into 2-input NAND 2-input OR into 3-input NAND 0.8 micron CMOS Gate Arrays Digital ASICs Products and Services August 1993 Inverting Drivers Name INV1 INV2 INV3 INV4 INV5 INV6 Eq Gates 1 1 2 2 3 3 Parameters tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Propagation Delay (ns) 2 FO 4 FO 8 FO 0.24 0.17 0.17 0.12 0.14 0.10 0.12 0.08 0.12 0.08 0.11 0.07 0.36 0.25 0.24 0.16 0.19 0.13 0.16 0.11 0.15 0.10 0.14 0.09 0.61 0.40 0.36 0.24 0.27 0.19 0.22 0.15 0.20 0.14 0.18 0.13 Description Inverter Inverter Inverter Inverter Inverter Inverter Internal 3-State Drivers Name Eq Gates 2 ITA1 A to Q EN to Q 4 ITA2 A to Q EN to Q 2 ITB1 A to QN EN to QN 4 ITB2 A to QN EN to QN 2 ITD1 A to QN E to QN 4 ITD2 A to QN E to QN 1 ITE1 Parameters A to QN EN to QN E to QN tPLH tPHL tZH tZL tPLH tPHL tZH tZL tPLH tPHL tZH tZL tPLH tPHL tZH tZL tPLH tPHL tZH tZL tPLH tPHL tZH tZL tPLH tPHL tZH tZL Propagation Delay (ns) 2 FO 4 FO 8 FO 0.65 0.48 0.37 0.34 0.58 0.53 0.23 0.30 0.51 0.28 0.37 0.33 0.36 0.21 0.23 0.30 0.52 0.28 0.45 0.20 0.38 0.19 0.36 0.12 0.51 0.28 0.44 0.26 0.87 0.60 0.60 0.46 0.66 0.58 0.31 0.35 0.74 0.40 0.59 0.45 0.44 0.25 0.31 0.35 0.74 0.39 0.68 0.32 0.46 0.24 0.44 0.17 0.74 0.39 0.67 0.38 1.34 0.84 1.06 0.70 0.81 0.67 0.45 0.44 1.20 0.64 1.05 0.69 0.59 0.34 0.45 0.43 1.20 0.63 1.13 0.56 0.61 0.32 0.59 0.25 1.19 0.63 1.12 0.61 11 Description Internal non-inverting tri-state buffer Internal non-inverting tri-state buffer Internal inverting tri-state buffer Internal inverting tri-state buffer Internal inverting tri-state buffer Internal inverting tri-state buffer Internal inverting tri-state buffer 0.8 micron CMOS Gate Arrays Digital ASICs Products and Services August 1993 Clock Drivers Name IID2 IID4 IID6 Eq Gates 2 3 4 Parameters tPLH tPHL tPLH tPHL tPLH tPHL Propagation Delay (ns) 2 FO 4 FO 8 FO 0.32 0.36 0.31 0.35 0.35 0.40 0.39 0.41 0.34 0.38 0.37 0.43 0.51 0.50 0.41 0.43 0.42 0.46 Description Non-inverting clock driver Non-inverting clock driver Non-inverting clock driver Muxes and Decoders Name Eq Gates 8 DC24 Sx to QN EN to QN 20 DC38 Sx to QN EN to QN 3 MX21 Ix to Q S to Q 8 MX41 Ix to Q S to Q 20 MX81 Parameters Ix to Q S to Q tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Propagation Delay (ns) 2 FO 4 FO 8 FO 0.48 0.61 0.64 0.77 0.63 0.88 0.89 1.15 0.59 0.66 0.77 0.85 1.14 1.09 1.16 1.46 1.47 1.46 1.45 1.52 0.61 0.78 0.76 0.93 0.71 1.00 1.02 1.36 0.72 0.78 0.90 0.97 1.28 1.28 1.30 1.64 1.59 1.57 1.58 1.64 0.85 1.10 1.01 1.01 0.88 1.25 1.28 1.76 0.98 0.98 1.15 1.16 1.54 1.58 1.57 1.92 1.84 1.77 1.82 1.83 12 Description 2:4 line decoder 3:8 line decoder 2:1 digital multiplexer 4:1 digital multiplexer 8:1 digital multiplexer 0.8 micron CMOS Gate Arrays Digital ASICs Products and Services August 1993 Sequential Logic Name Eq Gates Parameters 6 C to Q 7 D Setup D Hold C to Q 7 D Setup D Hold C to Q 9 D Setup D Hold C to Q 8 D Setup D Hold C to Q 8 D Setup D Hold C to Q 10 D Setup D Hold C to Q 3 D Setup D Hold D to Q DF081 DF091 DF0A1 DF0B1 DF101 DF111 DF121 GN to Q DL531 5 D Setup D Hold D to Q GN to Q DL541 D Setup D Hold 4 DL551 D to Q GN to Q D Setup D Hold tPLH tPHL tsu th tPLH tPHL tsu th tPLH tPHL tsu th tPLH tPHL tsu th tPLH tPHL tsu th tPLH tPHL tsu th tPLH tPHL tsu th tPLH tPHL tPLH tPHL tsu th tPLH tPHL tPLH tPHL tsu th tPLH tPHL tPLH tPHL tsu th Propagation Delay (ns) Description 2 FO 4 FO 8 FO 0.79 0.33 1.01 0.44 0.76 0.00 0.81 1.24 0.82 0.00 1.14 1.09 0.76 0.00 0.82 1.25 0.81 0.00 0.73 1.04 0.80 0.00 0.72 1.05 0.73 0.00 0.72 1.01 0.81 0.00 0.84 0.99 0.99 0.86 0.88 0.00 1.18 0.93 1.34 0.80 1.18 0.00 1.46 0.68 D-type F/F without set or reset 1.07 1.51 D-type F/F with active low set 1.60 1.29 D-type F/F with active low reset 1.07 1.51 D-type F/F with active low set and reset 0.98 1.24 D-type buffered F/F with active low set 0.97 1.25 D-type buffered F/F with active low reset 0.98 1.21 D-type buffered F/F with active low set and reset 1.09 1.18 1.23 1.06 D-type latch without set or reset 1.63 1.11 1.79 0.99 D-type latch with active low reset 1.10 1.35 1.25 1.23 D-type latch with active low set 0.68 1.10 0.91 0.98 0.69 1.11 0.59 0.91 0.59 0.92 0.59 0.89 0.71 0.88 0.86 0.75 0.96 0.83 1.12 0.71 0.73 0.97 0.87 0.85 0.85 1.10 1.00 0.98 1.10 0.00 13 0.8 micron CMOS Gate Arrays Digital ASICs Products and Services August 1993 Sequential Logic (Continued) Name Eq Gates 5 Parameters D to Q GN to Q DL561 6 D Setup D Hold D to Q GN to Q DL641 6 D Setup D Hold D to Q GN to Q DL651 6 D Setup D Hold D to Q GN to Q DL661 4 D Setup D Hold D to Q GN to Q DLZ01 5 D Setup D Hold D to Q GN to Q DLZ11 D Setup D Hold 11 JK091 C to Q J Setup J Hold K Setup K Hold Propagation Delay (ns) Description 2 FO 4 FO 8 FO tPLH tPHL tPLH tPHL tsu th tPLH tPHL tPLH tPHL tsu th tPLH tPHL tPLH tPHL tsu th tPLH tPHL tPLH tPHL tsu th tPLH tPHL tPLH tPHL tsu th tPLH tPHL tPLH tPHL tsu th 0.92 1.02 1.03 0.89 1.05 1.15 1.16 1.02 1.15 0.00 1.38 1.24 1.52 1.12 0.87 0.00 1.15 1.38 1.30 1.26 0.85 0.00 1.35 1.47 1.46 1.34 0.94 0.00 0.93 1.13 1.07 1.00 1.02 0.00 1.20 1.18 1.31 1.05 1.13 0.00 1.31 1.40 1.42 1.28 D-type latch with active low set and reset 1.62 1.39 1.76 1.27 D-type buffered latch with active low reset 1.39 1.53 1.54 1.42 D-type buffered latch with active low set 1.60 1.62 1.70 1.49 D-type buffered latch with active low set and reset 1.18 1.34 1.32 1.21 D-type latch without set or reset and a dual-enable tri-state output 1.47 1.39 1.57 1.27 D-type latch with active low reset and a dual-enable tri-state output tPLH tPHL tsu th tsu th 0.81 1.32 0.95 1.48 1.39 0.00 1.10 0.00 1.20 1.76 JK-type F/F with active low set 1.26 1.16 1.40 1.04 1.03 1.30 1.18 1.18 1.23 1.38 1.34 1.26 0.80 1.01 0.94 0.88 1.07 1.06 1.16 0.93 14 0.8 micron CMOS Gate Arrays Digital ASICs Products and Services August 1993 15 0.8 micron CMOS Gate Arrays Digital ASICs Products and Services August 1993 Special Cells Name BL02 QD01X1 QD03X1 QD11X1 TD08 PORA PORB Eq Gates 4 Parameters 2 I/O tPLH tPHL QO to QC 2 I/O QO to QC 2 I/O QO to QC 11 2 I/O 2 I/O tPLH tPHL RST to POR RST to POR Propagation Delay (ns) 2 FO 4 FO 8 FO tPLH 0.33 0.68 0.69 0.65 0.88 0.89 2.51 1.90 9.25 9.50 861.9 0.73 0.69 0.92 0.93 2.57 1.95 9.34 9.60 862.0 0.80 0.76 1.00 1.01 2.67 2.05 9.50 9.80 862.1 tPHL 4.95 5.10 5.26 tPLH 1587.3 1587.3 1587.5 tPHL 9.42 9.60 10.01 tPLH tPHL tPLH tPHL tPLH tPHL Description Tri-state bus latch 3.58MHz (1MHz - 10MHz) crystal oscillator 20MHz (10MHz - 32MHz) cyrstal oscillator 32KHz (1KHz - 1MHz) crystal oscillator with Schmitt Trigger Time delay cell, non-inverting Power-on-reset Power-on-reset for 3 volt operation Input Pad Cells Name IB01X1 IB03X1 IB05X1 IB07X1 IB09X1 IB0BX1 IB0DX1 IB30X1 Eq Gates 1 I/O 1 I/O 1 I/O 1 I/O 1 I/O 1 I/O 1 I/O 1 I/O Parameters tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Propagation Delay (ns) 2 FO 4 FO 8 FO 0.71 0.89 0.71 0.88 0.71 0.89 0.78 1.17 0.78 1.17 0.78 1.17 2.49 1.95 1.31 2.85 0.76 0.93 0.76 0.93 0.76 0.93 0.82 1.22 0.83 1.22 0.83 1.23 2.56 2.01 1.35 2.93 0.84 1.01 0.84 1.01 0.84 1.01 0.90 1.32 0.90 1.32 0.90 1.33 2.66 2.11 1.43 3.07 16 Description CMOS input buffer CMOS input buffer with pull-up CMOS input buffer with pull-down TTL input buffer TTL input buffer with pull-up TTL input buffer with pull-down CMOS Schmitt trigger input buffer TTL Schmitt trigger input buffer 0.8 micron CMOS Gate Arrays Digital ASICs Products and Services August 1993 Output Pad Cells Name OB01X1 OB01X2 OB01X3 OB01X5 OB03X1 OB03X2 OB03X3 OB03X5 OB06X1 OB06X2 OB06X3 OB07X1 OB07X2 OB07X3 Eq Gates 1 I/O 1 I/O 1 I/O 1 I/O 1 I/O 1 I/O 1 I/O 1 I/O 1 I/O 1 I/O 1 I/O 1 I/O 1 I/O 1 I/O 1 I/O OB09X1 tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPZ tPLH tPZ tPLH tPZ tPZ tPHL tPZ tPHL tPZ tPHL A to Q EN to Q 1 I/O OB09X2 A to Q EN to Q 1 I/O OB09X3 A to Q EN to Q 1 I/O OB15X1 Parameters A to Q EN to Q Propagation Delay (ns) Description 25pF 50pF 75pF 7.20 10.60 3.79 10.45 2.24 5.60 1.55 3.24 12.87 6.94 6.61 6.78 3.66 3.75 2.30 2.32 11.05 10.18 15.04 5.28 14.87 2.99 7.81 1.94 4.35 18.39 9.70 9.37 9.54 5.04 5.13 3.00 3.01 16.58 5.76 8.50 CMOS P-channel, open drain, inverting output buffer, 2mA 3.32 4.71 CMOS P-channel, open drain, inverting output buffer, 4mA 8.80 13.20 TTL N-channel, open drain output buffer, 1mA 8.47 12.87 TTL N-channel, open drain output buffer, 2mA tPLH tPHL tZH tZL 4.22 6.21 2.30 6.07 1.49 3.40 1.15 2.14 7.34 4.19 3.85 4.01 2.27 2.37 1.59 1.62 5.53 0.81 3.02 0.85 1.94 1.06 0.51 4.40 0.36 4.06 0.40 2.25 7.24 4.18 7.38 4.20 4.44 12.77 6.94 12.91 6.96 6.63 18.31 9.71 18.44 9.73 tPLH tPHL tZH tZL 4.10 4.21 4.25 4.21 6.86 6.96 7.01 6.97 9.62 9.72 9.77 9.73 CMOS tri-state output buffer, 2mA tPLH tPHL tZH tZL 2.41 2.43 2.64 2.41 3.80 3.81 4.02 3.80 5.19 5.19 5.40 5.19 CMOS tri-state output buffer, 4mA tPLH tPHL tZH tZL 4.13 6.20 4.26 6.23 7.11 10.61 7.24 10.64 10.09 15.04 10.22 15.06 TTL tri-state output buffer, 1mA 17 TTL output buffer, 1mA TTL output buffer, 2mA TTL output buffer, 4mA TTL output buffer, 8mA CMOS output buffer, 1mA CMOS output buffer, 2mA CMOS output buffer, 4mA CMOS output buffer, 8mA CMOS P-channel, open drain, inverting output buffer, 1mA TTL N-channel, open drain output buffer, 4mA CMOS tri-state output buffer, 1mA 0.8 micron CMOS Gate Arrays Digital ASICs Products and Services August 1993 Output Pad Cells (Continued) Name Eq Gates 1 I/O OB15X2 OB15X3 OB83X5 1 I/O 1 I/O OB86X5 OB87X5 1 I/O 1 I/O OB89X5 75pF tPLH tPHL tZH tZL 2.51 6.24 2.66 6.24 4.01 10.62 4.16 10.62 5.50 15.06 5.64 15.07 TTL tri-state output buffer, 2mA tPLH tPHL tZH tZL 1.60 3.45 1.82 3.44 2.36 5.65 2.58 5.65 3.11 7.86 3.33 7.86 TTL tri-state output buffer, 4mA tPLH tPHL tPLH tPHL tPLH tPZ 1.50 3.38 2.30 2.40 2.64 1.23 2.25 5.48 3.68 3.78 4.02 2.99 7.52 5.06 5.16 5.40 TTL output buffer, 8mA, with controlled slew rate output tPZ tPHL A to Q tPLH tPHL tZH tZL 0.56 3.03 2.42 2.46 2.76 2.44 5.10 3.81 3.84 4.15 3.82 7.17 5.20 5.22 5.54 5.21 tPLH tPHL tZH tZL 1.61 3.48 1.95 3.45 2.37 5.65 2.71 5.63 3.12 7.80 3.45 7.78 A to Q A to Q EN to Q 1 I/O OB95X5 Description 50pF EN to Q 1 I/O Propagation Delay (ns) 25pF EN to Q 1 I/O OB81X5 Parameters A to Q EN to Q CMOS output buffer with controlled slew rate output, 8mA CMOS inverting open drain P-channel output buffer with controlled slew rate output, 8mA TTL open drain N-channel output buffer with controlled slew rate output, 8mA CMOS tri-state output buffer with controlled slew rate output, 8mA TTL tri-state output buffer with controlled slew rate output, 8mA Input/Output Pad Cells Name Eq Gates 1 I/O IO01X1 A to IO EN to IO 1 I/O IO01X2 A to IO EN to IO 1 I/O IO01X3 Parameters A to IO EN to IO Propagation Delay (ns) Description 25pF 50pF 75pF tPLH tPHL tZH tZL 4.14 6.21 4.28 6.23 7.12 10.63 7.26 10.65 10.10 15.04 10.24 15.06 TTL I/O buffer, 1mA tPLH tPHL tZH tZL tPLH tPHL tZH tZL 2.52 6.23 2.67 6.23 1.61 3.46 1.82 3.44 4.02 10.65 4.16 10.65 2.36 5.66 2.58 5.65 5.51 15.06 5.65 15.07 3.11 7.86 3.33 7.86 TTL I/O buffer, 2mA 18 TTL I/O buffer, 4mA 0.8 micron CMOS Gate Arrays Digital ASICs Products and Services August 1993 Input/Output Pad Cells (Continued) Name Eq Gates 1 I/O IO03X1 A to IO EN to IO 1 I/O IO03X2 A to IO EN to IO 1 I/O IO03X3 A to IO EN to IO 1 I/O IO3CX1 A to IO EN to IO 1 I/O IO3CX2 A to IO EN to IO 1 I/O IO3CX3 A to IO EN to IO 1 I/O IO3FX1 A to IO EN to IO 1 I/O IO3FX2 A to IO EN to IO 1 I/O IO3FX3 A to IO EN to IO 1 I/O IO41X1 A to IO EN to IO 1 I/O IO41X2 Parameters A to IO EN to IO Propagation Delay (ns) Description 25pF 50pF 75pF tPLH tPHL tZH tZL 7.27 4.18 7.40 4.21 12.79 6.95 12.93 6.98 18.32 9.72 18.46 9.74 CMOS I/O buffer, 1mA tPLH tPHL tZH tZL 4.10 4.21 4.25 4.21 6.87 6.97 7.01 6.98 9.63 9.74 9.78 9.74 CMOS I/O buffer, 2mA tPLH tPHL tZH tZL 2.41 2.44 2.63 2.42 3.80 3.82 4.02 3.81 5.19 5.20 5.41 5.20 CMOS I/O buffer, 4mA tPLH tPHL tZH tZL 7.35 4.17 7.49 4.21 12.90 6.91 13.04 6.97 18.45 9.65 18.59 9.73 CMOS I/O buffer with pull-down, 1mA tPLH tPHL tZH tZL 4.14 4.20 4.28 4.21 6.91 6.95 7.05 6.97 9.68 9.70 9.83 9.73 CMOS I/O buffer with pull-down, 2mA tPLH tPHL tZH tZL 1.92 1.90 2.09 1.90 3.26 3.24 3.42 3.24 4.58 4.57 4.75 4.57 CMOS I/O buffer with pull-down, 4mA tPLH tPHL tZH tZL 4.19 6.21 4.33 6.25 7.18 10.59 7.32 10.65 10.17 14.98 10.30 15.05 TTL I/O buffer with pull-down, 1mA tPLH tPHL tZH tZL 2.55 6.24 2.69 6.25 4.04 10.63 4.19 10.65 5.53 15.02 5.68 15.04 TTL I/O buffer with pull-down, 2mA tPLH tPHL tZH tZL 1.63 3.47 1.85 3.45 2.39 5.66 2.61 5.66 3.14 7.86 3.36 7.87 TTL I/O buffer with pull-down, 4mA tPLH tPHL tZH tZL 4.12 6.24 4.26 6.27 7.07 10.67 7.23 10.69 10.02 15.09 10.19 15.12 TTL I/O buffer with pull-up, 1mA tPLH tPHL tZH tZL 2.52 6.26 2.67 6.26 4.00 10.69 4.16 10.69 5.48 15.11 5.64 15.12 TTL I/O buffer with pull-up, 2mA 19 0.8 micron CMOS Gate Arrays Digital ASICs Products and Services August 1993 Input/Output Pad Cells (Continued) Name Eq Gates 1 I/O IO41X3 A to IO EN to IO 1 I/O IO42X1 A to IO EN to IO 1 I/O IO42X2 A to IO EN to IO 1 I/O IO42X3 A to IO EN to IO 1 I/O IO51X1 A to IO EN to IO 1 I/O IO51X2 A to IO EN to IO 1 I/O IO51X3 A to IO EN to IO 1 I/O IO81X5 A to IO EN to IO 1 I/O IO83X5 A to IO EN to IO 1 I/O IOBCX5 A to IO EN to IO 1 I/O IOBFX5 Parameters A to IO EN to IO Propagation Delay (ns) Description 25pF 50pF 75pF tPLH tPHL tZH tZL 1.61 3.47 1.82 3.45 2.36 5.68 2.58 5.67 3.11 7.88 3.33 7.88 TTL I/O buffer with pull-up, 4mA tPLH tPHL tZH tZL 7.23 4.20 7.38 4.23 12.72 6.98 12.88 7.00 18.20 9.75 18.38 9.77 CMOS I/O buffer with pull-up, 1mA tPLH tPHL tZH tZL 4.10 4.23 4.25 4.23 6.85 7.00 7.00 7.00 9.60 9.77 9.76 9.77 CMOS I/O buffer with pull-up, 2mA tPLH tPHL tZH tZL 2.42 2.45 2.63 2.43 3.81 3.83 4.03 3.82 5.19 5.21 5.41 5.21 CMOS I/O buffer with pull-up, 4mA tPLH tPHL tZH tZL 7.27 4.19 7.41 4.22 12.80 6.96 12.93 6.98 18.33 9.72 18.46 9.75 CMOS I/O buffer with Schmitt trigger input, 1mA tPLH tPHL tZH tZL 4.11 4.21 4.25 4.21 6.87 6.98 7.02 6.98 9.63 9.74 9.78 9.75 CMOS I/O buffer with Schmitt trigger input, 2mA tPLH tPHL tZH tZL 1.92 1.91 2.08 1.90 3.25 3.24 3.41 3.24 4.58 4.58 4.74 4.58 CMOS I/O buffer with Schmitt trigger input, 4mA tPLH tPHL tZH tZL 1.62 3.50 1.95 3.47 2.37 5.67 2.71 5.65 3.12 7.82 3.46 7.80 TTL I/O tri-state buffer with controlled slew rate output, 8mA tPLH tPHL tZH tZL 2.43 2.47 2.77 2.44 3.82 3.85 4.16 3.83 5.21 5.23 5.54 5.21 CMOS I/O tri-state buffer with controlled slew rate output, 8mA tPLH tPHL tZH tZL 2.45 2.47 2.79 2.44 3.84 3.85 4.18 3.83 5.22 5.23 5.56 5.21 CMOS I/O tri-state buffer with pull-down and controlled slew rate output, 8mA tPLH tPHL tZH tZL 1.62 3.50 1.96 3.47 2.38 5.67 2.72 5.66 3.13 7.81 3.47 7.80 TTL I/O tri-state buffer with pull-down and controlled slew rate output, 8mA 20 0.8 micron CMOS Gate Arrays Digital ASICs Products and Services August 1993 Input/Output Pad Cells (Continued) Name Eq Gates 1 I/O IOC1X5 Parameters A to IO EN to IO 1 I/O IOC2X5 A to IO EN to IO 1 I/O IOD1X5 A to IO EN to IO Propagation Delay (ns) Description 25pF 50pF 75pF tPLH tPHL tZH tZL 1.61 3.51 1.95 3.48 2.37 5.69 2.71 5.66 3.11 7.83 3.45 7.81 TTL I/O tri-state buffer with pull-up and controlled slew rate output, 8mA tPLH tPHL tZH tZL 2.43 2.48 2.77 2.45 3.82 3.86 4.16 3.84 5.20 5.24 5.54 5.23 CMOS I/O tri-state buffer with pull-up, and controlled slew rate output, 8mA tPLH tPHL tZH tZL 2.43 2.47 2.77 2.44 3.82 3.85 4.16 3.83 5.21 5.23 5.54 5.22 CMOS I/O tri-state buffer with Schmitt trigger and controlled slew rate output, 8mA Power Cells Name Eq Gates Description CVDD 1 CVSS 1 PP01X 1 I/O Core cell input resistive tie-up to core Vdd bus Core cell input resistive tie-down to core Vss bus Vss power pad for core and pad cells PP02X 1 I/O Vdd power pad for core and pad cells PP04X 1 I/O PPC1X 1 I/O PPP1X 1 I/O Optional power pad pin for additional busses Vss power pad pin for input buffers and core cells only Vss power pad pin for output buffers only 21 0.8 micron CMOS Gate Arrays Digital ASICs Products and Services August 1993 Delay Derating Information The propagation delays listed in the Selection Guide (pages 9 to 21) are for typical temperature, 25oC, typical supply voltage, 5.0V., and typical processing conditions. To calculate the delay at other conditions (including Vdd equals 3.0V) the following equation can be used: Tpdx = Tpdx(typ)*KP*KV*KT where Tpdx(typ) is given in the Selection Guide. KP, the process derating coefficient, KT, the temperature derating coefficient, and KV, the supply voltage derating coefficient are described below. Delay Variations with Temperature (KT) Delay varies linearly with temperature. The following formulas and common operating points can be used. Temp KT -55 oC 0.79 -25 oC 0.87 0 oC 0.94 25 oC 1.00 70 oC 1.11 100 oC 1.19 125 oC 1.26 Temp. Range KT Formula -55oC to 25oC KT=1.0-(25-TJoC)*2.58 x 10-3 25oC to 140oC KT=1.0+(TJoC-25)*2.58 x 10-3 Where TJoC is the temperature at the silicon junction. Delay Variations with Process (KP) Delay variations with process are given as fixed constants determined at the limits of acceptable manufacturing of the process. These are described below. DeratingCoefficient(Kp) ProcessVariationPoint 1.40 Delay increase due to "Worst Case Speed" (WCS) fabrication 1.00 Typical delay; fabrication target 0.61 Delay reduction due to "Worst Case Power" (WCP) fabrication Delay Variations with Voltage (KV) VDD KV 2.7 V 1.74 3.0 V 1.54 3.3 V 1.39 4.5 V 1.07 4.75 V 1.03 5.0 V 1.00 5.25 V 0.97 5.5 V 0.94 Derating Coefficient,KV Delay varies nonlinearly with voltage. Some common operating points and a characteristic curve are shown. 1.8 1.5 1.2 0.9 2.5 22 3.0 3.5 4.0 4.5 Supply Voltage (volts) 5.0 5.5 0.8 micron CMOS Gate Arrays Digital ASICs Products and Services August 1993 Packaging The AMI8Gx gate array family can be packaged in a variety of popular packages. New packages are in development which will extend the package offering. Some special packages or packaging requirements can be supplied if requested. More details on specific packages are available from an AMI sales representative. Available Packages Array G5 G9 G15 G21 G34 G44 G55 G65 G93 G142 G201 G247 G392 G663 ( ) = Lead time required PQFP TQFP CQFP PLCC JLDCC CLCC 44,52,64,80 44,52,64,80,100,120 44,52,64,80,100,120 44,52,64,80,100,120,128 44,52,64,80,100,120,128,144 44,52,64,80,100,120,128,144,160 44,52,64,80,100,120,128,144,160 44,52,64,80,100,120,128,144,160 64,80,100,120,128,144,160,208 100,120,128,144,160,208 144,160,208 144,160,208,2562 208,3041,2 (48),64 64,100,(144) 64,(80),100,(128),(144) 64,(80),100,(128),(144) 64,(80),100,(128),(144) (80),100,(128),(144) (80),100,(128),(144) (80),100,(144),(176) 100,(144),(176) (176) 40 40 40 40 40,44,132 40,44,132 44,132 44,132 132,144 132,144 20,28,68 20,28,44,68 20,28,44,68,84 20,28,44,68,84 28,44,68,84 28,44,68,84 28,44,68,84 44,68,84 44,68,84 68,84 (84) 28 28 28,44,68,84 44,68,84 44,68,84 44,68,84 (44),68,(84) (44),68,84 68,84 68,84 84 20,24,28,44 24,28,44 24,28,36,40,44,48,52 28,36,40,44,48,52,84 28,36,40,44,48,52,68,84 36,40,44,48,52,68,84 44,48,68,84 44,48,68,84 68,84 68 Note1: The304pinPowerQuad2TMpackagehasaheatslugaddedtoimprovepowerdissipation. Array G5 G9 G15 G21 G34 G44 G55 G65 G93 G142 G201 G247 G392 G663 MQUAD PDIP 8,14,16,18,20,22,24,28,40,48 22,24,28,40,48 22,24,28,40,48 22,24,28,40,48 144 24,28,40,48 144 24,28,40,48 128,144 28,40,48 128,144 28,40 128,144,(160) (40) 128,(144),(160),(208) (144),(160),(208) (144),(160),(208) (144),(160),(208) PPGA CPGA 69,85,101,109,121,145 69,85,101,109,121,145 69,85,101,109,121,145 69,85,101,109,121,132,145 69,101,109,121,132,145 69,121,132,145,180 145,180 180 PQFP = Plastic Quad Flatpack TQFP = Thin Quad Flatpack (plastic) MQUAD = Metal Quad Flatpack CQFP = Ceramic Qual Flatpack PLCC = Plastic Leaded Chip Carrier - J lead JLDCC = Ceramic Leaded Chip Carrier - J lead 68 68 (65),68,69,(85),121,145 (65),68,69,(85),121,145 (65),68,69,85,101,121,145 68,69,85,101,121,145 68,69,85,101,121,145 68,69,85,101,(145) 68,84,85,109,121,132,(145),208 68,84,109,121,132,145,177,181,208 145 145 476 CLCC = Leadless Chip Carrier (ceramic) PDIP = Plastic Dual In-line Package PPGA = Plastic Pin Grid Array CPGA = Ceramic Pin Grid Array BGA = Ball Grid Array 23 23 BGA (169) (169) (169) (169) (169),(225) (169),(225),(313) (169),(225),(313) (169),(225),(313) (225),(313) (313) AMI Trademarks ACCESSTM Enhanced Design UtilitiesTM NETSCANTM Other Trademarks Synopsys is a registered trademark of Synopsys, Inc. Cadence, Valid, and Verilog are registered trademarks of Cadence Design Systems, Inc. Mentor Graphics is a registered trademark of Mentor Graphics Corporation. Viewlogic is a registered trademark of Viewlogic Systems, Inc. IKOS is a registered trademark of IKOS Systems, Inc. MQUAD is a registered trademark of Olin Corporation. PowerQuad is a trademark of Amkor Electronics Inc. TapePak is a registered trademark of National Semiconductor Corporation. Copyright(R)1997, American Microsystems, Inc. Devices sold by AMI are covered by the warranty and patent indemnification provisions appearing in its Terms of Sale only. AMI makes no warranty, express, statutory implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from patent infringement. AMI makes no warranty of merchantability or fitness for any purposes. AMI reserves the right to discontinue production and change specifications and prices at any time and without notice. AMI's products are intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recommended without additional processing by AMI for such applications. American Microsystems, Inc., 2300 Buckskin Rd., Pocatello, ID 83201, (208) 233-4690, FAX (208) 234-6796