"AMI’s 0.8
µ
m Gate Array family is simply
the best 0.8
µ
m on the market
. . . one of
the highest performance, yet lowest cost array
products available today . . ."
■
Designed for 3V, 5V, or 3V/5V mixed supplies
■
210 ps gate delays (fanout = 2)
■
5,000 to 663,000 available gate densities
■
Complete package lineup
quad flatpack (QFP), LCC, DIP, grid array . . .
■
Usable megafunctions
Families of single port RAMs, microprocessors,
controllers, datapath functions . . .
■
"Made in America"
engineering, manufacturing, and support
No ‘overseas’ delays to your important questions; we’re
right here, ready to help.
Table of Contents
Features…………………………………………………………………………… 1
AMI8Gx Gate Array Family …………………………………………………… 1
Architectural Overview ………………………………………………………… 2
Product Applications…………………………………………………………… 3
ASIC Design Tools and Methodology ……………………………………… 3
The Design Library……………………………………………………………… 5
DC Specifications ……………………………………………………………… 6
Library Cell Selection Guide …………………………………………… 8 - 21
Delay Derating Information …………………………………………………… 22
Packaging ………………………………………………………………………… 23
1
0.8 micron CMOS
Gate Arrays
Digital ASICs
August 1993
Products and Services
• JTAG Boundary Scan macro support
•
Cost driven architecture:
- Offers both 2 and 3 level metal interconnect to
provide the lowest user cost for the number of
gates and pads required.
- Provides 6 extra power pads per corner to pre-
serve more I/O cells for signal use.
- Contains extra I/O cells to provide extra drive
without wasting bond pads.
•
Extensive library for quick design:
- Complete primary cell and I/O library.
- Synchronous single port RAM compilers with
over 2000 compiled RAM sizes from 32x1 to
1Kx32 bits.
- MG65C02, MG29C01, MG29C10, MG80C85,
MG82Cxx, MGMC51 megacells.
- Various datapath logic synthesizers (FIFOs,
multipliers, adders, barrel shifters).
•
Wide range of packaging:
Full QFP and LCC line,
DIPs and PGAs, individual die, (ball grid array package
under study). Burn-in capability as needed.
• Full operating voltage range from 2.7V to 5.5V
• ESD protection > 2kV; latchup > 100mA
• Power equals 3.2
µ
W/MHz/cell
AMI’s “AMI8Gx” series of 0.8
µ
m gate arrays exploits a
proprietary power grid and track routing architecture on a
compact, channelless, sea-of-gates design to pro vide one
of the highest perfor mance, cost effective array products
available today.
Features
•
3V, 5V, and combined 3V/5V operation:
Each
individual pad cell can be driven independently b y a 3V
or 5V supply. 3V to 5V and 5V to 3V level shift is
available in all I/O cells. Core can be either 3V for low
power or 5V for high speed.
•
Operating T emp equals -55 to 125
o
C:
F ew competing
products allow this range.
•
Excellent performance:
- 260 MHz maximum toggle rate on clocked flip-flops
(T
J
= 135
o
C).
- 200 ps delay (FO=2) for a 2-input NAND gate.
Clock tree generation:
≤
400 ps clock skew
(fan out = 3500 at 80 MHz).
•
1 to 16 mA drive per single I/O cell:
Selectable I/O
drive with controllable slew rate. Extra I/O cells allow
combined I/O drive up to 96mA without reducing pad
count.
•
Automatic Test Program Generation:
Includes scan
macros (NETSCAN
) for high fault coverage.
AMI8Gx Gate Array Family
Note 1: Exact usable gate count will vary depending on design interconnect and macro selection.
Note 2: 24 optional fixed power pins (6 in each corner) are not included in this number.
Part Number Raw Gates Usable Gates
1
Available
I/O Cells Available
Bond Pads
2
Triple Metal Double Metal
AMI8G663 663,350 464,350 331,700 732 528
AMI8G392 392,160 274,500 196,100 564 424
AMI8G247 246,790 172,750 123,400 448 336
AMI8G201 200,740 140,500 100,400 404 304
AMI8G142 141,590 99,100 70,800 340 256
AMI8G93 92,740 64,900 46,400 276 208
AMI8G65 65,420 45,800 32,700 232 176
AMI8G55 54,700 38,300 27,400 212 160
AMI8G44 44,460 31,100 22,200 192 144
AMI8G34 33,860 23,700 16,900 168 128
AMI8G21 20,800 14,550 10,400 132 100
AMI8G15 14,960 10,470 7,480 112 84
AMI8G9 8,900 6,230 4,450 88 68
AMI8G5 5,250 3,670 2,630 68 52
2
0.8 micron CMOS
Gate Arrays
Digital ASICs
August 1993
Products and Services
Architectural Overview
Some important elements of the AMI8Gx gate array
family are:
•
[Note 1]
Drawn gate length of 0.8 micron; 2 or 3 level
metal interconnect selectable.
•
[Note 2]
Two p-channel and two n-channel transistors
per site (or cell). Sites are arrayed in a sea-of-gates
structure that can allow interconnect routing ov er activ e
sites. Also, p-channel transistors are sized larger than
the stronger n-channel transistors in each cell to
provide better matched rise times and fall times.
•
[Note 3]
Four separate power busses for I/O cells to
allow separate supplies f or output b uff ers, input b uffers ,
and mix ed V
DD
le vels all on an individual I/O cell basis.
Two separate power busses for core logic (not shown).
Extra corner power pads [note 4]
Core cell sites with 4 transistors [note 2]
2 P-channel
2 N-channel
Separately configured power busses for I/O and core [note 3]
Large I/O driver with prebuffer [note 5]
Selectable 2 or 3 metal interconnect [note 1]
FIGURE 1: GATE ARRAY ARCHITECTURE
•
[Note 4]
Twenty-four (six per cor ner) fixed power pads
(not included in Bond P ad count in Table 1) a v ailable on
each array for customer use.
• Each I/O cell can be configured as 5V V
DD
, 3V V
DD
,
V
SS
, or signal I/O.
•
[Note 5]
Each I/O cell has selectable driv e from 1mA to
16mA. All I/O cell logic can be built in the I/O cell
prebuffer. Level shifting (3V to 5V or 5V to 3V) may
require the use of a few core gates.
3
0.8 micron CMOS
Gate Arrays
Digital ASICs
August 1993
Products and Services
Product Applications
The f amily’s e xtended temper ature and voltage operation
range make it well suited for telecom, industrial, and
military applications. The low cost structure also makes it
ideal in computer and office automation ASIC
requirements.
FPGA OR PAL CONVERSION:
AMI can conver t netlists
from most FPGA and PAL devices to a more cost and
performance effective AMI8Gx gate array design for
volume production.
2ND SOURCE EXISTING PRODUCTS:
Netlist
conversion capabilities from AMI allow a competitive
alternate supply with AMI8Gx for current high volume
designs.
NEW DESIGN CAPTURE:
AMI8Gx design is suppor ted
by man y popular third party software platforms, as well as
AMI’s Enhanced Design Utilities
(EDU) environment.
PROCESS UPGRADE:
Designs done in AMI’s 1.25
µ
m
and 1.0
µ
m gate array families can easily be upgraded to
the AMI8Gx family. The AMI ASIC Standard Library
provides a common netlist design base.
ASIC Design Tools and Methodology
AMI8Gx and other AMI ASIC families are supported on
popular third party products:
• Cadence
• Mentor Graphics
• Synopsys
• Viewlogic
• Valid
• Verilog
simulation
•IKOS
simulation accelerator
(AMI’s sign-off simulator)
AMI has maintained critical proprietary software tools to
ensure a tight, well coupled design to our silicon process.
This methodology includes our expert-system design
analysis tools, AMI’s Enhanced Design Utilities (EDU), a
software support methodology that covers the complete
set of wafer processing possibilities, and a dedicated,
experienced engineering staff that can assist at any level
of the design process.
AMI Design Flow
AMI will supply an AMI8Gx design kit which includes a
cell library containing symbols, simulation models and
software for design verification, timing calculations, and
netlist generation. For pre-layout timing simulations,
capacitance values derived from statistical averages of
known layouts are used. Once actual layout is completed
by AMI, a post-layout interconnect capacitance table will
be supplied for final validation of device timing.
Figure 2 shows a typical design flow for a new design.
4
0.8 micron CMOS
Gate Arrays
Digital ASICs
August 1993
Products and Services
AMI Design Flow (cont.)
Working with an AMI design center, the customer is
responsible for capturing and verifying the design using
the AMI ASIC Standard Library. He is also responsible for
creating the test vectors that will eventually serve as the
logical par t of the manufacturing test. Software aids such
as logic synthesis, megacells, automatic test program
generation, netlist rule check ers, etc. can greatly speed up
this process. (A fault coverage check of the test vector set
is optional and can be done as an additional service.)
When the design is received by the factory, the “Design
Start Package” is reviewed by AMI engineers. This start
package, which is completed by the customer, contains
the device specification, netlist, critical timing paths, and
test vectors. The design is pre-screened on the Enhanced
Design Utilities (EDU) and then resimulated on IKOS,
AMI’s sign-off simulator. The results are compared to the
customer’s simulation from the third-party CAE tool.
Once the design has passed the initial screening it is then
ready for placement and routing. The layout proceeds by
first placing memory and megacells, assigning priority to
critical paths, and designing the distribution and buffer ing
of clocks. Next, the layout is completed with automatic
place-and-route on the balance of the circuit.
After layout has been completed the interconnect data is
extracted from the physical layout to be fed back to the
sign-off simulator for final circuit verification. This post
layout interconnect data can be sent to the customer for
final validation on his simulator. When the post-layout
simulation has been completed and approved by the
customer the design is then released for mask and wafer
fabrication.
The test program is developed in parallel using internal
automatic test program generation software. Prototypes
can then be tested before they are shipped.
Figure 3 outlines a typical software environment when
using third party tools. AMI uses EDIF to speed ports
between various software products.
AMI’s Enhanced Design Utilities tools are intended to be
used interactively at each stage of the design. EDU
software is a set of design analysis tools that check both
the design and test vectors for correctness and
compatibility with in-house ASIC testers, and analyz e the
design for inefficiencies and possible flaws that could
cause problems in manufacturing the device.
AMI Environment
Memory
Compiler
Models &
Symbols
Physical Data
Design
Verification
Place and Route
Post Route
Verification
ATPG
AMI ASIC
Std. Library
Synthesis T ool
Logic Synthesis
Schematic
Translation
HDL
VHDL
Schematic
Entry
Design
Database
Timing
Simulation
Estimated
Delays
Vector
Generation
Enhanced
Design Utilities
Netlist
Translation
AMI ASIC
Stnd. Library
Optional
Third Party
Environment
FIGURE 3: DESIGN ENVIRONMENT WITH THIRD PARTY SOFTWARE
in AMI Design Kit
**
**
**
Elements supplied
**
**
**
5
0.8 micron CMOS
Gate Arrays
Digital ASICs
August 1993
Products and Services
The Design Library
AMI provides a robust collection of building blocks for the
AMI8Gx gate array family. A broad range of pr imary cells
is complemented with memor y cell compilers and useful
megacells. With such broad, US-based design talent,
AMI can quickly design specific cells that customers need
to add an edge in customization.
The AMI ASIC Standard Library
The AMI ASIC Standard Library contains a rich set of
core and pad cells which allow great flexibility in building
competitive devices for customer applications . The libr ary
is portable across all AMI’s gate array and standard cell
families. The ASIC Standard Library is listed in detail on
pages 9 to 21.
Soft Datapath Library (xx by yy)
Name Function
MGAxxyyDv Adder
MGAxxyyEv Adder-subtracter
MGBxxyyAv Arithmetic/barrel shifter
MGBxxBv Barrel shifter
MGBxxCv Arithmetic shifter
MGCxxAv 2-function binary comparator
MGCxxBv 6-function binary comparator
MGDxxAv Decrementer
MGFxxyyC1 Latch-based FIFO
MGIxxAv Incrementer
MGIxxBv Incrementer/decrementer
MGMxxyyDv Signed/unsigned multiplier
MGMxxyyEv Multiplier-accumulator
MGSxxyyAv Signed/unsigned subtracter
Memory Compilers
The AMI8Gx family offers the memory compiler shown
above. Each of the thousands of possib le memory bloc ks
created by this compiler is optimized precisely to the
customers’ parameters rather than built from a presized
leaf cell that covers a range of sizes. This yields a better
size and performance match for each application.
Upon supplying the cell specification to AMI, the
customer can receive an accurate simulation timing
specification overnight by facsimile and a full simulation
model for any AMI supported software en vironment within
five working days.
Datapath Synthesizers
AMI8Gx also supports the complex datapath logic
functions listed here. These functions are synthesized
from an input set of design parameters, and can be
optimized for either minimum delay, minimum area or a
compromise between the two. Contact AMI for the size
range and parameter set for any desired functions.
These logic synthesizers produce soft megacell
schematics in the ASIC Standard Library, and a
schematic symbol for incorporation and simulation with
the design netlist.
Megacells
The AMI8Gx gate array family supports soft megacell
versions that are compatible with many popular
architectures. These products are listed on the following
page.
Soft megacells are functionally and logically compatible
with the stand alone products, but since the function is
captured in a gate array, each instance of the megacell
will differ slightly depending on its physical placement on
the array. Soft megacells become part of the design
netlist, requiring backannotation of interconnect
capacitance after place-and-route for final verification.
AMI supplies an actual gate le v el netlist and schematic of
the soft megacell allowing the user to make design
changes or remove unneeded features. Test vectors are
provided and can be used directly or incorporated into the
overall design test. All soft megacells are static designs
and use AMI’s ASIC Standard Library to ensure
portability.
Memory Compiler Library
NOTE: Other SRAM and ROM compilers are available for standard cell or embedded array design approaches.
Contact an AMI Design Center for details about these other product offerings.
Memory Compiler Size Increment Comments
min. max.
SRAM (single-port, synchronous) 32 x 1 1K x 32 16 words, 1 bit 9 ns typical access time on 1Kx16
6
0.8 micron CMOS
Gate Arrays
Digital ASICs
August 1993
Products and Services
MG82C50A Asynchronous comm. element
MG82C54 Programmable interval timer
MG82C55A Programmable peripheral interface
MG82C59A Programmable interrupt controller
MGMC51 8-bit microcontroller, 8051 compatible
MGMC51FB 8-bit microcontroller, 8051 compatible
Name Function
Soft Megacell Library
Name Function
MG1468C18 Real-time clock
MG29C01 4-bit microprocessor slice
MG29C10 Microprogram controller/sequencer
MG65C02 8-bit microprocessor
MG80C85 8-bit microprocessor
MG82C37A Programmable DMA controller
DC Specifications
Operating Specifications
Parameter Minimum Maximum Units
VDD, Supply Voltage 2.7 5.5 Volts
Ambient Temperature - Military -55 125 °C
- Commercial 0 70 °C
CMOS Input Specifications (4.5V<VDD<5.5V; -55oC<T<125oC)
Vil Low Level Input Voltage 0.3*VDD Volts
Vih High Level Input Voltage 0.7*VDD Volts
Iil Low Level Input Current -1.0 µA
Iih High Level Input Current 1.0 µA
Iil Input Pull-Up Current -30 -140 µA
Iih Input Pull-Down Current 30 185 µA
Vt- Schmitt Negative Threshold 0.2*VDD Volts
Vt+ Schmitt Positive Threshold 0.8*VDD Volts
Vh Schmitt Hysteresis 1.0 Volts
TTL Input Specifications (4.5V<VDD<5.5V; -55oC<T<125oC)
Vil Low Level Input Voltage 0.8 Volts
Vih High Level Input Voltage 2.0 Volts
Iil Low Level Input Current -1.0 µA
Iih High Level Input Current 1.0 µA
Iil Input Pull-Up Current -30 -140 µA
Iih Input Pull-Down Current 30 185 µA
Vt- Schmitt Negative Threshold 0.7 Volts
Vt+ Schmitt Positive Threshold 2.1 Volts
Vh Schmitt Hysteresis 0.4 Volts
7
0.8 micron CMOS
Gate Arrays
Digital ASICs
August 1993 Products and Services
8
0.8 micron CMOS
Gate Arrays
Digital ASICs
August 1993 Products and Services
Library Cell Selection Guide
This selection guide outlines the basic perfor mance of each cell in the AMI ASIC Standard Librar y. Other custom cells
can be created f or specific needs. F or detailed design analysis please contact an AMI ASIC Design Center f or a software
design kit and more detailed data sheets.
An explanation of the information contained in the selection guide is listed below:
Eq. Gates This column lists the equivalent gates of each core cell. It is a measure of the cell transistor count
but is normalized to the transistor count of a 2-input NAND gate. A 2-input NAND gate (NA21)
requires four transistors, hence, one equivalent gate equals four transistors.
I/O Cells This column lists the number of I/O sites (or pad sites) required to implement the listed I/O cell.
Parameters The parameters column lists the mnemonics for the propagation delay or timing parameter whose
values are given under “Propagation Delay”:
tPLH Input to output propagation delay for a rising edge on the output
tPHL Input to output propagation delay for a falling edge on the output
tZH High impedance to high level delay
tZL High impedance to low level delay
tsu Input setup time with respect to clock
th Input hold time
tPZ Valid to high impedance state on the output
Propagation This column shows the values of the delay parameter for three different loads. For output pad cells,
Delay 25pf, 50pf, and 75pf loads are used. For core cells and input pad cells, fanouts of two, four, and
eight gates are used. A fanout consists of that number of NA21 input capacitive loads and an aver-
age interconnect capacitance based on past layout experience. Delays are in nanoseconds.
Description This final column gives a short textual description of the cell.
9
0.8 micron CMOS
Gate Arrays
Digital ASICs
August 1993 Products and Services
Simple Gates
Name Eq
Gates Parameters Propagation Delay (ns) Description
2 FO 4 FO 8 FO
AA21 2t
PLH 0.47 0.60 0.84 2-input AND gate
tPHL 0.43 0.52 0.67
AA22 2t
PLH 0.46 0.53 0.66 2-input AND gate
tPHL 0.43 0.49 0.59
AA31 2t
PLH 0.67 0.80 1.06 3-input AND gate
tPHL 0.52 0.61 0.78
AA32 3t
PLH 0.70 0.78 0.92 3-input AND gate
tPHL 0.53 0.59 0.69
AA41 3t
PLH 0.89 1.03 1.30 4-input AND gate
tPHL 0.58 0.68 0.85
AA42 3t
PLH 0.92 1.01 1.16 4-input AND gate
tPHL 0.56 0.63 0.74
EN21 3t
PLH 0.56 0.72 1.18 Exclusive NOR
tPHL 0.52 0.64 0.88
EO21 3t
PLH 0.72 0.94 1.40 Exclusive OR
tPHL 0.61 0.70 0.86
NA21 1t
PLH 0.28 0.41 0.65 2-input NAND gate
tPHL 0.24 0.36 0.59
NA22 2t
PLH 0.22 0.28 0.41 2-input NAND gate
tPHL 0.18 0.24 0.36
NA31 2t
PLH 0.36 0.48 0.73 3-input NAND gate
tPHL 0.40 0.56 0.88
NA32 3t
PLH 0.28 0.34 0.47 3-input NAND gate
tPHL 0.29 0.38 0.54
NA41 2t
PLH 0.39 0.52 0.77 4-input NAND gate
tPHL 0.53 0.73 1.14
NA42 4t
PLH 0.32 0.39 0.52 4-input NAND gate
tPHL 0.43 0.54 0.75
NA51 3t
PLH 0.45 0.58 0.84 5-input NAND gate
tPHL 0.76 1.01 1.50
NA52 5t
PLH 0.36 0.43 0.57 5-input NAND gate
tPHL 0.61 0.74 0.99
NA61 5t
PLH 0.75 0.81 0.94 6-input NAND gate
tPHL 1.01 1.08 1.18
NA81 6t
PLH 0.77 0.83 0.96 8-input NAND gate
tPHL 1.12 1.19 1.29
NO21 1t
PLH 0.44 0.67 1.12 2-input NOR gate
tPHL 0.20 0.27 0.43
NO22 2t
PLH 0.33 0.44 0.68 2-input NOR gate
tPHL 0.15 0.19 0.27
NO31 2t
PLH 0.81 1.15 1.83 3-input NOR gate
tPHL 0.22 0.30 0.46
NO32 3t
PLH 0.59 0.77 1.12 3-input NOR gate
tPHL 0.16 0.21 0.29
NO41 2t
PLH 1.21 1.66 2.55 4-input NOR gate
tPHL 0.23 0.31 0.48
10
0.8 micron CMOS
Gate Arrays
Digital ASICs
August 1993 Products and Services
NO42 4t
PLH 0.93 1.16 1.63 4-input NOR gate
tPHL 0.17 0.21 0.30
NO51 3t
PLH 1.76 2.32 3.44 5-input NOR gate
tPHL 0.24 0.33 0.49
NO52 5t
PLH 1.40 1.69 2.27 5-input NOR gate
tPHL 0.18 0.22 0.31
OR21 2t
PLH 0.39 0.52 0.76 2-input OR gate
tPHL 0.53 0.63 0.80
OR22 2t
PLH 0.37 0.43 0.56 2-input OR gate
tPHL 0.58 0.64 0.75
OR31 2t
PLH 0.44 0.57 0.82 3-input OR gate
tPHL 0.88 1.00 1.20
OR32 3t
PLH 0.42 0.49 0.62 3-input OR gate
tPHL 0.97 1.05 1.18
OR41 3t
PLH 0.43 0.49 0.63 4-input OR gate
tPHL 1.36 1.45 1.60
OR42 5t
PLH 0.34 0.41 0.54 4-input OR gate
tPHL 1.07 1.15 1.29
Complex Gates
Name Eq
Gates Parameters Propagation Delay (ns) Description
2 FO 4 FO 8 FO
AN11 2t
PLH 0.72 0.95 1.41 Two 2-input ANDs into 2-input NOR
tPHL 0.37 0.49 0.73
AN31 2t
PLH 1.06 1.40 2.08 2-input AND into 3-input NOR
tPHL 0.31 0.42 0.65
AU11
7 A to S tPLH 1.45 1.58 1.83 One-bit full adder
tPHL 1.11 1.24 1.46
B to S tPLH 1.47 1.60 1.85
tPHL 1.13 1.24 1.43
CI to S tPLH 1.25 1.37 1.63
tPHL 1.11 1.23 1.42
ON11 2t
PLH 0.72 0.95 1.41 Two 2-input ORs into 2-input NAND
tPHL 0.42 0.54 0.79
ON31 2t
PLH 0.51 0.74 1.20 2-input OR into 3-input NAND
tPHL 0.49 0.65 0.98
Simple Gates (Continued)
Name Eq
Gates Parameters Propagation Delay (ns) Description
2 FO 4 FO 8 FO
11
0.8 micron CMOS
Gate Arrays
Digital ASICs
August 1993 Products and Services
Inverting Drivers
Name Eq
Gates Parameters Propagation Delay (ns) Description
2 FO 4 FO 8 FO
INV1 1t
PLH 0.24 0.36 0.61 Inverter
tPHL 0.17 0.25 0.40
INV2 1t
PLH 0.17 0.24 0.36 Inverter
tPHL 0.12 0.16 0.24
INV3 2t
PLH 0.14 0.19 0.27 Inverter
tPHL 0.10 0.13 0.19
INV4 2t
PLH 0.12 0.16 0.22 Inverter
tPHL 0.08 0.11 0.15
INV5 3t
PLH 0.12 0.15 0.20 Inverter
tPHL 0.08 0.10 0.14
INV6 3t
PLH 0.11 0.14 0.18 Inverter
tPHL 0.07 0.09 0.13
Internal 3-State Drivers
Name Eq
Gates Parameters Propagation Delay (ns) Description
2 FO 4 FO 8 FO
ITA1
2 A to Q tPLH 0.65 0.87 1.34 Internal non-inverting tri-state buffer
tPHL 0.48 0.60 0.84
EN to Q tZH 0.37 0.60 1.06
tZL 0.34 0.46 0.70
ITA2
4 A to Q tPLH 0.58 0.66 0.81 Internal non-inverting tri-state buffer
tPHL 0.53 0.58 0.67
EN to Q tZH 0.23 0.31 0.45
tZL 0.30 0.35 0.44
ITB1
2 A to QN tPLH 0.51 0.74 1.20 Internal inverting tri-state buffer
tPHL 0.28 0.40 0.64
EN to QN tZH 0.37 0.59 1.05
tZL 0.33 0.45 0.69
ITB2
4 A to QN tPLH 0.36 0.44 0.59 Internal inverting tri-state buffer
tPHL 0.21 0.25 0.34
EN to QN tZH 0.23 0.31 0.45
tZL 0.30 0.35 0.43
ITD1
2 A to QN tPLH 0.52 0.74 1.20 Internal inverting tri-state buffer
tPHL 0.28 0.39 0.63
E to QN tZH 0.45 0.68 1.13
tZL 0.20 0.32 0.56
ITD2
4 A to QN tPLH 0.38 0.46 0.61 Internal inverting tri-state buffer
tPHL 0.19 0.24 0.32
E to QN tZH 0.36 0.44 0.59
tZL 0.12 0.17 0.25
ITE1
1 A to QN tPLH 0.51 0.74 1.19 Internal inverting tri-state buffer
tPHL 0.28 0.39 0.63
EN to QN tZH 0.44 0.67 1.12
E to QN tZL 0.26 0.38 0.61
12
0.8 micron CMOS
Gate Arrays
Digital ASICs
August 1993 Products and Services
Clock Drivers
Name Eq
Gates Parameters Propagation Delay (ns) Description
2 FO 4 FO 8 FO
IID2 2t
PLH 0.32 0.39 0.51 Non-inverting clock driver
tPHL 0.36 0.41 0.50
IID4 3t
PLH 0.31 0.34 0.41 Non-inverting clock driver
tPHL 0.35 0.38 0.43
IID6 4t
PLH 0.35 0.37 0.42 Non-inverting clock driver
tPHL 0.40 0.43 0.46
Muxes and Decoders
Name Eq
Gates Parameters Propagation Delay (ns) Description
2 FO 4 FO 8 FO
DC24
8 Sx to QN tPLH 0.48 0.61 0.85 2:4 line decoder
tPHL 0.61 0.78 1.10
EN to QN tPLH 0.64 0.76 1.01
tPHL 0.77 0.93 1.01
DC38
20 Sx to QN tPLH 0.63 0.71 0.88 3:8 line decoder
tPHL 0.88 1.00 1.25
EN to QN tPLH 0.89 1.02 1.28
tPHL 1.15 1.36 1.76
MX21
3 Ix to Q tPLH 0.59 0.72 0.98 2:1 digital multiplexer
tPHL 0.66 0.78 0.98
S to Q tPLH 0.77 0.90 1.15
tPHL 0.85 0.97 1.16
MX41
8 Ix to Q tPLH 1.14 1.28 1.54 4:1 digital multiplexer
tPHL 1.09 1.28 1.58
S to Q tPLH 1.16 1.30 1.57
tPHL 1.46 1.64 1.92
MX81
20 Ix to Q tPLH 1.47 1.59 1.84 8:1 digital multiplexer
tPHL 1.46 1.57 1.77
S to Q tPLH 1.45 1.58 1.82
tPHL 1.52 1.64 1.83
13
0.8 micron CMOS
Gate Arrays
Digital ASICs
August 1993 Products and Services
Sequential Logic
Name Eq
Gates Parameters Propagation Delay (ns) Description
2 FO 4 FO 8 FO
DF081
6 C to Q tPLH 0.79 1.01 1.46 D-type F/F without set or reset
tPHL 0.33 0.44 0.68
D Setup tsu 0.76
D Hold th0.00
DF091
7 C to Q tPLH 0.68 0.81 1.07 D-type F/F with active low set
tPHL 1.10 1.24 1.51
D Setup tsu 0.82
D Hold th0.00
DF0A1
7 C to Q tPLH 0.91 1.14 1.60 D-type F/F with active low reset
tPHL 0.98 1.09 1.29
D Setup tsu 0.76
D Hold th0.00
DF0B1
9 C to Q tPLH 0.69 0.82 1.07 D-type F/F with active low set and reset
tPHL 1.11 1.25 1.51
D Setup tsu 0.81
D Hold th0.00
DF101
8 C to Q tPLH 0.59 0.73 0.98 D-type buffered F/F with active low set
tPHL 0.91 1.04 1.24
D Setup tsu 0.80
D Hold th0.00
DF111
8 C to Q tPLH 0.59 0.72 0.97 D-type buffered F/F with active low reset
tPHL 0.92 1.05 1.25
D Setup tsu 0.73
D Hold th0.00
DF121
10 C to Q tPLH 0.59 0.72 0.98 D-type buffered F/F with active low set
and reset
tPHL 0.89 1.01 1.21
D Setup tsu 0.81
D Hold th0.00
DL531
3 D to Q tPLH 0.71 0.84 1.09 D-type latch without set or reset
tPHL 0.88 0.99 1.18
GN to Q tPLH 0.86 0.99 1.23
tPHL 0.75 0.86 1.06
D Setup tsu 0.88
D Hold th0.00
DL541
5 D to Q tPLH 0.96 1.18 1.63 D-type latch with active low reset
tPHL 0.83 0.93 1.11
GN to Q tPLH 1.12 1.34 1.79
tPHL 0.71 0.80 0.99
D Setup tsu 1.18
D Hold th0.00
DL551
4 D to Q tPLH 0.73 0.85 1.10 D-type latch with active low set
tPHL 0.97 1.10 1.35
GN to Q tPLH 0.87 1.00 1.25
tPHL 0.85 0.98 1.23
D Setup tsu 1.10
D Hold th0.00
14
0.8 micron CMOS
Gate Arrays
Digital ASICs
August 1993 Products and Services
DL561
5 D to Q tPLH 0.92 1.05 1.31 D-type latch with activ e low set and reset
tPHL 1.02 1.15 1.40
GN to Q tPLH 1.03 1.16 1.42
tPHL 0.89 1.02 1.28
D Setup tsu 1.15
D Hold th0.00
DL641
6 D to Q tPLH 1.26 1.38 1.62 D-type buffered latch with active low
reset
tPHL 1.16 1.24 1.39
GN to Q tPLH 1.40 1.52 1.76
tPHL 1.04 1.12 1.27
D Setup tsu 0.87
D Hold th0.00
DL651
6 D to Q tPLH 1.03 1.15 1.39 D-type buffered latch with active low set
tPHL 1.30 1.38 1.53
GN to Q tPLH 1.18 1.30 1.54
tPHL 1.18 1.26 1.42
D Setup tsu 0.85
D Hold th0.00
DL661
6 D to Q tPLH 1.23 1.35 1.60 D-type buffered latch with active low set
and reset
tPHL 1.38 1.47 1.62
GN to Q tPLH 1.34 1.46 1.70
tPHL 1.26 1.34 1.49
D Setup tsu 0.94
D Hold th0.00
DLZ01
4 D to Q tPLH 0.80 0.93 1.18 D-type latch without set or reset and a
dual-enable tri-state output
tPHL 1.01 1.13 1.34
GN to Q tPLH 0.94 1.07 1.32
tPHL 0.88 1.00 1.21
D Setup tsu 1.02
D Hold th0.00
DLZ11
5 D to Q tPLH 1.07 1.20 1.47 D-type latch with active low reset and a
dual-enable tri-state output
tPHL 1.06 1.18 1.39
GN to Q tPLH 1.16 1.31 1.57
tPHL 0.93 1.05 1.27
D Setup tsu 1.13
D Hold th0.00
JK091
11 C to Q tPLH 0.81 0.95 1.20 JK-type F/F with active low set
tPHL 1.32 1.48 1.76
J Setup tsu 1.39
J Hold th0.00
K Setup tsu 1.10
K Hold th0.00
Sequential Logic (Continued)
Name Eq
Gates Parameters Propagation Delay (ns) Description
2 FO 4 FO 8 FO
15
0.8 micron CMOS
Gate Arrays
Digital ASICs
August 1993 Products and Services
16
0.8 micron CMOS
Gate Arrays
Digital ASICs
August 1993 Products and Services
Special Cells
Name Eq
Gates Parameters Propagation Delay (ns) Description
2 FO 4 FO 8 FO
BL02 4t
PLH 0.33 Tri-state bus latch
tPHL 0.68
QD01X1 2 I/O QO to QC tPLH 0.69 0.73 0.80 3.58MHz (1MHz - 10MHz) crystal oscil-
lator
tPHL 0.65 0.69 0.76
QD03X1 2 I/O QO to QC tPLH 0.88 0.92 1.00 20MHz (10MHz - 32MHz) cyrstal oscilla-
tor
tPHL 0.89 0.93 1.01
QD11X1 2 I/O QO to QC tPLH 2.51 2.57 2.67 32KHz (1KHz - 1MHz) crystal oscillator
with Schmitt Trigger
tPHL 1.90 1.95 2.05
TD08 11 tPLH 9.25 9.34 9.50 Time delay cell, non-inverting
tPHL 9.50 9.60 9.80
PORA 2 I/O RST to
POR tPLH 861.9 862.0 862.1 Power-on-reset
tPHL 4.95 5.10 5.26
PORB 2 I/O RST to
POR tPLH 1587.3 1587.3 1587.5 Power-on-reset for 3 volt operation
tPHL 9.42 9.60 10.01
Input Pad Cells
Name Eq
Gates Parameters Propagation Delay (ns) Description
2 FO 4 FO 8 FO
IB01X1 1 I/O tPLH 0.71 0.76 0.84 CMOS input buffer
tPHL 0.89 0.93 1.01
IB03X1 1 I/O tPLH 0.71 0.76 0.84 CMOS input buffer with pull-up
tPHL 0.88 0.93 1.01
IB05X1 1 I/O tPLH 0.71 0.76 0.84 CMOS input buffer with pull-down
tPHL 0.89 0.93 1.01
IB07X1 1 I/O tPLH 0.78 0.82 0.90 TTL input buffer
tPHL 1.17 1.22 1.32
IB09X1 1 I/O tPLH 0.78 0.83 0.90 TTL input buffer with pull-up
tPHL 1.17 1.22 1.32
IB0BX1 1 I/O tPLH 0.78 0.83 0.90 TTL input buffer with pull-down
tPHL 1.17 1.23 1.33
IB0DX1 1 I/O tPLH 2.49 2.56 2.66 CMOS Schmitt trigger input buffer
tPHL 1.95 2.01 2.11
IB30X1 1 I/O tPLH 1.31 1.35 1.43 TTL Schmitt trigger input buffer
tPHL 2.85 2.93 3.07
17
0.8 micron CMOS
Gate Arrays
Digital ASICs
August 1993 Products and Services
Output Pad Cells
Name Eq
Gates Parameters Propagation Delay (ns) Description
25pF 50pF 75pF
OB01X1 1 I/O tPLH 4.22 7.20 10.18 TTL output buffer, 1mA
tPHL 6.21 10.60 15.04
OB01X2 1 I/O tPLH 2.30 3.79 5.28 TTL output buffer, 2mA
tPHL 6.07 10.45 14.87
OB01X3 1 I/O tPLH 1.49 2.24 2.99 TTL output buffer, 4mA
tPHL 3.40 5.60 7.81
OB01X5 1 I/O tPLH 1.15 1.55 1.94 TTL output buffer, 8mA
tPHL 2.14 3.24 4.35
OB03X1 1 I/O tPLH 7.34 12.87 18.39 CMOS output buffer, 1mA
tPHL 4.19 6.94 9.70
OB03X2 1 I/O tPLH 3.85 6.61 9.37 CMOS output buffer, 2mA
tPHL 4.01 6.78 9.54
OB03X3 1 I/O tPLH 2.27 3.66 5.04 CMOS output buffer, 4mA
tPHL 2.37 3.75 5.13
OB03X5 1 I/O tPLH 1.59 2.30 3.00 CMOS output buffer, 8mA
tPHL 1.62 2.32 3.01
OB06X1 1 I/O tPLH 5.53 11.05 16.58 CMOS P-channel, open drain, inverting
output buffer, 1mA
tPZ 0.81
OB06X2 1 I/O tPLH 3.02 5.76 8.50 CMOS P-channel, open drain, inverting
output buffer, 2mA
tPZ 0.85
OB06X3 1 I/O tPLH 1.94 3.32 4.71 CMOS P-channel, open drain, inverting
output buffer, 4mA
tPZ 1.06
OB07X1 1 I/O tPZ 0.51 TTL N-channel, open drain output b uffer ,
1mA
tPHL 4.40 8.80 13.20
OB07X2 1 I/O tPZ 0.36 TTL N-channel, open drain output b uffer ,
2mA
tPHL 4.06 8.47 12.87
OB07X3 1 I/O tPZ 0.40 TTL N-channel, open drain output b uffer ,
4mA
tPHL 2.25 4.44 6.63
OB09X1
1 I/O A to Q tPLH 7.24 12.77 18.31 CMOS tri-state output buffer, 1mA
tPHL 4.18 6.94 9.71
EN to Q tZH 7.38 12.91 18.44
tZL 4.20 6.96 9.73
OB09X2
1 I/O A to Q tPLH 4.10 6.86 9.62 CMOS tri-state output buffer, 2mA
tPHL 4.21 6.96 9.72
EN to Q tZH 4.25 7.01 9.77
tZL 4.21 6.97 9.73
OB09X3
1 I/O A to Q tPLH 2.41 3.80 5.19 CMOS tri-state output buffer, 4mA
tPHL 2.43 3.81 5.19
EN to Q tZH 2.64 4.02 5.40
tZL 2.41 3.80 5.19
OB15X1
1 I/O A to Q tPLH 4.13 7.11 10.09 TTL tri-state output buffer, 1mA
tPHL 6.20 10.61 15.04
EN to Q tZH 4.26 7.24 10.22
tZL 6.23 10.64 15.06
18
0.8 micron CMOS
Gate Arrays
Digital ASICs
August 1993 Products and Services
OB15X2
1 I/O A to Q tPLH 2.51 4.01 5.50 TTL tri-state output buffer, 2mA
tPHL 6.24 10.62 15.06
EN to Q tZH 2.66 4.16 5.64
tZL 6.24 10.62 15.07
OB15X3
1 I/O A to Q tPLH 1.60 2.36 3.11 TTL tri-state output buffer, 4mA
tPHL 3.45 5.65 7.86
EN to Q tZH 1.82 2.58 3.33
tZL 3.44 5.65 7.86
OB81X5 1 I/O tPLH 1.50 2.25 2.99 TTL output buffer, 8mA, with controlled
slew rate output
tPHL 3.38 5.48 7.52
OB83X5 1 I/O tPLH 2.30 3.68 5.06 CMOS output buffer with controlled slew
rate output, 8mA
tPHL 2.40 3.78 5.16
OB86X5 1 I/O tPLH 2.64 4.02 5.40 CMOS inverting open drain P-channel
output buffer with controlled slew rate
output, 8mA
tPZ 1.23
OB87X5 1 I/O tPZ 0.56 TTL open drain N-channel output buffer
with controlled slew rate output, 8mA
tPHL 3.03 5.10 7.17
OB89X5
1 I/O A to Q tPLH 2.42 3.81 5.20 CMOS tri-state output buffer with con-
trolled slew rate output, 8mA
tPHL 2.46 3.84 5.22
EN to Q tZH 2.76 4.15 5.54
tZL 2.44 3.82 5.21
OB95X5
1 I/O A to Q tPLH 1.61 2.37 3.12 TTL tri-state output buff er with controlled
slew rate output, 8mA
tPHL 3.48 5.65 7.80
EN to Q tZH 1.95 2.71 3.45
tZL 3.45 5.63 7.78
Input/Output Pad Cells
Name Eq
Gates Parameters Propagation Delay (ns) Description
25pF 50pF 75pF
IO01X1
1 I/O A to IO tPLH 4.14 7.12 10.10 TTL I/O buffer, 1mA
tPHL 6.21 10.63 15.04
EN to IO tZH 4.28 7.26 10.24
tZL 6.23 10.65 15.06
IO01X2
1 I/O A to IO tPLH 2.52 4.02 5.51 TTL I/O buffer, 2mA
tPHL 6.23 10.65 15.06
EN to IO tZH 2.67 4.16 5.65
tZL 6.23 10.65 15.07
IO01X3
1 I/O A to IO tPLH 1.61 2.36 3.11 TTL I/O buffer, 4mA
tPHL 3.46 5.66 7.86
EN to IO tZH 1.82 2.58 3.33
tZL 3.44 5.65 7.86
Output Pad Cells (Continued)
Name Eq
Gates Parameters Propagation Delay (ns) Description
25pF 50pF 75pF
19
0.8 micron CMOS
Gate Arrays
Digital ASICs
August 1993 Products and Services
IO03X1
1 I/O A to IO tPLH 7.27 12.79 18.32 CMOS I/O buffer, 1mA
tPHL 4.18 6.95 9.72
EN to IO tZH 7.40 12.93 18.46
tZL 4.21 6.98 9.74
IO03X2
1 I/O A to IO tPLH 4.10 6.87 9.63 CMOS I/O buffer, 2mA
tPHL 4.21 6.97 9.74
EN to IO tZH 4.25 7.01 9.78
tZL 4.21 6.98 9.74
IO03X3
1 I/O A to IO tPLH 2.41 3.80 5.19 CMOS I/O buffer, 4mA
tPHL 2.44 3.82 5.20
EN to IO tZH 2.63 4.02 5.41
tZL 2.42 3.81 5.20
IO3CX1
1 I/O A to IO tPLH 7.35 12.90 18.45 CMOS I/O buffer with pull-down, 1mA
tPHL 4.17 6.91 9.65
EN to IO tZH 7.49 13.04 18.59
tZL 4.21 6.97 9.73
IO3CX2
1 I/O A to IO tPLH 4.14 6.91 9.68 CMOS I/O buffer with pull-down, 2mA
tPHL 4.20 6.95 9.70
EN to IO tZH 4.28 7.05 9.83
tZL 4.21 6.97 9.73
IO3CX3
1 I/O A to IO tPLH 1.92 3.26 4.58 CMOS I/O buffer with pull-down, 4mA
tPHL 1.90 3.24 4.57
EN to IO tZH 2.09 3.42 4.75
tZL 1.90 3.24 4.57
IO3FX1
1 I/O A to IO tPLH 4.19 7.18 10.17 TTL I/O buffer with pull-down, 1mA
tPHL 6.21 10.59 14.98
EN to IO tZH 4.33 7.32 10.30
tZL 6.25 10.65 15.05
IO3FX2
1 I/O A to IO tPLH 2.55 4.04 5.53 TTL I/O buffer with pull-down, 2mA
tPHL 6.24 10.63 15.02
EN to IO tZH 2.69 4.19 5.68
tZL 6.25 10.65 15.04
IO3FX3
1 I/O A to IO tPLH 1.63 2.39 3.14 TTL I/O buffer with pull-down, 4mA
tPHL 3.47 5.66 7.86
EN to IO tZH 1.85 2.61 3.36
tZL 3.45 5.66 7.87
IO41X1
1 I/O A to IO tPLH 4.12 7.07 10.02 TTL I/O buffer with pull-up, 1mA
tPHL 6.24 10.67 15.09
EN to IO tZH 4.26 7.23 10.19
tZL 6.27 10.69 15.12
IO41X2
1 I/O A to IO tPLH 2.52 4.00 5.48 TTL I/O buffer with pull-up, 2mA
tPHL 6.26 10.69 15.11
EN to IO tZH 2.67 4.16 5.64
tZL 6.26 10.69 15.12
Input/Output Pad Cells (Continued)
Name Eq
Gates Parameters Propagation Delay (ns) Description
25pF 50pF 75pF
20
0.8 micron CMOS
Gate Arrays
Digital ASICs
August 1993 Products and Services
IO41X3
1 I/O A to IO tPLH 1.61 2.36 3.11 TTL I/O buffer with pull-up, 4mA
tPHL 3.47 5.68 7.88
EN to IO tZH 1.82 2.58 3.33
tZL 3.45 5.67 7.88
IO42X1
1 I/O A to IO tPLH 7.23 12.72 18.20 CMOS I/O buffer with pull-up, 1mA
tPHL 4.20 6.98 9.75
EN to IO tZH 7.38 12.88 18.38
tZL 4.23 7.00 9.77
IO42X2
1 I/O A to IO tPLH 4.10 6.85 9.60 CMOS I/O buffer with pull-up, 2mA
tPHL 4.23 7.00 9.77
EN to IO tZH 4.25 7.00 9.76
tZL 4.23 7.00 9.77
IO42X3
1 I/O A to IO tPLH 2.42 3.81 5.19 CMOS I/O buffer with pull-up, 4mA
tPHL 2.45 3.83 5.21
EN to IO tZH 2.63 4.03 5.41
tZL 2.43 3.82 5.21
IO51X1
1 I/O A to IO tPLH 7.27 12.80 18.33 CMOS I/O buffer with Schmitt trigger
input, 1mA
tPHL 4.19 6.96 9.72
EN to IO tZH 7.41 12.93 18.46
tZL 4.22 6.98 9.75
IO51X2
1 I/O A to IO tPLH 4.11 6.87 9.63 CMOS I/O buffer with Schmitt trigger
input, 2mA
tPHL 4.21 6.98 9.74
EN to IO tZH 4.25 7.02 9.78
tZL 4.21 6.98 9.75
IO51X3
1 I/O A to IO tPLH 1.92 3.25 4.58 CMOS I/O buffer with Schmitt trigger
input, 4mA
tPHL 1.91 3.24 4.58
EN to IO tZH 2.08 3.41 4.74
tZL 1.90 3.24 4.58
IO81X5
1 I/O A to IO tPLH 1.62 2.37 3.12 TTL I/O tri-state buffer with controlled
slew rate output, 8mA
tPHL 3.50 5.67 7.82
EN to IO tZH 1.95 2.71 3.46
tZL 3.47 5.65 7.80
IO83X5
1 I/O A to IO tPLH 2.43 3.82 5.21 CMOS I/O tri-state buff er with controlled
slew rate output, 8mA
tPHL 2.47 3.85 5.23
EN to IO tZH 2.77 4.16 5.54
tZL 2.44 3.83 5.21
IOBCX5
1 I/O A to IO tPLH 2.45 3.84 5.22 CMOS I/O tri-state buffer with pull-down
and controlled slew rate output, 8mA
tPHL 2.47 3.85 5.23
EN to IO tZH 2.79 4.18 5.56
tZL 2.44 3.83 5.21
IOBFX5
1 I/O A to IO tPLH 1.62 2.38 3.13 TTL I/O tri-state buffer with pull-down
and controlled slew rate output, 8mA
tPHL 3.50 5.67 7.81
EN to IO tZH 1.96 2.72 3.47
tZL 3.47 5.66 7.80
Input/Output Pad Cells (Continued)
Name Eq
Gates Parameters Propagation Delay (ns) Description
25pF 50pF 75pF
21
0.8 micron CMOS
Gate Arrays
Digital ASICs
August 1993 Products and Services
IOC1X5
1 I/O A to IO tPLH 1.61 2.37 3.11 TTL I/O tri-state buffer with pull-up and
controlled slew rate output, 8mA
tPHL 3.51 5.69 7.83
EN to IO tZH 1.95 2.71 3.45
tZL 3.48 5.66 7.81
IOC2X5
1 I/O A to IO tPLH 2.43 3.82 5.20 CMOS I/O tri-state buffer with pull-up,
and controlled slew rate output, 8mA
tPHL 2.48 3.86 5.24
EN to IO tZH 2.77 4.16 5.54
tZL 2.45 3.84 5.23
IOD1X5
1 I/O A to IO tPLH 2.43 3.82 5.21 CMOS I/O tri-state buffer with Schmitt
trigger and controlled slew rate output,
8mA
tPHL 2.47 3.85 5.23
EN to IO tZH 2.77 4.16 5.54
tZL 2.44 3.83 5.22
Power Cells
Name Eq
Gates Description
CVDD 1 Core cell input resistive tie-up to core
Vdd bus
CVSS 1Core cell input resistive tie-down to core
Vss bus
PP01X 1 I/O Vss power pad for core and pad cells
PP02X 1 I/O Vdd power pad for core and pad cells
PP04X 1 I/O Optional power pad pin for additional
busses
PPC1X 1 I/O Vss power pad pin for input buffers and
core cells only
PPP1X 1 I/O Vss power pad pin for output buffers
only
Input/Output Pad Cells (Continued)
Name Eq
Gates Parameters Propagation Delay (ns) Description
25pF 50pF 75pF
22
0.8 micron CMOS
Gate Arrays
Digital ASICs
August 1993 Products and Services
2.5 3.0 3.5 4.0 4.5 5.0 5.5
0.9
1.2
1.5
1.8
Supply Voltage (volts)
Derating Coefficient,KV
Delay Derating Information
The propagation delays listed in the Selection Guide (pages 9 to 21) are for typical temperature, 25oC, typical supply
voltage, 5.0V., and typical processing conditions. To calculate the delay at other conditions (including Vdd equals 3.0V)
the following equation can be used: Tpdx = Tpdx(typ)*KP*KV*KT
where Tpdx(typ) is given in the Selection Guide. KP
, the process derating coefficient, KT, the temperature derating
coefficient, and KV, the supply voltage derating coefficient are described below.
Delay Variations with Temperature (KT)
Delay varies linearly with temperature. The following formulas and common operating points can be used.
Temp. Range KT Formula
-55oC to 25oCK
T
=1.0-(25-TJoC)*2.58 x 10-3
25oC to 140oCK
T
=1.0+(TJoC-25)*2.58 x 10-3
Temp KT
-55 oC 0.79
-25 oC 0.87
0 oC 0.94
25 oC 1.00
70 oC 1.11
100 oC 1.19
125 oC 1.26
Where TJoC is the temperature at the silicon junction.
Delay Variations with Process (KP)
Delay variations with process are given as fixed constants determined at the limits of acceptable manufacturing of the
process. These are described below.
Derating Coefficient (Kp) Process Variation Point
1.40 Delay increase due to “Worst Case Speed” (WCS) fabrication
1.00 Typical delay; fabrication target
0.61 Delay reduction due to “Worst Case Power” (WCP) fabrication
Delay V ariations with V oltage (KV)
Delay varies nonlinearly with voltage. Some common operating points and a characteristic curve are shown.
VDD KV
2.7 V 1.74
3.0 V 1.54
3.3 V 1.39
4.5 V 1.07
4.75 V 1.03
5.0 V 1.00
5.25 V 0.97
5.5 V 0.94
22
23
0.8 micron CMOS
Gate Arrays
Digital ASICs
August 1993 Products and Services
Packaging
The AMI8Gx gate array family can be packaged in a variety of popular packages.
New packages are in development which will extend the package offering. Some special packages or packaging
requirements can be supplied if requested. More details on specific packages are available from an AMI sales
representative.
Available Packages ( ) = Lead time required
Array PQFP TQFP CQFP PLCC JLDCC CLCC
G5 44,52,64,80 (48),64 40 20,28,68 28 20,24,28,44
G9 44,52,64,80,100,120 64,100,(144) 40 20,28,44,68 28 24,28,44
G15 44,52,64,80,100,120 64,(80),100,(128),(144) 40 20,28,44,68,84 28,44,68,84 24,28,36,40,44,48,52
G21 44,52,64,80,100,120,128 64,(80),100,(128),(144) 40 20,28,44,68,84 44,68,84 28,36,40,44,48,52,84
G34 44,52,64,80,100,120,128,144 64,(80),100,(128),(144) 40,44,132 28,44,68,84 44,68,84 28,36,40,44,48,52,68,84
G44 44,52,64,80,100,120,128,144,160 (80),100,(128),(144) 40,44,132 28,44,68,84 44,68,84 36,40,44,48,52,68,84
G55 44,52,64,80,100,120,128,144,160 (80),100,(128),(144) 44,132 28,44,68,84 (44),68,(84) 44,48,68,84
G65 44,52,64,80,100,120,128,144,160 (80),100,(144),(176) 44,132 44,68,84 (44),68,84 44,48,68,84
G93 64,80,100,120,128,144,160,208 100,(144),(176) 132,144 44,68,84 68,84 68,84
G142 100,120,128,144,160,208 (176) 132,144 68,84 68,84 68
G201 144,160,208 (84) 84
G247 144,160,208,2562
G392 208,3041,2
G663
Note 1: The 304 pin PowerQuad2™ package has a heat slug added to improve power dissipation.
Array MQUAD PDIP PPGA CPGA BGA
G5 8,14,16,18,20,22,24,28,40,48 68
G9 22,24,28,40,48 68
G15 22,24,28,40,48 (65),68,69,(85),121,145
G21 22,24,28,40,48 (65),68,69,(85),121,145
G34 144 24,28,40,48 69,85,101,109,121,145 (65),68,69,85,101,121,145 (169)
G44 144 24,28,40,48 69,85,101,109,121,145 68,69,85,101,121,145 (169)
G55 128,144 28,40,48 69,85,101,109,121,145 68,69,85,101,121,145 (169)
G65 128,144 28,40 69,85,101,109,121,132,145 68,69,85,101,(145) (169)
G93 128,144,(160) (40) 69,101,109,121,132,145 68,84,85,109,121,132,(145),208 (169),(225)
G142 128,(144),(160),(208) 69,121,132,145,180 68,84,109,121,132,145,177,181,208 (169),(225),(313)
G201 (144),(160),(208) 145,180 145 (169),(225),(313)
G247 (144),(160),(208) 180 145 (169),(225),(313)
G392 (144),(160),(208) 476 (225),(313)
G663 (313)
PQFP = Plastic Quad Flatpack
TQFP = Thin Quad Flatpack (plastic)
MQUAD = Metal Quad Flatpack
CQFP = Ceramic Qual Flatpack
PLCC = Plastic Leaded Chip Carrier - J lead
JLDCC = Ceramic Leaded Chip Carrier - J lead
CLCC = Leadless Chip Carrier (ceramic)
PDIP = Plastic Dual In-line Package
PPGA = Plastic Pin Grid Array
CPGA = Ceramic Pin Grid Array
BGA = Ball Grid Array
23
AMI Trademarks ACCESS
TM
Enhanced Design Utilities
TM
NETSCAN
TM
Other Trademarks Synopsys is a registered trademark of Synopsys, Inc.
Cadence, Valid, and Verilog are registered trademarks of Cadence Design Systems, Inc.
Mentor Graphics is a registered trademark of Mentor Graphics Corporation.
Viewlogic is a registered trademark of Viewlogic Systems, Inc.
IKOS is a registered trademark of IKOS Systems, Inc.
MQUAD is a registered trademark of Olin Corporation.
PowerQuad is a trademark of Amkor Electronics Inc.
TapePak is a registered trademark of National Semiconductor Corporation.
Copyright®1997, American Microsystems, Inc.
De vices sold b y AMI are cov ered b y the w arr anty and patent indemnification provisions appearing in its Terms of Sale only. AMI makes
no warranty, express, statutory implied or by description, regarding the information set forth herein or regarding the freedom of the
described devices from patent infringement. AMI makes no warranty of merchantability or fitness for any pur poses. AMI reser ves the
right to discontinue production and change specifications and prices at any time and without notice. AMI's products are intended fo r
use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high
reliability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recommended without
additional processing by AMI for such applications.
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