© Semiconductor Components Industries, LLC, 2017
November, 2018 Rev. 1
1Publication Order Number:
N24RF16E/D
N24RF16E
RFID 16 Kb EEPROM Tag
ISO 15693 RF, I2C Bus,
Energy Harvesting
Description
The N24RF16E is a RFID/NFC tag with a 16 Kb EEPROM device,
offering both contactless and contact interface. In addition to the
ISO/IEC 15693 radio frequency identification (RFID) interface
protocol, the device features an I2C interface to communicate with
a microcontroller. The I2C contact interface requires an external
power supply.
The 16 Kb EEPROM array is internally organized as 512 x 32 bits in
RF mode and as 2048 x 8 bits when accessed from the I2C interface.
Features
Contactless Transmission of Data
ISO 15693 / ISO 180003 Mode1 Compliant
Vicinity Range Communication (up to 150 cm)
Air Interface Communication at 13.56 MHz (HF)
To Tag: ASK Modulation with 1.65 Kbit/s or 26.48 Kbit/s Data
Rate
From Tag: Load Modulation Using Manchester Coding with
423 kHz and 484 kHz Subcarriers in Low (6.6 Kbit/s) or High
(26 Kbit/s) Data Rate Mode. Supports the 53 Kbit/s Data Rate
with Fast Commands
Read & Write 32bit Block Mode
Anticollision Support
Security:
64bit Unique Identifier (UID)
Multiple 32bit Passwords and Lock Feature for Each User
Memory Sector
Supports Fast (400 kHz) and FastPlus (1 MHz) I2C Protocol
1.8 V to 5.5 V Supply Voltage Range
4Byte Page Write Buffer
I2C Timeout
Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs
(SCL and SDA)
512 Blocks x 32 Bits (16 Sectors of 32 Blocks Each): RF Mode
2048 x 8 Bits I2C Mode
2,000,000 Program/Erase Cycles
200 Year Data Retention
40_C to +105_C Temperature Range
Configurable Output Pin: RF Write in Progress or RF Busy
Energy Harvesting Analog Output
SOIC, TSSOP 8lead Packages
These Devices are PbFree, Halogen Free/BFR Free and are RoHS
Compliant*
www.onsemi.com
SOIC 8
CASE 751BD
See detailed ordering and shipping information on page 22 of
this data sheet.
ORDERING INFORMATION
MARKING DIAGRAMS
PIN CONFIGURATION
PIN FUNCTION
VOUT
SDA
VCC
VSS
Energy Harvesting Output
Serial Data
Power Supply
Ground
Pin Name Function
*For additional information on our PbFree strategy
and soldering details, please download the
ON Semiconductor Soldering and Mounting
Techniques Reference Manual, SOLDERRM/D.
TSSOP8, 4.4x3
CASE 948AL
VOUT
AN1
AN2
VSS SDA
SCL
RF WIP/BUSY
VCC
SOIC (W, X), TSSOP (Y)
SCL
AN1, AN2
Serial Clock
Antenna Coil
A = Assembly Site Code
Y = Production Year (Last Digit)
M = Production Month Code
ZZZ = Last 3 Characters of Assembly Lot Number
RF16EH
AYMZZZ
16EH
AYMZZZ
RF WIP/BUSY Internal Write or RF command
in progress
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Figure 1. Functional Symbol
AN1
AN2
VOUT
SCL
SDA
N24RF16E
VSS
VCC
RF WIP/BUSY
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameter Rating Unit
Storage Temperature 65 to +150 °C
Ambient Operating Temperature 40 to +105 °C
Voltage on SCL, SDA, RF WIP/BUSY and VCC pins with respect to Ground (Note 1) 0.5 to 6.5 V
RF Input Voltage Peak to Peak Amplitude between AN1 and AN2, VSS pad floating 28 V
AC Voltage on AN1 or AN2 with respect to GND 1 to 15 V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. During transitions, the voltage undershoot on any pin should not exceed 1 V for more than 20 ns. Voltage overshoot on the SCL and SDA I2C
pins should not exceed the absolute maximum ratings, irrespective of VCC.
Table 2. RELIABILITY CHARACTERISTICS EEPROM (Note 2)
Symbol Parameter Test Conditions Max Unit
NEND Endurance TA 25_C, 1.8 V < VCC < 5.5 V 2,000,000 Write Cycles (Note 3)
TA = 85_C, 1.8 V < VCC < 5.5 V 800,000
TA = 105_C, 1.8 V < VCC < 5.5 V 300,000
TDR Data Retention TA = 25_C200 Year
2. Determined through qualification/characterization.
3. A Write Cycle refers to writing a Byte or a Page.
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Table 3. DC CHARACTERISTICS I2C MODE (VCC = 1.8 V to 5.5 V, TA = 40°C to +105°C, unless otherwise specified)
Symbol Parameter Test Conditions Min Max Unit
ICCR Supply Current (Read Mode) Read,
fSCL = 400 kHz
VCC = 1.8 V 0.15 mA
VCC = 2.5 V 0.2
VCC = 5.5 V 0.3
ICCW Supply Current (Write Mode) Write Cycle 0.4 mA
ISB1 Standby Current VIN = GND or VCC No RF Field on antenna coil 10 mA
Both VCC Supply and RF Field on
antenna coil
100 mA
IL Input Leakage Current VIN = GND or VCC 2 2 mA
ILO Output Leakage Current SDA = Hi Z, VOUT = GND or VCC 2 2 mA
VIL1 Input Low Voltage VCC 2.5 V 0.5 0.3 VCC V
VIH1 Input High Voltage VCC 2.5 V 0.7 VCC VCC+0.5 V
VIL2 Input Low Voltage VCC < 2.5 V 0.5 0.25 VCC V
VIH2 Input High Voltage VCC < 2.5 V 0.75 VCC VCC+0.5 V
VOL1 Output Low Voltage VCC 2.5 V, IOL = 3.0 mA 0.4 V
VOL2 Output Low Voltage VCC < 2.5 V, IOL = 2.1 mA 0.2 V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
Table 4. PIN IMPEDANCE CHARACTERISTICS
Symbol Parameter Conditions Max Unit
CIN (Note 4) I/O Pin Capacitance (SDA, RF WIP/BUSY) VIN = 0 V 8 pF
CIN (Note 4) Input Capacitance (other pins) VIN = 0 V 6 pF
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AECQ100
and JEDEC test methods.
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Table 5. AC CHARACTERISTICS I2C MODE (Note 5) (VCC = 1.8 V to 5.5 V, TA = 40°C to +105°C, unless otherwise specified)
Symbol Parameter
I2C Fast I2C Fast Plus
Unit
Min Max Min Max
FSCL Clock Frequency 25 400 25 1000 kHz
tLOW Low Period of SCL Clock 1.3 20000 0.45 20000 ms
tHIGH High Period of SCL Clock 0.6 20000 0.40 20000 ms
tSU:STA START Condition Setup Time 0.6 0.25 ms
tHD:STA START Condition Hold Time 0.6 20000 0.25 20000 ms
tHD:DAT Data In Hold Time 00ms
tSU:DAT Data In Setup Time 100 50 ns
tR (Note 6) SDA and SCL Rise Time 300 100 ns
tF (Note 6) SDA and SCL Fall Time 300 100 ns
tSU:STO STOP Condition Setup Time 0.6 0.25 ms
tBUF Bus Free Time Between STOP and START 1.3 0.5 ms
tAA SCL Low to Data Out Valid 0.9 0.4 ms
tDH Data Out Hold Time 100 50 ns
Ti (Note 6) Noise Pulse Filtered at SCL and SDA Inputs 50 50 ns
tWR Write Cycle Time 55 ms
tPU (Notes 6, 7) Powerup to Ready Mode 11 ms
5. Test conditions according to “AC Test Conditions” table.
6. Tested initially and after a design or process change that affects this parameter.
7. tPU is the delay between the time VCC is stable and the device is ready to accept commands.
Table 6. AC TEST CONDITIONS
Parameter Condition
Input Levels 0.2 x VCC to 0.8 x VCC
Input Rise and Fall Times 50 ns
Output Reference Levels 0.5 x VCC
Output Load Current Source: IOL = 3 mA (VCC 2.5 V); IOL = 2 mA (VCC < 2.5 V); CL = 100 pF
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Table 7. RF CHARACTERISTICS (TA = 40°C to +105°C, unless otherwise specified)
Symbol Parameter Test Conditions Min Typ Max Unit
fCC External RF signal frequency 13.553 13.56 13.567 MHz
H_ISO Operating field 150 5000 mA/m
MI_Carrier (10%) 10% Carrier Modulation Index MI = (a b) / (a + b) 150 mA/m
< H_ISO
< 1000 mA/m
10 30 %
H_ISO
> 1000 mA/m
15 30 %
t1:10% 10% Fall and Low Time t1 = t2 6.0 9.44 ms
t2:10% 10% Minimum Low Time t1 = 9.44 ms4.5 t1 ms
t3:10% 10% Rise Time t1 = 9.44 ms04.5 ms
MI_Carrier (100%) 100% Carrier Modulation Index MI = (a b) / (a + b) 95 100 %
t1:100% 100% Fall and Low Time t1 = t2 6.0 9.44 ms
t2:100% 100% Minimum Pulse Width Low Time t1 = 9.44 ms2.1 t1 ms
t3:100% 100% Rise Time t1 = 9.44 ms03ms
t4:100% 100% Rise Time to 60% of Amplitude 00.8 ms
tMIN CDMinimum delay from Carrier generation to first Data 150 mA/m
< H_ISO
< 1000 mA/m
1 ms
H_ISO > 1000 mA/m 2 ms
fSH Subcarrier Frequency High fCC/32 423.75 kHz
fSL Subcarrier Frequency Low fCC/28 484.28 kHz
tRESP N24RF16E Tag Response Time 4352/FS 318.4 320.9 323.5 ms
tWRF RF Write Time (with internal Verify) 78080/FS 5.753 5.758 5.763 ms
CTUN Internal Tuning Capacitor (TSSOP8) (Note 10) f = 13.56 MHz;
Van1 Van2 = 1 Vpp
26 pF
VMAX1RF Input Voltage between AN1 and AN2 (peak to
peak), VSS pad floating (Note 10)
22 V
VMAX2AC voltage on AN1 or AN2 with respect to GND
(Note 10)
111 V
VMIN1RF Input Voltage between AN1 and AN2 (peak to
peak), VSS pad floating (Note 10)
4V
VMIN2AC voltage on AN1 or AN2 with respect to GND
(Note 10)
2.1 V
VBACK Backscattered Level (ISO Test) ISO10373710 mV
TRFOFF RF Off Time Chip reset 2 ms
8. Characterized only.
9. All measurements performed on an antenna with the following characteristics:
· External size: 72 mm x 42 mm
· Number of turns: 7
· Antenna is printed on the PCB plated with 35 mm of Cooper
· Track width: 0.8 mm
· Space: 0.5 mm
· Coil: 5 mH
10.Characterized at room temperature only.
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Figure 2. 100% Modulation Waveform
105%
100%
95%
60%
5%
t2
t1t4
t3
t
The clock recovery must be operational after t4 max.
Figure 3. 10% Modulation Waveform
t2
t1
t3
hr
hf
b
a
yy
y
hf, hr
0.05 (a b)
0.1 (a b) max
t
PowerOn Reset (POR)
The N24RF16E incorporates PowerOn Reset (POR)
circuitry which protects the internal logic against powering
up in the wrong state. The N24RF16E will power up into
Standby mode after VCC exceeds the POR trigger level and
will power down into Reset mode when VCC drops below the
POR trigger level. This bidirectional POR behavior
protects the device against ‘brownout¢ failure following a
temporary loss of power.
Pin Description
SCL: The Serial Clock input pin accepts the clock signal
generated by the Master
SDA: The Serial Data I/O pin accepts input data and
delivers output data. In transmit mode, this pin is open
drain. Data is acquired on the positive edge, and is
delivered on the negative edge of SCL
AN1, AN2: These inputs are used to connect the device to
an external antenna. The coil is used to power and access
the device through the ISO 15693 and ISO 180003 mode
1 RF protocols
RF WIP/BUSY: This configurable output signal is used
either to indicate that the N24RF16E is executing an
internal write cycle from the RF channel or that an RF
command is in progress. RF WIP and signals are available
only when the N24RF16E is powered by the Vcc pin. It
is an open drain output and a pullup resistor must be
connected from RF WIP/BUSY to VCC
VOUT: This analog output pin is used to deliver the analog
voltage Vout available when the Energy harvesting mode
is enabled and the RF field strength is sufficient. When the
Energy harvesting mode is disabled or the RF field
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strength is not sufficient, the energy harvesting analog
voltage output Vout is in HighZ state
Functional Description
The N24RF16E is a dual interface RFID/NFC tag with 16
Kb EEPROM.
The device follows the ISO 15693 and ISO 180003 mode
1 standard for the radio frequency power and signal interface
via the 13.56 MHz carrier. When connected to an antenna
coil, no external power supply is required, as the operating
power is derived from the RF energy The communication
from the RF Reader to the N24RF16E tag takes place using
the ASK modulation with a 1.65 Kb/s data rate using the
1/256 pulse coding or a data rate of 26.48 Kb/s using the 1/4
pulse coding. The communication from the EEPROM tag to
the RF reader takes place via load modulation using
Manchester coding with 423 kHz and 484 kHz subcarrier
frequencies at 6.62 Kb/s or 26.48 Kb/s data rate. The device
supports also the 53 Kb/s fast mode.
The N24RF16E supports the InterIntegrated Circuit
(I2C) Bus protocol. The protocol relies on the use of a Master
device, which provides the clock and directs bus traffic and
Slave devices which execute requests. The N24RF16E
operates as a Slave device with a 4bit device identifier code
(1010b) according to the I2C standard definition.
Memory Organization
In the RF mode, the user memory area is organized into
16 sectors of 32 blocks each for a total of 512 blocks x 32
bits. The memory access from the I2C interface is organized
as 2048 x 8 bits, divided into 16 sectors of 128 bytes each.
The user and system memory organization is shown in
Figure 4. Each memory sector can be individually read
and/or write protected using a specific password. The
N24RF16E provides four 32bit blocks to store three RF
password and one I2C password codes.
In RF mode, the read and write access is done by 32bit
block. Read and Write access is controlled by a Sector
Security Status (SSS) byte which includes 5 significant bits:
Sector Lock bit, two Read / Write protection bits and two
Password Control Bits.
In I2C mode, a sector has 128 bytes that can be
individually accessed for Read and Write. Each sector can
be protected against write operations using the
I2CWrite_Lock bit from the 16bit block area.
The N24RF16E features a 64bit block to store the 64bit
Unique Identifier (UID) per the ISO 15963 requirements.
The UID value is written by ON Semiconductor during
manufacturing and it is used during the anticollision
sequence.
The system memory area also includes the application
family identifier (AFI) and a data storage family identifier
(DSFID) used in the anticollision algorithm.
The access to the user memory area requires the A2 bit
from the Slave address byte (Figure 6) set to “0”. All system
memory blocks (Table 8) are accessed with A2 bit set to “1”
Unique Identifier
The N24RF is programed at the factory with a 64bit
unique identifier. The UID conforms to IS0 15693 / ISO
18000 and is readonly. The UID is comprised of:
Eight MSBs with a value of 0xE0
IC manufacturer code for ON Semiconductor 0x67
Unique 48 bit serial number
MSB
63 56 55 48 47 0
0xE0 0x67 Unique serial number
Table 8. SYSTEM MEMORY
I2C Byte Address Bits [31:24] Bits [23:16] Bits [15:8] Bits [7:0]
A2=1 0 SSS 3 (00h) SSS 2 (00h) SSS 1 (00h) SSS 0 (00h)
A2=1 4 SSS 7 (00h) SSS 6 (00h) SSS 5 (00h) SSS 4 (00h)
A2=1 8 SSS 11 (00h) SSS 10 (00h) SSS 9 (00h) SSS 8 (00h)
A2=1 12 SSS 15 (00h) SSS 14 (00h) SSS 13 (00h) SSS 12 (00h)
A2=1 2048 I2C Write Lock [15:8] (00h) I2C Write Lock [7:0] (00h)
A2=1 2304 I2C password (0000 0000h)
A2=1 2308 RF password 1 (0000 0000h)
A2=1 2312 RF password 2 (0000 0000h)
A2=1 2316 RF password 3 (0000 0000h)
A2=1 2320 DSFID (FFh) AFI (00h) ON reserved Configuration byte (F4h)
A2=1 2324 UID UID UID UID
A2=1 2328 UID (E0h) UID (67h) UID UID
A2=1 2332 Mem Size (03 01FFh) IC Ref (4Eh)
A2=1 2336 Control Register
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Figure 4. Memory Organization
Sector Area
0
1
2
3
12
13
14
15
I2C Password
RF Password 1
RF Password 2
RF Password 3
8bit DSFID
8bit AFI
64bit UID
16bit I2C Write Lock bits
80bit SSS
1 Kbit EEPROM Sector
1 Kbit EEPROM Sector
1 Kbit EEPROM Sector
1 Kbit EEPROM Sector
1 Kbit EEPROM Sector
1 Kbit EEPROM Sector
1 Kbit EEPROM Sector
1 Kbit EEPROM Sector
System
System
System
System
System
System
System
System
System
Sector Security Status
The five Sector Security Status bits are organized as
follows (Table 9):
Table 9. SECTOR SECURITY STATUS BITS
b4 b3 b2 b1 b0
Password control bits Read/Write
Protection bits
Sector
Lock
The Sector Lock bit enables (1) or disables (0) the sector
protection. The read/write protection bits (Table 10)
determine whether reading and/or writing the sector is
permitted. The password control bits (Table 11) determine
whether and which password protects the sector.
Table 10. READ/WRITE PROTECTION BITS
Sector
Lock
(b0) b2, b1
Sector Access
When Password
Presented
Sector Access
When Password
Not Presented
0 xx Read Write Read Write
1 00 Read Write Read No Write
1 01 Read Write Read Write
1 10 Read Write No Read No Write
111 Read No Write No Read No Write
Table 11. PASSWORD CONTROL BITS
b4, b3 Password
00 Sector not protected by password
01 Sector protected by Password 1
10 Sector protected by Password 2
11 Sector protected by Password 3
I2C Bus Protocol
The 2wire I2C bus consists of two lines, SCL and SDA,
connected to the VCC supply via pullup resistors. The
Master provides the clock to the SCL line, and either the
Master or the Slaves drive the SDA line. A ‘0’ is transmitted
by pulling a line LOW and a ‘1’ by letting it stay HIGH. Data
transfer may be initiated only when the bus is not busy (see
AC Characteristics). During data transfer, SDA must remain
stable while SCL is HIGH.
START/STOP Condition
An SDA transition while SCL is HIGH creates a START
or STOP condition (Figure 5). The START consists of a
HIGH to LOW SDA transition, while SCL is HIGH. Absent
the START, a Slave will not respond to the Master. The
STOP completes all commands, and consists of a LOW to
HIGH SDA transition, while SCL is HIGH.
Device Addressing
The Master addresses a Slave by creating a START
condition and then broadcasting an 8bit Slave address. For
the N24RF64, the first four bits of the Slave address are set
to 1010. The A2 bit is used to control the access to the user
or system memory area. The next 2 bits are set to 11. The
R/W bit tells the Slave whether the Master intends to read (1)
or write (0) data (Figure 6).
Acknowledge
After processing the Slave address, the Slave responds
with an acknowledge (ACK) by pulling down the SDA line
during the 9th clock cycle (Figure 7). The Slave will also
acknowledge all address bytes and every data byte presented
in Write mode if the addressed location is not write
protected. In Read mode the Slave shifts out a data byte, and
then releases the SDA line during the 9th clock cycle. As
long as the Master acknowledges the data, the Slave will
continue transmitting. The Master terminates the session by
not acknowledging the last data byte (NoACK) and by
issuing a STOP condition. Bus timing is illustrated in
Figure 8.
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Figure 5. START/STOP Conditions
SCL
SDA
START
CONDITION
STOP
CONDITION
Figure 6. Slave Address Bits
DEVICE ADDRESS
101 0A21
NOTE: A2 bit is used to control the memory addressing: A2=0: User memory area; A2=1: System memory area
R/W
1
Figure 7. Acknowledge Timing
BUS RELEASE DELAY (TRANSMITTER) BUS RELEASE DELAY
SCL FROM
MASTER 189
DAT A OUTPUT
FROM TRANSMITTER
DAT A OUTPUT
FROM RECEIVER
START ACK DELAY ( tAA)
ACK SETUP ( tSU:DAT)
(RECEIVER)
Figure 8. Bus Timing
tF
tLOW
tHIGH tR
tLOW
SCL
tSU:STA
tHD:STA
tHD:DAT
tSU:DAT tSU:STO
SDA IN
SDA OUT
tAA tDH tBUF
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WRITE OPERATIONS
Byte Write
To write data to memory, the Master creates a START
condition on the bus and then broadcasts a Slave address
with the R/W bit set to ‘0’. The Master then sends two
address bytes and a data byte and concludes the session by
creating a STOP condition on the bus. The Slave responds
with ACK after every byte sent by the Master (Figure 9). The
STOP starts the internal Write cycle, and while this
operation is in progress (tWR), the SDA output is tristated
and the Slave does not acknowledge the Master (Figure 10).
Page Write
The Byte Write operation can be expanded to Page Write,
by sending more than one data byte to the Slave before
issuing the STOP condition (Figure 11). Up to 4 distinct data
bytes can be loaded into the internal Page Write Buffer
starting at the address provided by the Master. The page
address is latched, and as long as the Master keeps sending
data, the internal byte address is incremented up to the end
of page, where it then wraps around (within the page). New
data can therefore replace data loaded earlier. Following the
STOP, data loaded during the Page Write session will be
written to memory in a single internal Write cycle (tWR).
Acknowledge Polling
As soon (and as long) as internal Write is in progress, the
Slave will not acknowledge the Master. This feature enables
the Master to immediately followup with a new Read or
Write request, rather than wait for the maximum specified
Write time (tWR) to elapse. Upon receiving a NoACK
response from the Slave, the Master simply repeats the
request until the Slave responds with ACK.
The remainder of the instruction is identical to a normal
Page Write.
Delivery State
The N24RF16E is shipped erased, i.e., all bytes from user
memory area are FFh.
Figure 9. Byte Write Sequence
BUS ACTIVITY: S
T
ASLAVE
ADDRESS
BYTE
ADDRESS S
BYTE DATA T
MASTER R
T
S
SLAVE
ADDRESS a15a8a7a0
* *
BYTE O
P
P
AA
CC
KK
A
C
K
A
C
K
*a15 a11 = Don’t Care bits
* * *
Figure 10. Write Cycle Timing
SCL
SDA 8th Bit
Byte n
ACK
STOP
CONDITION
tWR
START
CONDITION
ADDRESS
Figure 11. Page Write Sequence
BUS ACTIVITY: S
T
ASLAVE
ADDRESS
BYTE
ADDRESS
BYTE
DATA
BYTE
DATA
BYTE
DATA S
BYTE T
MASTER R
T
S
SLAVE
ADDRESS a15a8a7a0n
* * *
n+1 n+P O
P
P
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
* *
*a15 a11 = Don’t Care bits
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READ OPERATIONS
Immediate Read
To read data from memory, the Master creates a START
condition on the bus and then broadcasts a Slave address
with the R/W bit set to ‘1’. The Slave responds with ACK
and starts shifting out data residing at the current address.
After receiving the data, the Master responds with NoACK
and terminates the session by creating a STOP condition on
the bus (Figure 12). The Slave then returns to Standby mode.
Selective Read
To read data residing at a specific address, the selected
address must first be loaded into the internal address register.
This is done by starting a Byte Write sequence, whereby the
Master creates a START condition, then broadcasts a Slave
address with the R/W bit set to ‘0’ and then sends two
address bytes to the Slave. Rather than completing the Byte
Write sequence by sending data, the Master then creates a
START condition and broadcasts a Slave address with the
R/W bit set to ‘1’. The Slave responds with ACK after every
byte sent by the Master and then sends out data residing at
the selected address. After receiving the data, the Master
responds with NoACK and then terminates the session by
creating a STOP condition on the bus (Figure 13).
Sequential Read
If, after receiving data sent by the Slave, the Master
responds with ACK, then the Slave will continue
transmitting until the Master responds with NoACK
followed by STOP (Figure 14). During Sequential Read the
internal byte address is automatically incremented up to the
end of memory, where it then wraps around to the beginning
of memory.
I2C SECURITY
In the I2C mode it is possible to protect each memory
sector from user area against write operations. The sector
write access is controlled using the 16bit I2C_Write_Lock
bit area and the 32bit I2C password. There are two
commands to control the I2C password: I2C Present
Password and I2C Write Password.
I2C Present Password
The I2C Present Password command is used to modify the
write access rights of the sectors protected by the I2C
WriteLock bits, including the password itself. N24RF16E
will allow this only if the correct password is presented, via
I2C bus. If the password is correct, the access rights remain
activated until a new I2C Present Password command is
received, or the device is powered off.
Following a Start condition, the master sends a write
instruction with the slave address with the Read/Write bit
equal to 0 and the A2 bit equal to 1 (system memory). The
device acknowledges this and expects two I2C password
address bytes, 09h and 00h. The device responds to each
address byte with an ACK. The device then expects the 4
password data bytes, the validation code, 09h, and a resend
of the 4 password data bytes. The most significant byte of the
password is sent first, followed by the least significant bytes.
The 32bit password must be sent twice to prevent any
data corruption during the sequence. If the two 32bit
passwords sent are not exactly the same, the command will
not be accepted.
When the bus master generates a Stop condition
immediately after the Ack bit, an internal delay equivalent
to the write cycle time is triggered. A Stop condition at any
other time does not trigger the internal delay. During that
delay, the N24RF16E compares the 32 received data bits
with the 32 bits of the stored I2C password.
If the values match, the write access rights to all protected
sectors are modified after the internal delay. If the values do
not match, the protected sectors remains protected.
During the internal delay, the SDA output is tristated and
the Slave does not acknowledge the Master.
I2C Write Password
The I2C Write Password command is used to overwrite the
32bit I2C password block. This command is used in I2C
mode to update the I2C password value. It cannot be used to
modify any of the RF passwords. After the write cycle, the
new I2C password value is automatically activated. The I2C
password value can only be modified after issuing a valid
I2C Present Password command.
Following a Start condition, the master sends a write
instruction with the slave address with the Read/Write bit
equal to 0 and the A2 bit equal to 1 (system memory). The
device acknowledges this and expects two I2C password
address bytes, 09h and 00h. The device responds to each
address byte with an ACK. The device then expects the 4
password data bytes, the validation code, 07h, and a resend
of the 4 password data bytes. The most significant byte of the
password is sent first, followed by the least significant bytes.
N24RF16E is shipped with the default I2C password
00000000h. By default, the password is activated.
The 32bit password must be sent twice to prevent any
data corruption during the sequence. If the two 32bit
passwords sent are not exactly the same, the command will
not be accepted.
When the bus master generates a Stop condition
immediately after the Ack bit, the internal write cycle is
triggered. A Stop condition at any other time does not trigger
the internal write cycle.
During the internal write cycle, the SDA output is
tristated and the Slave does not acknowledge the Master.
N24RF16E
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12
Figure 12. Immediate Read Sequence and Timing
BUS ACTIVITY: S
T
A
MASTER R
T
S
SLAVE
SLAVE
ADDRESS
A
C
K
N
OS
AT
CO
K
P
DATA
BYTE
SCL 89
SDA 8th Bit
DATA OUT NO ACK STOP
P
Figure 13. Selective Read Sequence
SS
TT
AA
MASTER R
T
S
SLAVE
ADDRESS RADDRESS
T
S
N
OS
AT
CO
KP
P
DATA
BYTE
SLAVE
A
C
K
A
C
KK
A
C
K
A
C
K
SLAVE
BYTE
ADDRESS
BUS ACTIVITY: ADDRESS
BYTE
a15a8
* * * * *
*a15 a11 = Don’t Care bits
Figure 14. Sequential Read Sequence
MASTER
N
OS
SLAVE AT
ADDRESS C
KP
P
SLAVE DATA
BYTE
n
DATA
BYTE
n+1
ADATA
C
KBYTE
n+2
DATA
BYTE
n+x
O
A
C
K
A
C
K
A
C
K
BUS ACTIVITY:
Configuration Byte
The configuration byte, as shown in Table 12, contains
8bit nonvolatile.
Table 12. CONFIGURATION BYTE
I2C byte Address 7 6 5 4 3 2 1 0
A2=1 2320 x x x x RF WIP/BUSY EH_mode EH_cfg1 EH_cfg1
NOTE: bit 4 bit 7 = don’t care bits
The EH_cfg0 and EH_cfg1 (Energy Harvesting
configuration) bits determine the limit of the current
consumption on the VOUT pin. They are set/reset in RF mode
by using the WriteEHCfg command.
The typical characteristics of the VOUT vs. ILoad for each
configuration are shown in Figure 15.
N24RF16E
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0
1
2
3
4
5
012345
Vout [V]
Iload [mA]
40°C +25°C +90°C +105°C
EH_cfg = 11, H_ISO = 1 A/m
0
1
2
3
4
5
012345678910
Vout [V]
Iload [mA]
EH_cfg = 01, H_ISO = 2.4 A/m
40°C +25°C +90°C +105°C
0
1
2
3
4
5
012345678910
Vout [V]
Iload [mA]
EH_cfg = 00, H_ISO = 3.5 A/m
40°C +25°C +90°C +105°C
0
1
2
3
4
5
012345
Vout [V]
40°C +25°C +90°C +105°C
EH_cfg = 10, H_ISO = 1.6 A/m
Iload [mA]
Figure 15. VOUT vs. ILOAD
The EH_mode ( Energy Harvesting mode) bit determine
the value of the EH_enable bit from the control register after
powerup (Table 14). This is set/reset in RF mode by using
the WriteEHCfg command.
The RF WIP/BUSY bit is used to configure the RF
WIP/BUSY output. When set to 0, the RF WIP/BUSY
output is configured in the RF busy mode and the RF
WIP/BUSY output is tied to 0 from the SOF until to the end
of the RF command. When set to1, the RF WIP/BUSY
output is configured in the RF write in progress mode and the
RF WIP/BUSY output is tied to 0 during an internal write
cycle. During an I2C write operation the RF WIP/BUSY
output is in HighZ state. This is set/reset in the RF mode by
using the WriteDOCfg command.
In the I2C mode, the configuration byte can be read and
write by using an I2C instruction.
Control Register
The control register, as shown in Table 13, contains 8bit
volatile.
Table 13. CONTROL REGISTER
I2C byte Address 7 6 5 4 3 2 1 0
A2=1 2336 WTL 0 0 0 0 0 FIELD_ON EH_enable
NOTE: bit 1- bit 7 = readonly bits
The EH_enable (Energy Harvesting enable) bit is set/reset
by using the SetRstEHEn command in the RF mode or by
using a write instruction in the I2C mode. When set to 1, the
Energy Harvesting mode is enabling and when set to 0, the
Energy Harvesting mode is disabling. After powerup, this
bit is updated according to the value of the EH_mode bit
from Configuration byte (Table 12).
The FIELD_ON bit indicates if the RF field is strong
enough to execute RF commands. When the FIELD_ON is
1 the N24RF16E is able to execute RF commands and when
N24RF16E
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14
the FIELD_ON is 0 the N24RF16E is not able to execute RF
commands.
The WTL (Write Time Latch) bit indicates whether the
device has performed a write operation. This bit is
automatically reset to 0 at the beginning of each internal
write cycle and set to 1 at the end of the internal write cycle.
This bit is readonly and reset to 0 after powerup.
In the I2C mode the control register can be read and write
by using an I2C instruction.
Table 14. EH_enable BIT AFTER POWERUP
EH_mode EH_enable after Powerup Energy Harvesting after Powerup
0 1 enabled
1 0 disabled
N24RF16E
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15
RF MODE OPERATION
The communication protocol between the RF Reader and
the N24RF16E tag is based on the RTF technique (Reader
Talks First):
Activation of the N24RF16E memory tag by the
electromagnetic field of the RF Reader
Transmission of a command / request by the RF Reader
Transmission of a response by the memory tag
The memory tag operates continuously under the
electromagnetic field (H) generated by the RF Reader. The
transmission of data and power is based on inductive
coupling using the carrier frequency (fC) as 13.56 MHz
±7 kHz per ISO 15693 standard.
Each request from the Reader and each response from the
N24RF16E tag are organized in a frame, delimited by a start
of frame (SOF) and an end of frame (EOF).
Communication from RF Reader to N24RF16E Tag
The communication between the RF Reader and memory
tag uses the ASK (Amplitude Shift Keying) modulation.
The received signal is demodulated by the ASK
demodulator of the memory tag. The N24RF16E supports
both 100% and 10% modulation index. The Reader selects
which index is used. Figure 2 shows the 100% ASK
modulation waveform.
The data transmission uses pulse position coding
described in the ISO 15693: 1 out of 256 data coding with
a resulting data rate of 1.65 Kb/s or 1 out of 4 data coding
with a data rate of 26.48 Kb/s.
The request from RF Reader to the memory tag consists
of: a request SOF, flags, command code, parameters, data,
2byte CRC, a request EOF. The SOF defines the data
coding mode that will be used by the RF Reader for the
following command. Figure 16 shows a SOF to select 1 out
of 256 data coding and Figure 17 illustrates the SOF to select
1 out of 4.
Figure 16. Request SOF for 1 Out of 256 Data Coding
9.44 ms9.44 ms
37.76 ms37.76 ms
Figure 17. Request SOF for 1 Out of 4 Data Coding
9.44 ms9.44 ms
37.76 ms37.76 ms
9.44 ms
Communication from N24RF64 Tag to RF Reader
The communication between the N24RF16E memory tag
and the RF reader uses the load modulation with Manchester
data coding. Via the inductive coupling, the carrier is loaded
to generate a subcarrier with fs frequency. The device
supports the onesubcarrier with 423.75 kHz (fc/32)
frequency and twosubcarrier response with 423.75 kHz
(fc/32) and 484.28 kHz (fc/28) frequencies. The
onesubcarrier or twosubcarrier response format is
selected by the RF Reader.
The N24RF16E responds using the low or high data rate
for standard commands. The fast commands use a data rate
multiplied by two. The data rate is selected by the RF Reader
through the protocol header. Table 15 shows the data rates
supported by the memory tag using one carrier and two
carriers format.
Table 15. TAG RESPONSE DATA RATES
Command Type Data Rate
One
Subcarrier
Two
Subcarrier
Standard Commands Low 6.62 Kb/s
(fc/2048)
6.67 Kb/s
(fc/2032)
Fast Commands Low 13.24 Kb/s
(fc/1024)
N/A
Standard Commands High 26.48 Kb/s
(fc/512)
26.69 Kb/s
(fc/508)
Fast Commands High 52.97 Kb/s
(fc/256)
N/A
N24RF16E
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The N24RF64 supports the following commands in RF mode:
Table 16. RF COMMAND DESCRIPTION
Nr Command Name Command Description
1 Inventory Perform the anticollision sequence
2Stay quiet Set the N24RF16E in the quiet state
3Read single block Read the requeted block
4Write single block Write the requested block if it is not locked
5Read multiple blocks Read the requested blocks
6 Select Set the N24RF16E in the selected state
7Reset to ready Set the N24RF16E in the ready state
8 Write AFI Write the AFI register
9Lock AFI Lock the AFI register
10 Write DSFID Write the DSFID register
11 Lock DSFID Lock the DSFID register.
12 Get system information Read the system information value
13 Get multiple block security status Read the sector security status of the requested blocks
14 Write sector password Write the selected password
15 Lock sector Write the sector security status bits of the requested sector
16 Present sector password Allows the user to present a password to unprotect the sectors or to change the password
17 Fast read single block Read the requested block
18 Fast inventory initiated Perform the anticollision sequence if the internal initiate flag is set
19 Fast initiate Set the internal initiate flag
20 Fast read multiple blocks Read the requested blocks
21 Inventory initiated Perform the anticollision sequence if the internal initiate flag is set
22 Initiate Set the internal initiate flag
23 ReadCfg Read the Configuration byte
24 WriteEHCfg Write the energy harvesting configuration bits into the Configuration byte
25 SetRstEHEn Write the EH_enable bit into the Control register
26 CheckEHEn Read the Control register
27 WriteDOCfg Write the RF WIP/BUSY bit into the Configuration byte
Table 17. RF COMMAND FORMAT
Nr. Crt. Function SOF Flags Command
IC Mfg.
Code UID
Optional
AFI Number Data CRC16 EOF
1 Inventory x 8 bits 01h 8 bits 8 bits
(Note 12)
0 to 8
bytes
(Note 15)
16 bits x
2Stay quiet x8 bits 02h 8 bytes 16 bits x
3Read single
block
x8 bits 20h 8 bytes
(Note 11)
16 bits
(Note 13)
16 bits x
4Write single
block
x8 bits 21H 8 bytes
(Note 11)
16 bits
(Note 13)
32 bits 16 bits x
5Read multiple
blocks
x8 bits 23H 8 bytes
(Note 11)
16 bits
(Note 13)
8 bits
(Note 16)
16 bits x
6 Select x 8 bits 25h 8 bytes 16 bits x
N24RF16E
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Table 17. RF COMMAND FORMAT (continued)
Nr. Crt. EOFCRC16DataNumber
Optional
AFI
UID
IC Mfg.
Code
CommandFlagsSOFFunction
7Reset to
ready
x8 bits 26h 8 bytes
(Note 11)
16 bits x
8Write AFI x8 bits 27h 8 bytes
(Note 11)
8 bits 16 bits x
9Lock AFI x8 bits 28h 8 bytes
(Note 11)
16 bits x
10 Write DSFID x8 bits 29h 8 bytes
(Note 11)
8 bits 16 bits x
11 Lock DSFID x8 bits 2Ah 8 bytes
(Note 11)
16 bits x
12 GET system
information
x8 bits 2Bh 8 bytes
(Note 11)
16 bits x
13 Get multiple
block security
status
x8 bits 2Ch 8 bytes
(Note 11)
16 bits
(Note 13)
16 bits
(Note 16)
16 bits x
14 Write sector
password
x8 bits B1h 67h 8 bytes
(Note 11)
8 bits
(Note 14)
32 bits 16 bits x
15 Lock sector x8 bits B2h 67h 8 bytes
(Note 11)
16 bits
(Note 13)
8 bits 16 bits x
16 Present sector
password
x8 bits B3h 67h 8 bytes
(Note 11)
8 bits
(Note 14)
32 bits 16 bits x
17 Fast read
single block
x8 bits C0h 67h 8 bytes
(Note 11)
16 bits
(Note 13)
16 bits x
18 Fast inventory
initiated
x8 bits C1h 67h 8 bits 8 bits
(Note 12)
0 to 8
bytes
(Note 15)
16 bits x
19 Fast initiate x8 bits C2h 67h 16 bits x
20 Fast read
multiple blocks
x8 bits C3h 67h 8 bytes
(Note 11)
16 bits
(Note 13)
8 bits
(Note 16)
16 bits x
21 Inventory
initiated
x8 bits D1h 67h 8 bits 8 bits
(Note 12)
0 to 8
bytes
(Note 15)
16 bits x
22 Initiate x 8 bits D2h 67h 16 bits x
23 ReadCfg x 8 bits A0h 67h 8 bytes
(Note 11)
16 bits x
24 WriteEHCfg x 8 bits A1h 67h 8 bytes
(Note 11)
8 bits 16 bits x
25 SetRstEHEn x 8 bits A2h 67h 8 bytes
(Note 11)
8 bits 16 bits x
26 CheckEHEn x 8 bits A3h 67h 8 bytes
(Note 11)
16 bits x
27 WriteDoCfg x 8 bits A4h 67h 8 bytes
(Note 11)
8 bits 16 bits x
11. UID optional.
12.Mask length.
13.Block number/First block number.
14.Password number.
15.Mask value.
16.Number of blocks.
N24RF16E
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Table 18. INSTRUCTION RESPONSE FORMAT (No Error)
Nr.
Crt. Function SOF
Flags
Response Data Byte UID DSFID AFI
Memory
Size
IC
Ref Data CRC16 EOF
1 Inventory x 00h DSFID 8
bytes
16 bits x
2Stay quiet
3Read single
block
x 00h SSS
(Note 17)
32 bits 16 bits x
4Write single
block
x 00h 16 bits x
5Read multiple
blocks
x 00h SSS
(Note 17, 18)
32 bits
(Note 18)
16 bits x
6 Select x 00h 16 bits x
7Reset to ready x 00h 16 bits x
8Write AFI x 00h 16 bits x
9Lock AFI x 00h 16 bits x
10 Write DSFID x 00h 16 bits x
11 Lock DSFID x 00h 16 bits x
12 Get system
information
FL_PE = 0
x 00h 0Bh 8
bytes
8 bits 8
bits
8bits 16 bits x
Get system
information
FL_PE = 1
x 00h 0Fh 8
bytes
8 bits 8
bits
24 bits 8bits 16 bits x
13 Get multiple
block security
status
x 00h SSS
(Note 18)
16 bits x
14 Write sector
password
x 00h 16 bits x
15 Lock sector x 00h 16 bits x
16 Present sector
password
x 00h 16 bits x
17 Fast read
single block
x 00h SSS
(Note 17)
32 bits 16 bits x
18 Fast inventory
Initiated
x 00h DSFID 8
bytes
16 bits x
19 Fast initiate x 00h DSFID 8
bytes
16 bits x
20 Fast read
multiple blocks
x 00h SSS
(Note 17, 18)
32 bits
(Note 18)
16 bits x
21 Inventory
initiated
x 00h DSFID 8
bytes
16 bits x
22 Initiate x 00h DSFID 8
bytes
16 bits x
23 ReadCfg x 00h 8 bits 16 bits x
24 WriteEHCfg x 00h 16 bits x
25 SetRstEHEn x 00h 16 bits x
26 CheckEHEn x 00h 8 bits 16 bits x
27 WriteDoCfg x 00h 16 bits x
17.SSS optional (FL_OPT = 1).
18.Repeated as needed.
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Table 19. INSTRUCTION RESPONSE FORMAT (Error Flag = 1)
Nr. Crt. Function SOF
Flags
Response Error Code CRC16 EOF
1 Inventory −−−−−
2Stay quiet −−−−−
3Read single block x 01h 8 bits 16 bits x
4Write single block x 01h 8 bits 16 bits x
5Read multiple block x 01h 8 bits 16 bits x
6 Select x 01h 8 bits 16 bits x
7Reset to ready x 01h 8 bits 16 bits x
8Write AFI x 01h 8 bits 16 bits x
9Lock AFI x 01h 8 bits 16 bits x
10 Write DSFID x 01h 8 bits 16 bits x
11 Lock DSFID x 01h 8 bits 16 bits x
12 Get system information x 01h 8 bits 16 bits x
13 Get multiple block security status x 01h 8 bits 16 bits x
14 Write sector password x 01h 8 bits 16 bits x
15 Lock sector x 01h 8 bits 16 bits x
16 Present sector password x 01h 8 bits 16 bits x
17 Fast read single block x 01h 8 bits 16 bits x
18 Fast inventory initiated −−−−−
19 Fast initiate −−−−−
20 Fast read multiple blocks x 01h 8 bits 16 bits x
21 Inventory initiated −−−−−
22 Initiate −−−−−
23 ReadCfg x 01h 8 bits 16 bits x
24 WriteEHCfg x 01h 8 bits 16 bits x
25 SetRstEHEn x 01h 8 bits 16 bits x
26 CheckEHEn x 01h 8 bits 16 bits x
27 WriteDoCfg x 01h 8 bits 16 bits x
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Table 20. RESPONSE ERROR CODE
Nr. Crt. Function
Error Code
02h 03h 0Fh 10h 11h 12h 13h 14h 15h
1 Inventory −−−−−−−−−
2Stay quiet −−−−−−−−−
3Read single block xx x
4Write single block xxx x
5Read multiple blocks x x x x
6 Select x−−−−−−−
7Reset to ready x−−−−−−−
8Write AFI x−−−x x
9Lock AFI x x x
10 Write DSFID x−−−x x
11 Lock DSFID x x x
12 Get system information x−−−−−−−
13 Get multiple block security
status
x x x
14 Write sector password x x xx x
15 Lock sector x x x x x
16 Present sector password x x x x
17 Fast read single block x x x x
18 Fast inventory initiated −−−−−−−−−
19 Fast initiate −−−−−−−−−
20 Fast read multiple blocks x x x x x
21 Inventory initiated −−−−−−−−−
22 Initiate −−−−−−−−−
23 ReadCfg x x −−−−−−−
24 WriteEHCfg x x −−−−x
25 SetRstEHEn x x −−−−−−−
26 CheckEHEn x x −−−−−−
27 WriteDoCfg x x −−−−x
Table 21. ERROR CODE
Error Code Meaning
02h The command is not recognized
03h The option is not supported
0Fh Error with no information given
10h The specified block is not available (doesn’t exist)
11h The specified block is already locked and thus cannot be locked again
12h The specified block is locked and its content cannot be changed
13h The specified block was not successfully programmed
14h The specified block was not successfully locked
15h The specified block is readprotected
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Table 22. REQUEST FLAGS
Nr. Crt. Function
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
RFU
Option
Flag
Address
Flag
Nb_Slots
Flag
Select
Flag
AFI
Flag
Protocol
Extension
Flag
Inventory
Flag
Data
Rate
Flag
Sub
Carrier
Flag
1 Inventory 0 0 0/1 0/1 0 1 0/1 0/1
2Stay quiet 00100 0 0/1 0/1
3Read single block 0 0/1 0/1 0/1 1 0 0/1 0/1
4Write single block 0 0/1 0/1 0/1 1 0 0/1 0/1
5Read multiple
blocks
0 0/1 0/1 0/1 1 0 0/1 0/1
6 Select 0 0 1 00 0 0/1 0/1
7Reset to ready 0 0 0/1 0/1 0 0 0/1 0/1
8Write AFI 0 0/1 0/1 0/1 0 0 0/1 0/1
9Lock AFI 0 0/1 0/1 0/1 0 0 0/1 0/1
10 Write DSFID 0 0/1 0/1 0/1 0 0 0/1 0/1
11 Lock DSFID 0 0/1 0/1 0/1 0 0 0/1 0/1
12 Get system
information
0 0 0/1 0/1 0/1 0 0/1 0/1
13 Get multiple
block security
status
0 0 0/1 0/1 1 0 0/1 0/1
14 Write sector
password
0 0/1 0/1 0/1 0 0 0/1 0/1
15 Lock sector 0 0/1 0/1 0/1 1 0 0/1 0/1
16 Present sector
password
0 0 0/1 0/1 0 0 0/1 0/1
17 Fast read single
block
0 0/1 0/1 0/1 1 0 0/1 0
18 Fast inventory
initiated
0 0 0/1 0/1 0 1 0/1 0
19 Fast initiate 00000 0 0/1 0
20 Fast read
multiple blocks
0 0/1 0/1 0/1 1 0 0/1 0
21 Inventory
iInitiated
0 0 0/1 0/1 0 1 0/1 0/1
22 Initiate 0 0 0 00 0 0/1 0/1
23 ReadCfg 0 0 0/1 0/1 0 0 0/1 0/1
24 WriteEHCfg 0 0/1 0/1 0/1 0 0 0/1 0/1
25 SetRstEHEn 0 0 0/1 0/1 0 0 0/1 0/1
26 CheckEHEn 0 0 0/1 0/1 0 0 0/1 0/1
27 WriteDoCfg 0 0/1 0/1 0/1 0 0 0/1 0/1
N24RF16E
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ORDERING INFORMATION
Device Order Number
Specific Device
Marking Package Type Temperature Range Lead Finish Shipping
N24RF16EDWPT3G RF16EH SOIC8
(PbFree) 40°C to 105°CNiPdAu 3000 / Tape & Reel
N24RF16EDTPT3G 16EH TSSOP8
(PbFree) 40°C to 105°CNiPdAu 3000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
19.All packages are RoHScompliant (PbFree, Halogenfree).
20.Contact factory for availability.
N24RF16E
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PACKAGE DIMENSIONS
SOIC 8, 150 mils
CASE 751BD01
ISSUE O
E1 E
A
A1
h
θ
L
c
eb
D
PIN # 1
IDENTIFICATION
TOP VIEW
SIDE VIEW END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
SYMBOL MIN NOM MAX
θ
A
A1
b
c
D
E
E1
e
h
0.10
0.33
0.19
0.25
4.80
5.80
3.80
1.27 BSC
1.75
0.25
0.51
0.25
0.50
5.00
6.20
4.00
L0.40 1.27
1.35
N24RF16E
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TSSOP8, 4.4x3
CASE 948AL01
ISSUE O
E1 E
A2
A1
e
b
D
c
A
TOP VIEW
SIDE VIEW END VIEW
q1
L1 L
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
SYMBOL
θ
MIN NOM MAX
A
A1
A2
b
c
D
E
E1
e
L1
L
0.05
0.80
0.19
0.09
0.50
2.90
6.30
4.30
0.65 BSC
1.00 REF
1.20
0.15
1.05
0.30
0.20
0.75
3.10
6.50
4.50
0.90
0.60
3.00
6.40
4.40
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Email: orderlit@onsemi.com
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative