MIEGE 10.000 LOGIC DIAGRAMS Numbers in parenthesis dencte pin numbers for F package (Case 650). FUNCTIONS AND CHARACTERISTICS (continued) Type 0) Propagation Power Dissipation Delay mW Function -30 to +85C | -55 to +125C ns typ typ/pkg* Case Universal Decade Counter MC10137 MC10537 f= 150 MHz 625 620,650 Bi-Quinary Counter MC10138 _ f= 150 MHz 370 620 64-Bit Random Access Memory (90 2) MCM10140 - taccess = 15 (max) 420 620,690 Four-Bit Universal Shift Register MC10141 MC 10541 # = 200 MHz 425 620,648 650 64 Bit Random Access Memory (50 $2) MCM10142 ~ taAccess = 10 (max) 420 620 8 x 2 Muitiport Register File (RAM} MCM10143 - taccess = 10 610 623 256-Bit Random Access Memory MCM10144 - taccess = 30 (max) 420 620,690 64-Bit Register File (RAM) MCM10145 - taccess = 10 625 620 128-Bit Random Access Memory MCM10147 - taccess = 12 (max) 420 620 64-Bit Random Access Memory (50 92) MCM10148 _ taccess = 15 (max) 420 620 1024-Bit Programmable Read Only Memory MCM10150 _ taccess = 20 = 690 Quad Latch MC10153 _ 4.0 310 620 12-Bit Parity Generator-Checker MC10160 MC10560 5.0 320 620,648 650 Binary to 1-8 Decoder (Low) MC10161 Mc10561 4.0 315 620,648,650 Binary to 1-8 Decoder (High) MC 10162 MC10562 4.0 315 620,648 ,650 Error Detection-Correction Circuit MC10163 _ 5.0 520 620 8-Line Multiplexer MC10164 MC 10564 3.0 310 620,648,650 8-Input Priority Encoder MC10165 _ 7.0 545 620,648 5-Bit Magnitude Comparator MC10166 - 6.0 440 620 Quad Latch MC 10168 - 3.0 310 620 Oual Binary To t-4 Decoder (Low) MC10171 Mc10571 4.0 32S 620,648,650 Dual Binary To 1-4 Decoder (High) MC10172 MC10572 4.0 325 620,648,650 Quad 2-Input Multiplexer/Latch MC10173 - 2.5 278 620,648 Dual 4 To 1 Multiplexer MC10174 McC 10574 3.5 305 620,650 Quint Latch MC10175 MC10575 2.5 400 620 Hex D" Master-Slave Flip-Flop mMC10176 - f = 250 MHz 460 620 Triple MECL to NMOS Translator MC10177 _ - 1.0W 620 Binary Counter MC 10178 _ f = 150 MHz 370 620 Look-Ahead Carry Block MC10179 Mc 10579 3,0 (Cn,P} 4.0 (G) 300 620,648,650 Dua! High Speed Adder/Subtractor MC 70180 Mc 10580 4.5 360 620,648,650 4-Bit Arithmetic Logic Unit/Function Generator MC10181 McC10581 See Logic Diag. 600 623,649,652 2-Bit Arithmetic Logic Unit/Function Generator MC10182 - See Logic Diag. 575 620 Error Detection-Correction Circuit MC10193 _ 7.5 520 620 Hex inverter/Buffer MC10195 - 2.0 200 620 Hex AND Gate MC10197 - 2.8 200 620 High Speed Dual 3-Input 3-Output OR Gate MC10210 _ 1.5 160 620 High Speed Oual 3-input 3-Output NOR Gate MC10211 =_ 1.5 160 620 High Speed Dual 3-Input 3-Output OR/NOR Gate MCc10212 _ 1.5 160 620 High Speed Tripie Line Receiver MC 10216 Mc 10616 1.8 100 620,648,650 High Speed Dual Type D Master-Slave Flip-Flop Mc10231 mMc10631 f = 225 MHz 270 620,648,650 High Speed 2 x 1 Bit Array Multiplier Block MC 10287 - ~ 400 620 q@ L suffix denotes Dual In-Line Ceramic Package, P suffix denotes Dual In-Line Plastic Package, F suffix denotes flat package {i.e., MC101001. = Ceramic Dual In-Line Package, MC10100P = Plastic Dual !n-Line Package and MC 10S500F = Ceramic Flat Package.) *Load Power not included~ SHIFT REGISTERS LOGIC DIAGRAMS (continued) (1) 37 OL ((g) 4 c ao 14 (2) (16) 12 bo (15) 11 01 ai 15 (3) (13) 9 02 (10) 6 b3 a2 2 (6) (14) 10 $1 a1) 7 $2 a3 3 (7) OR (9) MC 10141 MC 10541 Four-Bit Universal Shift Register TRUTH TABLE SELECT OUTPUTS $1 S2 | OPERATING MODE | Q0,44| Q1n+4 | Q2n4+4 | Q3n41 L Lt Paratlel Entry po o1 D2 03 L H Shift Right* at, | Q2, | a3, DR H L Shift Left* DL ao, | Qt, | a2, H H Stop Shift ao, | at, | a2, | 03, * Outputs as exist after pulse appears at C input with input conditions as shown, (Pulse = Positive transition of clock input). Pp = 425 mw typ/pkg f shift = 200 MHz typ ERROR DETECTION-CORRECTION MC 10163 LOGIC DIAGRAM B17 ro B2 6 } _B412 8711 H _BS 4 5 B6 5 72. BO 9 + B3 10 4 | |} 18M CODE PO, = B1, B2, B4, B7 P0g = 80, B3, B5, BG P1= B1, B3, BS, B7 P2 = B2, B3, 86, B7 P3 = B4, 85, BG, B7 MC 10163 e MC 10193 Error Detectian-Correction Circuit MC 10193 LOGIC DIAGRAM B17 B2 6 T 15 PO, 8412 5 87 11 } 3P3 BS 4 + B6 5 } 2P05 Bo 9 83 10 4} 14P4 13 P2 15 Pa 2P5 14 P1 13 P2 Pp = 520 mW typ/pkg (No Load) tod = 5.0 ns typ MOTOROLA CODE P1 = B1, B3, BS, B7 P2 = B2, B3, BG, B7 P3 = 84, BS, B6, B7 P4 = B1, B2, B4, B7 PS = Byte (B0, 1, 2, 3, 4, 5, 6, 7) Pp = 520 mW typ/pkg (No Load) tod = 7.5 ns typ (Pin 7 to Pin 2) 2-22FOUR-BIT UNIVERSAL SHIFT REGISTER MECL 10,000 series MC10541 (1) 13> DL (8) 4 Cc ag 14 (2) (16) 12- bo (15) 11 D1 Qi 15 (3) (13) 9 D2 (10) 6 B3 a2 2 (6) (14) 10 $1 (11) 7 s2 a3 3 (7) OR (9) >___ TRUTH TABLE SELECT OUTPUTS S1 | S2 | OPERATING MODE | Q0444] Q1n41| Q2p41 |Q3p+1 L lL Parallel Entry bo D1 02 D3 L H Shift Right* aly. Q2, Q3, DR H t Shift Left* BL ao, | atn O22 H H Stop Shift ao, Qty, | Q2y_ | a3, *Ourputs as exist after pulse appears Bt OC" input with input conditions as shown. (Pulse = Positive transition of clock input). The MC10541 is a four-bit universal shift register which performs shift left, or shift right, serial/paratlel in, and serial/parallel out opera- tions with no external gating. Inputs $1 and $2 control the four possible operations of the register without external gating of the clock. The flip-flops shift information on the positive edge of the clock. The four operations are stop shift, shift left, shift right, and parallel entry of data. The other six inputs are al} data type in- puts; four for parallel entry data, and one for shifting in from the left (DL) and one for shift- ing in from the right (DR). All four outputs are capable of driving 100 ohm lines. When the register is used for serial output only, the unused emitter follower outputs can be left-open. Pp = 425 mW typ/pkg (No Load) fghitt 150 MHz tye \ Case vde1 Vec2 VEE Numbers at end of terminals are pin numbers for | package (Case 620). 620 | Pin 1 | Pin 16| Pin8 Numbers in parenthesis denotes pin numbers for F package (Case 650). 650 Pin Pin 4 |Pin 12 LOGIC DIAGRAM bs o2 D1 DO 510~ { eocate Enter i [ lot 4 - $20-1 H] Bhift Right _ DS DH Shift Left - OL Hold t >] : o 4 bd a oa c c c co_f> a2 at ao See General Information section for pack aging. 3-30860E- ELECTRICAL CHARACTERISTICS Each full temperature range MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been estab- lished. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 iinear fpm is maintained. Outputs are terminated through a 100-ohm resistor to -2.0 volts. Test procedures are shown only for se- lected inputs and outputs. Other inputs and outputs are tested in a similar manner. 13 44c 12 DO WY D1 9 b2 6 D3 10-_4$1 7 $2 OL Qo0h-14 Qi 15 Q2 2 aQ3- 3 OR L SUFFIX CERAMIC PACKAGE CASE 620 TEST VOLTAGE VALUES {Volts} Pq rq eo VIL ViL (2) See switching time test circuit far test procedures. (3) See shift frequency test circuit for test procedures. (4) Reset to zero before performing test. (5) Reset to one before performing test. @ Test J Temperature} iHmax | Vitmin} VinAmin|iLAmax| VEE 8 -ssc [| -0.880 | -1.920 | -1.255 | -1.510 |-5.2 +26C =| -0.780 | -1.850 | -1.105 | -1.475 |-5.2 +125C__| -0.630 | -1.820 | -1.000 | 1.400 |-5.2 Pin MC 105414 Test Limits TEST VOLTAGE APPLIED TO Under -55C +#25C +125C PINS LISTED BELOW: ce) Characteristic Symbol | Test Min Max Min Typ Max Min Max Unit | Vitmax | Vitmin] VidAmin ViLAmax|VEE | 21] P2) 3 | Gnd Power Supply Drain Current le 8 = 110 = 100 110 mAdc _ = - 8 = - = 1,16 Input Current tin 5 = 375 = 220 - 220 wade 5 - = - 8 ~[ - | - [116 6 - 375 - - 220 ~ 220 6 ~ ~ - -{ -[ 7 - 415 ~ - 245 - 245 | 7 - - - | - -| - 4 - 450 - = 265 - 265 4 = - - -~f{ -| - lint. 42 0.5 - 0.5 = - 0.3 - pAde |4,5,6,7,9} 12 - - 8 | - | 1,16 10,11,13 Logie *1'" Output Voltage Vou 3 -1.080 | -0.880 | -0.930 = -0.780 | -0.825 | -0.630 } Vde 6 - - - 8 4 | ~ | 116 Logic 0 Output Voltage VoL 3 -1.920 | -1.655 | -1.850 -1.620 | -1.820 | -1.545 [| Vdc = = = = 8 4 -~ | 7] 1,16 Logic 1 Threshold Voltage VOHA 3 -1.100 = -0.950 = - -0.845 - Vde - ~ 6 = 8 4 =] = 7 1,16 a { - - - - 6 @ - 7 | aq - ~ _ _ _ 6 @ _ _ 4 - = ~ - = = = = - -| -| 4 Lagic Q" Threshold Valtage VOLA 3 - -7.835 = - -1.625 Vde ~ - - 6 8 4 | 1,16 - - - - = - 7 4 =~} - MTL PT st EAE: - - ~ - 6 = = = -| -| 4 Switching Times (100 2 Load) 3.2V +2.0V Propagation Delay ta434 3 ~ - 1.0 29 38 - - ns @ - - - 8 - - - 1 1,16 Setup Time (setup) 142444 14 = _ 2.5 - = = _ = _ _ - - 12-4+ - - 2.5 - - - - - - - - - - - t0+4+ - - 5.0 - - - - - - - - -fo-] - 9-44 - - 5.0 - = - - _ - - = - - = Hold Time (thoid) tq+12+ - - 15 ~ - - - - - = - - - - 14+12- - _ V5 - - - _ - - - - - - 1a+10+ - - 1.0 ~ - - - - - - - - -~| - t4+10- - - 1.0 - - - = - - -]| -]- Rise Time (20% to 80%) 134 3 - - 11 17 3.3 - - @ ~ - - - - - Fali Time (20% to 80%) t3- 3 - - 14 17 33 - - @ - ~ - - - - Shift Frequency f Shite - - 150 ~ = - ~ MHz @ ~ - - - = = a These tests to be performed in sequence as shown. VILA (panul1u09) LYGOLOWOLE- ELECTRICAL CHARACTERISTICS Each full temperature range MECL 10,000 series circuit has been designed to meet the DL de specifications shown in the test table, 8 Cc ao 2 after thermal equilibrium has been estab- he ba lished. The circuit is in a test socket or " _ F SUFFIX mounted on a printed circuit board and 15 Dt ai 3 CERAMIC PACKAGE transverse air flow greater than 500 linear 13 02 CASE 650 fem 1 an, Outputs are tegeminated 10 D3 a2 6 through a TOM-ohm resis MONS. 14 51 TEST VOLTAGE VALUES Test procedures are shown only for se- (ols) lected inputs and outputs. Other inputs A $2 a3 7 er = ted in a similar manner. R est p and outputs are teste ' S Temperature | ViHmax | ViLmin| VIHAmin Vit Amax{ VEE $ -55C -0.880 | -1.920 | -1.265 | -1.510 |-5.2 +25C -0.780 | -1.850 | -1.105 | -1.475 |-5.2 +125C 0.630 | -1.820 } -1.000 | -1.400 [-5.2 Pin MCTOSA1F Test Limits TEST VOLTAGE APPLIED TO Under -55C +25C +125C PINS LISTED BELOW: (Veco) Characteristic Symbol | Test | Min Max Min Typ Max Min Max | Unit | Vitimax | Vitmin| VitAmin VitAmax|Vee | Pt} P2] P3 | Gnd Power Supply Drain Current le 12 _ 110 - 400 - 110 mAdc - - - - 12 - - = 45 Input Current lin 9 - 365 - = 220 - 220 BAdC 9 - - - 12 _ - _ 45 10 _ 365 - _ 220 - 220 10 - - - - ~ - Ww - 420 - - 245 - 245 vi - _ - - - = 8 = 455 = = 265 = 268 8 = = _ = = = lint 16 as - 0.5 = _ 03 - BAdc 48,9,10,11, 16 - - 12 - = - 45 13,14,15, 4 Logic 1" Output Voltage VOH 7 -1.080 | -0.880 | -0.930 ~ -0.780 | -0.825 | -0.630 Vde 10 - = - 12 8 - = 45 Logic 0" Output Voltage VoL 7 -1.920 | -1.655 | -1.850 - -1,.620.| -1.820 | -1.545 [Vac - = = = iz2f{s]-j] - [45 Logic 1" Threshold Voltage VOHA 7 -1.100 - -0.950 _ = -0.845 - Voc - - 10 - 42 8 - _ 45 ae - - - - 10 (4) _ "1 8 - - - ~ - - 10 (4) - - -| 8 - = - = - ~ - _ = = = 8 Logic 0 Threshold Voltage VOLA 7 - -1.635 ~ - -1.600 ~ -1.525 | Vde - - - 10 w2]a]-]-] 4s - - - - - - nH a} -} - - = = _ = - - ~ 3 = = - - - 10 = - - -|-{|{ 8 Y Switching Times (100 Load) [3.2 +2.0V Propagation Delay 1gt7+ 7 - - 10 29 3.8 - - ns ~ - - 124) - ~ - 4,5 Setup Time (tsetup) 116+8+ 2 - - 2.5 - - - = - = - - ~ - - 46-8+ - - 25 - - ~ - - - - - -~}| -f = 114+8+ ~ - 5.0 - - - - - - - _ - - - t14-8+ - - 5.0 = - - - - - - - = - = Hold Time {thoid) tg+16+ - - 15 - - - - - - - - - _ - te+16- = - 1.5 - - = - ~ - - - - - - (g+14+ - - 1.0 - - - - - - - = - - - tg+14- - - 1.0 - - = - - - - - - - - Rise Time (20% to 80%) H+ 7 - - 1 1.7 3.3 - - @ - - - -} -] - Fall Time (20% to 80%) 17 7 - - if WW 3.3 - - @ - - ~ -|} -f - Shift Frequency fShitt - - - 150 = - - - MHz = - - -} -] - @ These tests to be performed in sequence as shown. VIHA VILA JOL Vie Vin JL Vit (2) See switching time test circuit for test procedures. (3) See shift frequency test circuit for test procedures. (4) Reset to zero before performing test. (5) Reset to one before performing test. (panuizu0s) LYGOLOWMC 10541 (continued) SWITCHING TIME TEST CIRCUIT AND WAVEFORMS @ 25C 50-ohm termination to ground lo- cated in each scope channel input. All input and output cables to the scope are equal tengths of 50-ohm coaxial cable. Wire length should be. <1/4 inch from TPip, to input pin and TPgyz to output pin. Vout is 2:1 attenuated. Clock 50% Q Output Yec1 = Yec2 Vin +2.0 Vde Vout Coax Coax Input Pulse th = 1- = 2.040.2 ns (20 to 80%) 50 tnput DL O OC aQ0ko b Pulse Generator ob0 oo D1 Qip---O o 02 O o D3 a2----O oS1 o S82 a3h-O DR +1494 o-_ +0.31V T 0.1 uF tc-a- = Veg = -3.2 Vde Mc10102 " <I 100 SHIFT FREQUENCY TEST CIRCUIT Coax Input Pulse Generator 50-ohm termination to ground lo cated in each scope channel input. Voco1 = Yoc2 +2.0 Vdc Vout eee To BE Coax 50 . OL oe Qao-+O Oo* o7 DO 0.1 uF thAB Veg = -32 Vde All input and output cables to the scope are equal lengths of 50-ohm coaxial cable. Wire length should be <1/4 inch from TPj, to input pin and TPoyt to Output pin. Vout is 2:1 attenuated. Test Procedures: 1. Set 01, D2, D3 = +0.31 Vde (Logie L) DO = +1.11 Vde (Logic A) 2. Apply Clock putse j ty to set QO high. Ie 3. Maintain Clock Low. Set S1 = +0.31 Vde (Logic L) $2 = 41.11 Vde (Logic H) 4. Test Shift Frequency All unused outputs are connected to 100-ohm resistor to ground. 3-311