MR0A08B FEATURES 128K x 8 MRAM Memory * Fast 35 ns Read/Write Cycle * SRAM Compatible Timing, Uses Existing SRAM Controllers Without Redesign * Unlimited Read & Write Endurance * Data Always Non-volatile for >20-years at Temperature * One Memory Replaces Flash, SRAM, EEPROM and BBSRAM in System for Simpler, More Efficient Design * Replace battery-backed SRAM solutions with MRAM to eliminate battery assembly improving reliability * 3.3 Volt Power Supply * Automatic Data Protection on Power Loss * Commercial, Industrial, Automotive Temperatures * RoHS-Compliant SRAM TSOPII Package * RoHS-Compliant SRAM BGA Package Shrinks Board Area By Three Times INTRODUCTION RoHS The MR0A08B is a 1,048,576-bit magnetoresistive random access memory (MRAM) device organized as 131,072 words of 8 bits. The MR0A08B offers SRAM compatible 35 ns read/write timing with unlimited endurance. Data is always nonvolatile for greater than 20-years. Data is automatically protected on power loss by low-voltage inhibit circuitry to prevent writes with voltage out of specification. The MR0A08B is the ideal memory solution for applications that must permanently store and retrieve critical data and programs quickly. The MR0A08B is available in small footprint 400-mil, 44-lead plastic small-outline TSOP type-II package or 8 mm x 8 mm, 48-pin ball grid array (BGA) package with 0.75 mm ball centers. These packages are compatible with similar low-power SRAM products and other non-volatile RAM products. The MR0A08B provides highly reliable data storage over a wide range of temperatures. The product is offered with commercial temperature (0 to +70 C), industrial temperature (-40 to +85 C), and automotive temperature (-40 to +125 C) range options. CONTENTS 1. DEVICE PIN ASSIGNMENT......................................................................... 2 2. ELECTRICAL SPECIFICATIONS................................................................. 4 3. TIMING SPECIFICATIONS.......................................................................... 7 4. ORDERING INFORMATION....................................................................... 12 5. MECHANICAL DRAWING.......................................................................... 13 6. REVISION HISTORY...................................................................................... 15 How to Reach Us.......................................................................................... 15 Everspin Technologies (c) 2009 1 Document Number: MR0A08B Rev. 2, 6/2009 MR0A08B 1. DEVICE PIN ASSIGNMENT Figure 1.1 Block Diagram OUTPUT ENABLE BUFFER G A[16:0] 17 ADDRESS BUFFER OUTPUT ENABLE 7 10 CHIP ENABLE BUFFER E COLUMN DECODER 8 SENSE AMPS 128k x 8 BIT MEMORY ARRAY WRITE ENABLE BUFFER W ROW DECODER 8 FINAL WRITE DRIVERS 8 OUTPUT BUFFER 8 WRITE DRIVER 8 8 DQ[7:0] WRITE ENABLE Table 1.1 Pin Functions Signal Name Function A Address Input E Chip Enable W Write Enable G Output Enable DQ Data I/O VDD Power Supply VSS Ground DC Do Not Connect NC No Connection - Pin 2, 40, 41, 43 (TSOPII), Ball D3, H1, H6, G2 (BGA) Reserved For Future Expansion Everspin Technologies (c) 2009 2 Document Number: MR0A08B Rev. 2, 6/2009 MR0A08B DEVICE PIN ASSIGNMENT Figure 1.2 Pin Diagrams for Available Packages (Top View) DC NC A0 A1 A2 A3 A4 E DQ0 DQ1 VDD VSS DQ2 DQ3 W A5 A6 A7 A8 A9 DC DC 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 DC NC DC NC NC A16 A15 G DQ7 DQ6 VSS VDD DQ5 DQ4 DC A14 A13 A12 A11 A10 DC DC 1 2 3 4 5 6 DC G A0 A1 A2 DC A NC DC A3 A4 E DC B DQ0 NC A5 A6 NC DQ4 C VSS DQ1 NC A7 DQ5 VDD D VDD DQ2 DC A16 DQ6 VSS E DQ3 NC A14 A15 NC DQ7 F NC NC A12 A13 W NC G NC A8 A9 A10 A11 NC H 44 Pin TSOP II 48 Pin FBGA Table 1.2 Operating Modes E1 G1 W1 Mode VDD Current DQ[7:0]2 H X X Not selected ISB1, ISB2 Hi-Z L H H Output disabled IDDR Hi-Z L L H Byte Read IDDR DOut L X L Byte Write IDDW Din H = high, L = low, X = don't care 1 Hi-Z = high impedance 2 Everspin Technologies (c) 2009 3 Document Number: MR0A08B Rev. 2, 6/2009 MR0A08B 2. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings This device contains circuitry to protect the inputs against damage caused by high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage greater than maximum rated voltages to these high-impedance (Hi-Z) circuits. The device also contains protection against external magnetic fields. Precautions should be taken to avoid application of any magnetic field more intense than the maximum field intensity specified in the maximum ratings. Table 2.1 Absolute Maximum Ratings1 Parameter Symbol Value Unit Supply voltage2 VDD -0.5 to 4.0 V Voltage on an pin2 VIN -0.5 to VDD + 0.5 V Output current per pin IOUT 20 mA Package power dissipation PD 0.600 W Temperature under bias MR0A08B (Commercial) MR0A08BC (Industrial) MR0A08BM (Automotive) TBIAS -10 to 85 -45 to 95 -45 to 130 Storage Temperature Tstg -55 to 150 C Lead temperature during solder (3 minute max) TLead 260 C Maximum magnetic field during write MR0A08B (All Temperatures) Hmax_write 2000 A/m Maximum magnetic field during read or standby Hmax_read 8000 A/m C 1 Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted to recommended operating conditions. Exposure to excessive voltages or magnetic fields could affect device reliability. 2 All voltages are referenced to VSS. 3 Power dissipation capability depends on package characteristics and use environment. Everspin Technologies (c) 2009 4 Document Number: MR0A08B Rev. 2, 6/2009 MR0A08B Electrical Specifications Table 2.2 Operating Conditions i ii iii iv Parameter Symbol Value Typical Max Unit Power supply voltage VDD 3.0 i 3.3 3.6 V Write inhibit voltage VWI 2.5 2.7 3.0 i V Input high voltage VIH 2.2 - VDD + 0.3 ii V Input low voltage VIL -0.5 iii - 0.8 Temperature under bias MR0A08B (Commercial) MR0A08BC (Industrial) MR0A08BM (Automotive)iv TA 0 -40 -40 70 85 125 V C There is a 2 ms startup time once VDD exceeds VDD,(max). See Power Up and Power Down Sequencing below. VIH(max) = VDD + 0.3 VDC ; VIH(max) = VDD + 2.0 VAC (pulse width 10 ns) for I 20.0 mA. VIL(min) = -0.5 VDC ; VIL(min) = -2.0 VAC (pulse width 10 ns) for I 20.0 mA. Automotive temperature profile assumes 10% duty cycle at maximum temperature (2-years out of 20-year life) Power Up and Power Down Sequencing MRAM is protected from write operations whenever VDD is less than VWI. As soon as VDD exceeds VDD(min), there is a startup time of 2 ms before read or write operations can start. This time allows memory power supplies to stabilize. The E and W control signals should track VDD on power up to VDD- 0.2 V or VIH (whichever is lower) and remain high for the startup time. In most systems, this means that these signals should be pulled up with a resistor so that signal remains high if the driving signal is Hi-Z during power up. Any logic that drives E and W should hold the signals high with a power-on reset signal for longer than the startup time. During power loss or brownout where VDD goes below VWI, writes are protected and a startup time must be observed when power returns above VDD(min). Figure 2.1 Power Up and Power Down Diagram STARTUP TIME STARTUP TIME VDD VDD VWI VWI BROWNOUT OR POWER LOSS WRITES INHIBITED E W NORMAL OPERATION Everspin Technologies (c) 2009 NORMAL OPERATION 5 Document Number: MR0A08B Rev. 2, 6/2009 MR0A08B Electrical Specifications Table 2.3 DC Characteristics Parameter Symbol Min Typical Max Unit Input leakage current Ilkg(I) - - 1 A Output leakage current Ilkg(O) - - 1 A Output low voltage (IOL = +4 mA) (IOL = +100 A) VOL - - 0.4 VSS + 0.2 V Output high voltage (IOL = -4 mA) (IOL = -100 A) VOH 2.4 VDD - 0.2 - - V Table 2.4 Power Supply Characteristics 1 Parameter Symbol Typical Max Unit AC active supply current - read modes1 (IOUT= 0 mA, VDD= max) IDDR 25 30 mA AC active supply current - write modes1 (VDD= max) MR0A08B (Commercial) MR0A08BC (Industrial) MR0A08BM (Automotive) IDDW 55 55 TBD 65 70 TBD mA AC standby current (VDD= max, E = VIH) no other restrictions on other inputs ISB1 6 7 mA CMOS standby current (E VDD - 0.2 V and VIn VSS + 0.2 V or VDD - 0.2 V) (VDD = max, f = 0 MHz) ISB2 5 6 mA All active current measurements are measured with one address transition per cycle and at minimum cycle time. Everspin Technologies (c) 2009 6 Document Number: MR0A08B Rev. 2, 6/2009 MR0A08B 3. TIMING SPECIFICATIONS Table 3.1 Capacitance1 1 Parameter Symbol Typical Max Unit Address input capacitance CIn - 6 pF Control input capacitance CIn - 6 pF Input/Output capacitance CI/O - 8 pF Parameter Value Unit Logic input timing measurement reference level 1.5 V Logic output timing measurement reference level 1.5 V Logic input pulse levels 0 or 3.0 V Input rise/fall time 2 ns Output load for low and high impedance parameters See Figure 3.1 Output load for all other timing parameters See Figure 3.2 f = 1.0 MHz, dV = 3.0 V, TA = 25 C, periodically sampled rather than 100% tested. Table 3.2 AC Measurement Conditions Figure 3.1 Output Load Test Low and High ZD= 50 Output RL = 50 VL = 1.5 V Figure 3.2 Output Load Test All Others 3.3 V 590 Output 5 pF 435 Everspin Technologies (c) 2009 7 Document Number: MR0A08B Rev. 2, 6/2009 MR0A08B Timing Specifications Read Mode Table 3.3 Read Cycle Timing1 Parameter Symbol Min Max Unit Read cycle time tAVAV 35 - ns Address access time tAVQV - 35 ns Enable access time2 tELQV - 35 ns Output enable access time tGLQV - 15 ns Output hold from address change tAXQX 3 - ns Enable low to output active tELQX 3 - ns Output enable low to output active3 tGLQX 0 - ns Enable high to output Hi-Z tEHQZ 0 15 ns Output enable high to output Hi-Z3 tGHQZ 0 10 ns 3 3 1 2 3 W is high for read cycle. Power supplies must be properly grounded and decoupled, and bus contention conditions must be minimized or eliminated during read or write cycles. Addresses valid before or at the same time E goes low. This parameter is sampled and not 100% tested. Transition is measured 200 mV from the steady-state voltage. Figure 3.3A Read Cycle 1 Figure 3.3B Read Cycle 2 Everspin Technologies (c) 2009 8 Document Number: MR0A08B Rev. 2, 6/2009 MR0A08B Timing Specifications Table 3.4 Write Cycle Timing 1 (W Controlled)1 Parameter Symbol Min Max Unit Write cycle time2 tAVAV 35 - ns Address set-up time tAVWL 0 - ns Address valid to end of write (G high) tAVWH 18 - ns Address valid to end of write (G low) tAVWH 20 - ns 15 - ns 15 - ns tWLWH tWLEH tWLWH tWLEH Write pulse width (G high) Write pulse width (G low) Data valid to end of write tDVWH 10 - ns Data hold time tWHDX 0 - ns tWLQZ 0 12 ns Write high to output active tWHQX 3 - ns Write recovery time tWHAX 12 - ns Write low to data Hi-Z3 3 1 2 3 All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after W goes low, the output will remain in a high impedance state. After W or E has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. All write cycle timings are referenced from the last valid address to the first transition address. This parameter is sampled and not 100% tested. Transition is measured 200 mV from the steady-state voltage. At any given voltage or temperate, tWLQZ(max) < tWHQX(min) Figure 3.4 Write Cycle Timing 1 (W Controlled) Everspin Technologies (c) 2009 9 Document Number: MR0A08B Rev. 2, 6/2009 MR0A08B Timing Specifications Table 3.5 Write Cycle Timing 2 (E Controlled)1 1 2 3 Parameter Symbol Min Max Unit Write cycle time2 tAVAV 35 - ns Address set-up time tAVEL 0 - ns Address valid to end of write (G high) tAVEH 18 - ns Address valid to end of write (G low) tAVEH 20 - ns Enable to end of write (G high) tELEH tELWH 15 - ns Enable to end of write (G low)3 tELEH tELWH 15 - ns Data valid to end of write tDVEH 10 - ns Data hold time tEHDX 0 - ns Write recovery time tEHAX 12 - ns All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after W goes low, the output will remain in a high impedance state. After W or E has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. All write cycle timings are referenced from the last valid address to the first transition address. If E goes low at the same time or after W goes low, the output will remain in a high-impedance state. If E goes high at the same time or before W goes high, the output will remain in a high-impedance state. Figure 3.5 Write Cycle Timing 2 (E Controlled) Everspin Technologies (c) 2009 10 Document Number: MR0A08B Rev. 2, 6/2009 MR0A08B Timing Specifications Table 3.6 Write Cycle Timing 3 (Shortened tWHAX, W and E Controlled)1 Parameter Symbol Min Max Unit Write cycle time2 tAVAV 35 - ns Address set-up time tAVWL 0 - ns Address valid to end of write (G high) tAVWH 18 - ns Address valid to end of write (G low) tAVWH 20 - ns Write pulse width tWLWH tWLEH 15 - ns Data valid to end of write tDVWH 10 - ns Data hold time tWHDX 0 - ns Enable recovery time tEHAX -2 - ns tWHAX 6 - ns tWHEL 12 - ns Write recovery time3 Write to enable recovery time 3 1 2 3 All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after W goes low, the output will remain in a high impedance state. After W, or E has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device. All write cycle timings are referenced from the last valid address to the first transition address. If E goes low at the same time or after W goes low the output will remain in a high impedance state. If E goes high at the same time or before W goes high the output will remain in a high impedance state. E must be brought high each cycle. Table 3.6 Write Cycle Timing 3 (Shortened tWHAX, W and E Controlled) t AVAV A (ADDRESS) t WHAX t AVWH E (CHIP ENABLE) t EHAX t WLEH W (WRITE ENABLE) t WHEL t WLWH t AVWL t DVWH t WHDX D (DATA IN) Everspin Technologies (c) 2009 11 Document Number: MR0A08B Rev. 2, 6/2009 MR0A08B 4. ORDERING INFORMATION Figure 4.1 Part Numbering System MR 0 A 08 B C YS 35 R Carrier (Blank = Tray, R = Tape & Reel) Speed (35 ns) Package (YS = TSOPII, MA = FBGA) Temperature Range (Blank= 0 to +70 C, C= -40 to +85 C, M= -40 to +125 C) Revision (A = 180 nm, B = 130 nm) Data Width (08 = 8-Bit, 16 = 16-bit) Type (A = Asynchronous, S = Synchronous) Density (256 = 256 Kb, 0 = 1Mb, 1 =2Mb, 2 =4Mb, 4 =16Mb) Magnetoresistive RAM (MR) Part Number Table 4.1 Available Parts Description Temperature MR0A08BYS35 MR0A08BCYS35 MR0A08BMYS351 MR0A08BYS35R MR0A08BCYS35R MR0A08BMYS35R 1 3.3 V 128Kx8 MRAM 44-TSOP 3.3 V 128Kx8 MRAM 44-TSOP 3.3 V 128Kx8 MRAM 44-TSOP 3.3 V 128Kx8 MRAM 44-TSOP T&R 3.3 V 128Kx8 MRAM 44-TSOP T&R 3.3 V 128Kx8 MRAM 44-TSOP T&R Commercial Industrial Automotive Commercial Industrial Automotive MR0A08BMA35 MR0A08BCMA35 3.3 V 128Kx8 MRAM 48-BGA 3.3 V 128Kx8 MRAM 48-BGA MR0A08BMMA351 3.3 V 128Kx8 MRAM 48-BGA Commercial Industrial Automotive The automotive temperature grade parts are classified as Preliminary. 1 Everspin Technologies (c) 2009 12 Document Number: MR0A08B Rev. 2, 6/2009 MR0A08B 5. MECHANICAL DRAWING Figure 5.1 TSOP-II 1. 2. 3. 4. Print Version Not To Scale Dimensions and tolerances per ASME Y14.5M - 1994. Dimensions in Millimeters. Dimensions do not include mold protrusion. Dimension does not include DAM bar protrusions. DAM Bar protrusion shall not cause the lead width to exceed 0.58. Everspin Technologies (c) 2009 13 Document Number: MR0A08B Rev. 2, 6/2009 MR0A08B Mechanical Drawings Figure 5.2 FBGA TOP VIEW SIDE VIEW BOTTOM VIEW 1. 2. 3. 4. 5. Print Version Not To Scale Dimensions in Millimeters. Dimensions and tolerances per ASME Y14.5M - 1994. Maximum solder ball diameter measured parallel to DATUM A DATUM A, the seating plane is determined by the spherical crowns of the solder balls. Parallelism measurement shall exclude any effect of mark on top surface of package. Everspin Technologies (c) 2009 14 Document Number: MR0A08B Rev. 2, 6/2009 MR0A08B 6. REVISION HISTORY Revision Date 0 Sep 12, 2008 Description of Change Initial Advance Information Release Revised format; Add Table 3.6 Write Timing Cycle 3; Add Figure 3.6 Write TimMay 8, 2009 ing Cycle 3; Add TSOPII Lead Width Info; Changed to Preliminary from Product Concept. Changed from datasheet from Preliminary to Production except where June 18, 2009 noted. 1 2 Unless Otherwise Noted, This is a Production Product - This product conforms to specifications per the terms of the Everspin standard warranty. The product has completed Everspin internal qualification testing and has reached production status. How to Reach Us: Home Page: www.everspin.com E-Mail: support@everspin.com orders@everspin.com sales@everspin.com USA/Asia/Pacific Everspin Technologies 1300 N. Alma School Road, CH-409 Chandler, Arizona 85224 +1-877-347-MRAM (6726) +1-480-347-1111 Europe, Middle East and Africa support.europe@everspin.com Wokingham, United Kingdom +44 (0)118 907 6155 Information in this document is provided solely to enable system and software implementers to use Everspin Technologies products. There are no express or implied licenses granted hereunder to design or fabricate any integrated circuit or circuits based on the information in this document. Everspin Technologies reserves the right to make changes without further notice to any products herein. Everspin makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Everspin Technologies assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters, which may be provided in Everspin Technologies data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters including "Typicals" must be validated for each customer application by customer's technical experts. Everspin Technologies does not convey any license under its patent rights nor the rights of others. Everspin Technologies products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Everspin Technologies product could create a situation where personal injury or death may occur. Should Buyer purchase or use Everspin Technologies products for any such unintended or unauthorized application, Buyer shall indemnify and hold Everspin Technologies and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Everspin Technologies was negligent regarding the design or manufacture of the part. EverspinTM and the Everspin logo are trademarks of Everspin Technologies, Inc. All other product or service names are the property of their respective owners. (c)Everspin Technologies, Inc. 2008 Japan support.japan@everspin.com Yokohama, Japan +81 (0) 45-846-6299 Document Number: MR0A08B, Revision 2, 6/2009 Everspin Technologies (c) 2009 15 Document Number: MR0A08B Rev. 2, 6/2009