5 V Precision Voltage
Reference/Temperature Transducer
REF02
Rev. I
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 www.analog.com
Fax: 781.461.3113 © 2005 Analog Devices, Inc. All rights reserved.
FEATURES
5 V output: ±0.3% maximum
Temperature voltage output: 1.96 mV/°C
Adjustment range: ±3% minimum
Excellent temperature stability: 8.5 ppm/°C maximum
Low noise: 15 µV p-p maximum
Low supply current: 1.4 mA maximum
Wide input voltage range: 7 V to 40 V
High load-driving capability: 10 mA
No external components
Short-circuit proof
GENERAL DESCRIPTION
The REF02 precision voltage reference provides a stable 5 V
output that can be adjusted over a ±6% range with minimal
effect on temperature stability. Single-supply operation over an
input voltage range of 7 V to 40 V, low current drain of 1 mA,
and excellent temperature stability are achieved with an
improved band gap design. Low cost, low noise, and low power
make the REF02 an excellent choice whenever a stable voltage
reference is required. Applications include DACs and ADCs,
portable instrumentation, and digital voltmeters. The versatility
of the REF02 is enhanced by its use as a monolithic temperature
transducer. For new designs, refer to the ADR02.
PIN CONFIGURATIONS
00375-F-001
1
2
345
6
7
8
NC
GROUND
(CASE)
NC
V
IN
V
OUT
NC
NC TRIM
NC = NO CONNECT. DO NOT CONNECT ANYTHING
ON THESE PINS. SOME OF THEM ARE RESERVED
FOR FACTORY TESTING PURPOSES.
Figure 1. 8-Lead TO-99 (J-Suffix)
00375-F-002
REF02
TOP VIEW
(Not to Scale)
NC
1
V
IN 2
TEMP
3
GND
4
NC
NC
V
OUT
TRIM
8
7
6
5
NC = NO CONNECT. DO NOT CONNECT ANYTHING
ON THESE PINS. SOME OF THEM ARE RESERVED
FOR FACTORY TESTING PURPOSES.
Figure 2. 8-Lead PDIP (P-Suffix), 8-Lead CERDIP (Z-Suffix)
and 8-Lead SOIC (S-Suffix)
00375-F-003
4
NC
5
V
IN
6
NC
7
TEMP
8
NC
18
NC
17
NC
16
NC
15
V
OUT
14
NC
19
NC
20
NC
1
NC
2
NC
3
NC
13
NC
12
TRIM
11
NC
10
GND
9
NC
REF02
TOP VIEW
(Not to Scale)
NC = NO CONNECT. DO NOT CONNECT ANYTHING
ON THESE PINS. SOME OF THEM ARE RESERVED
FOR FACTORY TESTING PURPOSES.
Figure 3. 20-Terminal LCC (RC-Suffix)
REF02 OPTION R9 R11 R12
P, S, J, Z PACKAGES 18kΩ4.5kΩ15kΩ
OUTPUT RESISTORS
00375-F-004
C1
R3
R6
R4
R5
R1
Q1
R2
R10
OUTPUT
GROUND
R12*
TRIM
Q19
R15
INPUT
Q15
Q18
Q16
Q13
Q21
Q17
R13
Q20
Q4 Q3
Q5
Q6
Q9
Q7 Q14
Q12
Q11
Q8
R8 R7 R14
Q10
Q2
R11*
R9*
4
5
6
≈
1.23V
2
TEMP 3
*SEE OUTPUT RESISTORS
883C PRODUCT 18kΩ2kΩ6.1kΩ
Figure 4. Simplified Schematic
REF02
Rev. I | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
General Description......................................................................... 1
Pin Configurations ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Electrical Specifications............................................................... 3
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution.................................................................................. 7
Typical Performance Characteristics ..............................................8
Output Adjustment ........................................................................ 10
Temperature Monitoring........................................................... 11
Reference Stack with Excellent Line Regulation.................... 11
Precision Current Source .......................................................... 12
Supply Bypassing........................................................................ 12
Outline Dimensions ....................................................................... 13
Ordering Guide .......................................................................... 15
REVISION HISTORY
12/05—Rev. H to Rev. I
Changes to Figure 14...................................................................... 10
Changes to Ordering Guide .......................................................... 15
5/05—Rev. G to Rev. H
Updated Figure 4 .............................................................................. 1
Changes to Specifications................................................................ 3
Updated Outline Dimensions....................................................... 13
Changes to Ordering Guide .......................................................... 15
2/05—Rev. F to Rev. G
Changes to Specifications................................................................ 3
Change to Outline Dimensions .................................................... 13
7/04—Rev. E to Rev. F
Updated Format..................................................................Universal
Changes to Simplified Schematic ................................................... 1
Changes to Specifications................................................................ 3
Changes to Specifications................................................................ 4
Changes to Specifications................................................................ 5
Changes to Specifications................................................................ 6
Changes to Figure 18...................................................................... 10
Changes to Ordering Guide .......................................................... 15
3/04—Rev. D to Rev. E
Changes to Features.......................................................................... 1
Changes to Specifications................................................................ 2
Changes to Ordering Guide ............................................................ 4
Replaced TPCs 3 and 4 .................................................................... 5
Added Temperature Monitoring section ...................................... 7
Updated Figure 5 ............................................................................. 7
Deleted Table I .................................................................................. 7
Updated Figure 6 ............................................................................. 7
10/03—Rev. C to Rev. D
Updated TPCs.....................................................................Universal
Changes to Features .........................................................................1
Changes to Electrical Specifications ..............................................2
Change to Absolute Maximum Ratings ........................................4
Changes to Ordering Guide.............................................................4
Deleted Typical Electrical Characteristics table ........................... 4
Deleted Wafer Test Limits ................................................................4
Deleted Figure 1.................................................................................4
10/02—Rev. B to Rev. C
Changes to Features ..........................................................................1
Changes to General Description .....................................................1
Changes to Simplified Schematic ....................................................1
Changes to Specifications.................................................................2
Changes to Absolute Maximum Ratings .......................................5
Changes to Package Type ................................................................5
Changes to Ordering Guide.............................................................5
Updated to Outline Dimensions .................................................. 11
REF02
Rev. I | Page 3 of 16
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
@ VIN = 15 V, TA = 25°C, unless otherwise noted.
Table 1.
REF02A/REF02E REF02/REF02H
Parameter Symbol Conditions Min Typ Max Min Typ Max Unit
Output Voltage VO IL = 0 mA 4.985 5.000 5.015 4.975 5.000 5.025 V
Output Adjustment Range ∆VTRIM RP = 10 kΩ ±3 ±6 ±3 ±6 %
Output Voltage Noise1 en p-p 0.1 Hz to 10 Hz
P, Z, and S Packages 15 15 µV p-p
J Package 20 20 µV p-p
883 Parts 10 15 10 15 µV p-p
Line Regulation2 V
IN = 8 V to 40 V 0.006 0.010 0.006 0.010 %/V
Load Regulation2 I
L = 0 mA to 10 mA 0.005 0.010 0.006 0.010 %/mA
Turn-On Settling Time1 t
ON To ±0.1% of final value 5 5 µs
Quiescent Supply Current ISY No load 1.0 1.4 1.0 1.4 mA
Load Current IL 10 10 mA
Sink Current3 IS −0.3 –0.5 –0.3 –0.5 mA
Short-Circuit Current ISC VO = 0 30 30 mA
Temperature Voltage Output4
883C Product VT 630 630 mV
P, S, J, and Z Packages VT 550 550 mV
1 Guaranteed by design.
2 Line and load regulation specifications include the effect of self-heating.
3 During sink current test, the device meets the output voltage specified.
4 Limit current in or out of Pin 3 to 50 nA and capacitance on Pin 3 to 30 pF.
REF02
Rev. I | Page 4 of 16
@ VIN = 15 V, −55°C ≤ TA ≤ +125°C for REF02A and REF02; 0°C ≤ TA ≤ 70°C for REF02E and REF02H; IL = 0 mA, unless otherwise
noted.
Table 2.
REF02A/REF02E REF02/REF02H
Parameter Symbol Conditions Min Typ Max Min Typ Max Unit
0°C ≤ TA ≤ 70°C 0.02 0.06 0.07 0.17 %
Output Voltage Change
with Temperature1, 2
∆VOT
−55°C ≤ TA ≤ +125°C 0.06 0.15 0.18 0.45 %
Output Voltage Temperature Coefficient3TCVO 3 8.5 10 25 ppm/°C
Change in VO Temperature Coefficient
with Output Adjustment
R
P = 10 kΩ 0.7 0.7 ppm/%
0°C ≤ TA ≤ 70°C 0.007 0.012 0.007 0.012 %/V
Line Regulation
VIN = 8 V to 40 V4
−55°C ≤ TA ≤ +125°C
0.009 0.015
0.009 0.015 %/V
0°C ≤ TA ≤ 70°C 0.006 0.010 0.007 0.012 %/mA
Load Regulation
IL = 0 mA to 8 mA4
−55°C ≤ TA ≤ +125°C
0.007 0.012
0.009 0.015 %/mA
TCVT
2.10 2.10 mV/°C
Temperature Voltage Output Temperature
Coefficient5
883C Product
P, S, J, and Z Packages 1.96 1.96 mV/°C
1 ΔVOT is defined as the absolute difference between the maximum output voltage and the minimum output voltage over the specified temperature range expressed
as a percentage of 5 V.
100
V5 ×
−
=∆ MINMAX
OT VV
V
2 ∆VOT specification applies trimmed to 5,000 V or untrimmed.
3 TCVO is defined as ∆VOT divided by the temperature range.
C70°
∆
=OT
OV
TCV
4 Line and load regulation specifications include the effect of self-heating.
5 Limit current in or out of Pin 3 to 50 nA and capacitance on Pin 3 to 30 pF.
REF02
Rev. I | Page 5 of 16
@ VIN = 15 V, TA = 25°C, unless otherwise noted.
Table 3.
REF02C REF02D
Parameter Symbol Conditions Min Typ Max Min Typ Max
Unit
Output Voltage VO IL = 0 mA 4.950 5.000 5.050 4.900 5.000 5.100 V
Output Adjustment Range ∆VTRIM RP = 10 kΩ ±2.7 ±6.0 ±2.0 ±6.0 %
Output Voltage Noise1 en p-p 0.1 Hz to 10 Hz
P, Z, and S Packages 15 µV p-p
J Package 20 15 µV p-p
883 Parts 12 18 20 µV p-p
Line Regulation2 V
IN = 8 V to 40 V 0.009 0.015 0.010 0.04 %/V
IL = 0 mA to 8 mA 0.006 0.015 %/mA Load Regulation2
IL = 0 mA to 4 mA 0.015 0.04 %/mA
Turn-On Settling Time1 t
ON To ±0.1% of final value 5 5 µs
Quiescent Supply Current ISY No load 1.0 1.6 1.0 2.0 mA
Load Current IL 8 8 mA
Sink Current3 IS −0.3 −0.5 −0.3 −0.5 mA
Short-Circuit Current ISC VO = 0 30 30 mA
Temperature Voltage Output4
883C Product VT 630 630 mV
P, S, J, and Z Packages VT
550 550 mV
1 Guaranteed by design.
2 Line and load regulation specifications include the effect of self-heating.
3 During sink current test, the device meets the output voltage specified.
4 Limit current in or out of Pin 3 to 50 nA and capacitance on Pin 3 to 30 pF.
REF02
Rev. I | Page 6 of 16
@ VIN = 15 V, IL = 0 mA, 0°C ≤ TA ≤ 70°C for REF02CJ, REF02CZ, and REF02DP; and −40°C ≤ TA ≤ +85°C for REF02CP and REF02CS,
unless otherwise noted.
Table 4.
REF02C REF02D
Parameter Symbol Conditions Min Typ Max Min Typ Max Unit
Output Voltage Change
with Temperature1, 2
∆VOT 0.14 0.45 0.49 1.7 %
Output Voltage Temperature Coefficient3 TCVO 20 65 70 250 ppm/°C
Change in VO Temperature Coefficient
with Output Adjustment
R
P = 10 kΩ 0.7 0.7 ppm/%
Line Regulation4 VIN = 8 V to 40 V 0.011 0.018 0.012 0.05 %/V
Load Regulation4 I
L = 0 mA to 5 mA 0.008 0.018 0.016 0.05 %/mA
Temperature Voltage Output
Temperature Coefficient5 TCVT
883C Product 2.10 2.10 mV/°C
P, S, J, and Z Packages 1.96 1.96 mV/°C
1 ΔVOT is defined as the absolute difference between the maximum output voltage and the minimum output voltage over the specified temperature range expressed
as a percentage of 5 V.
100
V5 ×
−
=∆ MINMAX
OT VV
V
2 ∆VOT specification applies trimmed to 5,000 V or untrimmed.
3 TCVO is defined as ΔVOT divided by the temperature range.
C70°
∆
=OT
OV
TCV
4 Line and load regulation specifications include the effect of self-heating.
5 Limit current in or out of Pin 3 to 50 nA and capacitance on Pin 3 to 30 pF.
REF02
Rev. I | Page 7 of 16
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter Rating1
Input Voltage 40 V
Output Short-Circuit Duration
to Ground or VIN
Indefinite
Storage Temperature Range
J, RC, and Z Packages –65°C to +150°C
P Package –65°C to +125°C
Operating Temperature Range
REF02A, REF02J, REF02RC –55°C to +125°C
REF02CJ, REF02CZ 0°C to 70°C
REF02CP, REF02CS, REF02E, and REF02H –40°C to +85°C
Lead Temperature Range (Soldering 10 sec) 300°C
1 Absolute maximum ratings apply to both DICE packaged parts, unless
otherwise noted.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
Table 6.
Package Type θJA1θJC Unit
TO-99 (J) 170 24 °C/W
8-Lead CERDIP (Z) 162 26 °C/W
8-Lead PDIP (P) 110 50 °C/W
20-Terminal Ceramic LCC (RC) 120 40 °C/W
8-Lead SOIC (S) 160 44 °C/W
1 θJA is specified for worst-case mounting conditions; device in socket for TO,
CERDIP, PDIP, and LCC packages; and device soldered to printed circuit
board for SOIC package.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
REF02
Rev. I | Page 8 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
10k
1k
100
1010 100 1k 10k 100k 1M
00375-F-005
FREQUENCY (Hz)
OUTPUT NOISE (µV p-p)
V
IN
= 15V
T
A
= 25°C
Figure 5. Output Wideband Noise vs. Bandwidth
(0.1 Hz to Frequency Indicated)
76
0
16
26
36
46
56
66
10 100 1k 10k 100k 1M
00375-F-006
FREQUENCY (Hz)
LINE REGULATION (dB)
LINE REGULATION (%/V)
VIN = 15V
TA = 25°C
0.0031
0.0100
0.0310
0.1000
0.3100
1.0000
3.1000
10.0000
Figure 6. Line Regulation vs. Frequency
0.016
0.014
0.012
0.010
0.008
0.006
0.004
0.002
0
–10 0 10 20 30 40 50
00375-F-007
TIME (s)
PERCENT CHANGE IN OUTPUT VOLTAGE (%)
V
IN
= 15V
25°CDEVICE IMMERSED
IN 75°C OIL BATH
Figure 7. Output Change Due to Thermal Shock
20
19
18
17
16
15
1410 15 20 25 30 35 40
00375-F-008
INPUT VOLTAGE (V)
MAXIMUM LOAD CURRENT (mA)
T
A
= 25°C
Figure 8. Maximum Load Current vs. Input Voltage
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
–60 –40 –20 0 20 40 60 80 100 120 140
00375-F-009
TEMPERATURE (°C)
LOAD REG–T/LOAD REG (25°C)
V
IN
= 15V
Figure 9. Normalized Load Regulation (∆IL = 10 mA) vs. Temperature
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
–60 –40 –20 0 20 40 60 80 100 120 140
00375-F-010
TEMPERATURE (°C)
LINE REG–T/LINE REG (25°C)
Figure 10. Normalized Line Regulation vs. Temperature
REF02
Rev. I | Page 9 of 16
0
0.03
0.02
0.01
05 101520253
00375-F-011
INPUT VOLTAGE (V)
LINE REGULATION (%/V)
T
A
= 25°C
Figure 11. Line Regulation vs. Input Voltage
1.3
1.2
1.1
1.0
0.9
0.8
0.7
–60 –40 –20 0 20 40 60 80 100 120 140
00375-F-026
TEMPERATURE (°C)
QUIESCENT CURRENT (mA)
V
IN
= 15V
Figure 12. Quiescent Current vs. Temperature
30
25
20
15
10
5
0
–60 –40 –20 0 20 40 60 80 100 120 140
00375-F-012
TEMPERATURE (°C)
MAXIMUM LOAD CURRENT (mA)
V
IN
= 15V
Figure 13. Maximum Load Current vs. Temperature
REF02
Rev. I | Page 10 of 16
OUTPUT ADJUSTMENT
The REF02 trim terminal can be used to adjust the output
voltage over a 5 V ± 300 mV range. This feature lets the system
designer trim system errors by setting the reference to a voltage
other than 5 V. The output also can be set to exactly 5.00 V or to
5.12 V for binary applications.
Adjustment of the output does not significantly affect the
temperature performance of the device. The temperature
coefficient change is approximately 0.7 ppm/°C for 100 mV of
output adjustment.
U1
REF02
V
IN
V
OUT
TEMP TRIM
GND
V
IN
V
O
pot
10kΩ
R2
1kΩ
R1
470kΩ
00375-027
Figure 14. Output Adjustment Circuit
00375-F-014
V
IN
GND
–18V
+18V
4
2
REF02
Figure 15. Burn-In Circuit
00375-F-015
V
IN
GND
REF02
V
O
TRIMTEMP
0.1µF
5kΩ
OP02
10kΩ
10kΩ
+15V
–15V
+15V
+5V
–5V
4
53
6
2
Figure 16. ±5 V Reference
00375-F-016
REF02
R1
5.6kΩ
R2
5.6kΩ2
+5V
4
6
2
OP02
–
+3
4
6
7
–9V
V
REF
V
O
+
+2.5V
+V
O
–2.5V
V
O
+ = (V
REF
),
R1
R1 + R2 V
O
– = (V
REF
)
R2
R1 + R2
Figure 17. ±2.5 V Reference
REF02
Rev. I | Page 11 of 16
TEMPERATURE MONITORING
The REF02 provides a TEMP output (Pin 3) that varies linearly
with temperature. This output can be used to monitor the
temperature change in the system. The voltage at VTEMP is
approximately 550 mV at 25°C, and the temperature coefficient
is approximately 1.96 mV/°C (see Figure 18).
850
800
750
700
650
600
550
500
450
400
–50 –25 0 25 50 75 100 125
00375-F-017
TEMPERATURE (°C)
TEMP PIN OUTPUT (mV)
∆
V
TEMP
/
∆
T = 1.96mV/°C
V
IN
= 9V
SAMPLE SIZE = 6
J, S, AND P PACKAGES
Z PACKAGE AND 833 PRODUCT
∆
V
TEMP
/
∆
T = 2.1mV/°C
Figure 18. Voltage at TEMP Pin vs. Temperature
A voltage change of 39.2 mV at the TEMP pin corresponds to a
20°C change in temperature.
The TEMP function is provided as a convenience rather than a
precise feature. Since the voltage at the TEMP node is acquired
from the band gap core, current pulling from this pin has a
significant effect on VOUT. Care must be taken to buffer the
TEMP output with a suitable low bias current op amp, such as
the AD8601, AD820, or OP1177. Using any of these three op
amps results in less than a 100 µV change in ΔVOUT (see
Figure 19). Without buffering, even tens of microamps drawn
from the TEMP pin can cause VOUT to fall out of specification.
00375-F-018
TEMP TRIM
GND
U1
OP1177
V+
V–
15V
U2
V
O
V
OUT
V
IN
V
TEMP
1.9mV/°C
V
IN
REF02
Figure 19. Temperature Monitoring
00375-F-019
GND
REF02
4
6
2
TEMP 3
CMP02
2
3
8
4
R6
1
7
R7
27kΩ
R1
(9.2kΩ)
R3
(1.3kΩ)
R2
1.5kΩ
R4
2.7kΩ
R5
2.2kΩ
V+ V–
–
+
HEATING
ELEMENT
V+ (12V TO 32V)
VIN VO
(SEE NOTE 1)
NOTES
1. REF02 SHOULD BE THERMALLY CONNECTED
TO SUBSTANCE BEING HEATED.
2. NUMBERS IN PARENTHESES ARE FOR A
SETPOINT TEMPERATURE OF 60°C.
3. R3 = R1 || R2 || R6
Figure 20. Temperature Controller
REFERENCE STACK WITH EXCELLENT LINE
REGULATION
Two REF01s and one REF02 can be stacked to yield 5.00 V,
15.00 V, and 25.00 V outputs. An additional advantage is near-
perfect line regulation of the 5.0 V and 15.0 V output. A 27 V to
55 V input change produces an output change that is less than
the noise voltage of the devices. A load bypass resistor (RB)
provides a path for the supply current (ISY) of the 15.00 V
regulator.
In general, any number of REF01s and REF02s can be stacked
this way. For example, 10 devices yield 10 outputs in 5 V or 10 V
steps. The line voltage can change from 100 V to 130 V. Care
must be taken, however, to ensure that the total load currents
do not exceed the maximum usable current (typically 21 mA).
00375-F-020
GND
REF02
GND
REF02
GND
REF02
TRIM
TRIM
10kΩ
10kΩ
R
B
6.8kΩ
10kΩ
2
6
5
4
2
6
5
4
2
6
5
4
15V
10V
5V
TRIM
27V TO 55V
V
IN
V
O
V
IN
V
O
V
IN
V
O
Figure 21. Reference Stack
REF02
Rev. I | Page 12 of 16
PRECISION CURRENT SOURCE
A current source with 35 V output compliance and excellent
output impedance can be obtained using this circuit. REF02
keeps the line voltage and power dissipation constant in the
device; the only important error consideration at room
temperature is the negative supply rejection of the op amp. The
typical 3 µV/V PSRR of the OP02E creates a 20 ppm change
(3 µV/V × 35 V/5 V) in output current over a 25 V range. For
example, a 5 mA current source can be built (R = 1 kΩ) with
350 MΩ output impedance.
00375-F-021
GND
REF02
GND
REF02
OP02E
C
C
R
2
2
2
6
6
7
3
4
6
4
4
+50V
–5V I
O
=5V
R
R
O
=35V
20
×
10
–6
×
5mA
R
(TRIM FOR
CALIBRATION)
V
IN
V
O
V
IN
V
O
V
O
= 0V
TO 25V
1
2
Figure 22. Precision Current Source
00375-F-022
V
IN
GND
TRIM
V
O
REF02
2
6
5
4
R
TEMP
3
15V
I
OUT
I
OUT
= + 5V
R+ 1mA
VOLTAGE COMPLIANCE: –25V TO +8V
Figure 23. Current Source
SUPPLY BYPASSING
For best results, it is recommended that the power supply pin be
bypassed with a 0.1 µF disc ceramic capacitor.
00375-F-023
V
IN
GND
TRIM
V
O
REF02
2
6
5
4
R
TEMP
3
–15V
I
OUT
I
OUT
= + 5V
R+ 1mA
VOLTAGE COMPLIANCE: –9V TO +25V
Figure 24. Current Sink
00375-F-024
REF02
DAC08 OP02
0.1µF
+15V
4
6
5
5kΩ
5kΩ
5kΩ
5kΩ
+15V –15V –15V
+15V
E
O
LSB
MSB
2B1 B2 B3 B4 B5 B6 B7 B8
V+ V– C
C
V
LC
2
4
V
IN
V
O
GND
l
O
l
O
Figure 25. DAC Reference
00375-F-025
GND
REF02HJ
2
6
4
A1
–7.5V
+7.5V
A2
–7.5V
1/2 OP04CK
1/2 OP04CK
–7.5V (±10%)
+7.5V (±10%)
R3
1kΩ
R1
20kΩ
R2
13.3kΩ
V
O
(–) = –3V
V
O
(+) = +3V
R4
2kΩ
V
IN
V
O
Figure 26. ±3 V Reference
REF02
Rev. I | Page 13 of 16
OUTLINE DIMENSIONS
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
0.310 (7.87)
0.220 (5.59)
0.005 (0.13)
MIN 0.055 (1.40)
MAX
0.100 (2.54) BSC
15°
0°
0.320 (8.13)
0.290 (7.37)
0.015 (0.38)
0.008 (0.20)
SEATING
PLANE
0.200 (5.08)
MAX
0.405 (10.29) MAX
0.150 (3.81)
MIN
0.200 (5.08)
0.125 (3.18)
0.023 (0.58)
0.014 (0.36) 0.070 (1.78)
0.030 (0.76)
0.060 (1.52)
0.015 (0.38)
14
58
Figure 27. 8-Lead Ceramic Dual In-Line Package [CERDIP]
Z-Suffix
(Q-8)
Dimensions shown in inches and (millimeters)
COMPLIANT TO JEDEC STANDARDS MS-001-BA
0.022 (0.56)
0.018 (0.46)
0.014 (0.36)
SEATING
PLANE
0.015
(0.38)
MIN
0.210
(5.33)
MAX
PIN 1
0.150 (3.81)
0.130 (3.30)
0.115 (2.92)
0.070 (1.78)
0.060 (1.52)
0.045 (1.14)
8
14
5
0.280 (7.11)
0.250 (6.35)
0.240 (6.10)
0.100 (2.54)
BSC
0.400 (10.16)
0.365 (9.27)
0.355 (9.02)
0.060 (1.52)
MAX
0.430 (10.92)
MAX
0.014 (0.36)
0.010 (0.25)
0.008 (0.20)
0.325 (8.26)
0.310 (7.87)
0.300 (7.62)
0.195 (4.95)
0.130 (3.30)
0.115 (2.92)
0.015 (0.38)
GAUGE
PLANE
0.005 (0.13)
MIN
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
CORNER LEADS MAY BE CONFIGURED AS WHOLE OR HALF LEADS.
Figure 28. 8-Lead Plastic Dual In-Line Package [PDIP]
Narrow Body
P-Suffix
(N-8)
Dimensions shown in inches and (millimeters)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MO-002-AK
0.2500 (6.35) MIN
0.5000 (12.70)
MIN
0.1850 (4.70)
0.1650 (4.19)
REFERENCE PLANE
0.0500 (1.27) MAX
0.0190 (0.48)
0.0160 (0.41)
0.0210 (0.53)
0.0160 (0.41)
0.0400 (1.02)
0.0100 (0.25)
0.0400 (1.02) MAX 0.0340 (0.86)
0.0280 (0.71)
0.0450 (1.14)
0.0270 (0.69)
0.1600 (4.06)
0.1400 (3.56)
0.1000 (2.54)
BSC
6
28
7
5
4
3
1
0.2000
(5.08)
BSC
0.1000
(2.54)
BSC
0.3700 (9.40)
0.3350 (8.51)
0.3350 (8.51)
0.3050 (7.75)
45° BSC
BASE & SEATING PLANE
Figure 29. 8-Lead Metal Header Package [TO-99]
J-Suffix
(H-08)
Dimensions shown in inches and (millimeters)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
1
20 4
9
8
13
19
14
3
18
BOTTOM
VIEW
0.028 (0.71)
0.022 (0.56)
45° TYP
0.015 (0.38)
MIN
0.055 (1.40)
0.045 (1.14)
0.050 (1.27)
BSC
0.075 (1.91)
REF
0.011 (0.28)
0.007 (0.18)
R TYP
0.095 (2.41)
0.075 (1.90)
0.100 (2.54) REF
0.200 (5.08)
REF
0.150 (3.81)
BSC
0.075 (1.91)
REF
0.358 (9.09)
0.342 (8.69)
SQ
0.358
(9.09)
MAX
SQ
0.100 (2.54)
0.064 (1.63)
0.088 (2.24)
0.054 (1.37)
Figure 30. 20-Terminal Ceramic Leadless Chip Carrier [LCC]
RC-Suffix
(E-20A)
Dimensions shown in inches and (millimeters)
REF02
Rev. I | Page 14 of 16
0.25 (0.0098)
0.17 (0.0067)
1.27 (0.0500)
0.40 (0.0157)
0.50 (0.0196)
0.25 (0.0099)× 45°
8°
0°
1.75 (0.0688)
1.35 (0.0532)
SEATING
PLANE
0.25 (0.0098)
0.10 (0.0040)
41
85
5.00 (0.1968)
4.80 (0.1890)
4.00 (0.1574)
3.80 (0.1497)
1.27 (0.0500)
BSC
6.20 (0.2440)
5.80 (0.2284)
0.51 (0.0201)
0.31 (0.0122)
COPLANARITY
0.10
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN.
COMPLIANT TO JEDEC STANDARDS MS-012-AA
Figure 31. 8-Lead Standard Small Outline Package [SOIC]
Narrow Body
S-Suffix
(R-8)
Dimensions shown in millimeters and (inches)
REF02
Rev. I | Page 15 of 16
ORDERING GUIDE
Model
TA = 25°C
∆VOS Max (mV) Temperature Range Package Description Package Option
REF02AJ/883C1 ±15 −55°C to +125°C 8-Lead TO-99 J-Suffix (H-08)
REF02AZ ±15 −55°C to +125°C 8-Lead CERDIP Z-Suffix (Q-8)
REF02AZ/883C1 ±15 −55°C to +125°C 8-Lead CERDIP Z-Suffix (Q-8)
REF02CJ ±50 0°C to 70°C 8-Lead TO-99 J-Suffix (H-08)
REF02CP ±50 −40°C to +85°C 8-Lead PDIP P-Suffix (N-8)
REF02CPZ2±50 −40°C to +85°C 8-Lead PDIP P-Suffix (N-8)
REF02CS ±50 −40°C to +85°C 8-Lead SOIC S-Suffix (R-8)
REF02CS-REEL ±50 −40°C to +85°C 8-Lead SOIC S-Suffix (R-8)
REF02CS-REEL7 ±50 −40°C to +85°C 8-Lead SOIC S-Suffix (R-8)
REF02CSZ2 ±50 −40°C to +85°C 8-Lead SOIC S-Suffix (R-8)
REF02CSZ-REEL2 ±50 −40°C to +85°C 8-Lead SOIC S-Suffix (R-8)
REF02CSZ-REEL72 ±50 −40°C to +85°C 8-Lead SOIC S-Suffix (R-8)
REF02CZ ±50 0°C to 70°C 8-Lead CERDIP Z-Suffix (Q-8)
REF02DP ±100 0°C to 70°C 8-Lead PDIP P-Suffix (N-8)
REF02DPZ2 ±100 0°C to 70°C 8-Lead PDIP P-Suffix (N-8)
REF02EJ ±15 −40°C to +85°C 8-Lead TO-99 J-Suffix (H-08)
REF02EZ ±15 −40°C to +85°C 8-Lead CERDIP Z-Suffix (Q-8)
REF02J ±25 −55°C to +125°C 8-Lead TO-99 J-Suffix (H-08)
REF02HJ ±25 −40°C to +85°C 8-Lead TO-99 J-Suffix (H-08)
REF02HZ ±25 −40°C to +85°C 8-Lead CERDIP Z-Suffix (Q-8)
REF02HP ±25 −40°C to +85°C 8-Lead PDIP P-Suffix (N-8)
REF02HPZ2 ±25 −40°C to +85°C 8-Lead PDIP P-Suffix (N-8)
REF02HS ±25 −40°C to +85°C 8-Lead SOIC S-Suffix (R-8)
REF02HSZ2 ±25 −40°C to +85°C 8-Lead SOIC S-Suffix (R-8)
REF02RC/8831 ±25 −55°C to +125°C 20-Lead LCC RC-Suffix (E-20A)
REF02Z ±25 −55°C to +125°C 8-Lead CERDIP Z-Suffix (Q-8)
1 Consult sales for 883 data sheet.
2 Z = Pb-free part.
REF02
Rev. I | Page 16 of 16
NOTES
© 2005 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
C00375-0-12/05(I)
