MSP430G2x33 MSP430G2x03 SLAS734D - APRIL 2011 - REVISED NOVEMBER 2011 www.ti.com MIXED SIGNAL MICROCONTROLLER FEATURES 1 * * * * * * * * Low Supply-Voltage Range: 1.8 V to 3.6 V Ultra-Low Power Consumption - Active Mode: 230 A at 1 MHz, 2.2 V - Standby Mode: 0.5 A - Off Mode (RAM Retention): 0.1 A Five Power-Saving Modes Ultra-Fast Wake-Up From Standby Mode in Less Than 1 s 16-Bit RISC Architecture, 62.5-ns Instruction Cycle Time Basic Clock Module Configurations - Internal Frequencies up to 16 MHz With Four Calibrated Frequency - Internal Very-Low-Power Low-Frequency (LF) Oscillator - 32-kHz Crystal - External Digital Clock Source Two 16-Bit Timer_A With Three Capture/Compare Registers Up to 24 Touch-Sense-Enabled I/O Pins * * * * * * * * Universal Serial Communication Interface (USCI) - Enhanced UART Supporting Auto Baudrate Detection (LIN) - IrDA Encoder and Decoder - Synchronous SPI - I2CTM 10-Bit 200-ksps Analog-to-Digital (A/D) Converter With Internal Reference, Sample-and-Hold, and Autoscan (See Table 1) Brownout Detector Serial Onboard Programming, No External Programming Voltage Needed, Programmable Code Protection by Security Fuse On-Chip Emulation Logic With Spy-Bi-Wire Interface Family Members are Summarized in Table 1 Package Options - TSSOP: 20 Pin, 28 Pin - PDIP: 20 Pin - QFN: 32 Pin For Complete Module Descriptions, See the MSP430x2xx Family User's Guide (SLAU144) DESCRIPTION The Texas Instruments MSP430 family of ultra-low-power microcontrollers consists of several devices featuring different sets of peripherals targeted for various applications. The architecture, combined with five low-power modes, is optimized to achieve extended battery life in portable measurement applications. The device features a powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency. The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1 s. The MSP430G2x03 and MSP430G2x33 series are ultra-low-power mixed signal microcontrollers with built-in 16-bit timers, up to 24 I/O touch-sense-enabled pins, and built-in communication capability using the universal serial communication interface. In addition, the MSP430G2x33 family members have a 10-bit A/D converter. For configuration details see Table 1. Typical applications include low-cost sensor systems that capture analog signals, convert them to digital values, and then process the data for display or for transmission to a host system. 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2011, Texas Instruments Incorporated MSP430G2x33 MSP430G2x03 SLAS734D - APRIL 2011 - REVISED NOVEMBER 2011 www.ti.com Table 1. Available Options (1) (2) Device BSL EEM Flash (KB) RAM (B) Timer_A ADC10 Channel USCI A0/B0 Clock 1 LF, DCO, VLO MSP430G2533IRHB32 MSP430G2533IPW28 MSP430G2533IPW20 1 1 16 512 2x TA3 8 MSP430G2533IN20 MSP430G2433IRHB32 I/O Package Type 24 32-QFN 24 28-TSSOP 16 20-TSSOP 16 20-PDIP 24 32-QFN 24 28-TSSOP 16 20-TSSOP MSP430G2433IN20 16 20-PDIP MSP430G2333IRHB32 24 32-QFN 24 28-TSSOP 16 20-TSSOP MSP430G2333IN20 16 20-PDIP MSP430G2233IRHB32 24 32-QFN 24 28-TSSOP MSP430G2433IPW28 MSP430G2433IPW20 MSP430G2333IPW28 MSP430G2333IPW20 MSP430G2233IPW28 MSP430G2233IPW20 1 1 1 1 1 1 8 4 2 512 256 256 2x TA3 2x TA3 2x TA3 8 8 8 1 1 1 LF, DCO, VLO LF, DCO, VLO LF, DCO, VLO 16 20-TSSOP MSP430G2233IN20 16 20-PDIP MSP430G2403IRHB32 24 32-QFN 24 28-TSSOP 16 20-TSSOP MSP430G2403IN20 16 20-PDIP MSP430G2303IRHB32 24 32-QFN 24 28-TSSOP 16 20-TSSOP 16 20-PDIP MSP430G2403IPW28 MSP430G2403IPW20 MSP430G2303IPW28 MSP430G2303IPW20 1 1 1 1 8 4 512 256 2x TA3 2x TA3 - - 1 1 LF, DCO, VLO LF, DCO, VLO MSP430G2303IN20 MSP430G2203IRHB32 MSP430G2203IPW28 MSP430G2203IPW20 1 MSP430G2203IN20 (1) (2) 2 1 2 256 2x TA3 - 1 LF, DCO, VLO 24 32-QFN 24 28-TSSOP 16 20-TSSOP 16 20-PDIP For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated MSP430G2x33 MSP430G2x03 SLAS734D - APRIL 2011 - REVISED NOVEMBER 2011 www.ti.com Device Pinout, MSP430G2x03 and MSP430G2x33, 20-Pin Devices, TSSOP and PDIP DVCC P1.0/TA0CLK/ACLK/A0 P1.1/TA0.0/UCA0RXD/UCA0SOMI/A1 P1.2/TA0.1/UCA0TXD/PUCA0SIMO/A2 P1.3/ADC10CLK/VREF-/VEREF-/A3 P1.4/SMCLK/UCB0STE/UCA0CLK/VREF+/VEREF+/A4/TCK P1.5/TA0.0/UCB0CLK/UCA0STE/A5/TMS P2.0/TA1.0 P2.1/TA1.1 P2.2/TA1.1 1 20 2 19 3 18 4 5 6 17 N20 PW20 (TOP VIEW) 16 15 7 14 8 13 9 12 10 11 DVSS XIN/P2.6/TA0.1 XOUT/P2.7 TEST/SBWTCK RST/NMI/SBWTDIO P1.7/UCB0SIMO/UCB0SDA/A7/TDO/TDI P1.6/TA0.1/UCB0SOMI/UCB0SCL/A6/TDI/TCLK P2.5/TA1.2 P2.4/TA1.2 P2.3/TA1.0 NOTE: ADC10 is available on MSP430G2x33 devices only. NOTE: The pulldown resistors of port P3 should be enabled by setting P3REN.x = 1. Device Pinout, MSP430G2x03 and MSP430G2x33, 28-Pin Devices, TSSOP DVCC P1.0/TA0CLK/ACLK/A0 P1.1/TA0.0/UCA0RXD/UCA0SOMI/A1 P1.2/TA0.1/UCA0TXD/PUCA0SIMO/A2 P1.3/ADC10CLK/VREF-/VEREF-/A3 P1.4/SMCLK/UCB0STE/UCA0CLK/VREF+/VEREF+/A4/TCK P1.5/TA0.0/UCB0CLK/UCA0STE/A5/TMS P3.1/TA1.0 P3.0/TA0.2 P2.0/TA1.0 P2.1/TA1.1 P2.2/TA1.1 P3.2/TA1.1 P3.3/TA1.2 1 28 2 27 3 26 4 25 5 24 6 7 8 23 PW28 (TOP VIEW) 22 21 9 20 10 19 11 18 12 17 13 16 14 15 DVSS XIN/P2.6/TA0.1 XOUT/P2.7 TEST/SBWTCK RST/NMI/SBWTDIO P1.7/UCB0SIMO/UCB0SDA/A7/TDO/TDI P1.6/TA0.1/UCB0SOMI/UCB0SCL/A6/TDI/TCLK P3.7/TA1CLK P3.6/TA0.2 P3.5/TA0.1 P2.5/TA1.2 P2.4/TA1.2 P2.3/TA1.0 P3.4/TA0.0 NOTE: ADC10 is available on MSP430G2x33 devices only. Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback 3 MSP430G2x33 MSP430G2x03 SLAS734D - APRIL 2011 - REVISED NOVEMBER 2011 www.ti.com NC P1.0/TA0CLK/ACLK/A0/CA0 DVCC AVCC DVSS AVSS XIN/P2.6/TA0.1 XOUT/P2.7 Device Pinout, MSP430G2x03 and MSP430G2x33, 32-Pin Devices, QFN 32 31 30 29 28 27 26 25 P1.1/TA0.0/UCA0RXD/UCA0SOMI/A1 P1.2/TA0.1/UCA0TXD/UCA0SIMO/A2 P1.3/ADC10CLK/VREF-/VEREF-/A3 P1.4/SMCLK/UCB0STE/UCA0CLK/VREF+/VEREF+/A4/TCK P1.5/TA0.0/UCB0CLK/UCA0STE/A5/TMS P3.1/TA1.0 P3.0/TA0.2 NC 1 24 2 23 3 4 5 22 RHB32 (TOP VIEW) 21 20 6 19 7 18 8 17 TEST/SBWTCK RST/NMI/SBWTDIO P1.7/UCB0SIMO/UCB0SDA/A7/TDO/TDI P1.6/TA0.1/UCB0SOMI/UCB0SCL/A6/TDI/TCLK P3.7/TA1CLK P3.6/TA0.2 P3.5/TA0.1 P2.5/TA1.2 P2.0/TA1.0 P2.1/TA1.1 P2.2/TA1.1 P3.2/TA1.1 P3.3/TA1.2 P3.4/TA0.0 P2.3/TA1.0 P2.4/TA1.2 9 10 11 12 13 14 15 16 NOTE: ADC10 is available on MSP430G2x33 devices only. 4 Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated MSP430G2x33 MSP430G2x03 SLAS734D - APRIL 2011 - REVISED NOVEMBER 2011 www.ti.com Functional Block Diagram, MSP430G2x33 XIN XOUT DVCC DVSS P1.x 8 P2.x 8 P3.x 8 Port P1 Port P2 Port P3 8 I/O Interrupt capability pullup/down resistors 8 I/O Interrupt capability pullup/down resistors 8 I/O ACLK Clock System Flash SMCLK 16KB 8KB 4KB 2KB MCLK 16MHz CPU ADC RAM 512B 256B 10-Bit 8 Ch. Autoscan 1 ch DMA pullup pulldown resistors MAB MDB incl. 16 Registers Emulation 2BP Watchdog WDT+ Brownout Protection JTAG Interface 15-Bit Timer0_A3 Timer1_A3 3 CC Registers 3 CC Registers USCI A0 UART/ LIN, IrDA, SPI USCI B0 SPI, I2C Spy-BiWire RST/NMI NOTE: Port P3 is available on 28-pin and 32-pin devices only. Functional Block Diagram, MSP430G2x03 XIN XOUT DVCC DVSS P1.x 8 P2.x 8 P3.x 8 Port P1 Port P2 Port P3 8 I/O Interrupt capability pullup/down resistors 8 I/O Interrupt capability pullup/down resistors pullup/ pulldown resistors ACLK Clock System Flash SMCLK RAM 8KB 4KB 2KB MCLK 16MHz CPU incl. 16 Registers 256B MAB MDB Emulation 2BP JTAG Interface 8 I/O Brownout Protection Watchdog WDT+ 15-Bit Spy-BiWire Timer0_A3 Timer1_A3 3 CC Registers 3 CC Registers USCI A0 UART/ LIN, IrDA, SPI USCI B0 SPI, I2C RST/NMI NOTE: Port P3 is available on 28-pin and 32-pin devices only. Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback 5 MSP430G2x33 MSP430G2x03 SLAS734D - APRIL 2011 - REVISED NOVEMBER 2011 www.ti.com Table 2. Terminal Functions TERMINAL NO. NAME PW20, N20 PW28 I/O DESCRIPTION RHB32 P1.0/ General-purpose digital I/O pin TA0CLK/ ACLK/ 2 2 31 I/O Timer0_A, clock signal TACLK input ACLK signal output A0 ADC10 analog input A0 (1) P1.1/ General-purpose digital I/O pin TA0.0/ Timer0_A, capture: CCI0A input, compare: Out0 output / BSL transmit UCA0RXD/ 3 3 1 I/O USCI_A0 receive data input in UART mode UCA0SOMI/ USCI_A0 slave data out/master in SPI mode A1 ADC10 analog input A1 (1) P1.2/ General-purpose digital I/O pin TA0.1/ Timer0_A, capture: CCI1A input, compare: Out1 output UCA0TXD/ 4 4 2 I/O USCI_A0 transmit data output in UART mode UCA0SIMO/ USCI_A0 slave data in/master out in SPI mode A2 ADC10 analog input A2 (1) P1.3/ General-purpose digital I/O pin ADC10CLK/ A3/ 5 5 3 I/O ADC10, conversion clock output (1) ADC10 analog input A3 (1) VREF-/VEREF- ADC10 negative reference voltage P1.4/ General-purpose digital I/O pin SMCLK/ SMCLK signal output UCB0STE/ UCA0CLK/ (1) USCI_B0 slave transmit enable 6 6 4 I/O USCI_A0 clock input/output A4/ ADC10 analog input A4 (1) VREF+/VEREF+ ADC10 positive reference voltage (1) TCK JTAG test clock, input terminal for device programming and test P1.5/ General-purpose digital I/O pin TA0.0/ Timer0_A, compare: Out0 output / BSL receive UCB0CLK/ UCA0STE/ 7 7 5 I/O USCI_B0 clock input/output USCI_A0 slave transmit enable A5/ ADC10 analog input A5 (1) TMS JTAG test mode select, input terminal for device programming and test P1.6/ General-purpose digital I/O pin TA0.1/ Timer0_A, compare: Out1 output A6/ UCB0SOMI/ 14 22 21 I/O ADC10 analog input A6 (1) USCI_B0 slave out/master in SPI mode, UCB0SCL/ USCI_B0 SCL I2C clock in I2C mode TDI/TCLK JTAG test data input or test clock input during programming and test P1.7/ General-purpose digital I/O pin A7/ ADC10 analog input A7 (1) UCB0SIMO/ 15 23 22 I/O USCI_B0 slave in/master out in SPI mode UCB0SDA/ USCI_B0 SDA I2C data in I2C mode TDO/TDI JTAG test data output terminal or test data input during programming and test (2) (1) (2) 6 MSP430G2x33 devices only TDO or TDI is selected via JTAG instruction. Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated MSP430G2x33 MSP430G2x03 SLAS734D - APRIL 2011 - REVISED NOVEMBER 2011 www.ti.com Table 2. Terminal Functions (continued) TERMINAL NO. NAME P2.0/ TA1.0 P2.1/ TA1.1 P2.2/ TA1.1 P2.3/ TA1.0 P2.4/ TA1.2 P2.5/ TA1.2 I/O PW20, N20 PW28 RHB32 8 10 9 I/O 9 11 10 I/O 10 12 11 I/O 11 16 15 I/O 12 17 16 I/O 13 18 17 I/O 19 27 26 I/O XIN/ P2.6/ P2.7 P3.0/ TA0.2 P3.1/ TA1.0 P3.2/ TA1.1 P3.3/ TA1.2 P3.4/ TA0.0 P3.5/ TA0.1 P3.6/ TA0.2 P3.7/ TA1CLK Timer1_A, capture: CCI0A input, compare: Out0 output General-purpose digital I/O pin Timer1_A, capture: CCI1A input, compare: Out1 output General-purpose digital I/O pin Timer1_A, capture: CCI1B input, compare: Out1 output General-purpose digital I/O pin Timer1_A, capture: CCI0B input, compare: Out0 output General-purpose digital I/O pin Timer1_A, capture: CCI2A input, compare: Out2 output General-purpose digital I/O pin Timer1_A, capture: CCI2B input, compare: Out2 output General-purpose digital I/O pin Timer0_A, compare: Out1 output 18 26 25 I/O - 9 7 I/O - 8 6 I/O - 13 12 I/O - 14 13 I/O - 15 14 I/O - 19 18 I/O - 20 19 I/O - 21 20 I/O RST/ NMI/ General-purpose digital I/O pin Input terminal of crystal oscillator TA0.1 XOUT/ DESCRIPTION Output terminal of crystal oscillator (3) General-purpose digital I/O pin General-purpose digital I/O pin Timer0_A, capture: CCI2A input, compare: Out2 output General-purpose digital I/O pin Timer1_A, compare: Out0 output General-purpose digital I/O pin Timer1_A, compare: Out1 output General-purpose digital I/O Timer1_A, compare: Out2 output General-purpose digital I/O Timer0_A, compare: Out0 output General-purpose digital I/O Timer0_A, compare: Out1 output General-purpose digital I/O Timer0_A, compare: Out2 output General-purpose digital I/O Timer1_A, clock signal TACLK input Reset 16 24 23 I SBWTDIO Nonmaskable interrupt input Spy-Bi-Wire test data input/output during programming and test TEST/ Selects test mode for JTAG pins on Port 1. The device protection fuse is connected to TEST. 17 25 24 I AVCC NA NA 29 NA Analog supply voltage DVCC 1 1 30 NA Digital supply voltage SBWTCK Spy-Bi-Wire test clock input during programming and test DVSS 20 28 27, 28 NA Ground reference NC NA NA 8, 32 NA Not connected (3) If XOUT/P2.7 is used as an input, excess current will flow until P2SEL.7 is cleared. This is due to the oscillator output driver connection to this pad after reset. Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback 7 MSP430G2x33 MSP430G2x03 SLAS734D - APRIL 2011 - REVISED NOVEMBER 2011 www.ti.com Table 2. Terminal Functions (continued) TERMINAL NO. NAME QFN Pad 8 I/O PW20, N20 PW28 RHB32 NA NA Pad Submit Documentation Feedback NA DESCRIPTION QFN package pad connection to VSS recommended. Copyright (c) 2011, Texas Instruments Incorporated MSP430G2x33 MSP430G2x03 SLAS734D - APRIL 2011 - REVISED NOVEMBER 2011 www.ti.com SHORT-FORM DESCRIPTION CPU The MSP430 CPU has a 16-bit RISC architecture that is highly transparent to the application. All operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. Program Counter PC/R0 Stack Pointer SP/R1 Status Register SR/CG1/R2 Constant Generator The CPU is integrated with 16 registers that provide reduced instruction execution time. The register-to-register operation execution time is one cycle of the CPU clock. Four of the registers, R0 to R3, are dedicated as program counter, stack pointer, status register, and constant generator, respectively. The remaining registers are general-purpose registers. Peripherals are connected to the CPU using data, address, and control buses, and can be handled with all instructions. The instruction set consists of the original 51 instructions with three formats and seven address modes and additional instructions for the expanded address range. Each instruction can operate on word and byte data. Instruction Set The instruction set consists of 51 instructions with three formats and seven address modes. Each instruction can operate on word and byte data. Table 3 shows examples of the three types of instruction formats; Table 4 shows the address modes. CG2/R3 General-Purpose Register R4 General-Purpose Register R5 General-Purpose Register R6 General-Purpose Register R7 General-Purpose Register R8 General-Purpose Register R9 General-Purpose Register R10 General-Purpose Register R11 General-Purpose Register R12 General-Purpose Register R13 General-Purpose Register R14 General-Purpose Register R15 Table 3. Instruction Word Formats EXAMPLE OPERATION Dual operands, source-destination INSTRUCTION FORMAT ADD R4,R5 R4 + R5 ---> R5 Single operands, destination only CALL R8 PC -->(TOS), R8--> PC JNE Jump-on-equal bit = 0 Relative jump, un/conditional Table 4. Address Mode Descriptions (1) (1) ADDRESS MODE S D SYNTAX EXAMPLE OPERATION Register MOV Rs,Rd MOV R10,R11 R10 -- --> R11 Indexed MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5) -- --> M(6+R6) Symbolic (PC relative) MOV EDE,TONI M(EDE) -- --> M(TONI) Absolute MOV &MEM,&TCDAT M(MEM) -- --> M(TCDAT) Indirect MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) -- --> M(Tab+R6) Indirect autoincrement MOV @Rn+,Rm MOV @R10+,R11 M(R10) -- --> R11 R10 + 2-- --> R10 Immediate MOV #X,TONI MOV #45,TONI #45 -- --> M(TONI) S = source, D = destination Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback 9 MSP430G2x33 MSP430G2x03 SLAS734D - APRIL 2011 - REVISED NOVEMBER 2011 www.ti.com Operating Modes The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt event can wake up the device from any of the low-power modes, service the request, and restore back to the low-power mode on return from the interrupt program. The following six operating modes can be configured by software: * Active mode (AM) - All clocks are active * Low-power mode 0 (LPM0) - CPU is disabled - ACLK and SMCLK remain active, MCLK is disabled * Low-power mode 1 (LPM1) - CPU is disabled - ACLK and SMCLK remain active, MCLK is disabled - DCO's dc generator is disabled if DCO not used in active mode * Low-power mode 2 (LPM2) - CPU is disabled - MCLK and SMCLK are disabled - DCO's dc generator remains enabled - ACLK remains active * Low-power mode 3 (LPM3) - CPU is disabled - MCLK and SMCLK are disabled - DCO's dc generator is disabled - ACLK remains active * Low-power mode 4 (LPM4) - CPU is disabled - ACLK is disabled - MCLK and SMCLK are disabled - DCO's dc generator is disabled - Crystal oscillator is stopped 10 Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated MSP430G2x33 MSP430G2x03 SLAS734D - APRIL 2011 - REVISED NOVEMBER 2011 www.ti.com Interrupt Vector Addresses The interrupt vectors and the power-up starting address are located in the address range 0FFFFh to 0FFC0h. The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence. If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, flash is not programmed), the CPU goes into LPM4 immediately after power-up. Table 5. Interrupt Sources, Flags, and Vectors INTERRUPT SOURCE INTERRUPT FLAG Power-Up External Reset Watchdog Timer+ Flash key violation PC out-of-range (1) PORIFG RSTIFG WDTIFG KEYV (2) NMI Oscillator fault Flash memory access violation NMIIFG OFIFG ACCVIFG (2) (3) Timer1_A3 TACCR0 CCIFG (4) Timer1_A3 TACCR2 TACCR1 CCIFG, TAIFG Watchdog Timer+ Timer0_A3 (1) (2) (3) (4) (5) (6) (7) (8) (2) (4) WDTIFG TACCR0 CCIFG (4) SYSTEM INTERRUPT WORD ADDRESS PRIORITY Reset 0FFFEh 31, highest (non)-maskable (non)-maskable (non)-maskable 0FFFCh 30 maskable 0FFFAh 29 maskable 0FFF8h 28 0FFF6h 27 maskable 0FFF4h 26 maskable 0FFF2h 25 maskable 0FFF0h 24 maskable 0FFEEh 23 maskable 0FFECh 22 maskable 0FFEAh 21 Timer0_A3 TACCR2 TACCR1 CCIFG, TAIFG USCI_A0/USCI_B0 receive USCI_B0 I2C status UCA0RXIFG, UCB0RXIFG (2) (5) USCI_A0/USCI_B0 transmit USCI_B0 I2C receive/transmit UCA0TXIFG, UCB0TXIFG (2) (6) ADC10 (MSP430G2x33 only) ADC10IFG (4) 0FFE8h 20 I/O Port P2 (up to eight flags) P2IFG.0 to P2IFG.7 (2) (4) maskable 0FFE6h 19 I/O Port P1 (up to eight flags) (2) (4) maskable 0FFE4h 18 0FFE2h 17 0FFE0h 16 See (7) 0FFDEh 15 See (8) 0FFDEh to 0FFC0h 14 to 0, lowest (5) (4) P1IFG.0 to P1IFG.7 A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from within unused address ranges. Multiple source flags (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot. Interrupt flags are located in the module. In SPI mode: UCB0RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG. In UART/SPI mode: UCB0TXIFG. In I2C mode: UCB0RXIFG, UCB0TXIFG. This location is used as bootstrap loader security key (BSLSKEY). A 0xAA55 at this location disables the BSL completely. A zero (0h) disables the erasure of the flash if an invalid password is supplied. The interrupt vectors at addresses 0FFDEh to 0FFC0h are not used in this device and can be used for regular program code if necessary. Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback 11 MSP430G2x33 MSP430G2x03 SLAS734D - APRIL 2011 - REVISED NOVEMBER 2011 www.ti.com Special Function Registers (SFRs) Most interrupt and module enable bits are collected into the lowest address space. Special function register bits not allocated to a functional purpose are not physically present in the device. Simple software access is provided with this arrangement. Legend rw: rw-0,1: rw-(0,1): Bit can be read and written. Bit can be read and written. It is reset or set by PUC. Bit can be read and written. It is reset or set by POR. SFR bit is not present in device. Table 6. Interrupt Enable Register 1 and 2 Address 7 6 00h WDTIE OFIE NMIIE ACCVIE Address 5 4 1 0 ACCVIE NMIIE OFIE WDTIE rw-0 rw-0 rw-0 rw-0 2 Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer is configured in interval timer mode. Oscillator fault interrupt enable (Non)maskable interrupt enable Flash access violation interrupt enable 7 6 5 4 01h UCA0RXIE UCA0TXIE UCB0RXIE UCB0TXIE 3 3 2 1 0 UCB0TXIE UCB0RXIE UCA0TXIE UCA0RXIE rw-0 rw-0 rw-0 rw-0 USCI_A0 receive interrupt enable USCI_A0 transmit interrupt enable USCI_B0 receive interrupt enable USCI_B0 transmit interrupt enable Table 7. Interrupt Flag Register 1 and 2 Address 7 6 5 02h WDTIFG OFIFG PORIFG RSTIFG NMIIFG Address 12 3 2 1 0 RSTIFG PORIFG OFIFG WDTIFG rw-0 rw-(0) rw-(1) rw-1 rw-(0) Set on watchdog timer overflow (in watchdog mode) or security key violation. Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode. Flag set on oscillator fault. Power-On Reset interrupt flag. Set on VCC power-up. External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power-up. Set via RST/NMI pin 7 6 03h UCA0RXIFG UCA0TXIFG UCB0RXIFG UCB0TXIFG 4 NMIIFG 5 4 3 2 1 0 UCB0TXIFG UCB0RXIFG UCA0TXIFG UCA0RXIFG rw-1 rw-0 rw-1 rw-0 USCI_A0 receive interrupt flag USCI_A0 transmit interrupt flag USCI_B0 receive interrupt flag USCI_B0 transmit interrupt flag Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated MSP430G2x33 MSP430G2x03 SLAS734D - APRIL 2011 - REVISED NOVEMBER 2011 www.ti.com Memory Organization Table 8. Memory Organization MSP430G2233 MSP430G2203 MSP430G2333 MSP430G2303 MSP430G2433 MSP430G2403 MSP430G2533 Size 2kB 4kB 8kB 16kB Main: interrupt vector Flash 0xFFFF to 0xFFC0 0xFFFF to 0xFFC0 0xFFFF to 0xFFC0 0xFFFF to 0xFFC0 Main: code memory Flash 0xFFFF to 0xF800 0xFFFF to 0xF000 0xFFFF to 0xE000 0xFFFF to 0xC000 Information memory Size 256 Byte 256 Byte 256 Byte 256 Byte Flash 010FFh to 01000h 010FFh to 01000h 010FFh to 01000h 010FFh to 01000h Memory RAM Size Peripherals 256 Byte 256 Byte 512 Byte 512 Byte 0x02FF to 0x0200 0x02FF to 0x0200 0x03FF to 0x0200 0x03FF to 0x0200 16-bit 01FFh to 0100h 01FFh to 0100h 01FFh to 0100h 01FFh to 0100h 8-bit 0FFh to 010h 0FFh to 010h 0FFh to 010h 0FFh to 010h 0Fh to 00h 0Fh to 00h 0Fh to 00h 0Fh to 00h 8-bit SFR Bootstrap Loader (BSL) The MSP430 BSL enables users to program the flash memory or RAM using a UART serial interface. Access to the MSP430 memory via the BSL is protected by user-defined password. For complete description of the features of the BSL and its implementation, see the MSP430 Programming Via the Bootstrap Loader User's Guide (SLAU319). Table 9. BSL Function Pins BSL FUNCTION 20-PIN PW PACKAGE 20-PIN N PACKAGE 28-PIN PACKAGE PW 32-PIN PACKAGE RHB Data transmit 3 - P1.1 3 - P1.1 1 - P1.1 Data receive 7 - P1.5 7 - P1.5 5 - P1.5 Flash Memory The flash memory can be programmed via the Spy-Bi-Wire/JTAG port or in-system by the CPU. The CPU can perform single-byte and single-word writes to the flash memory. Features of the flash memory include: * Flash memory has n segments of main memory and four segments of information memory (A to D) of 64 bytes each. Each segment in main memory is 512 bytes in size. * Segments 0 to n may be erased in one step, or each segment may be individually erased. * Segments A to D can be erased individually or as a group with segments 0 to n. Segments A to D are also called information memory. * Segment A contains calibration data. After reset segment A is protected against programming and erasing. It can be unlocked but care should be taken not to erase this segment if the device-specific calibration data is required. Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback 13 MSP430G2x33 MSP430G2x03 SLAS734D - APRIL 2011 - REVISED NOVEMBER 2011 www.ti.com Peripherals Peripherals are connected to the CPU through data, address, and control buses and can be handled using all instructions. For complete module descriptions, see the MSP430x2xx Family User's Guide (SLAU144). Oscillator and System Clock The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal oscillator, an internal very-low-power low-frequency oscillator and an internal digitally controlled oscillator (DCO). The basic clock module is designed to meet the requirements of both low system cost and low power consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1 s. The basic clock module provides the following clock signals: * Auxiliary clock (ACLK), sourced either from a 32768-Hz watch crystal or the internal LF oscillator. * Main clock (MCLK), the system clock used by the CPU. * Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules. The DCO settings to calibrate the DCO output frequency are stored in the information memory segment A. Calibration Data Stored in Information Memory Segment A Calibration data is stored for both the DCO and for ADC10 organized in a tag-length-value structure. Table 10. Tags Used by the ADC Calibration Tags NAME ADDRESS VALUE DESCRIPTION TAG_DCO_30 0x10F6 0x01 DCO frequency calibration at VCC = 3 V and TA = 30C at calibration TAG_ADC10_1 0x10DA 0x10 ADC10_1 calibration tag TAG_EMPTY - 0xFE Identifier for empty memory areas Table 11. Labels Used by the ADC Calibration Tags LABEL ADDRESS OFFSET SIZE CAL_ADC_25T85 0x0010 word INCHx = 0x1010, REF2_5 = 1, TA = 85C CONDITION AT CALIBRATION / DESCRIPTION CAL_ADC_25T30 0x000E word INCHx = 0x1010, REF2_5 = 1, TA = 30C CAL_ADC_25VREF_FACTOR 0x000C word REF2_5 = 1, TA = 30C, IVREF+ = 1 mA CAL_ADC_15T85 0x000A word INCHx = 0x1010, REF2_5 = 0, TA = 85C CAL_ADC_15T30 0x0008 word INCHx = 0x1010, REF2_5 = 0, TA = 30C CAL_ADC_15VREF_FACTOR 0x0006 word REF2_5 = 0, TA = 30C, IVREF+ = 0.5 mA CAL_ADC_OFFSET 0x0004 word External VREF = 1.5 V, fADC10CLK = 5 MHz CAL_ADC_GAIN_FACTOR 0x0002 word External VREF = 1.5 V, fADC10CLK = 5 MHz CAL_BC1_1MHZ 0x0009 byte - CAL_DCO_1MHZ 0x0008 byte - CAL_BC1_8MHZ 0x0007 byte - CAL_DCO_8MHZ 0x0006 byte - CAL_BC1_12MHZ 0x0005 byte - CAL_DCO_12MHZ 0x0004 byte - CAL_BC1_16MHZ 0x0003 byte - CAL_DCO_16MHZ 0x0002 byte - Brownout The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and power off. 14 Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated MSP430G2x33 MSP430G2x03 SLAS734D - APRIL 2011 - REVISED NOVEMBER 2011 www.ti.com Digital I/O Up to three 8-bit I/O ports are implemented: * All individual I/O bits are independently programmable. * Any combination of input, output, and interrupt condition (port P1 and port P2 only) is possible. * Edge-selectable interrupt input capability for all bits of port P1 and port P2 (if available). * Read/write access to port-control registers is supported by all instructions. * Each I/O has an individually programmable pullup/pulldown resistor. * Each I/O has an individually programmable pin oscillator enable bit to enable low-cost touch sensing. WDT+ Watchdog Timer The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog function is not needed in an application, the module can be disabled or configured as an interval timer and can generate interrupts at selected time intervals. Timer_A3 (TA0, TA1) Timer0_A3 and Timer1_A3 are 16-bit timers/counters with three capture/compare registers. Timer_A3 can support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. Table 12. Timer0_A3 Signal Connections INPUT PIN NUMBER PW20, N20 PW28 RHB32 DEVICE INPUT SIGNAL P1.0-2 P1.0-2 P1.0-31 TACLK MODULE INPUT NAME TACLK ACLK ACLK SMCLK SMCLK MODULE BLOCK MODULE OUTPUT SIGNAL Timer NA OUTPUT PIN NUMBER PW20, N20 PW28 RHB32 P1.1-1 PinOsc PinOsc PinOsc TACLK INCLK P1.1-3 P1.1-3 P1.1-1 TA0.0 CCI0A P1.1-3 P1.1-3 ACLK CCI0B P1.5-7 P1.5-7 P1.5-5 VSS GND - P3.4-15 P3.4-14 P1.2-4 P1.2-4 P1.2-2 CCR0 TA0 VCC VCC TA0.1 CCI1A P1.2-4 P1.2-4 P1.2-2 CAOUT CCI1B P1.6-14 P1.6-22 P1.6-21 VSS GND P2.6-19 P2.6-27 P2.6-26 VCC VCC - P3.5-19 P3.5-18 CCR1 TA1 - P3.0-9 P3.0-7 TA0.2 CCI2A - P3.0-9 P3.0-7 PinOsc PinOsc PinOsc TA0.2 CCI2B - P3.6-20 P3.6-19 VSS GND VCC VCC Copyright (c) 2011, Texas Instruments Incorporated CCR2 TA2 Submit Documentation Feedback 15 MSP430G2x33 MSP430G2x03 SLAS734D - APRIL 2011 - REVISED NOVEMBER 2011 www.ti.com Table 13. Timer1_A3 Signal Connections INPUT PIN NUMBER PW20, N20 PW28 RHB32 DEVICE INPUT SIGNAL - P3.7-21 P3.7-20 TACLK MODULE INPUT NAME TACLK ACLK ACLK SMCLK SMCLK MODULE BLOCK MODULE OUTPUT SIGNAL Timer NA OUTPUT PIN NUMBER PW20, N20 PW28 RHB32 - P3.7-21 P3.7-20 TACLK INCLK P2.0-8 P2.0-10 P2.0-9 TA1.0 CCI0A P2.0-8 P2.0-10 P2.0-9 P2.3-11 P2.3-16 P2.3-12 TA1.0 CCI0B P2.3-11 P2.3-16 P2.3-15 VSS GND P3.1-8 P3.1-6 VCC VCC CCR0 TA0 P2.1-9 P2.1-11 P2.1-10 TA1.1 CCI1A P2.1-9 P2.1-11 P2.1-10 P2.2-10 P2.2-12 P2.2-11 TA1.1 CCI1B P2.2-10 P2.2-12 P2.2-11 P3.2-13 P3.2-12 P2.4-12 P2.4-17 P2.4-16 P2.5-13 P2.5-18 P2.5-17 P3.3-14 P3.3-13 VSS GND VCC VCC P2.4-12 P2.4-17 P2.4-16 TA1.2 CCI2A P2.5-13 P2.5-18 P2.5-17 TA1.2 CCI2B VSS GND VCC VCC CCR1 CCR2 TA1 TA2 Universal Serial Communications Interface (USCI) The USCI module is used for serial data communication. The USCI module supports synchronous communication protocols such as SPI (3 or 4 pin) and I2C, and asynchronous communication protocols such as UART, enhanced UART with automatic baudrate detection (LIN), and IrDA. Not all packages support the USCI functionality. USCI_A0 provides support for SPI (3 or 4 pin), UART, enhanced UART, and IrDA. USCI_B0 provides support for SPI (3 or 4 pin) and I2C. ADC10 (MSP430G2x33 Only) The ADC10 module supports fast 10-bit analog-to-digital conversions. The module implements a 10-bit SAR core, sample select control, reference generator, and data transfer controller (DTC) for automatic conversion result handling, allowing ADC samples to be converted and stored without any CPU intervention. 16 Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated MSP430G2x33 MSP430G2x03 SLAS734D - APRIL 2011 - REVISED NOVEMBER 2011 www.ti.com Peripheral File Map Table 14. Peripherals With Word Access MODULE ADC10 (MSP430G2x33 devices only) Timer1_A3 REGISTER DESCRIPTION ADC data transfer start address ADC10SA 1BCh ADC10MEM 1B4h ADC control register 1 ADC10CTL1 1B2h ADC control register 0 ADC10CTL0 1B0h Capture/compare register TACCR2 0196h Capture/compare register TACCR1 0194h Capture/compare register TACCR0 0192h TAR 0190h Capture/compare control TACCTL2 0186h Capture/compare control TACCTL1 0184h Capture/compare control TACCTL0 0182h TACTL 0180h Timer_A interrupt vector TAIV 011Eh Capture/compare register TACCR2 0176h Capture/compare register TACCR1 0174h Capture/compare register TACCR0 0172h Timer_A control Timer_A register TAR 0170h Capture/compare control TACCTL2 0166h Capture/compare control TACCTL1 0164h Capture/compare control TACCTL0 0162h Timer_A control TACTL 0160h TAIV 012Eh Flash control 3 FCTL3 012Ch Flash control 2 FCTL2 012Ah Flash control 1 FCTL1 0128h WDTCTL 0120h REGISTER NAME OFFSET USCI_B0 transmit buffer UCB0TXBUF 06Fh USCI_B0 receive buffer UCB0RXBUF 06Eh UCB0STAT 06Dh USCI B0 I2C Interrupt enable UCB0CIE 06Ch USCI_B0 bit rate control 1 UCB0BR1 06Bh USCI_B0 bit rate control 0 UCB0BR0 06Ah USCI_B0 control 1 UCB0CTL1 069h USCI_B0 control 0 UCB0CTL0 068h USCI_B0 I2C slave address UCB0SA 011Ah USCI_B0 I2C own address UCB0OA 0118h Timer_A interrupt vector Flash Memory Watchdog Timer+ OFFSET ADC memory Timer_A register Timer0_A3 REGISTER NAME Watchdog/timer control Table 15. Peripherals With Byte Access MODULE USCI_B0 REGISTER DESCRIPTION USCI_B0 status Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback 17 MSP430G2x33 MSP430G2x03 SLAS734D - APRIL 2011 - REVISED NOVEMBER 2011 www.ti.com Table 15. Peripherals With Byte Access (continued) REGISTER NAME OFFSET USCI_A0 transmit buffer UCA0TXBUF 067h USCI_A0 receive buffer UCA0RXBUF 066h USCI_A0 status UCA0STAT 065h USCI_A0 modulation control UCA0MCTL 064h USCI_A0 baud rate control 1 UCA0BR1 063h USCI_A0 baud rate control 0 UCA0BR0 062h USCI_A0 control 1 UCA0CTL1 061h USCI_A0 control 0 UCA0CTL0 060h USCI_A0 IrDA receive control UCA0IRRCTL 05Fh USCI_A0 IrDA transmit control UCA0IRTCTL 05Eh USCI_A0 auto baud rate control MODULE USCI_A0 ADC10 (MSP430G2x33 devices only) Basic Clock System+ Port P3 (28-pin PW and 32-pin RHB only) REGISTER DESCRIPTION UCA0ABCTL 05Dh ADC analog enable 0 ADC10AE0 04Ah ADC analog enable 1 ADC10AE1 04Bh ADC data transfer control register 1 ADC10DTC1 049h ADC data transfer control register 0 ADC10DTC0 048h Basic clock system control 3 BCSCTL3 053h Basic clock system control 2 BCSCTL2 058h Basic clock system control 1 BCSCTL1 057h DCO clock frequency control DCOCTL 056h Port P3 selection 2. pin P3SEL2 043h Port P3 resistor enable P3REN 010h Port P3 selection P3SEL 01Bh Port P3 direction P3DIR 01Ah Port P3 output P3OUT 019h P3IN 018h Port P2 selection 2 P2SEL2 042h Port P2 resistor enable P2REN 02Fh Port P2 selection P2SEL 02Eh Port P3 input Port P2 Port P2 interrupt enable P2IE 02Dh P2IES 02Ch Port P2 interrupt flag P2IFG 02Bh Port P2 direction P2DIR 02Ah Port P2 output P2OUT 029h Port P2 interrupt edge select Port P2 input Port P1 P2IN 028h Port P1 selection 2 P1SEL2 041h Port P1 resistor enable P1REN 027h Port P1 selection P1SEL 026h P1IE 025h Port P1 interrupt edge select P1IES 024h Port P1 interrupt flag P1IFG 023h Port P1 direction P1DIR 022h Port P1 output P1OUT 021h Port P1 input P1IN 020h SFR interrupt flag 2 IFG2 003h SFR interrupt flag 1 IFG1 002h SFR interrupt enable 2 IE2 001h SFR interrupt enable 1 IE1 000h Port P1 interrupt enable Special Function 18 Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated MSP430G2x33 MSP430G2x03 SLAS734D - APRIL 2011 - REVISED NOVEMBER 2011 www.ti.com Absolute Maximum Ratings (1) Voltage applied at VCC to VSS -0.3 V to 4.1 V Voltage applied to any pin (2) -0.3 V to VCC + 0.3 V 2 mA Diode current at any device pin Storage temperature range, Tstg (3) Unprogrammed device -55C to 150C Programmed device -55C to 150C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is applied to the TEST pin when blowing the JTAG fuse. Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels. (1) (2) (3) Recommended Operating Conditions MIN VCC Supply voltage VSS Supply voltage TA (1) (2) MAX During program execution 1.8 3.6 During flash programming/erase 2.2 3.6 I version -40 85 T version -40 105 VCC = 1.8 V, Duty cycle = 50% 10% dc 6 VCC = 2.7 V, Duty cycle = 50% 10% dc 12 VCC = 3.3 V, Duty cycle = 50% 10% dc 16 0 Operating free-air temperature Processor frequency (maximum MCLK frequency using the USART module) (1) (2) fSYSTEM NOM UNIT V V C MHz The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the specified maximum frequency. Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet. Legend : System Frequency - MHz 16 MHz Supply voltage range, during flash memory programming 12 MHz Supply voltage range, during program execution 6 MHz 1.8 V Note: 2.7 V 2.2 V Supply Voltage - V 3.3 V 3.6 V Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC of 2.2 V. Figure 1. Safe Operating Area Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback 19 MSP430G2x33 MSP430G2x03 SLAS734D - APRIL 2011 - REVISED NOVEMBER 2011 www.ti.com Electrical Characteristics Active Mode Supply Current Into VCC Excluding External Current over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) (2) PARAMETER Active mode (AM) current at 1 MHz IAM,1MHz (1) (2) TEST CONDITIONS TA fDCO = fMCLK = fSMCLK = 1 MHz, fACLK = 0 Hz, Program executes in flash, BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, CPUOFF = 0, SCG0 = 0, SCG1 = 0, OSCOFF = 0 VCC MIN TYP 2.2 V 230 3V 330 MAX UNIT A 420 All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external load capacitance is chosen to closely match the required 9 pF. Typical Characteristics, Active Mode Supply Current (Into VCC) 5.0 4.0 Active Mode Current - mA Active Mode Current - mA f DCO = 16 MHz 4.0 3.0 f DCO = 12 MHz 2.0 f DCO = 8 MHz 1.0 TA = 85 C 3.0 TA = 25 C VCC = 3 V 2.0 TA = 85 C TA = 25 C 1.0 f DCO = 1 MHz 0.0 1.5 2.0 2.5 3.0 3.5 VCC = 2.2 V 4.0 VCC - Supply Voltage - V Figure 2. Active Mode Current vs VCC, TA = 25C 20 Submit Documentation Feedback 0.0 0.0 4.0 8.0 12.0 16.0 f DCO - DCO Frequency - MHz Figure 3. Active Mode Current vs DCO Frequency Copyright (c) 2011, Texas Instruments Incorporated MSP430G2x33 MSP430G2x03 SLAS734D - APRIL 2011 - REVISED NOVEMBER 2011 www.ti.com Low-Power Mode Supply Currents (Into VCC) Excluding External Current over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) PARAMETER TA VCC Low-power mode 0 (LPM0) current (3) fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz, fACLK = 32768 Hz, BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 25C 2.2 V 56 A ILPM2 Low-power mode 2 (LPM2) current (4) fMCLK = fSMCLK = 0 MHz, fDCO = 1 MHz, fACLK = 32768 Hz, BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 25C 2.2 V 22 A ILPM3,LFXT1 Low-power mode 3 (LPM3) current (4) fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 32768 Hz, CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 25C 2.2 V 0.7 1.5 A ILPM3,VLO Low-power mode 3 current, (LPM3) (4) fDCO = fMCLK = fSMCLK = 0 MHz, fACLK from internal LF oscillator (VLO), CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 25C 2.2 V 0.5 0.7 A 0.5 ILPM4 fDCO = fMCLK = fSMCLK = 0 MHz, fACLK = 0 Hz, CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 0.1 Low-power mode 4 (LPM4) current (5) 0.8 1.7 ILPM0,1MHz (1) (2) (3) (4) (5) TEST CONDITIONS MIN (2) TYP 25C 2.2 V 85C MAX UNIT A All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current. The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external load capacitance is chosen to closely match the required 9 pF. Current for brownout and WDT clocked by SMCLK included. Current for brownout and WDT clocked by ACLK included. Current for brownout included. Typical Characteristics, Low-Power Mode Supply Currents 3.00 2.50 2.75 2.25 ILPM4 - Low-Power Mode Current - A ILPM3 - Low-Power Mode Current - A over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) 2.50 2.25 2.00 1.75 1.50 Vcc = 3.6 V 1.25 Vcc = 3 V 1.00 Vcc = 2.2 V 0.75 0.50 Vcc = 1.8 V 0.25 0.00 -40 -20 0 20 40 60 TA - Temperature - C Figure 4. LPM3 Current vs Temperature Copyright (c) 2011, Texas Instruments Incorporated 80 2.00 1.75 1.50 1.25 Vcc = 3.6 V 1.00 Vcc = 3 V 0.75 Vcc = 2.2 V 0.50 0.25 0.00 -40 Vcc = 1.8 V -20 0 20 40 60 80 TA - Temperature - C Figure 5. LPM4 Current vs Temperature Submit Documentation Feedback 21 MSP430G2x33 MSP430G2x03 SLAS734D - APRIL 2011 - REVISED NOVEMBER 2011 www.ti.com Schmitt-Trigger Inputs, Ports Px over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VIT+ Positive-going input threshold voltage VIT- Negative-going input threshold voltage Vhys Input voltage hysteresis (VIT+ - VIT-) VCC MIN RPull Pullup/pulldown resistor CI Input capacitance VIN = VSS or VCC MAX 0.45 VCC 0.75 VCC 1.35 2.25 3V For pullup: VIN = VSS For pulldown: VIN = VCC TYP UNIT V 0.25 VCC 0.55 VCC 3V 0.75 1.65 3V 0.3 1 V 3V 20 50 k 35 V 5 pF Leakage Current, Ports Px over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER Ilkg(Px.y) (1) (2) TEST CONDITIONS VCC (1) (2) High-impedance leakage current MIN 3V MAX UNIT 50 nA The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted. The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is disabled. Outputs, Ports Px over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT VOH High-level output voltage I(OHmax) = -6 mA (1) 3V VCC - 0.3 V VOL Low-level output voltage I(OLmax) = 6 mA (1) 3V VSS + 0.3 V (1) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed 48 mA to hold the maximum voltage drop specified. Output Frequency, Ports Px over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS fPx.y Port output frequency (with load) Px.y, CL = 20 pF, RL = 1 k fPort_CLK Clock output frequency Px.y, CL = 20 pF (2) (1) (2) 22 (1) (2) VCC MIN TYP MAX UNIT 3V 12 MHz 3V 16 MHz A resistive divider with two 0.5-k resistors between VCC and VSS is used as load. The output is connected to the center tap of the divider. The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency. Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated MSP430G2x33 MSP430G2x03 SLAS734D - APRIL 2011 - REVISED NOVEMBER 2011 www.ti.com Typical Characteristics, Outputs over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE TYPICAL LOW-LEVEL OUTPUT CURRENT vs LOW-LEVEL OUTPUT VOLTAGE 50 VCC = 2.2 V P1.7 TA = 25C 25 TA = 85C 20 15 10 5 I OL - Typical Low-Level Output Current - mA I OL - Typical Low-Level Output Current - mA 30 0 VCC = 3 V P1.7 40 TA = 85C 30 20 10 0 0 0.5 1 1.5 2 2.5 0 VOL - Low-Level Output Voltage - V 0.5 1 1.5 2 2.5 3 3.5 VOL - Low-Level Output Voltage - V Figure 6. Figure 7. TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE TYPICAL HIGH-LEVEL OUTPUT CURRENT vs HIGH-LEVEL OUTPUT VOLTAGE 0 0 VCC = 2.2 V P1.7 I OH - Typical High-Level Output Current - mA I OH - Typical High-Level Output Current - mA TA = 25C -5 -10 -15 TA = 85C -20 TA = 25C -25 0 0.5 VCC = 3 V P1.7 -10 -20 -30 TA = 85C -40 TA = 25C -50 1 1.5 2 VOH - High-Level Output Voltage - V Figure 8. Copyright (c) 2011, Texas Instruments Incorporated 2.5 0 0.5 1 1.5 2 2.5 3 3.5 VOH - High-Level Output Voltage - V Figure 9. Submit Documentation Feedback 23 MSP430G2x33 MSP430G2x03 SLAS734D - APRIL 2011 - REVISED NOVEMBER 2011 www.ti.com Pin-Oscillator Frequency - Ports Px over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS foP1.x Port output oscillation frequency foP2.x Port output oscillation frequency foP2.6/7 Port output oscillation frequency foP3.x (1) (2) Port output oscillation frequency P1.y, CL = 10 pF, RL = 100 k VCC MIN (1) (2) 3V P1.y, CL = 20 pF, RL = 100 k (1) (2) P2.0 to P2.5, CL = 10 pF, RL = 100 k (1) (2) P2.0 to P2.5, CL = 20 pF, RL = 100 k (1) (2) P2.6 and P2.7, CL = 20 pF, RL = 100 k (1) (2) P3.y, CL = 10 pF, RL = 100 k (1) (2) P3.y, CL = 20 pF, RL = 100 k (1) (2) 3V 3V 3V TYP MAX UNIT 1400 kHz 900 1800 kHz 1000 kHz 700 kHz 1800 kHz 1000 A resistive divider with two 0.5-k resistors between VCC and VSS is used as load. The output is connected to the center tap of the divider. The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency. Typical Characteristics, Pin-Oscillator Frequency TYPICAL OSCILLATING FREQUENCY vs LOAD CAPACITANCE TYPICAL OSCILLATING FREQUENCY vs LOAD CAPACITANCE 1.50 VCC = 3.0 V 1.35 1.20 1.05 P1.y 0.90 P2.0 ... P2.5 0.75 P2.6, P2.7 0.60 0.45 0.30 0.15 0.00 VCC = 2.2 V 1.35 1.20 1.05 P1.y 0.90 P2.0 ... P2.5 0.75 P2.6, P2.7 0.60 0.45 0.30 0.15 0.00 10 50 100 CLOAD - External Capacitance - pF A. One output active at a time. 10 50 100 CLOAD - External Capacitance - pF A. One output active at a time. Figure 10. 24 fosc - Typical Oscillation Frequency - MHz fosc - Typical Oscillation Frequency - MHz 1.50 Submit Documentation Feedback Figure 11. Copyright (c) 2011, Texas Instruments Incorporated MSP430G2x33 MSP430G2x03 SLAS734D - APRIL 2011 - REVISED NOVEMBER 2011 www.ti.com POR/Brownout Reset (BOR) (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT VCC(start) See Figure 12 dVCC/dt 3 V/s 0.7 x V(B_IT--) V(B_IT-) See Figure 12 through Figure 14 dVCC/dt 3 V/s 1.35 V Vhys(B_IT-) See Figure 12 dVCC/dt 3 V/s 140 mV td(BOR) See Figure 12 2000 s t(reset) Pulse length needed at RST/NMI pin to accepted reset internally (1) 2.2 V 2 V s The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT-) + Vhys(B_IT-)is 1.8 V. VCC Vhys(B_IT-) V(B_IT-) VCC(start) 1 0 t d(BOR) Figure 12. POR/Brownout Reset (BOR) vs Supply Voltage Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback 25 MSP430G2x33 MSP430G2x03 SLAS734D - APRIL 2011 - REVISED NOVEMBER 2011 www.ti.com Typical Characteristics, POR/Brownout Reset (BOR) VCC 3V 2 VCC(drop) - V VCC = 3 V Typical Conditions t pw 1.5 1 VCC(drop) 0.5 0 0.001 1 1000 1 ns t pw - Pulse Width - s 1 ns t pw - Pulse Width - s Figure 13. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal VCC 2 t pw 3V VCC(drop) - V VCC = 3 V 1.5 Typical Conditions 1 VCC(drop) 0.5 0 0.001 t f = tr 1 t pw - Pulse Width - s 1000 tf tr t pw - Pulse Width - s Figure 14. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal 26 Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated MSP430G2x33 MSP430G2x03 SLAS734D - APRIL 2011 - REVISED NOVEMBER 2011 www.ti.com Main DCO Characteristics * * * All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14 overlaps RSELx = 15. DCO control bits DCOx have a step size as defined by parameter SDCO. Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles. The frequency is an average equal to: faverage = 32 x fDCO(RSEL,DCO) x fDCO(RSEL,DCO+1) MOD x fDCO(RSEL,DCO) + (32 - MOD) x fDCO(RSEL,DCO+1) DCO Frequency over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VCC Supply voltage TEST CONDITIONS VCC MIN TYP MAX UNIT RSELx < 14 1.8 3.6 V RSELx = 14 2.2 3.6 V RSELx = 15 3 3.6 V fDCO(0,0) DCO frequency (0, 0) RSELx = 0, DCOx = 0, MODx = 0 3V 0.06 0.14 MHz fDCO(0,3) DCO frequency (0, 3) RSELx = 0, DCOx = 3, MODx = 0 3V 0.07 0.17 MHz fDCO(1,3) DCO frequency (1, 3) RSELx = 1, DCOx = 3, MODx = 0 3V 0.15 MHz fDCO(2,3) DCO frequency (2, 3) RSELx = 2, DCOx = 3, MODx = 0 3V 0.21 MHz fDCO(3,3) DCO frequency (3, 3) RSELx = 3, DCOx = 3, MODx = 0 3V 0.30 MHz fDCO(4,3) DCO frequency (4, 3) RSELx = 4, DCOx = 3, MODx = 0 3V 0.41 MHz fDCO(5,3) DCO frequency (5, 3) RSELx = 5, DCOx = 3, MODx = 0 3V fDCO(6,3) DCO frequency (6, 3) RSELx = 6, DCOx = 3, MODx = 0 3V 0.54 1.06 MHz fDCO(7,3) DCO frequency (7, 3) RSELx = 7, DCOx = 3, MODx = 0 3V 0.80 1.50 MHz fDCO(8,3) DCO frequency (8, 3) RSELx = 8, DCOx = 3, MODx = 0 3V 1.6 MHz fDCO(9,3) DCO frequency (9, 3) RSELx = 9, DCOx = 3, MODx = 0 3V 2.3 MHz fDCO(10,3) DCO frequency (10, 3) RSELx = 10, DCOx = 3, MODx = 0 3V 3.4 MHz fDCO(11,3) DCO frequency (11, 3) RSELx = 11, DCOx = 3, MODx = 0 3V 4.25 MHz fDCO(12,3) DCO frequency (12, 3) RSELx = 12, DCOx = 3, MODx = 0 3V 4.30 7.30 MHz fDCO(13,3) DCO frequency (13, 3) RSELx = 13, DCOx = 3, MODx = 0 3V 6.00 9.60 MHz fDCO(14,3) DCO frequency (14, 3) RSELx = 14, DCOx = 3, MODx = 0 3V 8.60 13.9 MHz fDCO(15,3) DCO frequency (15, 3) RSELx = 15, DCOx = 3, MODx = 0 3V 12.0 18.5 MHz fDCO(15,7) DCO frequency (15, 7) RSELx = 15, DCOx = 7, MODx = 0 3V 16.0 26.0 MHz SRSEL Frequency step between range RSEL and RSEL+1 SRSEL = fDCO(RSEL+1,DCO)/fDCO(RSEL,DCO) 3V 1.35 ratio SDCO Frequency step between tap DCO and DCO+1 SDCO = fDCO(RSEL,DCO+1)/fDCO(RSEL,DCO) 3V 1.08 ratio Measured at SMCLK output 3V 50 Duty cycle Copyright (c) 2011, Texas Instruments Incorporated 0.58 MHz Submit Documentation Feedback % 27 MSP430G2x33 MSP430G2x03 SLAS734D - APRIL 2011 - REVISED NOVEMBER 2011 www.ti.com Calibrated DCO Frequencies, Tolerance over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS TA VCC MIN TYP MAX UNIT 1-MHz tolerance over temperature (1) BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, calibrated at 30C and 3 V 0C to 85C 3V -3 0.5 +3 % 1-MHz tolerance over VCC BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, calibrated at 30C and 3 V 30C 1.8 V to 3.6 V -3 2 +3 % 1-MHz tolerance overall BCSCTL1 = CALBC1_1MHZ, DCOCTL = CALDCO_1MHZ, calibrated at 30C and 3 V -40C to 85C 1.8 V to 3.6 V -6 3 +6 % 8-MHz tolerance over temperature (1) BCSCTL1 = CALBC1_8MHZ, DCOCTL = CALDCO_8MHZ, calibrated at 30C and 3 V 0C to 85C 3V -3 0.5 +3 % 8-MHz tolerance over VCC BCSCTL1 = CALBC1_8MHZ, DCOCTL = CALDCO_8MHZ, calibrated at 30C and 3 V 30C 2.2 V to 3.6 V -3 2 +3 % 8-MHz tolerance overall BCSCTL1 = CALBC1_8MHZ, DCOCTL = CALDCO_8MHZ, calibrated at 30C and 3 V -40C to 85C 2.2 V to 3.6 V -6 3 +6 % 12-MHz tolerance over temperature (1) BCSCTL1 = CALBC1_12MHZ, DCOCTL = CALDCO_12MHZ, calibrated at 30C and 3 V 0C to 85C 3V -3 0.5 +3 % 12-MHz tolerance over VCC BCSCTL1 = CALBC1_12MHZ, DCOCTL = CALDCO_12MHZ, calibrated at 30C and 3 V 30C 2.7 V to 3.6 V -3 2 +3 % 12-MHz tolerance overall BCSCTL1 = CALBC1_12MHZ, DCOCTL = CALDCO_12MHZ, calibrated at 30C and 3 V -40C to 85C 2.7 V to 3.6 V -6 3 +6 % 16-MHz tolerance over temperature (1) BCSCTL1 = CALBC1_16MHZ, DCOCTL = CALDCO_16MHZ, calibrated at 30C and 3 V 0C to 85C 3V -3 0.5 +3 % 16-MHz tolerance over VCC BCSCTL1 = CALBC1_16MHZ, DCOCTL = CALDCO_16MHZ, calibrated at 30C and 3 V 30C 3.3 V to 3.6 V -3 2 +3 % 16-MHz tolerance overall BCSCTL1 = CALBC1_16MHZ, DCOCTL = CALDCO_16MHZ, calibrated at 30C and 3 V -40C to 85C 3.3 V to 3.6 V -6 3 +6 % (1) 28 This is the frequency change from the measured frequency at 30C over temperature. Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated MSP430G2x33 MSP430G2x03 SLAS734D - APRIL 2011 - REVISED NOVEMBER 2011 www.ti.com Wake-Up From Lower-Power Modes (LPM3/4) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS tDCO,LPM3/4 DCO clock wake-up time from LPM3/4 (1) tCPU,LPM3/4 CPU wake-up time from LPM3/4 (2) (1) (2) VCC BCSCTL1 = CALBC1_1MHz, DCOCTL = CALDCO_1MHz MIN 3V TYP MAX UNIT 1.5 s 1/fMCLK + tClock,LPM3/4 The DCO clock wake-up time is measured from the edge of an external wake-up signal (e.g., port interrupt) to the first clock edge observable externally on a clock pin (MCLK or SMCLK). Parameter applicable only if DCOCLK is used for MCLK. Typical Characteristics, DCO Clock Wake-Up Time From LPM3/4 DCO Wake Time - s 10.00 RSELx = 0...11 RSELx = 12...15 1.00 0.10 0.10 1.00 10.00 DCO Frequency - MHz Figure 15. DCO Wake-Up Time From LPM3 vs DCO Frequency Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback 29 MSP430G2x33 MSP430G2x03 SLAS734D - APRIL 2011 - REVISED NOVEMBER 2011 www.ti.com Crystal Oscillator, XT1, Low-Frequency Mode (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS fLFXT1,LF LFXT1 oscillator crystal frequency, LF mode 0, 1 fLFXT1,LF,logic LFXT1 oscillator logic level square wave input frequency, XTS = 0, XCAPx = 0, LFXT1Sx = 3 LF mode OALF Oscillation allowance for LF crystals Integrated effective load capacitance, LF mode (2) CL,eff XTS = 0, LFXT1Sx = 0 or 1 10000 32768 200 1 XTS = 0, XCAPx = 1 5.5 XTS = 0, XCAPx = 2 8.5 XTS = 0, XCAPx = 3 11 XTS = 0, XCAPx = 0, LFXT1Sx = 3 (4) UNIT Hz 50000 Hz k XTS = 0, XCAPx = 0 Oscillator fault frequency, LF mode (3) (4) 1.8 V to 3.6 V XTS = 0, LFXT1Sx = 0, fLFXT1,LF = 32768 Hz, CL,eff = 12 pF fFault,LF MAX 32768 500 LF mode (3) TYP XTS = 0, LFXT1Sx = 0, fLFXT1,LF = 32768 Hz, CL,eff = 6 pF Duty cycle (2) MIN 1.8 V to 3.6 V XTS = 0, Measured at P2.0/ACLK, fLFXT1,LF = 32768 Hz (1) VCC 2.2 V 30 2.2 V 10 50 pF 70 % 10000 Hz To improve EMI on the XT1 oscillator, the following guidelines should be observed. (a) Keep the trace between the device and the crystal as short as possible. (b) Design a good ground plane around the oscillator pins. (c) Prevent crosstalk from other clock or data lines into oscillator pins XIN and XOUT. (d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins. (e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins. (f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins. (g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This signal is no longer required for the serial programming adapter. Includes parasitic bond and package capacitance (approximately 2 pF per pin). Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a correct setup, the effective load capacitance should always match the specification of the used crystal. Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag. Frequencies in between might set the flag. Measured with logic-level input frequency but also applies to operation with crystals. Internal Very-Low-Power Low-Frequency Oscillator (VLO) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) TA VCC MIN TYP MAX fVLO VLO frequency PARAMETER -40C to 85C 3V 4 12 20 dfVLO/dT VLO frequency temperature drift -40C to 85C 3V 25C 1.8 V to 3.6 V dfVLO/dVCC VLO frequency supply voltage drift UNIT kHz 0.5 %/C 4 %/V Timer_A over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS fTA Timer_A input clock frequency SMCLK, duty cycle = 50% 10% tTA,cap Timer_A capture timing TA0, TA1 30 Submit Documentation Feedback VCC MIN TYP fSYSTEM 3V 20 MAX UNIT MHz ns Copyright (c) 2011, Texas Instruments Incorporated MSP430G2x33 MSP430G2x03 SLAS734D - APRIL 2011 - REVISED NOVEMBER 2011 www.ti.com USCI (UART Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN SMCLK, duty cycle = 50% 10% fUSCI USCI input clock frequency fmax,BITCLK Maximum BITCLK clock frequency (equals baudrate in MBaud) (1) 3V 2 t UART receive deglitch time (2) 3V 50 (1) (2) TYP MAX fSYSTEM UNIT MHz MHz 100 600 ns The DCO wake-up time must be considered in LPM3/4 for baud rates above 1 MHz. Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are correctly recognized, their width should exceed the maximum specification of the deglitch time. USCI (SPI Master Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 16 and Figure 17) PARAMETER TEST CONDITIONS VCC MIN SMCLK, duty cycle = 50% 10% TYP MAX UNIT fSYSTEM MHz fUSCI USCI input clock frequency tSU,MI SOMI input data setup time 3V 75 ns tHD,MI SOMI input data hold time 3V 0 ns tVALID,MO SIMO output data valid time UCLK edge to SIMO valid, CL = 20 pF 3V 20 ns 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLO/HI tLO/HI tSU,MI tHD,MI SOMI tHD,MO tVALID,MO SIMO Figure 16. SPI Master Mode, CKPH = 0 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLO/HI tLO/HI tSU,MI tHD,MI SOMI tHD,MO tVALID,MO SIMO Figure 17. SPI Master Mode, CKPH = 1 Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback 31 MSP430G2x33 MSP430G2x03 SLAS734D - APRIL 2011 - REVISED NOVEMBER 2011 www.ti.com USCI (SPI Slave Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 18 and Figure 19) PARAMETER TEST CONDITIONS VCC MIN TYP MAX STE lead time, STE low to clock 3V tSTE,LAG STE lag time, Last clock to STE high 3V tSTE,ACC STE access time, STE low to SOMI data out 3V 50 ns tSTE,DIS STE disable time, STE high to SOMI high impedance 3V 50 ns tSU,SI SIMO input data setup time 3V 15 ns tHD,SI SIMO input data hold time 3V 10 ns tVALID,SO UCLK edge to SOMI valid, CL = 20 pF SOMI output data valid time tSTE,LEAD 3V 50 UNIT tSTE,LEAD ns 10 ns 50 75 ns tSTE,LAG STE 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLO/HI tSU,SI tLO/HI tHD,SI SIMO tHD,SO tVALID,SO tSTE,ACC tSTE,DIS SOMI Figure 18. SPI Slave Mode, CKPH = 0 tSTE,LAG tSTE,LEAD STE 1/fUCxCLK CKPL = 0 UCLK CKPL = 1 tLO/HI tLO/HI tHD,SI tSU,SI SIMO tSTE,ACC tHD,MO tVALID,SO tSTE,DIS SOMI Figure 19. SPI Slave Mode, CKPH = 1 32 Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated MSP430G2x33 MSP430G2x03 SLAS734D - APRIL 2011 - REVISED NOVEMBER 2011 www.ti.com USCI (I2C Mode) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 20) PARAMETER TEST CONDITIONS fUSCI USCI input clock frequency fSCL SCL clock frequency VCC MIN 3V 0 TYP SMCLK, duty cycle = 50% 10% fSCL 100 kHz MAX UNIT fSYSTEM MHz 400 kHz 4.0 3V s tHD,STA Hold time (repeated) START tSU,STA Setup time for a repeated START tHD,DAT Data hold time 3V 0 tSU,DAT Data setup time 3V 250 ns tSU,STO Setup time for STOP 3V 4.0 s tSP Pulse width of spikes suppressed by input filter 3V 50 fSCL > 100 kHz fSCL 100 kHz 4.7 3V fSCL > 100 kHz tSU,STA tHD,STA 0.6 s 0.6 tHD,STA ns 100 600 ns tBUF SDA tLOW tHIGH tSP SCL tSU,DAT tSU,STO tHD,DAT Figure 20. I2C Mode Timing Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback 33 MSP430G2x33 MSP430G2x03 SLAS734D - APRIL 2011 - REVISED NOVEMBER 2011 www.ti.com 10-Bit ADC, Power Supply and Input Range Conditions (MSP430G2x33 Only) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (1) PARAMETER VCC TEST CONDITIONS Analog supply voltage VAx Analog input voltage IADC10 IREF+ VCC VSS = 0 V (2) ADC10 supply current TA (3) Reference supply current, reference buffer disabled (4) All Ax terminals, Analog inputs selected in ADC10AE register fADC10CLK = 5.0 MHz, ADC10ON = 1, REFON = 0, ADC10SHT0 = 1, ADC10SHT1 = 0, ADC10DIV = 0 fADC10CLK = 5.0 MHz, ADC10ON = 0, REF2_5V = 0, REFON = 1, REFOUT = 0 fADC10CLK = 5.0 MHz, ADC10ON = 0, REF2_5V = 1, REFON = 1, REFOUT = 0 3V 25C 3V MIN TYP MAX UNIT 2.2 3.6 V 0 VCC V 0.6 mA 0.25 25C 3V mA 0.25 IREFB,0 fADC10CLK = 5.0 MHz, Reference buffer supply ADC10ON = 0, REFON = 1, current with ADC10SR = 0 (4) REF2_5V = 0, REFOUT = 1, ADC10SR = 0 25C 3V 1.1 mA IREFB,1 fADC10CLK = 5.0 MHz, Reference buffer supply ADC10ON = 0, REFON = 1, current with ADC10SR = 1 (4) REF2_5V = 0, REFOUT = 1, ADC10SR = 1 25C 3V 0.5 mA CI Input capacitance Only one terminal Ax can be selected at one time 25C 3V RI Input MUX ON resistance 0 V VAx VCC 25C 3V (1) (2) (3) (4) 34 27 1000 pF The leakage current is defined in the leakage current table with Px.y/Ax parameter. The analog input voltage range must be within the selected reference voltage range VR+ to VR- for valid conversion results. The internal reference supply current is not included in current consumption parameter IADC10. The internal reference current is supplied via terminal VCC. Consumption is independent of the ADC10ON control bit, unless a conversion is active. The REFON bit enables the built-in reference to settle before starting an A/D conversion. Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated MSP430G2x33 MSP430G2x03 SLAS734D - APRIL 2011 - REVISED NOVEMBER 2011 www.ti.com 10-Bit ADC, Built-In Voltage Reference (MSP430G2x33 Only) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC,REF+ IVREF+ 1 mA, REF2_5V = 0 Positive built-in reference analog supply voltage range IVREF+ 1 mA, REF2_5V = 1 VREF+ Positive built-in reference voltage ILD,VREF+ Maximum VREF+ load current VREF+ load regulation IVREF+ IVREF+max, REF2_5V = 0 IVREF+ IVREF+max, REF2_5V = 1 VCC IVREF+ = 500 A 100 A, Analog input voltage VAx 1.25 V, REF2_5V = 1 TYP MAX 2.2 3V UNIT V 2.9 3V IVREF+ = 500 A 100 A, Analog input voltage VAx 0.75 V, REF2_5V = 0 MIN 1.41 1.5 1.59 2.35 2.5 2.65 1 V mA 2 3V LSB 2 VREF+ load regulation response time IVREF+ = 100 A900 A, VAx 0.5 x VREF+, Error of conversion result 1 LSB, ADC10SR = 0 3V 400 ns CVREF+ Maximum capacitance at pin VREF+ IVREF+ 1 mA, REFON = 1, REFOUT = 1 3V 100 pF TCREF+ Temperature coefficient IVREF+ = const with 0 mA IVREF+ 1 mA 3V 100 ppm/ C tREFON Settling time of internal reference voltage to 99.9% VREF IVREF+ = 0.5 mA, REF2_5V = 0, REFON = 0 1 3.6 V 30 s tREFBURST Settling time of reference buffer to 99.9% VREF IVREF+ = 0.5 mA, REF2_5V = 1, REFON = 1, REFBURST = 1, ADC10SR = 0 3V 2 s Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback 35 MSP430G2x33 MSP430G2x03 SLAS734D - APRIL 2011 - REVISED NOVEMBER 2011 www.ti.com 10-Bit ADC, External Reference (1) (MSP430G2x33 Only) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VEREF+ TEST CONDITIONS Positive external reference input voltage range (2) 1.4 3 0 1.2 V 1.4 VCC V Differential external reference input voltage range, VEREF = VEREF+ - VEREF- VEREF+ > VEREF- (1) (2) (3) (4) (5) UNIT VEREF- VEREF+ VCC - 0.15 V, SREF1 = 1, SREF0 = 1 (3) VEREF Static input current into VEREF- MAX VCC VEREF+ > VEREF- IVEREF- TYP 1.4 Negative external reference input voltage range (4) Static input current into VEREF+ MIN VEREF+ > VEREF-, SREF1 = 1, SREF0 = 0 VEREF- IVEREF+ VCC V (5) 0 V VEREF+ VCC, SREF1 = 1, SREF0 = 0 3V 1 0 V VEREF+ VCC - 0.15 V 3 V, SREF1 = 1, SREF0 = 1 (3) 3V 0 0 V VEREF- VCC 3V 1 A A The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also the dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy. The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced accuracy requirements. Under this condition the external reference is internally buffered. The reference buffer is active and requires the reference buffer supply current IREFB. The current consumption can be limited to the sample and conversion period with REBURST = 1. The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced accuracy requirements. The accuracy limits the minimum external differential reference voltage. Lower differential reference voltage levels may be applied with reduced accuracy requirements. 10-Bit ADC, Timing Parameters (MSP430G2x33 Only) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS ADC10SR = 0 fADC10CLK ADC10 input clock frequency For specified performance of ADC10 linearity parameters fADC10OSC ADC10 built-in oscillator frequency ADC10DIVx = 0, ADC10SSELx = 0, fADC10CLK = fADC10OSC ADC10 built-in oscillator, ADC10SSELx = 0, fADC10CLK = fADC10OSC tCONVERT Conversion time tADC10ON Turn-on settling time of the ADC (1) ADC10SR = 1 VCC MIN TYP MAX 0.45 6.3 0.45 1.5 3V 3.7 6.3 3V 2.06 3.51 3V UNIT MHz MHz s 13 x ADC10DIV x 1/fADC10CLK fADC10CLK from ACLK, MCLK, or SMCLK: ADC10SSELx 0 (1) 100 ns The condition is that the error in a conversion started after tADC10ON is less than 0.5 LSB. The reference and input signal are already settled. 10-Bit ADC, Linearity Parameters (MSP430G2x33 Only) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) MAX UNIT EI Integral linearity error PARAMETER 3V 1 LSB ED Differential linearity error 3V 1 LSB EO Offset error 3V 1 LSB EG Gain error 3V 1.1 2 LSB ET Total unadjusted error 3V 2 5 LSB 36 Submit Documentation Feedback TEST CONDITIONS Source impedance RS < 100 VCC MIN TYP Copyright (c) 2011, Texas Instruments Incorporated MSP430G2x33 MSP430G2x03 SLAS734D - APRIL 2011 - REVISED NOVEMBER 2011 www.ti.com 10-Bit ADC, Temperature Sensor and Built-In VMID (MSP430G2x33 Only) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER ISENSOR Temperature sensor supply current (1) TCSENSOR TEST CONDITIONS VCC REFON = 0, INCHx = 0Ah, TA = 25C ADC10ON = 1, INCHx = 0Ah (2) 60 3V 3.55 tSensor(sample) ADC10ON = 1, INCHx = 0Ah, Error of conversion result 1 LSB 3V IVMID Current into divider at channel 11 ADC10ON = 1, INCHx = 0Bh 3V VMID VCC divider at channel 11 ADC10ON = 1, INCHx = 0Bh, VMID 0.5 x VCC 3V tVMID(sample) Sample time required if channel 11 is selected (5) ADC10ON = 1, INCHx = 0Bh, Error of conversion result 1 LSB 3V (2) (3) (4) (5) TYP 3V Sample time required if channel 10 is selected (3) (1) MIN MAX UNIT A mV/C s 30 (4) A 1.5 V 1220 ns The sensor current ISENSOR is consumed if (ADC10ON = 1 and REFON = 1) or (ADC10ON = 1 and INCH = 0Ah and sample signal is high). When REFON = 1, ISENSOR is included in IREF+. When REFON = 0, ISENSOR applies during conversion of the temperature sensor input (INCH = 0Ah). The following formula can be used to calculate the temperature sensor output voltage: VSensor,typ = TCSensor (273 + T [C] ) + VOffset,sensor [mV] or VSensor,typ = TCSensor T [C] + VSensor(TA = 0C) [mV] The typical equivalent impedance of the sensor is 51 k. The sample time required includes the sensor-on time tSENSOR(on). No additional current is needed. The VMID is used during sampling. The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed. Flash Memory over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT VCC(PGM/ERASE) Program and erase supply voltage 2.2 3.6 V fFTG Flash timing generator frequency 257 476 kHz IPGM Supply current from VCC during program 2.2 V/3.6 V 1 5 mA IERASE Supply current from VCC during erase 2.2 V/3.6 V 1 7 mA tCPT Cumulative program time (1) 2.2 V/3.6 V 10 ms tCMErase Cumulative mass erase time 2.2 V/3.6 V 20 104 Program/erase endurance ms 105 cycles tRetention Data retention duration TJ = 25C tWord Word or byte program time (2) 30 tFTG 0 Block program time for first byte or word (2) 25 tFTG tBlock, 1-63 Block program time for each additional byte or word (2) 18 tFTG tBlock, End Block program end-sequence wait time (2) 6 tFTG tMass Erase Mass erase time (2) 10593 tFTG tSeg Erase Segment erase time (2) 4819 tFTG tBlock, (1) (2) 100 years The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming methods: individual word/byte write and block write modes. These values are hardwired into the Flash Controller's state machine (tFTG = 1/fFTG). Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback 37 MSP430G2x33 MSP430G2x03 SLAS734D - APRIL 2011 - REVISED NOVEMBER 2011 www.ti.com RAM over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER V(RAMh) (1) RAM retention supply voltage TEST CONDITIONS (1) MIN CPU halted MAX 1.6 UNIT V This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution should happen during this supply voltage condition. JTAG and Spy-Bi-Wire Interface over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) MAX UNIT fSBW Spy-Bi-Wire input frequency PARAMETER 2.2 V 0 20 MHz tSBW,Low Spy-Bi-Wire low clock pulse length 2.2 V 0.025 15 s tSBW,En Spy-Bi-Wire enable time (TEST high to acceptance of first clock edge (1)) 2.2 V 1 s tSBW,Ret Spy-Bi-Wire return to normal operation time 2.2 V 15 100 fTCK TCK input frequency (2) 2.2 V 0 5 MHz RInternal Internal pulldown resistance on TEST 2.2 V 25 90 k (1) (2) TEST CONDITIONS VCC MIN TYP 60 s Tools accessing the Spy-Bi-Wire interface need to wait for the maximum tSBW,En time after pulling the TEST/SBWCLK pin high before applying the first SBWCLK clock edge. fTCK may be restricted to meet the timing requirements of the module selected. JTAG Fuse (1) over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) PARAMETER VCC(FB) Supply voltage during fuse-blow condition VFB Voltage level on TEST for fuse blow IFB Supply current into TEST during fuse blow tFB Time to blow fuse (1) 38 TEST CONDITIONS TA = 25C MIN MAX 2.5 6 UNIT V 7 V 100 mA 1 ms Once the fuse is blown, no further access to the JTAG/Test, Spy-Bi-Wire, and emulation feature is possible, and JTAG is switched to bypass mode. Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated MSP430G2x33 MSP430G2x03 SLAS734D - APRIL 2011 - REVISED NOVEMBER 2011 www.ti.com PORT SCHEMATICS Port P1 Pin Schematic: P1.0 to P1.2, Input/Output With Schmitt Trigger To ADC10 * INCHx = y * ADC10AE0.y * PxSEL2.y PxSEL.y PxDIR.y 0 From Timer 1 1 2 Direction 0: Input 1: Output 3 From USCI PxSEL2.y PxSEL.y PxREN.y 0 1 1 0 1 PxSEL2.y PxSEL.y DVSS DVCC PxOUT.y 0 From Timer 1 0 3 0 1 2 Bus Keeper EN TAx.y TAxCLK 1 P1.0/TA0CLK/ ACLK/A0* P1.1/TA0.0/ UCA0RXD/UCA0SOMI/A1* P1.2/TA0.1/ UCA0TXD/UCA0SIMO/A2* PxIN.y EN To Module D PxIE.y PxIRQ.y Q EN Set PxIFG.y PxSEL.y PxIES.y Interrupt Edge Select * Note: MSP430G2x33 devices only. MSP430G2x03 devices have no ADC10. Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback 39 MSP430G2x33 MSP430G2x03 SLAS734D - APRIL 2011 - REVISED NOVEMBER 2011 www.ti.com Table 16. Port P1 (P1.0 to P1.2) Pin Functions PIN NAME (P1.x) CONTROL BITS / SIGNALS (1) x FUNCTION P1DIR.x P1SEL.x P1SEL2.x ADC10AE.x (INCH.y = 1) (2) P1.0/ P1.x (I/O) I: 0; O: 1 0 0 0 TA0CLK/ TA0.TACLK 0 1 0 0 ACLK 1 1 0 0 A0 / A0 X X X 1 (y = 0) Pin Osc Capacitive sensing X 0 1 0 P1.1/ P1.x (I/O) I: 0; O: 1 0 0 0 TA0.0/ TA0.0 1 1 0 0 TA0.CCI0A 0 1 0 0 UCA0RXD from USCI 1 1 0 UCA0SOMI from USCI 1 1 0 ACLK/ 0 (2) UCA0RXD/ 1 UCA0SOMI/ (2) A1 / A1 X X X 1 (y = 1) Pin Osc Capacitive sensing X 0 1 0 P1.2/ P1.x (I/O) I: 0; O: 1 0 0 0 TA0.1/ TA0.1 1 1 0 0 TA0.CCI1A 0 1 0 0 UCA0TXD from USCI 1 1 0 UCA0SIMO/ UCA0SIMO from USCI 1 1 0 A2 (2)/ A2 X X X 1 (y = 2) Pin Osc Capacitive sensing X 0 1 0 UCA0TXD/ (1) (2) 40 2 X = don't care MSP430G2x33 devices only Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated MSP430G2x33 MSP430G2x03 SLAS734D - APRIL 2011 - REVISED NOVEMBER 2011 www.ti.com Port P1 Pin Schematic: P1.3, Input/Output With Schmitt Trigger SREF2 * To ADC10 VREF- * VSS 0 1 To ADC10 * INCHx = y * ADC10AE0.y * PxSEL2.y PxSEL.y PxDIR.y 0,2,3 1 Direction 0: Input 1: Output PxSEL2.y PxSEL.y PxREN.y 0 1 1 0 1 PxSEL2.y PxSEL.y PxOUT.y From ADC10 * DVSS DVCC 0 1 1 0 1 2 Bus Keeper EN 3 P1.3/ADC10CLK*/ A3*/VREF-*/VEREF-* TAx.y TAxCLK PxIN.y EN To Module D PxIE.y PxIRQ.y Q Set PxIFG.y PxSEL.y PxIES.y EN Interrupt Edge Select * Note: MSP430G2x33 devices only. MSP430G2x03 devices have no ADC10. Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback 41 MSP430G2x33 MSP430G2x03 SLAS734D - APRIL 2011 - REVISED NOVEMBER 2011 www.ti.com Table 17. Port P1 (P1.3) Pin Functions PIN NAME (P1.x) CONTROL BITS / SIGNALS (1) x FUNCTION P1DIR.x P1SEL.x P1SEL2.x ADC10AE.x (INCH.x = 1) (2) 0 P1.3/ P1.x (I/O) I: 0; O: 1 0 0 ADC10CLK (2)/ ADC10CLK 1 1 0 0 A3 (2)/ A3 X X X 1 (y = 3) VREF- (2)/ 3 VREF- X X X 1 VEREF- (2)/ VEREF- X X X 1 Pin Osc Capacitive sensing X 0 1 0 (1) (2) 42 X = don't care MSP430G2x33 devices only Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated MSP430G2x33 MSP430G2x03 SLAS734D - APRIL 2011 - REVISED NOVEMBER 2011 www.ti.com Port P1 Pin Schematic: P1.4, Input/Output With Schmitt Trigger From/To ADC10 Ref+ * To ADC10 * INCHx = y * ADC10AE0.y * PxSEL.y PxDIR.y 0 1 Direction 0: Input 1: Output PxSEL2.y PxSEL.y PxREN.y 0 1 1 PxSEL2.y PxSEL.y 0 1 DVSS 0 1 DVCC PxOUT.y SMCLK 0 1 from Module 2 3 Bus Keeper EN 1 P1.4/SMCLK/UCB0STE/UCA0CLK/ VREF+/VEREF+/A4/TCK TAx.y TAxCLK PxIN.y EN To Module D PxIE.y PxIRQ.y EN Q Set PxIFG.y PxSEL.y PxIES.y Interrupt Edge Select From JTAG To JTAG * Note: MSP430G2x33 devices only. MSP430G2x03 devices have no ADC10. Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback 43 MSP430G2x33 MSP430G2x03 SLAS734D - APRIL 2011 - REVISED NOVEMBER 2011 www.ti.com Table 18. Port P1 (P1.4) Pin Functions CONTROL BITS / SIGNALS (1) PIN NAME (P1.x) x FUNCTION P1DIR.x P1SEL.x P1SEL2.x ADC10AE.x (INCH.x = 1) (2) JTAG Mode I: 0; O: 1 0 0 0 0 1 1 0 0 0 P1.4/ P1.x (I/O) SMCLK/ SMCLK UCB0STE/ UCB0STE from USCI 1 1 0 0 UCA0CLK/ UCA0CLK from USCI 1 1 0 0 VREF+ X X X 1 0 VEREF+ / VEREF+ X X X 1 0 A4 (2)/ A4 X X X 1 (y = 4) 0 TCK/ TCK X X X 0 1 Pin Osc Capacitive sensing X 0 1 0 0 VREF+ (2)/ (2) (1) (2) 44 4 X = don't care MSP430G2x33 devices only Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated MSP430G2x33 MSP430G2x03 SLAS734D - APRIL 2011 - REVISED NOVEMBER 2011 www.ti.com Port P1 Pin Schematic: P1.5 to P1.7, Input/Output With Schmitt Trigger To ADC10 * INCHx = y * ADC10AE0.y * PxSEL2.y PxSEL.y PxDIR.y 0 From Module 1 Direction 0: Input 1: Output 2 From Module 3 PxSEL2.y PxSEL.y PxREN.y 0 1 1 PxSEL2.y PxSEL.y 0 1 DVSS DVCC PxOUT.y 0 From Module 1 From Module 3 0 1 1 2 Bus Keeper EN TAx.y TAxCLK P1.5/TA0.0/UCB0CLK/ UCA0STE/A5*/TMS P1.6/TA0.1/UCB0SOMI/ UCB0SCL/A6*/TDI/TCLK P1.7/CAOUT/UCB0SIMO/ UCB0SDA/A7*/TDO/TDI PxIN.y EN To Module D PxIE.y PxIRQ.y EN Q Set PxIFG.y PxSEL.y PxIES.y Interrupt Edge Select From JTAG To JTAG * Note: MSP430G2x33 devices only. MSP430G2x03 devices have no ADC10. Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback 45 MSP430G2x33 MSP430G2x03 SLAS734D - APRIL 2011 - REVISED NOVEMBER 2011 www.ti.com Table 19. Port P1 (P1.5 to P1.7) Pin Functions CONTROL BITS / SIGNALS (1) PIN NAME (P1.x) P1DIR.x P1SEL.x P1SEL2.x ADC10AE.x (INCH.x = 1) (2) JTAG Mode I: 0; O: 1 0 0 0 0 1 1 0 0 0 UCB0CLK from USCI 1 1 0 0 UCA0STE from USCI 1 1 0 0 x FUNCTION P1.5/ P1.x (I/O) TA0.0/ TA0.0 UCB0CLK/ UCA0STE/ 5 A5 (2)/ A5 X X X 1 (y = 5) 0 TMS TMS X X X 0 1 Pin Osc Capacitive sensing X 0 1 0 0 P1.6/ P1.x (I/O) I: 0; O: 1 0 0 0 0 TA0.1/ TA0.1 1 1 0 0 0 UCB0SOMI from USCI 1 1 0 0 UCB0SCL from USCI 1 1 0 0 UCB0SOMI/ UCB0SCL/ 6 A6 (2)/ A6 X X X 1 (y = 6) 0 TDI/TCLK/ TDI/TCLK X X X 0 1 Pin Osc Capacitive sensing X 0 1 0 0 P1.7/ P1.x (I/O) I: 0; O: 1 0 0 0 0 UCB0SIMO/ UCB0SIMO from USCI 1 1 0 0 UCB0SDA/ UCB0SDA from USCI 1 1 0 0 A7 X X X 1 (y = 7) 0 TDO/TDI/ TDO/TDI X X X 0 1 Pin Osc Capacitive sensing X 0 1 0 0 A7 (2)/ (1) (2) 46 7 X = don't care MSP430G2x33 devices only Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated MSP430G2x33 MSP430G2x03 SLAS734D - APRIL 2011 - REVISED NOVEMBER 2011 www.ti.com Port P2 Pin Schematic: P2.0 to P2.5, Input/Output With Schmitt Trigger PxSEL.y PxDIR.y 0 1 Direction 0: Input 1: Output PxSEL2.y PxSEL.y PxREN.y 0 1 1 0 PxSEL2.y PxSEL.y PxOUT.y 0 From Timer 1 1 DVSS 0 DVCC 1 1 2 0 P2.0/TA1.0 P2.1/TA1.1 P2.2/TA1.1 P2.3/TA1.0 P2.4/TA1.2 P2.5/TA1.2 3 TAx.y TAxCLK PxIN.y EN To Module D PxIE.y PxIRQ.y EN Q Set PxIFG.y PxSEL.y PxIES.y Interrupt Edge Select Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback 47 MSP430G2x33 MSP430G2x03 SLAS734D - APRIL 2011 - REVISED NOVEMBER 2011 www.ti.com Table 20. Port P2 (P2.0 to P2.5) Pin Functions PIN NAME (P2.x) x FUNCTION CONTROL BITS / SIGNALS (1) P2DIR.x P2SEL.x P2SEL2.x P2.0/ P2.x (I/O) I: 0; O: 1 0 0 TA1.0/ Timer1_A3.CCI0A 0 1 0 Timer1_A3.TA0 1 1 0 Pin Osc Capacitive sensing X 0 1 P2.1/ P2.x (I/O) I: 0; O: 1 0 0 TA1.1/ Timer1_A3.CCI1A 0 1 0 Timer1_A3.TA1 1 1 0 0 1 Pin Osc Capacitive sensing P2.2/ P2.x (I/O) TA1.1/ Timer1_A3.CCI1B 2 X 0 1 I: 0; O: 1 0 0 0 1 0 Timer1_A3.TA1 1 1 0 Pin Osc Capacitive sensing X 0 1 P2.3/ P2.x (I/O) I: 0; O: 1 0 0 TA1.0/ Timer1_A3.CCI0B 0 1 0 3 Timer1_A3.TA0 1 1 0 Pin Osc Capacitive sensing X 0 1 P2.4/ P2.x (I/O) I: 0; O: 1 0 0 Timer1_A3.CCI2A 0 1 0 Timer1_A3.TA2 1 1 0 Pin Osc Capacitive sensing X 0 1 P2.5/ P2.x (I/O) I: 0; O: 1 0 0 TA1.2/ Timer1_A3.CCI2B 0 1 0 Timer1_A3.TA2 1 1 0 Capacitive sensing X 0 1 TA1.2/ 4 5 Pin Osc (1) 48 X = don't care Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated MSP430G2x33 MSP430G2x03 SLAS734D - APRIL 2011 - REVISED NOVEMBER 2011 www.ti.com Port P2 Pin Schematic: P2.6, Input/Output With Schmitt Trigger XOUT/P2.7 LF off PxSEL.6, PxSEL.7 BCSCTL3.LFXT1Sx = 11 0 1 LFXT1CLK PxSEL.y PxDIR.y 0 1 Direction 0: Input 1: Output PxSEL2.y PxSEL.y PxREN.y 0 1 1 0 1 PxSEL2.y PxSEL.y DVSS DVCC PxOUT.y 0 From Module 1 0 1 1 2 XIN/P2.6/TA0.1 3 TAx.y TAxCLK PxIN.y EN D To Module PxIE.y PxIRQ.y Q EN Set PxIFG.y PxSEL.y PxIES.y Copyright (c) 2011, Texas Instruments Incorporated Interrupt Edge Select Submit Documentation Feedback 49 MSP430G2x33 MSP430G2x03 SLAS734D - APRIL 2011 - REVISED NOVEMBER 2011 www.ti.com Table 21. Port P2 (P2.6) Pin Functions PIN NAME (P2.x) CONTROL BITS / SIGNALS (1) x FUNCTION XIN XIN P2.6 P2.x (I/O) P2DIR.x P2SEL.6 P2SEL.7 P2SEL2.6 P2SEL2.7 0 1 1 0 0 I: 0; O: 1 0 X 0 0 6 TA0.1 Timer0_A3.TA1 1 1 0 0 0 Pin Osc Capacitive sensing X 0 X 1 X (1) 50 X = don't care Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated MSP430G2x33 MSP430G2x03 SLAS734D - APRIL 2011 - REVISED NOVEMBER 2011 www.ti.com Port P2 Pin Schematic: P2.7, Input/Output With Schmitt Trigger XIN LF off PxSEL.6, PxSEL.7 BCSCTL3.LFXT1Sx = 11 0 1 LFXT1CLK from P2.6 PxSEL.y PxDIR.y 0 1 Direction 0: Input 1: Output PxSEL2.y PxSEL.y PxREN.y 0 1 1 0 1 PxSEL2.y PxSEL.y DVSS DVCC PxOUT.y 0 From Module 1 0 1 1 2 XOUT/P2.7 3 TAx.y TAxCLK PxIN.y EN D To Module PxIE.y PxIRQ.y Q EN Set PxIFG.y PxSEL.y PxIES.y Copyright (c) 2011, Texas Instruments Incorporated Interrupt Edge Select Submit Documentation Feedback 51 MSP430G2x33 MSP430G2x03 SLAS734D - APRIL 2011 - REVISED NOVEMBER 2011 www.ti.com Table 22. Port P2 (P2.7) Pin Functions PIN NAME (P2.x) CONTROL BITS / SIGNALS (1) x XOUT/ XOUT P2.7/ 7 Pin Osc (1) 52 FUNCTION P2.x (I/O) Capacitive sensing P2DIR.x P2SEL.6 P2SEL.7 P2SEL2.6 P2SEL2.7 1 1 1 0 0 I: 0; O: 1 0 X 0 0 X 0 X 1 X X = don't care Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated MSP430G2x33 MSP430G2x03 SLAS734D - APRIL 2011 - REVISED NOVEMBER 2011 www.ti.com Port P3 Pin Schematic: P3.0 to P3.7, Input/Output With Schmitt Trigger (RHB Package Only) PxSEL.y PxDIR.y 0 1 Direction 0: Input 1: Output PxSEL2.y PxSEL.y PxREN.y 0 1 1 PxSEL2.y PxSEL.y PxOUT.y From Module 0 1 DVSS DVCC 0 1 1 0 1 2 P3.0/TA0.2 P3.1/TA1.0 P3.2/TA1.1 P3.3/TA1.2 P3.4/TA0.0 P3.5/TA0.1 P3.6/TA0.2 P3.7/TA1CLK/CAOUT 3 TAx.y TAxCLK PxIN.y EN To Module D Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback 53 MSP430G2x33 MSP430G2x03 SLAS734D - APRIL 2011 - REVISED NOVEMBER 2011 www.ti.com Table 23. Port P3 (P3.0 to P3.7) Pin Functions (RHB Package Only) PIN NAME (P3.x) x FUNCTION CONTROL BITS / SIGNALS (1) P3DIR.x P3SEL.x P3SEL2.x P3.0/ P3.x (I/O) I: 0; O: 1 0 0 TA0.2/ Timer0_A3.CCI2A 0 1 0 Timer0_A3.TA2 1 1 0 Capacitive sensing X 0 1 0 Pin Osc P3.1/ P3.x (I/O) TA1.0/ 1 Pin Osc P3.2/ I: 0; O: 1 0 0 Timer1_A3.TA0 1 1 0 Capacitive sensing X 0 1 P3.x (I/O) TA1.1/ 2 Pin Osc P3.3/ I: 0; O: 1 0 0 Timer1_A3.TA1 1 1 0 Capacitive sensing X 0 1 P3.x (I/O) I: 0; O: 1 0 0 Timer1_A3.TA2 1 1 0 Pin Osc Capacitive sensing X 0 1 P3.4/ P3.x (I/O) I: 0; O: 1 0 0 TA1.2/ 3 TA0.0/ Timer0_A3.TA0 1 1 0 Pin Osc 4 Capacitive sensing X 0 1 P3.5/ P3.x (I/O) I: 0; O: 1 0 0 TA0.1/ Timer0_A3.TA1 1 1 0 Pin Osc 5 Capacitive sensing X 0 1 P3.6/ P3.x (I/O) I: 0; O: 1 0 0 TA0.2/ Timer0_A3.TA2 1 1 0 Pin Osc 6 Capacitive sensing X 0 1 P3.7/ P3.x (I/O) I: 0; O: 1 0 0 Timer1_A3.TACLK 0 1 0 Capacitive sensing X 0 1 TA1CLK/ Pin Osc (1) 54 7 X = don't care Submit Documentation Feedback Copyright (c) 2011, Texas Instruments Incorporated MSP430G2x33 MSP430G2x03 SLAS734D - APRIL 2011 - REVISED NOVEMBER 2011 www.ti.com REVISION HISTORY REVISION SLAS734 DESCRIPTION Production Data release SLAS734A Corrections to Control Bits / Signals column in Table 18 Corrections to Pin Name and Function columns in Table 23 SLAS734B Changed Storage temperature range limit in Absolute Maximum Ratings Added BSL functions to P1.1 and P1.5 in Table 2 Port P1 Pin Schematic, corrected pin name SLAS734C Changed Tstg, Programmed device, to -55C to 150C in Absolute Maximum Ratings. Changed TAG_ADC10_1 value to 0x10 in Table 10. SLAS734D Added AVCC (RHB package only, pin 29) to Table 2 Terminal Functions. Correct typo in P3.7/TA1CLK description in Table 2. Corrected pin number for PW28 Input and Output columns in Table 13. Changed all port schematics (added buffer after PxOUT.y mux) in Port Schematics. Copyright (c) 2011, Texas Instruments Incorporated Submit Documentation Feedback 55 PACKAGE OPTION ADDENDUM www.ti.com 14-Sep-2011 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) MSP430G2203IN20 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM MSP430G2203IPW20 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2203IPW20R ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2203IPW28 ACTIVE TSSOP PW 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2203IPW28R ACTIVE TSSOP PW 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2203IRHB32R ACTIVE QFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430G2203IRHB32T ACTIVE QFN RHB 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430G2233IN20 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM MSP430G2233IPW20 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2233IPW20R ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2233IPW28 ACTIVE TSSOP PW 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2233IPW28R ACTIVE TSSOP PW 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2233IRHB32R ACTIVE QFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430G2233IRHB32T ACTIVE QFN RHB 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430G2303IN20 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM MSP430G2303IPW20 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2303IPW20R ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2303IPW28 ACTIVE TSSOP PW 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Addendum-Page 1 Samples (Requires Login) PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 14-Sep-2011 Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) MSP430G2303IPW28R ACTIVE TSSOP PW 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2303IRHB32R ACTIVE QFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430G2303IRHB32T ACTIVE QFN RHB 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430G2333IN20 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM MSP430G2333IPW20 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2333IPW20R ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2333IPW28 ACTIVE TSSOP PW 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2333IPW28R ACTIVE TSSOP PW 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2333IRHB32R ACTIVE QFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430G2333IRHB32T ACTIVE QFN RHB 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430G2403IN20 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM MSP430G2403IPW20 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2403IPW20R ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2403IPW28 ACTIVE TSSOP PW 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2403IPW28R ACTIVE TSSOP PW 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2403IRHB32R ACTIVE QFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430G2403IRHB32T ACTIVE QFN RHB 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430G2433IN20 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM MSP430G2433IPW20 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM Addendum-Page 2 Samples (Requires Login) PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 14-Sep-2011 Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/ Ball Finish MSL Peak Temp (3) MSP430G2433IPW20R ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2433IPW28 ACTIVE TSSOP PW 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2433IPW28R ACTIVE TSSOP PW 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2433IRHB32R ACTIVE QFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430G2433IRHB32T ACTIVE QFN RHB 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430G2533IN20 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM MSP430G2533IPW20 ACTIVE TSSOP PW 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2533IPW20R ACTIVE TSSOP PW 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2533IPW28 ACTIVE TSSOP PW 28 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2533IPW28R ACTIVE TSSOP PW 28 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM MSP430G2533IRHB32R ACTIVE QFN RHB 32 3000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR MSP430G2533IRHB32T ACTIVE QFN RHB 32 250 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR Samples (Requires Login) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Addendum-Page 3 PACKAGE OPTION ADDENDUM www.ti.com 14-Sep-2011 Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. 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