MSP430G2203IPW20R - Texas Instruments

MSP430G2x33

MSP430G2x03

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SLAS734D –APRIL 2011–REVISED NOVEMBER 2011

MIXED SIGNAL MICROCONTROLLER

1FEATURES

•Low Supply-Voltage Range: 1.8 V to 3.6 V •Universal Serial Communication Interface

(USCI)

•Ultra-Low Power Consumption

–Enhanced UART Supporting Auto Baudrate

–Active Mode: 230 µA at 1 MHz, 2.2 V Detection (LIN)

–Standby Mode: 0.5 µA–IrDA Encoder and Decoder

–Off Mode (RAM Retention): 0.1 µA–Synchronous SPI

•Five Power-Saving Modes –I2C™

•Ultra-Fast Wake-Up From Standby Mode in •10-Bit 200-ksps Analog-to-Digital (A/D)

Less Than 1 µsConverter With Internal Reference,

•16-Bit RISC Architecture, 62.5-ns Instruction Sample-and-Hold, and Autoscan (See Table 1)

Cycle Time •Brownout Detector

•Basic Clock Module Configurations •Serial Onboard Programming,

–Internal Frequencies up to 16 MHz With No External Programming Voltage Needed,

Four Calibrated Frequency Programmable Code Protection by Security

–Internal Very-Low-Power Low-Frequency Fuse

(LF) Oscillator •On-Chip Emulation Logic With Spy-Bi-Wire

–32-kHz Crystal Interface

–External Digital Clock Source •Family Members are Summarized in Table 1

•Two 16-Bit Timer_A With Three •Package Options

Capture/Compare Registers –TSSOP: 20 Pin, 28 Pin

•Up to 24 Touch-Sense-Enabled I/O Pins –PDIP: 20 Pin

–QFN: 32 Pin

•For Complete Module Descriptions, See the

MSP430x2xx Family User’s Guide (SLAU144)

DESCRIPTION

The Texas Instruments MSP430 family of ultra-low-power microcontrollers consists of several devices featuring

different sets of peripherals targeted for various applications. The architecture, combined with five low-power

modes, is optimized to achieve extended battery life in portable measurement applications. The device features a

powerful 16-bit RISC CPU, 16-bit registers, and constant generators that contribute to maximum code efficiency.

The digitally controlled oscillator (DCO) allows wake-up from low-power modes to active mode in less than 1 µs.

The MSP430G2x03 and MSP430G2x33 series are ultra-low-power mixed signal microcontrollers with built-in

16-bit timers, up to 24 I/O touch-sense-enabled pins, and built-in communication capability using the universal

serial communication interface. In addition, the MSP430G2x33 family members have a 10-bit A/D converter. For

configuration details see Table 1.

Typical applications include low-cost sensor systems that capture analog signals, convert them to digital values,

and then process the data for display or for transmission to a host system.

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

MSP430G2x33

MSP430G2x03

SLAS734D –APRIL 2011–REVISED NOVEMBER 2011

www.ti.com

Table 1. Available Options(1)(2)

Flash RAM ADC10 USCI Package

Device BSL EEM Timer_A Clock I/O

(KB) (B) Channel A0/B0 Type

MSP430G2533IRHB32 24 32-QFN

LF,

MSP430G2533IPW28 24 28-TSSOP

1 1 16 512 2x TA3 8 1 DCO,

MSP430G2533IPW20 16 20-TSSOP

VLO

MSP430G2533IN20 16 20-PDIP

MSP430G2433IRHB32 24 32-QFN

LF,

MSP430G2433IPW28 24 28-TSSOP

1 1 8 512 2x TA3 8 1 DCO,

MSP430G2433IPW20 16 20-TSSOP

VLO

MSP430G2433IN20 16 20-PDIP

MSP430G2333IRHB32 24 32-QFN

LF,

MSP430G2333IPW28 24 28-TSSOP

1 1 4 256 2x TA3 8 1 DCO,

MSP430G2333IPW20 16 20-TSSOP

VLO

MSP430G2333IN20 16 20-PDIP

MSP430G2233IRHB32 24 32-QFN

LF,

MSP430G2233IPW28 24 28-TSSOP

1 1 2 256 2x TA3 8 1 DCO,

MSP430G2233IPW20 16 20-TSSOP

VLO

MSP430G2233IN20 16 20-PDIP

MSP430G2403IRHB32 24 32-QFN

LF,

MSP430G2403IPW28 24 28-TSSOP

1 1 8 512 2x TA3 - 1 DCO,

MSP430G2403IPW20 16 20-TSSOP

VLO

MSP430G2403IN20 16 20-PDIP

MSP430G2303IRHB32 24 32-QFN

LF,

MSP430G2303IPW28 24 28-TSSOP

1 1 4 256 2x TA3 - 1 DCO,

MSP430G2303IPW20 16 20-TSSOP

VLO

MSP430G2303IN20 16 20-PDIP

MSP430G2203IRHB32 24 32-QFN

LF,

MSP430G2203IPW28 24 28-TSSOP

1 1 2 256 2x TA3 - 1 DCO,

MSP430G2203IPW20 16 20-TSSOP

VLO

MSP430G2203IN20 16 20-PDIP

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

DVCC

P1.0/TA0CLK/ACLK/A0

P1.3/ADC10CLK/VREF-/VEREF-/A3

P2.0/TA1.0

P2.1/TA1.1

P2.2/TA1.1 11 P2.3/TA1.0

12 P2.4/TA1.2

13 P2.5/TA1.2

16 RST/NMI/SBWTDIO

17 TEST/SBWTCK

18 XOUT/P2.7

19 XIN/P2.6/TA0.1

20 DVSS

P1.6/TA0.1/ /TDI/TCLKUCB0SOMI/UCB0SCL/A6

P1.7/ /A7/TDO/TDIUCB0SIMO/UCB0SDA

P1.1/TA0.0/ A1/UCA0RXD/UCA0SOMI

P1.2/TA0.1/ A2/UCA0TXD/PUCA0SIMO

P1.4/SMCLK/ /TCK/VREF+/VEREF+/A4UCB0STE/UCA0CLK

P1.5/TA0.0/ A5/TMS/UCB0CLK/UCA0STE

N20

PW20

(TOP VIEW)

PW28

(TOP VIEW)

DVCC

P1.0/TA0CLK/ACLK/A0

P1.3/ADC10CLK/VREF-/VEREF-/A3

P3.0/TA0.2 9

P3.1/TA1.0

P2.0/TA1.0 19 P3.5/TA0.1

20 P3.6/TA0.2

21 P3.7/TA1CLK

24 RST/NMI/SBWTDIO

25 TEST/SBWTCK

26 XOUT/P2.7

27 XIN/P2.6/TA0.1

28 DVSS

P1.6/TA0.1/ TDI/TCLKUCB0SOMI/UCB0SCL/A6/

P1.7/ /A7/TDO/TDIUCB0SIMO/UCB0SDA

P1.1/TA0.0/ A1/UCA0RXD/UCA0SOMI

P1.2/TA0.1/ A2/UCA0TXD/PUCA0SIMO

P1.4/SMCLK/ TCK/VREF+/VEREF+/A4/UCB0STE/UCA0CLK

P1.5/TA0.0/ A5/TMS/UCB0CLK/UCA0STE

P2.2/TA1.1

P3.2/TA1.1

P3.3/TA1.2 15 P3.4/TA0.0

16 P2.3/TA1.0

17 P2.4/TA1.2

18 P2.5/TA1.2

P2.1/TA1.1

MSP430G2x33

MSP430G2x03

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SLAS734D –APRIL 2011–REVISED NOVEMBER 2011

Device Pinout, MSP430G2x03 and MSP430G2x33, 20-Pin Devices, TSSOP and PDIP

NOTE: ADC10 is available on MSP430G2x33 devices only.

NOTE: The pulldown resistors of port P3 should be enabled by setting P3REN.x = 1.

Device Pinout, MSP430G2x03 and MSP430G2x33, 28-Pin Devices, TSSOP

NOTE: ADC10 is available on MSP430G2x33 devices only.

RHB32

(TOP VIEW)

P2.0/TA1.0

P2.1/TA1.1

8NC

P2.2/TA1.1

P3.0/TA0.2

P3.1/TA1.0

P3.2/TA1.1

P3.3/TA1.2

P3.4/TA0.0

P3.5/TA0.1

P2.3/TA1.0

P2.4/TA1.2

P2.5/TA1.2

P3.6/TA0.2

P3.7/TA1CLK

23 RST/NMI/SBWTDIO

24 TEST/SBWTCK

XOUT/P2.7

XIN/P2.6/TA0.1

AVSS

DVSS

AVCC

DVCC

P1.0/TA0CLK/ACLK/A0/CA0

P1.3/ADC10CLK/VREF-/VEREF-/A3

P1.1/TA0.0/ A1/

UCA0RXD/UCA0SOMI

P1.2/TA0.1/ A2/UCA0TXD/UCA0SIMO

P1.4/SMCLK/ /TCK/VREF+/VEREF+/A4UCB0STE/UCA0CLK

P1.5/TA0.0/ A5/TMS/UCB0CLK/UCA0STE

P1.6/TA0.1/ /TDI/TCLKUCB0SOMI/UCB0SCL/A6

P1.7 /TDO/TDI/UCB0SIMO/UCB0SDA/A7

MSP430G2x33

MSP430G2x03

SLAS734D –APRIL 2011–REVISED NOVEMBER 2011

www.ti.com

Device Pinout, MSP430G2x03 and MSP430G2x33, 32-Pin Devices, QFN

NOTE: ADC10 is available on MSP430G2x33 devices only.

Clock

System

Brownout

Protection

RST/NMI

DVCC DVSS

MCLK

Watchdog

WDT+

15-Bit

Timer0_A3

3 CC

Registers

16MHz

CPU

incl. 16

Registers

Emulation

2BP

JTAG

Interface

SMCLK

ACLK

Port P1

8 I/O

Interrupt

capability

pullup/down

resistors

P1.x

P2.x

Port P2

8 I/O

Interrupt

capability

pullup/down

resistors

Spy-Bi-

Wire

Timer1_A3

3 CC

Registers

XIN XOUT

Port P3

8 I/O

pullup

pulldown

resistors

P3.x

8 8

RAM

512B

256B

Flash

16KB

8KB

4KB

2KB

USCI A0

UART/

LIN, IrDA,

SPI

USCI B0

SPI, I2C

ADC

10-Bit

8 Ch.

Autoscan

1 ch DMA

MDB

MAB

Clock

System

Brownout

Protection

RST/NMI

DVCC DVSS

MCLK

Watchdog

WDT+

15-Bit

Timer0_A3

3 CC

Registers

16MHz

CPU

incl. 16

Registers

Emulation

2BP

JTAG

Interface

SMCLK

ACLK

Port P1

8 I/O

Interrupt

capability

pullup/down

resistors

P1.x

P2.x

Port P2

8 I/O

Interrupt

capability

pullup/down

resistors

Spy-Bi-

Wire

Timer1_A3

3 CC

Registers

XIN XOUT

Port P3

8 I/O

pullup/

pulldown

resistors

P3.x

8 8

RAM

256B

Flash

8KB

4KB

2KB

USCI A0

UART/

LIN, IrDA,

SPI

USCI B0

SPI, I2C

MDB

MAB

MSP430G2x33

MSP430G2x03

www.ti.com

SLAS734D –APRIL 2011–REVISED NOVEMBER 2011

Functional Block Diagram, MSP430G2x33

NOTE: Port P3 is available on 28-pin and 32-pin devices only.

Functional Block Diagram, MSP430G2x03

NOTE: Port P3 is available on 28-pin and 32-pin devices only.

MSP430G2x33

MSP430G2x03

SLAS734D –APRIL 2011–REVISED NOVEMBER 2011

www.ti.com

Table 2. Terminal Functions

TERMINAL

NO. I/O DESCRIPTION

NAME PW20, PW28 RHB32

N20

P1.0/ General-purpose digital I/O pin

TA0CLK/ Timer0_A, clock signal TACLK input

2 2 31 I/O

ACLK/ ACLK signal output

A0 ADC10 analog input A0(1)

P1.1/ General-purpose digital I/O pin

TA0.0/ Timer0_A, capture: CCI0A input, compare: Out0 output / BSL transmit

UCA0RXD/ 3 3 1 I/O USCI_A0 receive data input in UART mode

UCA0SOMI/ USCI_A0 slave data out/master in SPI mode

A1 ADC10 analog input A1(1)

P1.2/ General-purpose digital I/O pin

TA0.1/ Timer0_A, capture: CCI1A input, compare: Out1 output

UCA0TXD/ 4 4 2 I/O USCI_A0 transmit data output in UART mode

UCA0SIMO/ USCI_A0 slave data in/master out in SPI mode

A2 ADC10 analog input A2(1)

P1.3/ General-purpose digital I/O pin

ADC10CLK/ ADC10, conversion clock output(1)

5 5 3 I/O

A3/ ADC10 analog input A3(1)

VREF-/VEREF- ADC10 negative reference voltage (1)

P1.4/ General-purpose digital I/O pin

SMCLK/ SMCLK signal output

UCB0STE/ USCI_B0 slave transmit enable

UCA0CLK/ 6 6 4 I/O USCI_A0 clock input/output

A4/ ADC10 analog input A4(1)

VREF+/VEREF+ ADC10 positive reference voltage(1)

TCK JTAG test clock, input terminal for device programming and test

P1.5/ General-purpose digital I/O pin

TA0.0/ Timer0_A, compare: Out0 output / BSL receive

UCB0CLK/ USCI_B0 clock input/output

7 7 5 I/O

UCA0STE/ USCI_A0 slave transmit enable

A5/ ADC10 analog input A5(1)

TMS JTAG test mode select, input terminal for device programming and test

P1.6/ General-purpose digital I/O pin

TA0.1/ Timer0_A, compare: Out1 output

A6/ ADC10 analog input A6(1)

14 22 21 I/O

UCB0SOMI/ USCI_B0 slave out/master in SPI mode,

UCB0SCL/ USCI_B0 SCL I2C clock in I2C mode

TDI/TCLK JTAG test data input or test clock input during programming and test

P1.7/ General-purpose digital I/O pin

A7/ ADC10 analog input A7(1)

UCB0SIMO/ USCI_B0 slave in/master out in SPI mode

15 23 22 I/O

UCB0SDA/ USCI_B0 SDA I2C data in I2C mode

TDO/TDI JTAG test data output terminal or test data input during programming and

test(2)

(1) MSP430G2x33 devices only

(2) TDO or TDI is selected via JTAG instruction.

MSP430G2x33

MSP430G2x03

www.ti.com

SLAS734D –APRIL 2011–REVISED NOVEMBER 2011

Table 2. Terminal Functions (continued)

TERMINAL

NO. I/O DESCRIPTION

NAME PW20, PW28 RHB32

N20

P2.0/ General-purpose digital I/O pin

8 10 9 I/O

TA1.0 Timer1_A, capture: CCI0A input, compare: Out0 output

P2.1/ General-purpose digital I/O pin

9 11 10 I/O

TA1.1 Timer1_A, capture: CCI1A input, compare: Out1 output

P2.2/ General-purpose digital I/O pin

10 12 11 I/O

TA1.1 Timer1_A, capture: CCI1B input, compare: Out1 output

P2.3/ General-purpose digital I/O pin

11 16 15 I/O

TA1.0 Timer1_A, capture: CCI0B input, compare: Out0 output

P2.4/ General-purpose digital I/O pin

12 17 16 I/O

TA1.2 Timer1_A, capture: CCI2A input, compare: Out2 output

P2.5/ General-purpose digital I/O pin

13 18 17 I/O

TA1.2 Timer1_A, capture: CCI2B input, compare: Out2 output

XIN/ Input terminal of crystal oscillator

P2.6/ 19 27 26 I/O General-purpose digital I/O pin

TA0.1 Timer0_A, compare: Out1 output

XOUT/ Output terminal of crystal oscillator(3)

18 26 25 I/O

P2.7 General-purpose digital I/O pin

P3.0/ General-purpose digital I/O pin

- 9 7 I/O

TA0.2 Timer0_A, capture: CCI2A input, compare: Out2 output

P3.1/ General-purpose digital I/O pin

- 8 6 I/O

TA1.0 Timer1_A, compare: Out0 output

P3.2/ General-purpose digital I/O pin

- 13 12 I/O

TA1.1 Timer1_A, compare: Out1 output

P3.3/ General-purpose digital I/O

- 14 13 I/O

TA1.2 Timer1_A, compare: Out2 output

P3.4/ General-purpose digital I/O

- 15 14 I/O

TA0.0 Timer0_A, compare: Out0 output

P3.5/ General-purpose digital I/O

- 19 18 I/O

TA0.1 Timer0_A, compare: Out1 output

P3.6/ General-purpose digital I/O

- 20 19 I/O

TA0.2 Timer0_A, compare: Out2 output

P3.7/ General-purpose digital I/O

- 21 20 I/O

TA1CLK Timer1_A, clock signal TACLK input

RST/ Reset

NMI/ 16 24 23 I Nonmaskable interrupt input

SBWTDIO Spy-Bi-Wire test data input/output during programming and test

TEST/ Selects test mode for JTAG pins on Port 1. The device protection fuse is

connected to TEST.

17 25 24 I

SBWTCK Spy-Bi-Wire test clock input during programming and test

AVCC NA NA 29 NA Analog supply voltage

DVCC 1 1 30 NA Digital supply voltage

DVSS 20 28 27, 28 NA Ground reference

NC NA NA 8, 32 NA Not connected

(3) If XOUT/P2.7 is used as an input, excess current will flow until P2SEL.7 is cleared. This is due to the oscillator output driver connection

to this pad after reset.

MSP430G2x33

MSP430G2x03

SLAS734D –APRIL 2011–REVISED NOVEMBER 2011

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Table 2. Terminal Functions (continued)

TERMINAL

NO. I/O DESCRIPTION

NAME PW20, PW28 RHB32

N20

QFN Pad NA NA Pad NA QFN package pad connection to VSS recommended.

Program Counter PC/R0

Stack Pointer SP/R1

Status Register SR/CG1/R2

Constant Generator CG2/R3

General-Purpose Register R4

General-Purpose Register R5

General-Purpose Register R6

General-Purpose Register R7

General-Purpose Register R8

General-Purpose Register R9

General-Purpose Register R10

General-Purpose Register R11

General-Purpose Register R12

General-Purpose Register R13

General-Purpose Register R15

General-Purpose Register R14

MSP430G2x33

MSP430G2x03

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SLAS734D –APRIL 2011–REVISED NOVEMBER 2011

SHORT-FORM DESCRIPTION

CPU

The MSP430 CPU has a 16-bit RISC architecture

that is highly transparent to the application. All

operations, other than program-flow instructions, are

performed as register operations in conjunction with

seven addressing modes for source operand and four

addressing modes for destination operand.

The CPU is integrated with 16 registers that provide

reduced instruction execution time. The

cycle of the CPU clock.

Four of the registers, R0 to R3, are dedicated as

program counter, stack pointer, status register, and

constant generator, respectively. The remaining

registers are general-purpose registers.

Peripherals are connected to the CPU using data,

address, and control buses, and can be handled with

all instructions.

The instruction set consists of the original 51

instructions with three formats and seven address

modes and additional instructions for the expanded

address range. Each instruction can operate on word

and byte data.

Instruction Set

The instruction set consists of 51 instructions with

three formats and seven address modes. Each

instruction can operate on word and byte data.

Table 3 shows examples of the three types of

instruction formats; Table 4 shows the address

modes.

Table 3. Instruction Word Formats

INSTRUCTION FORMAT EXAMPLE OPERATION

Dual operands, source-destination ADD R4,R5 R4 + R5 --->R5

Single operands, destination only CALL R8 PC -->(TOS), R8-->PC

Relative jump, un/conditional JNE Jump-on-equal bit = 0

Table 4. Address Mode Descriptions(1)

ADDRESS MODE S D SYNTAX EXAMPLE OPERATION

Indexed ✓ ✓ MOV X(Rn),Y(Rm) MOV 2(R5),6(R6) M(2+R5) -- -->M(6+R6)

Symbolic (PC relative) ✓ ✓ MOV EDE,TONI M(EDE) -- -->M(TONI)

Absolute ✓ ✓ MOV &MEM,&TCDAT M(MEM) -- -->M(TCDAT)

Indirect ✓MOV @Rn,Y(Rm) MOV @R10,Tab(R6) M(R10) -- -->M(Tab+R6)

M(R10) -- -->R11

Indirect autoincrement ✓MOV @Rn+,Rm MOV @R10+,R11 R10 + 2-- -->R10

Immediate ✓MOV #X,TONI MOV #45,TONI #45 -- -->M(TONI)

(1) S = source, D = destination

MSP430G2x33

MSP430G2x03

SLAS734D –APRIL 2011–REVISED NOVEMBER 2011

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Operating Modes

The MSP430 has one active mode and five software selectable low-power modes of operation. An interrupt

event can wake up the device from any of the low-power modes, service the request, and restore back to the

low-power mode on return from the interrupt program.

The following six operating modes can be configured by software:

•Active mode (AM)

–All clocks are active

•Low-power mode 0 (LPM0)

–CPU is disabled

–ACLK and SMCLK remain active, MCLK is disabled

•Low-power mode 1 (LPM1)

–CPU is disabled

–ACLK and SMCLK remain active, MCLK is disabled

–DCO's dc generator is disabled if DCO not used in active mode

•Low-power mode 2 (LPM2)

–CPU is disabled

–MCLK and SMCLK are disabled

–DCO's dc generator remains enabled

–ACLK remains active

•Low-power mode 3 (LPM3)

–CPU is disabled

–MCLK and SMCLK are disabled

–DCO's dc generator is disabled

–ACLK remains active

•Low-power mode 4 (LPM4)

–CPU is disabled

–ACLK is disabled

–MCLK and SMCLK are disabled

–DCO's dc generator is disabled

–Crystal oscillator is stopped

MSP430G2x33

MSP430G2x03

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SLAS734D –APRIL 2011–REVISED NOVEMBER 2011

Interrupt Vector Addresses

The interrupt vectors and the power-up starting address are located in the address range 0FFFFh to 0FFC0h.

The vector contains the 16-bit address of the appropriate interrupt handler instruction sequence.

If the reset vector (located at address 0FFFEh) contains 0FFFFh (for example, flash is not programmed), the

CPU goes into LPM4 immediately after power-up.

Table 5. Interrupt Sources, Flags, and Vectors

SYSTEM WORD

INTERRUPT SOURCE INTERRUPT FLAG PRIORITY

INTERRUPT ADDRESS

Power-Up PORIFG

External Reset RSTIFG

Watchdog Timer+ WDTIFG Reset 0FFFEh 31, highest

Flash key violation KEYV(2)

PC out-of-range(1)

NMI NMIIFG (non)-maskable

Oscillator fault OFIFG (non)-maskable 0FFFCh 30

Flash memory access violation ACCVIFG(2)(3) (non)-maskable

Timer1_A3 TACCR0 CCIFG(4) maskable 0FFFAh 29

Timer1_A3 TACCR2 TACCR1 CCIFG, TAIFG(2)(4) maskable 0FFF8h 28

0FFF6h 27

Watchdog Timer+ WDTIFG maskable 0FFF4h 26

Timer0_A3 TACCR0 CCIFG(4) maskable 0FFF2h 25

Timer0_A3 TACCR2 TACCR1 CCIFG, TAIFG maskable 0FFF0h 24

(5)(4)

USCI_A0/USCI_B0 receive UCA0RXIFG, UCB0RXIFG(2)(5) maskable 0FFEEh 23

USCI_B0 I2C status

USCI_A0/USCI_B0 transmit UCA0TXIFG, UCB0TXIFG(2)(6) maskable 0FFECh 22

USCI_B0 I2C receive/transmit

ADC10 ADC10IFG(4) maskable 0FFEAh 21

(MSP430G2x33 only) 0FFE8h 20

I/O Port P2 (up to eight flags) P2IFG.0 to P2IFG.7(2)(4) maskable 0FFE6h 19

I/O Port P1 (up to eight flags) P1IFG.0 to P1IFG.7(2)(4) maskable 0FFE4h 18

0FFE2h 17

0FFE0h 16

See (7) 0FFDEh 15

See (8) 0FFDEh to 14 to 0, lowest

0FFC0h

(1) A reset is generated if the CPU tries to fetch instructions from within the module register memory address range (0h to 01FFh) or from

within unused address ranges.

(2) Multiple source flags

(3) (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot.

(4) Interrupt flags are located in the module.

(5) In SPI mode: UCB0RXIFG. In I2C mode: UCALIFG, UCNACKIFG, ICSTTIFG, UCSTPIFG.

(6) In UART/SPI mode: UCB0TXIFG. In I2C mode: UCB0RXIFG, UCB0TXIFG.

(7) This location is used as bootstrap loader security key (BSLSKEY). A 0xAA55 at this location disables the BSL completely. A zero (0h)

disables the erasure of the flash if an invalid password is supplied.

(8) The interrupt vectors at addresses 0FFDEh to 0FFC0h are not used in this device and can be used for regular program code if

necessary.

MSP430G2x33

MSP430G2x03

SLAS734D –APRIL 2011–REVISED NOVEMBER 2011

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Special Function Registers (SFRs)

Most interrupt and module enable bits are collected into the lowest address space. Special function register bits

not allocated to a functional purpose are not physically present in the device. Simple software access is provided

with this arrangement.

Legend rw: Bit can be read and written.

rw-0,1: Bit can be read and written. It is reset or set by PUC.

rw-(0,1): Bit can be read and written. It is reset or set by POR.

SFR bit is not present in device.

Table 6. Interrupt Enable Register 1 and 2

Address 76543210

00h ACCVIE NMIIE OFIE WDTIE

rw-0 rw-0 rw-0 rw-0

WDTIE Watchdog Timer interrupt enable. Inactive if watchdog mode is selected. Active if Watchdog Timer is configured in

interval timer mode.

OFIE Oscillator fault interrupt enable

NMIIE (Non)maskable interrupt enable

ACCVIE Flash access violation interrupt enable

Address 76543210

01h UCB0TXIE UCB0RXIE UCA0TXIE UCA0RXIE

rw-0 rw-0 rw-0 rw-0

UCA0RXIE USCI_A0 receive interrupt enable

UCA0TXIE USCI_A0 transmit interrupt enable

UCB0RXIE USCI_B0 receive interrupt enable

UCB0TXIE USCI_B0 transmit interrupt enable

Table 7. Interrupt Flag Register 1 and 2

Address 76543210

02h NMIIFG RSTIFG PORIFG OFIFG WDTIFG

rw-0 rw-(0) rw-(1) rw-1 rw-(0)

WDTIFG Set on watchdog timer overflow (in watchdog mode) or security key violation.

Reset on VCC power-on or a reset condition at the RST/NMI pin in reset mode.

OFIFG Flag set on oscillator fault.

PORIFG Power-On Reset interrupt flag. Set on VCC power-up.

RSTIFG External reset interrupt flag. Set on a reset condition at RST/NMI pin in reset mode. Reset on VCC power-up.

NMIIFG Set via RST/NMI pin

Address 76543210

03h UCB0TXIFG UCB0RXIFG UCA0TXIFG UCA0RXIFG

rw-1 rw-0 rw-1 rw-0

UCA0RXIFG USCI_A0 receive interrupt flag

UCA0TXIFG USCI_A0 transmit interrupt flag

UCB0RXIFG USCI_B0 receive interrupt flag

UCB0TXIFG USCI_B0 transmit interrupt flag

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Memory Organization

Table 8. Memory Organization

MSP430G2233 MSP430G2333 MSP430G2433 MSP430G2533

MSP430G2203 MSP430G2303 MSP430G2403

Memory Size 2kB 4kB 8kB 16kB

Main: interrupt vector Flash 0xFFFF to 0xFFC0 0xFFFF to 0xFFC0 0xFFFF to 0xFFC0 0xFFFF to 0xFFC0

Main: code memory Flash 0xFFFF to 0xF800 0xFFFF to 0xF000 0xFFFF to 0xE000 0xFFFF to 0xC000

Information memory Size 256 Byte 256 Byte 256 Byte 256 Byte

Flash 010FFh to 01000h 010FFh to 01000h 010FFh to 01000h 010FFh to 01000h

RAM Size 256 Byte 256 Byte 512 Byte 512 Byte

0x02FF to 0x0200 0x02FF to 0x0200 0x03FF to 0x0200 0x03FF to 0x0200

Peripherals 16-bit 01FFh to 0100h 01FFh to 0100h 01FFh to 0100h 01FFh to 0100h

8-bit 0FFh to 010h 0FFh to 010h 0FFh to 010h 0FFh to 010h

8-bit SFR 0Fh to 00h 0Fh to 00h 0Fh to 00h 0Fh to 00h

Bootstrap Loader (BSL)

The MSP430 BSL enables users to program the flash memory or RAM using a UART serial interface. Access to

the MSP430 memory via the BSL is protected by user-defined password. For complete description of the

features of the BSL and its implementation, see the MSP430 Programming Via the Bootstrap Loader User's

Guide (SLAU319).

Table 9. BSL Function Pins

20-PIN PW PACKAGE

BSL FUNCTION 28-PIN PACKAGE PW 32-PIN PACKAGE RHB

20-PIN N PACKAGE

Data transmit 3 - P1.1 3 - P1.1 1 - P1.1

Data receive 7 - P1.5 7 - P1.5 5 - P1.5

Flash Memory

The flash memory can be programmed via the Spy-Bi-Wire/JTAG port or in-system by the CPU. The CPU can

perform single-byte and single-word writes to the flash memory. Features of the flash memory include:

•Flash memory has n segments of main memory and four segments of information memory (A to D) of

64 bytes each. Each segment in main memory is 512 bytes in size.

•Segments 0 to n may be erased in one step, or each segment may be individually erased.

•Segments A to D can be erased individually or as a group with segments 0 to n. Segments A to D are also

called information memory.

•Segment A contains calibration data. After reset segment A is protected against programming and erasing. It

can be unlocked but care should be taken not to erase this segment if the device-specific calibration data is

required.

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Peripherals

Peripherals are connected to the CPU through data, address, and control buses and can be handled using all

instructions. For complete module descriptions, see the MSP430x2xx Family User's Guide (SLAU144).

Oscillator and System Clock

The clock system is supported by the basic clock module that includes support for a 32768-Hz watch crystal

oscillator, an internal very-low-power low-frequency oscillator and an internal digitally controlled oscillator (DCO).

The basic clock module is designed to meet the requirements of both low system cost and low power

consumption. The internal DCO provides a fast turn-on clock source and stabilizes in less than 1 µs. The basic

clock module provides the following clock signals:

•Auxiliary clock (ACLK), sourced either from a 32768-Hz watch crystal or the internal LF oscillator.

•Main clock (MCLK), the system clock used by the CPU.

•Sub-Main clock (SMCLK), the sub-system clock used by the peripheral modules.

The DCO settings to calibrate the DCO output frequency are stored in the information memory segment A.

Calibration Data Stored in Information Memory Segment A

Calibration data is stored for both the DCO and for ADC10 organized in a tag-length-value structure.

Table 10. Tags Used by the ADC Calibration Tags

NAME ADDRESS VALUE DESCRIPTION

DCO frequency calibration at VCC = 3 V and TA= 30°C at

TAG_DCO_30 0x10F6 0x01 calibration

TAG_ADC10_1 0x10DA 0x10 ADC10_1 calibration tag

TAG_EMPTY - 0xFE Identifier for empty memory areas

Table 11. Labels Used by the ADC Calibration Tags

ADDRESS

LABEL SIZE CONDITION AT CALIBRATION / DESCRIPTION

OFFSET

CAL_ADC_25T85 0x0010 word INCHx = 0x1010, REF2_5 = 1, TA= 85°C

CAL_ADC_25T30 0x000E word INCHx = 0x1010, REF2_5 = 1, TA= 30°C

CAL_ADC_25VREF_FACTOR 0x000C word REF2_5 = 1, TA= 30°C, IVREF+ = 1 mA

CAL_ADC_15T85 0x000A word INCHx = 0x1010, REF2_5 = 0, TA= 85°C

CAL_ADC_15T30 0x0008 word INCHx = 0x1010, REF2_5 = 0, TA= 30°C

CAL_ADC_15VREF_FACTOR 0x0006 word REF2_5 = 0, TA= 30°C, IVREF+ = 0.5 mA

CAL_ADC_OFFSET 0x0004 word External VREF = 1.5 V, fADC10CLK = 5 MHz

CAL_ADC_GAIN_FACTOR 0x0002 word External VREF = 1.5 V, fADC10CLK = 5 MHz

CAL_BC1_1MHZ 0x0009 byte -

CAL_DCO_1MHZ 0x0008 byte -

CAL_BC1_8MHZ 0x0007 byte -

CAL_DCO_8MHZ 0x0006 byte -

CAL_BC1_12MHZ 0x0005 byte -

CAL_DCO_12MHZ 0x0004 byte -

CAL_BC1_16MHZ 0x0003 byte -

CAL_DCO_16MHZ 0x0002 byte -

Brownout

The brownout circuit is implemented to provide the proper internal reset signal to the device during power on and

power off.

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Digital I/O

Up to three 8-bit I/O ports are implemented:

•All individual I/O bits are independently programmable.

•Any combination of input, output, and interrupt condition (port P1 and port P2 only) is possible.

•Edge-selectable interrupt input capability for all bits of port P1 and port P2 (if available).

•Read/write access to port-control registers is supported by all instructions.

•Each I/O has an individually programmable pullup/pulldown resistor.

•Each I/O has an individually programmable pin oscillator enable bit to enable low-cost touch sensing.

WDT+ Watchdog Timer

The primary function of the watchdog timer (WDT+) module is to perform a controlled system restart after a

software problem occurs. If the selected time interval expires, a system reset is generated. If the watchdog

function is not needed in an application, the module can be disabled or configured as an interval timer and can

generate interrupts at selected time intervals.

Timer_A3 (TA0, TA1)

Timer0_A3 and Timer1_A3 are 16-bit timers/counters with three capture/compare registers. Timer_A3 can

support multiple capture/compares, PWM outputs, and interval timing. Timer_A3 also has extensive interrupt

capabilities. Interrupts may be generated from the counter on overflow conditions and from each of the

capture/compare registers.

Table 12. Timer0_A3 Signal Connections

INPUT PIN NUMBER DEVICE MODULE MODULE OUTPUT PIN NUMBER

MODULE

INPUT INPUT OUTPUT

BLOCK

PW20, N20 PW28 RHB32 PW20, N20 PW28 RHB32

SIGNAL NAME SIGNAL

P1.0-2 P1.0-2 P1.0-31 TACLK TACLK

ACLK ACLK Timer NA

SMCLK SMCLK

PinOsc PinOsc PinOsc TACLK INCLK

P1.1-3 P1.1-3 P1.1-1 TA0.0 CCI0A P1.1-3 P1.1-3 P1.1-1

ACLK CCI0B P1.5-7 P1.5-7 P1.5-5

CCR0 TA0

VSS GND - P3.4-15 P3.4-14

VCC VCC

P1.2-4 P1.2-4 P1.2-2 TA0.1 CCI1A P1.2-4 P1.2-4 P1.2-2

CAOUT CCI1B P1.6-14 P1.6-22 P1.6-21

CCR1 TA1

VSS GND P2.6-19 P2.6-27 P2.6-26

VCC VCC - P3.5-19 P3.5-18

- P3.0-9 P3.0-7 TA0.2 CCI2A - P3.0-9 P3.0-7

PinOsc PinOsc PinOsc TA0.2 CCI2B - P3.6-20 P3.6-19

CCR2 TA2

VSS GND

VCC VCC

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Table 13. Timer1_A3 Signal Connections

INPUT PIN NUMBER DEVICE MODULE MODULE OUTPUT PIN NUMBER

MODULE

INPUT INPUT OUTPUT

BLOCK

PW20, N20 PW28 RHB32 PW20, N20 PW28 RHB32

SIGNAL NAME SIGNAL

- P3.7-21 P3.7-20 TACLK TACLK

ACLK ACLK Timer NA

SMCLK SMCLK

- P3.7-21 P3.7-20 TACLK INCLK

P2.0-8 P2.0-10 P2.0-9 TA1.0 CCI0A P2.0-8 P2.0-10 P2.0-9

P2.3-11 P2.3-16 P2.3-12 TA1.0 CCI0B P2.3-11 P2.3-16 P2.3-15

CCR0 TA0

VSS GND P3.1-8 P3.1-6

VCC VCC

P2.1-9 P2.1-11 P2.1-10 TA1.1 CCI1A P2.1-9 P2.1-11 P2.1-10

P2.2-10 P2.2-12 P2.2-11 TA1.1 CCI1B P2.2-10 P2.2-12 P2.2-11

CCR1 TA1

VSS GND P3.2-13 P3.2-12

VCC VCC

P2.4-12 P2.4-17 P2.4-16 TA1.2 CCI2A P2.4-12 P2.4-17 P2.4-16

P2.5-13 P2.5-18 P2.5-17 TA1.2 CCI2B P2.5-13 P2.5-18 P2.5-17

CCR2 TA2

VSS GND P3.3-14 P3.3-13

VCC VCC

Universal Serial Communications Interface (USCI)

The USCI module is used for serial data communication. The USCI module supports synchronous

communication protocols such as SPI (3 or 4 pin) and I2C, and asynchronous communication protocols such as

UART, enhanced UART with automatic baudrate detection (LIN), and IrDA. Not all packages support the USCI

functionality.

USCI_A0 provides support for SPI (3 or 4 pin), UART, enhanced UART, and IrDA.

USCI_B0 provides support for SPI (3 or 4 pin) and I2C.

ADC10 (MSP430G2x33 Only)

The ADC10 module supports fast 10-bit analog-to-digital conversions. The module implements a 10-bit SAR

core, sample select control, reference generator, and data transfer controller (DTC) for automatic conversion

result handling, allowing ADC samples to be converted and stored without any CPU intervention.

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Peripheral File Map

Table 14. Peripherals With Word Access

MODULE REGISTER DESCRIPTION OFFSET

NAME

ADC10 ADC data transfer start address ADC10SA 1BCh

(MSP430G2x33 devices only) ADC memory ADC10MEM 1B4h

ADC control register 1 ADC10CTL1 1B2h

ADC control register 0 ADC10CTL0 1B0h

Timer1_A3 Capture/compare register TACCR2 0196h

Capture/compare register TACCR1 0194h

Capture/compare register TACCR0 0192h

Timer_A register TAR 0190h

Capture/compare control TACCTL2 0186h

Capture/compare control TACCTL1 0184h

Capture/compare control TACCTL0 0182h

Timer_A control TACTL 0180h

Timer_A interrupt vector TAIV 011Eh

Timer0_A3 Capture/compare register TACCR2 0176h

Capture/compare register TACCR1 0174h

Capture/compare register TACCR0 0172h

Timer_A register TAR 0170h

Capture/compare control TACCTL2 0166h

Capture/compare control TACCTL1 0164h

Capture/compare control TACCTL0 0162h

Timer_A control TACTL 0160h

Timer_A interrupt vector TAIV 012Eh

Flash Memory Flash control 3 FCTL3 012Ch

Flash control 2 FCTL2 012Ah

Flash control 1 FCTL1 0128h

Watchdog Timer+ Watchdog/timer control WDTCTL 0120h

Table 15. Peripherals With Byte Access

MODULE REGISTER DESCRIPTION OFFSET

NAME

USCI_B0 USCI_B0 transmit buffer UCB0TXBUF 06Fh

USCI_B0 receive buffer UCB0RXBUF 06Eh

USCI_B0 status UCB0STAT 06Dh

USCI B0 I2C Interrupt enable UCB0CIE 06Ch

USCI_B0 bit rate control 1 UCB0BR1 06Bh

USCI_B0 bit rate control 0 UCB0BR0 06Ah

USCI_B0 control 1 UCB0CTL1 069h

USCI_B0 control 0 UCB0CTL0 068h

USCI_B0 I2C slave address UCB0SA 011Ah

USCI_B0 I2C own address UCB0OA 0118h

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Table 15. Peripherals With Byte Access (continued)

MODULE REGISTER DESCRIPTION OFFSET

NAME

USCI_A0 USCI_A0 transmit buffer UCA0TXBUF 067h

USCI_A0 receive buffer UCA0RXBUF 066h

USCI_A0 status UCA0STAT 065h

USCI_A0 modulation control UCA0MCTL 064h

USCI_A0 baud rate control 1 UCA0BR1 063h

USCI_A0 baud rate control 0 UCA0BR0 062h

USCI_A0 control 1 UCA0CTL1 061h

USCI_A0 control 0 UCA0CTL0 060h

USCI_A0 IrDA receive control UCA0IRRCTL 05Fh

USCI_A0 IrDA transmit control UCA0IRTCTL 05Eh

USCI_A0 auto baud rate control UCA0ABCTL 05Dh

ADC10 ADC analog enable 0 ADC10AE0 04Ah

(MSP430G2x33 devices only) ADC analog enable 1 ADC10AE1 04Bh

ADC data transfer control register 1 ADC10DTC1 049h

ADC data transfer control register 0 ADC10DTC0 048h

Basic Clock System+ Basic clock system control 3 BCSCTL3 053h

Basic clock system control 2 BCSCTL2 058h

Basic clock system control 1 BCSCTL1 057h

DCO clock frequency control DCOCTL 056h

Port P3 Port P3 selection 2. pin P3SEL2 043h

(28-pin PW and 32-pin RHB only) Port P3 resistor enable P3REN 010h

Port P3 selection P3SEL 01Bh

Port P3 direction P3DIR 01Ah

Port P3 output P3OUT 019h

Port P3 input P3IN 018h

Port P2 Port P2 selection 2 P2SEL2 042h

Port P2 resistor enable P2REN 02Fh

Port P2 selection P2SEL 02Eh

Port P2 interrupt enable P2IE 02Dh

Port P2 interrupt edge select P2IES 02Ch

Port P2 interrupt flag P2IFG 02Bh

Port P2 direction P2DIR 02Ah

Port P2 output P2OUT 029h

Port P2 input P2IN 028h

Port P1 Port P1 selection 2 P1SEL2 041h

Port P1 resistor enable P1REN 027h

Port P1 selection P1SEL 026h

Port P1 interrupt enable P1IE 025h

Port P1 interrupt edge select P1IES 024h

Port P1 interrupt flag P1IFG 023h

Port P1 direction P1DIR 022h

Port P1 output P1OUT 021h

Port P1 input P1IN 020h

Special Function SFR interrupt flag 2 IFG2 003h

SFR interrupt flag 1 IFG1 002h

SFR interrupt enable 2 IE2 001h

SFR interrupt enable 1 IE1 000h

Supply voltage range,

during flash memory

programming

Supply voltage range,

during program execution

Legend:

16 MHz

System Frequency - MHz

12 MHz

6 MHz

1.8 V

Supply Voltage - V

3.3 V

2.7 V

2.2 V 3.6 V

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Absolute Maximum Ratings(1)

Voltage applied at VCC to VSS –0.3 V to 4.1 V

Voltage applied to any pin(2) –0.3 V to VCC + 0.3 V

Diode current at any device pin ±2 mA

Unprogrammed device –55°C to 150°C

Storage temperature range, Tstg (3) Programmed device –55°C to 150°C

(1) Stresses beyond those listed under "absolute maximum ratings"may cause permanent damage to the device. These are stress ratings

only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating

conditions"is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages referenced to VSS. The JTAG fuse-blow voltage, VFB, is allowed to exceed the absolute maximum rating. The voltage is

applied to the TEST pin when blowing the JTAG fuse.

(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow

temperatures not higher than classified on the device label on the shipping boxes or reels.

Recommended Operating Conditions MIN NOM MAX UNIT

During program execution 1.8 3.6

VCC Supply voltage V

During flash 2.2 3.6

programming/erase

VSS Supply voltage 0 V

I version -40 85

TAOperating free-air temperature °C

T version -40 105

VCC = 1.8 V, dc 6

Duty cycle = 50% ±10%

Processor frequency (maximum MCLK frequency using the VCC = 2.7 V,

fSYSTEM dc 12 MHz

USART module)(1)(2) Duty cycle = 50% ±10%

VCC = 3.3 V, dc 16

Duty cycle = 50% ±10%

(1) The MSP430 CPU is clocked directly with MCLK. Both the high and low phase of MCLK must not exceed the pulse width of the

specified maximum frequency.

(2) Modules might have a different maximum input clock specification. See the specification of the respective module in this data sheet.

Note: Minimum processor frequency is defined by system clock. Flash program or erase operations require a minimum VCC

of 2.2 V.

Figure 1. Safe Operating Area

0.0

1.0

2.0

3.0

4.0

5.0

1.5 2.0 2.5 3.0 3.5 4.0

VCC − Supply Voltage − V

Active Mode Current − mA

fDCO = 1 MHz

fDCO = 8 MHz

fDCO = 12 MHz

fDCO = 16 MHz

0.0

1.0

2.0

3.0

4.0

0.0 4.0 8.0 12.0 16.0

fDCO − DCO Frequency − MHz

Active Mode Current − mA

TA= 25 °C

TA= 85 °C

VCC = 2.2 V

VCC = 3 V

TA= 25 °C

TA= 85 °C

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Electrical Characteristics

Active Mode Supply Current Into VCC Excluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)(2)

PARAMETER TEST CONDITIONS TAVCC MIN TYP MAX UNIT

fDCO = fMCLK = fSMCLK = 1 MHz, 2.2 V 230

fACLK = 0 Hz,

Program executes in flash,

Active mode (AM)

IAM,1MHz BCSCTL1 = CALBC1_1MHZ, µA

current at 1 MHz 3 V 330 420

DCOCTL = CALDCO_1MHZ,

CPUOFF = 0, SCG0 = 0, SCG1 = 0,

OSCOFF = 0

(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.

(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external

load capacitance is chosen to closely match the required 9 pF.

Typical Characteristics, Active Mode Supply Current (Into VCC)

Figure 2. Active Mode Current vs VCC, TA= 25°C Figure 3. Active Mode Current vs DCO Frequency

0.00

0.25

0.50

0.75

1.00

1.25

1.50

1.75

2.00

2.25

2.50

-40

I – Low-Power Mode Current – µA

LPM4

Vcc = 3.6 V

T – Temperature – °C

Vcc = 1.8 V

Vcc = 3 V

Vcc = 2.2 V

-20 020 40 60 80

0.00

0.25

0.50

0.75

1.00

1.25

1.50

1.75

2.00

2.25

2.50

2.75

3.00

-40

I – Low-Power Mode Current – µA

LPM3

Vcc = 3.6 V

T – Temperature – °C

Vcc = 1.8 V

Vcc = 3 V

Vcc = 2.2 V

-20 020 40 60 80

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Low-Power Mode Supply Currents (Into VCC) Excluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1) (2)

PARAMETER TEST CONDITIONS TAVCC MIN TYP MAX UNIT

fMCLK = 0 MHz,

fSMCLK = fDCO = 1 MHz,

fACLK = 32768 Hz,

Low-power mode 0

ILPM0,1MHz BCSCTL1 = CALBC1_1MHZ, 25°C 2.2 V 56 µA

(LPM0) current(3) DCOCTL = CALDCO_1MHZ,

CPUOFF = 1, SCG0 = 0, SCG1 = 0,

OSCOFF = 0

fMCLK = fSMCLK = 0 MHz,

fDCO = 1 MHz,

fACLK = 32768 Hz,

Low-power mode 2

ILPM2 BCSCTL1 = CALBC1_1MHZ, 25°C 2.2 V 22 µA

(LPM2) current(4) DCOCTL = CALDCO_1MHZ,

CPUOFF = 1, SCG0 = 0, SCG1 = 1,

OSCOFF = 0

fDCO = fMCLK = fSMCLK = 0 MHz,

Low-power mode 3 fACLK = 32768 Hz,

ILPM3,LFXT1 25°C 2.2 V 0.7 1.5 µA

(LPM3) current(4) CPUOFF = 1, SCG0 = 1, SCG1 = 1,

OSCOFF = 0

fDCO = fMCLK = fSMCLK = 0 MHz,

Low-power mode 3 fACLK from internal LF oscillator (VLO),

ILPM3,VLO 25°C 2.2 V 0.5 0.7 µA

current, (LPM3)(4) CPUOFF = 1, SCG0 = 1, SCG1 = 1,

OSCOFF = 0

fDCO = fMCLK = fSMCLK = 0 MHz, 25°C 0.1 0.5

Low-power mode 4 fACLK = 0 Hz,

ILPM4 2.2 V µA

(LPM4) current(5) CPUOFF = 1, SCG0 = 1, SCG1 = 1, 85°C 0.8 1.7

OSCOFF = 1

(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.

(2) The currents are characterized with a Micro Crystal CC4V-T1A SMD crystal with a load capacitance of 9 pF. The internal and external

load capacitance is chosen to closely match the required 9 pF.

(3) Current for brownout and WDT clocked by SMCLK included.

(4) Current for brownout and WDT clocked by ACLK included.

(5) Current for brownout included.

Typical Characteristics, Low-Power Mode Supply Currents

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

Figure 4. LPM3 Current vs Temperature Figure 5. LPM4 Current vs Temperature

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Schmitt-Trigger Inputs, Ports Px

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

0.45 VCC 0.75 VCC

VIT+ Positive-going input threshold voltage V

3 V 1.35 2.25

0.25 VCC 0.55 VCC

VIT–Negative-going input threshold voltage V

3 V 0.75 1.65

Vhys Input voltage hysteresis (VIT+ –VIT–) 3 V 0.3 1 V

For pullup: VIN = VSS

RPull Pullup/pulldown resistor 3 V 20 35 50 kΩ

For pulldown: VIN = VCC

CIInput capacitance VIN = VSS or VCC 5 pF

Leakage Current, Ports Px

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN MAX UNIT

Ilkg(Px.y) High-impedance leakage current (1) (2) 3 V ±50 nA

(1) The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.

(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is

disabled.

Outputs, Ports Px

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

VOH High-level output voltage I(OHmax) =–6 mA(1) 3 V VCC –0.3 V

VOL Low-level output voltage I(OLmax) = 6 mA(1) 3 V VSS + 0.3 V

(1) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop

specified.

Output Frequency, Ports Px

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

Port output frequency

fPx.y Px.y, CL= 20 pF, RL= 1 kΩ(1) (2) 3 V 12 MHz

(with load)

fPort_CLK Clock output frequency Px.y, CL= 20 pF(2) 3 V 16 MHz

(1) A resistive divider with two 0.5-kΩresistors between VCC and VSS is used as load. The output is connected to the center tap of the

divider.

(2) The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.

VOL − Low-Level Output Voltage − V

0 0.5 1 1.5 2 2.5

VCC = 2.2 V

P1.7 TA= 25°C

TA= 85°C

I − Typical Low-Level Output Current − mA

VOL − Low-Level Output Voltage − V

0 0.5 1 1.5 2 2.5 3 3.5

VCC = 3 V

P1.7 TA= 25°C

TA= 85°C

I − Typical Low-Level Output Current − mA

VOH − High-Level Output Voltage − V

−25

−20

−15

−10

−5

0 0.5 1 1.5 2 2.5

VCC = 2.2 V

P1.7

TA= 25°C

TA= 85°C

I − Typical High-Level Output Current − mA

VOH − High-Level Output Voltage − V

−50

−40

−30

−20

−10

0 0.5 1 1.5 2 2.5 3 3.5

VCC = 3 V

P1.7

TA= 25°C

TA= 85°C

I − Typical High-Level Output Current − mA

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Typical Characteristics, Outputs

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

TYPICAL LOW-LEVEL OUTPUT CURRENT TYPICAL LOW-LEVEL OUTPUT CURRENT

vs vs

LOW-LEVEL OUTPUT VOLTAGE LOW-LEVEL OUTPUT VOLTAGE

Figure 6. Figure 7.

TYPICAL HIGH-LEVEL OUTPUT CURRENT TYPICAL HIGH-LEVEL OUTPUT CURRENT

vs vs

HIGH-LEVEL OUTPUT VOLTAGE HIGH-LEVEL OUTPUT VOLTAGE

Figure 8. Figure 9.

CLOAD − External Capacitance − pF

0.00

0.15

0.30

0.45

0.60

0.75

0.90

1.05

1.20

1.35

1.50

10 50 100

P1.y

P2.0 ... P2.5

P2.6, P2.7

VCC = 3.0 V

fosc − Typical Oscillation Frequency − MHz

CLOAD − External Capacitance − pF

0.00

0.15

0.30

0.45

0.60

0.75

0.90

1.05

1.20

1.35

1.50

10 50 100

P1.y

P2.0 ... P2.5

P2.6, P2.7

VCC = 2.2 V

fosc − Typical Oscillation Frequency − MHz

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Pin-Oscillator Frequency –Ports Px

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

P1.y, CL= 10 pF, RL= 100 kΩ(1)(2) 1400

foP1.x Port output oscillation frequency 3 V kHz

P1.y, CL= 20 pF, RL= 100 kΩ(1)(2) 900

P2.0 to P2.5, CL= 10 pF, RL= 100 kΩ(1)(2) 1800 kHz

foP2.x Port output oscillation frequency 3 V

P2.0 to P2.5, CL= 20 pF, RL= 100 kΩ(1)(2) 1000 kHz

P2.6 and P2.7, CL= 20 pF, RL= 100

foP2.6/7 Port output oscillation frequency 3 V 700 kHz

kΩ(1)(2)

P3.y, CL= 10 pF, RL= 100 kΩ(1)(2) 1800

foP3.x Port output oscillation frequency 3 V kHz

P3.y, CL= 20 pF, RL= 100 kΩ(1)(2) 1000

(1) A resistive divider with two 0.5-kΩresistors between VCC and VSS is used as load. The output is connected to the center tap of the

divider.

(2) The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.

Typical Characteristics, Pin-Oscillator Frequency

TYPICAL OSCILLATING FREQUENCY TYPICAL OSCILLATING FREQUENCY

vs vs

LOAD CAPACITANCE LOAD CAPACITANCE

A. One output active at a time. A. One output active at a time.

Figure 10. Figure 11.

td(BOR)

VCC

V(B_IT−)

Vhys(B_IT−)

VCC(start)

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POR/Brownout Reset (BOR)(1)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

0.7 ×

VCC(start) See Figure 12 dVCC/dt ≤3 V/s V

V(B_IT--)

V(B_IT–)See Figure 12 through Figure 14 dVCC/dt ≤3 V/s 1.35 V

Vhys(B_IT–)See Figure 12 dVCC/dt ≤3 V/s 140 mV

td(BOR) See Figure 12 2000 µs

Pulse length needed at RST/NMI pin to

t(reset) 2.2 V 2 µs

accepted reset internally

(1) The current consumption of the brownout module is already included in the ICC current consumption data. The voltage level V(B_IT–)+

Vhys(B_IT–)is ≤1.8 V.

Figure 12. POR/Brownout Reset (BOR) vs Supply Voltage

VCC(drop)

VCC

3 V

tpw

0.5

1.5

0.001 1 1000

Typical Conditions

1 ns 1 ns

tpw − Pulse Width − µs

VCC(drop) − V

tpw − Pulse Width − µs

VCC = 3 V

VCC

0.5

1.5

VCC(drop)

tpw

tpw − Pulse Width − µs

VCC(drop) − V

3 V

0.001 1 1000 tftr

tpw − Pulse Width − µs

tf= tr

Typical Conditions

VCC = 3 V

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Typical Characteristics, POR/Brownout Reset (BOR)

Figure 13. VCC(drop) Level With a Square Voltage Drop to Generate a POR/Brownout Signal

Figure 14. VCC(drop) Level With a Triangle Voltage Drop to Generate a POR/Brownout Signal

DCO(RSEL,DCO+1)

DCO(RSEL,DCO)

average DCO(RSEL,DCO) DCO(RSEL,DCO+1)

32 × f × f

f = MOD × f + (32 – MOD) × f

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Main DCO Characteristics

•All ranges selected by RSELx overlap with RSELx + 1: RSELx = 0 overlaps RSELx = 1, ... RSELx = 14

overlaps RSELx = 15.

•DCO control bits DCOx have a step size as defined by parameter SDCO.

•Modulation control bits MODx select how often fDCO(RSEL,DCO+1) is used within the period of 32 DCOCLK

cycles. The frequency fDCO(RSEL,DCO) is used for the remaining cycles. The frequency is an average equal to:

DCO Frequency

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

RSELx <14 1.8 3.6 V

VCC Supply voltage RSELx = 14 2.2 3.6 V

RSELx = 15 3 3.6 V

fDCO(0,0) DCO frequency (0, 0) RSELx = 0, DCOx = 0, MODx = 0 3 V 0.06 0.14 MHz

fDCO(0,3) DCO frequency (0, 3) RSELx = 0, DCOx = 3, MODx = 0 3 V 0.07 0.17 MHz

fDCO(1,3) DCO frequency (1, 3) RSELx = 1, DCOx = 3, MODx = 0 3 V 0.15 MHz

fDCO(2,3) DCO frequency (2, 3) RSELx = 2, DCOx = 3, MODx = 0 3 V 0.21 MHz

fDCO(3,3) DCO frequency (3, 3) RSELx = 3, DCOx = 3, MODx = 0 3 V 0.30 MHz

fDCO(4,3) DCO frequency (4, 3) RSELx = 4, DCOx = 3, MODx = 0 3 V 0.41 MHz

fDCO(5,3) DCO frequency (5, 3) RSELx = 5, DCOx = 3, MODx = 0 3 V 0.58 MHz

fDCO(6,3) DCO frequency (6, 3) RSELx = 6, DCOx = 3, MODx = 0 3 V 0.54 1.06 MHz

fDCO(7,3) DCO frequency (7, 3) RSELx = 7, DCOx = 3, MODx = 0 3 V 0.80 1.50 MHz

fDCO(8,3) DCO frequency (8, 3) RSELx = 8, DCOx = 3, MODx = 0 3 V 1.6 MHz

fDCO(9,3) DCO frequency (9, 3) RSELx = 9, DCOx = 3, MODx = 0 3 V 2.3 MHz

fDCO(10,3) DCO frequency (10, 3) RSELx = 10, DCOx = 3, MODx = 0 3 V 3.4 MHz

fDCO(11,3) DCO frequency (11, 3) RSELx = 11, DCOx = 3, MODx = 0 3 V 4.25 MHz

fDCO(12,3) DCO frequency (12, 3) RSELx = 12, DCOx = 3, MODx = 0 3 V 4.30 7.30 MHz

fDCO(13,3) DCO frequency (13, 3) RSELx = 13, DCOx = 3, MODx = 0 3 V 6.00 9.60 MHz

fDCO(14,3) DCO frequency (14, 3) RSELx = 14, DCOx = 3, MODx = 0 3 V 8.60 13.9 MHz

fDCO(15,3) DCO frequency (15, 3) RSELx = 15, DCOx = 3, MODx = 0 3 V 12.0 18.5 MHz

fDCO(15,7) DCO frequency (15, 7) RSELx = 15, DCOx = 7, MODx = 0 3 V 16.0 26.0 MHz

Frequency step between

SRSEL SRSEL = fDCO(RSEL+1,DCO)/fDCO(RSEL,DCO) 3 V 1.35 ratio

range RSEL and RSEL+1

Frequency step between

SDCO SDCO = fDCO(RSEL,DCO+1)/fDCO(RSEL,DCO) 3 V 1.08 ratio

tap DCO and DCO+1

Duty cycle Measured at SMCLK output 3 V 50 %

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Calibrated DCO Frequencies, Tolerance

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS TAVCC MIN TYP MAX UNIT

BCSCTL1 = CALBC1_1MHZ,

1-MHz tolerance over DCOCTL = CALDCO_1MHZ, 0°C to 85°C 3 V -3 ±0.5 +3 %

temperature(1) calibrated at 30°C and 3 V

BCSCTL1 = CALBC1_1MHZ,

1-MHz tolerance over VCC DCOCTL = CALDCO_1MHZ, 30°C 1.8 V to 3.6 V -3 ±2 +3 %

calibrated at 30°C and 3 V

BCSCTL1 = CALBC1_1MHZ,

1-MHz tolerance overall DCOCTL = CALDCO_1MHZ, -40°C to 85°C 1.8 V to 3.6 V -6 ±3 +6 %

calibrated at 30°C and 3 V

BCSCTL1 = CALBC1_8MHZ,

8-MHz tolerance over DCOCTL = CALDCO_8MHZ, 0°C to 85°C 3 V -3 ±0.5 +3 %

temperature(1) calibrated at 30°C and 3 V

BCSCTL1 = CALBC1_8MHZ,

8-MHz tolerance over VCC DCOCTL = CALDCO_8MHZ, 30°C 2.2 V to 3.6 V -3 ±2 +3 %

calibrated at 30°C and 3 V

BCSCTL1 = CALBC1_8MHZ,

8-MHz tolerance overall DCOCTL = CALDCO_8MHZ, -40°C to 85°C 2.2 V to 3.6 V -6 ±3 +6 %

calibrated at 30°C and 3 V

BCSCTL1 = CALBC1_12MHZ,

12-MHz tolerance over DCOCTL = CALDCO_12MHZ, 0°C to 85°C 3 V -3 ±0.5 +3 %

temperature(1) calibrated at 30°C and 3 V

BCSCTL1 = CALBC1_12MHZ,

12-MHz tolerance over VCC DCOCTL = CALDCO_12MHZ, 30°C 2.7 V to 3.6 V -3 ±2 +3 %

calibrated at 30°C and 3 V

BCSCTL1 = CALBC1_12MHZ,

12-MHz tolerance overall DCOCTL = CALDCO_12MHZ, -40°C to 85°C 2.7 V to 3.6 V -6 ±3 +6 %

calibrated at 30°C and 3 V

BCSCTL1 = CALBC1_16MHZ,

16-MHz tolerance over DCOCTL = CALDCO_16MHZ, 0°C to 85°C 3 V -3 ±0.5 +3 %

temperature(1) calibrated at 30°C and 3 V

BCSCTL1 = CALBC1_16MHZ,

16-MHz tolerance over VCC DCOCTL = CALDCO_16MHZ, 30°C 3.3 V to 3.6 V -3 ±2 +3 %

calibrated at 30°C and 3 V

BCSCTL1 = CALBC1_16MHZ,

16-MHz tolerance overall DCOCTL = CALDCO_16MHZ, -40°C to 85°C 3.3 V to 3.6 V -6 ±3 +6 %

calibrated at 30°C and 3 V

(1) This is the frequency change from the measured frequency at 30°C over temperature.

DCO Frequency − MHz

0.10

1.00

10.00

0.10 1.00 10.00

DCO Wake Time − µs

RSELx = 0...11

RSELx = 12...15

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Wake-Up From Lower-Power Modes (LPM3/4)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

DCO clock wake-up time from BCSCTL1 = CALBC1_1MHz,

tDCO,LPM3/4 3 V 1.5 µs

LPM3/4(1) DCOCTL = CALDCO_1MHz 1/fMCLK +

tCPU,LPM3/4 CPU wake-up time from LPM3/4(2) tClock,LPM3/4

(1) The DCO clock wake-up time is measured from the edge of an external wake-up signal (e.g., port interrupt) to the first clock edge

observable externally on a clock pin (MCLK or SMCLK).

(2) Parameter applicable only if DCOCLK is used for MCLK.

Typical Characteristics, DCO Clock Wake-Up Time From LPM3/4

Figure 15. DCO Wake-Up Time From LPM3 vs DCO Frequency

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Crystal Oscillator, XT1, Low-Frequency Mode(1)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

LFXT1 oscillator crystal

fLFXT1,LF XTS = 0, LFXT1Sx = 0 or 1 1.8 V to 3.6 V 32768 Hz

frequency, LF mode 0, 1

LFXT1 oscillator logic level

fLFXT1,LF,logic square wave input frequency, XTS = 0, XCAPx = 0, LFXT1Sx = 3 1.8 V to 3.6 V 10000 32768 50000 Hz

LF mode XTS = 0, LFXT1Sx = 0, 500

fLFXT1,LF = 32768 Hz, CL,eff = 6 pF

Oscillation allowance for

OALF kΩ

LF crystals XTS = 0, LFXT1Sx = 0, 200

fLFXT1,LF = 32768 Hz, CL,eff = 12 pF

XTS = 0, XCAPx = 0 1

XTS = 0, XCAPx = 1 5.5

Integrated effective load

CL,eff pF

capacitance, LF mode(2) XTS = 0, XCAPx = 2 8.5

XTS = 0, XCAPx = 3 11

XTS = 0, Measured at P2.0/ACLK,

Duty cycle LF mode 2.2 V 30 50 70 %

fLFXT1,LF = 32768 Hz

Oscillator fault frequency,

fFault,LF XTS = 0, XCAPx = 0, LFXT1Sx = 3(4) 2.2 V 10 10000 Hz

LF mode(3)

(1) To improve EMI on the XT1 oscillator, the following guidelines should be observed.

(a) Keep the trace between the device and the crystal as short as possible.

(b) Design a good ground plane around the oscillator pins.

(d) Avoid running PCB traces underneath or adjacent to the XIN and XOUT pins.

(e) Use assembly materials and praxis to avoid any parasitic load on the oscillator XIN and XOUT pins.

(f) If conformal coating is used, ensure that it does not induce capacitive/resistive leakage between the oscillator pins.

(g) Do not route the XOUT line to the JTAG header to support the serial programming adapter as shown in other documentation. This

signal is no longer required for the serial programming adapter.

(2) Includes parasitic bond and package capacitance (approximately 2 pF per pin).

Since the PCB adds additional capacitance, it is recommended to verify the correct load by measuring the ACLK frequency. For a

correct setup, the effective load capacitance should always match the specification of the used crystal.

(3) Frequencies below the MIN specification set the fault flag. Frequencies above the MAX specification do not set the fault flag.

Frequencies in between might set the flag.

(4) Measured with logic-level input frequency but also applies to operation with crystals.

Internal Very-Low-Power Low-Frequency Oscillator (VLO)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TAVCC MIN TYP MAX UNIT

fVLO VLO frequency -40°C to 85°C 3 V 4 12 20 kHz

dfVLO/dTVLO frequency temperature drift -40°C to 85°C 3 V 0.5 %/°C

dfVLO/dVCC VLO frequency supply voltage drift 25°C 1.8 V to 3.6 V 4 %/V

Timer_A

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

fTA Timer_A input clock frequency SMCLK, duty cycle = 50% ±10% fSYSTEM MHz

tTA,cap Timer_A capture timing TA0, TA1 3 V 20 ns

tSU,MI

tHD,MI

UCLK

SOMI

SIMO

tVALID,MO

tHD,MO

CKPL = 0

CKPL = 1

tLO/HI tLO/HI

1/fUCxCLK

tSU,MI

tHD,MI

UCLK

SOMI

SIMO

tVALID,MO

CKPL = 0

CKPL = 1

1/fUCxCLK

tHD,MO

tLO/HI tLO/HI

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USCI (UART Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

fUSCI USCI input clock frequency SMCLK, duty cycle = 50% ±10% fSYSTEM MHz

Maximum BITCLK clock frequency

fmax,BITCLK 3 V 2 MHz

(equals baudrate in MBaud)(1)

tτUART receive deglitch time(2) 3 V 50 100 600 ns

(1) The DCO wake-up time must be considered in LPM3/4 for baud rates above 1 MHz.

(2) Pulses on the UART receive input (UCxRX) shorter than the UART receive deglitch time are suppressed. To ensure that pulses are

correctly recognized, their width should exceed the maximum specification of the deglitch time.

USCI (SPI Master Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 16 and

Figure 17)PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

fUSCI USCI input clock frequency SMCLK, duty cycle = 50% ±10% fSYSTEM MHz

tSU,MI SOMI input data setup time 3 V 75 ns

tHD,MI SOMI input data hold time 3 V 0 ns

tVALID,MO SIMO output data valid time UCLK edge to SIMO valid, CL= 20 pF 3 V 20 ns

Figure 16. SPI Master Mode, CKPH = 0

Figure 17. SPI Master Mode, CKPH = 1

STE

UCLK

CKPL = 0

CKPL = 1

SOMI

SIMO

tSU,SI

tHD,SI

tVALID,SO

tSTE,LEAD

1/fUCxCLK

tLO/HI tLO/HI

tSTE,LAG

tSTE,DIS

tSTE,ACC

tHD,SO

STE

UCLK

CKPL = 0

CKPL = 1

SOMI

SIMO

tSU,SI

tHD,SI

tVALID,SO

tSTE,LEAD

1/fUCxCLK

tSTE,LAG

tSTE,DIS

tSTE,ACC

tHD,MO

tLO/HI tLO/HI

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USCI (SPI Slave Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 18 and

Figure 19)PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

tSTE,LEAD STE lead time, STE low to clock 3 V 50 ns

tSTE,LAG STE lag time, Last clock to STE high 3 V 10 ns

tSTE,ACC STE access time, STE low to SOMI data out 3 V 50 ns

STE disable time, STE high to SOMI high

tSTE,DIS 3 V 50 ns

impedance

tSU,SI SIMO input data setup time 3 V 15 ns

tHD,SI SIMO input data hold time 3 V 10 ns

UCLK edge to SOMI valid,

tVALID,SO SOMI output data valid time 3 V 50 75 ns

CL= 20 pF

Figure 18. SPI Slave Mode, CKPH = 0

Figure 19. SPI Slave Mode, CKPH = 1

SDA

SCL

tHD,DAT

tSU,DAT

tHD,STA

tHIGH

tLOW

tBUF

tHD,STA

tSU,STA

tSP

tSU,STO

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USCI (I2C Mode)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (see Figure 20)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

fUSCI USCI input clock frequency SMCLK, duty cycle = 50% ±10% fSYSTEM MHz

fSCL SCL clock frequency 3 V 0 400 kHz

fSCL ≤100 kHz 4.0

tHD,STA Hold time (repeated) START 3 V µs

fSCL >100 kHz 0.6

fSCL ≤100 kHz 4.7

tSU,STA Setup time for a repeated START 3 V µs

fSCL >100 kHz 0.6

tHD,DAT Data hold time 3 V 0 ns

tSU,DAT Data setup time 3 V 250 ns

tSU,STO Setup time for STOP 3 V 4.0 µs

Pulse width of spikes suppressed by

tSP 3 V 50 100 600 ns

input filter

Figure 20. I2C Mode Timing

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10-Bit ADC, Power Supply and Input Range Conditions (MSP430G2x33 Only)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)

PARAMETER TEST CONDITIONS TAVCC MIN TYP MAX UNIT

VCC Analog supply voltage VSS = 0 V 2.2 3.6 V

All Ax terminals, Analog inputs

VAx Analog input voltage(2) 3 V 0 VCC V

selected in ADC10AE register

fADC10CLK = 5.0 MHz,

ADC10ON = 1, REFON = 0,

IADC10 ADC10 supply current(3) 25°C 3 V 0.6 mA

ADC10SHT0 = 1, ADC10SHT1 = 0,

ADC10DIV = 0

fADC10CLK = 5.0 MHz,

ADC10ON = 0, REF2_5V = 0, 0.25

REFON = 1, REFOUT = 0

Reference supply current,

IREF+ 25°C 3 V mA

reference buffer disabled(4) fADC10CLK = 5.0 MHz,

ADC10ON = 0, REF2_5V = 1, 0.25

REFON = 1, REFOUT = 0

fADC10CLK = 5.0 MHz,

Reference buffer supply ADC10ON = 0, REFON = 1,

IREFB,0 25°C 3 V 1.1 mA

current with ADC10SR = 0(4) REF2_5V = 0, REFOUT = 1,

ADC10SR = 0

fADC10CLK = 5.0 MHz,

Reference buffer supply ADC10ON = 0, REFON = 1,

IREFB,1 25°C 3 V 0.5 mA

current with ADC10SR = 1(4) REF2_5V = 0, REFOUT = 1,

ADC10SR = 1

Only one terminal Ax can be selected

CIInput capacitance 25°C 3 V 27 pF

at one time

RIInput MUX ON resistance 0 V ≤VAx ≤VCC 25°C 3 V 1000 Ω

(1) The leakage current is defined in the leakage current table with Px.y/Ax parameter.

(2) The analog input voltage range must be within the selected reference voltage range VR+ to VR–for valid conversion results.

(3) The internal reference supply current is not included in current consumption parameter IADC10.

(4) The internal reference current is supplied via terminal VCC. Consumption is independent of the ADC10ON control bit, unless a

conversion is active. The REFON bit enables the built-in reference to settle before starting an A/D conversion.

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10-Bit ADC, Built-In Voltage Reference (MSP430G2x33 Only)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

IVREF+ ≤1 mA, REF2_5V = 0 2.2

Positive built-in reference

VCC,REF+ V

analog supply voltage range IVREF+ ≤1 mA, REF2_5V = 1 2.9

IVREF+ ≤IVREF+max, REF2_5V = 0 1.41 1.5 1.59

Positive built-in reference

VREF+ 3 V V

voltage IVREF+ ≤IVREF+max, REF2_5V = 1 2.35 2.5 2.65

Maximum VREF+ load

ILD,VREF+ 3 V ±1 mA

current IVREF+ = 500 µA±100 µA,

Analog input voltage VAx ≉0.75 V, ±2

REF2_5V = 0

VREF+ load regulation 3 V LSB

IVREF+ = 500 µA±100 µA,

Analog input voltage VAx ≉1.25 V, ±2

REF2_5V = 1

IVREF+ = 100 µA→900 µA,

VREF+ load regulation VAx ≉0.5 ×VREF+, 3 V 400 ns

response time Error of conversion result ≤1 LSB,

ADC10SR = 0

Maximum capacitance at

CVREF+ IVREF+ ≤ ±1 mA, REFON = 1, REFOUT = 1 3 V 100 pF

pin VREF+ ppm/

TCREF+ Temperature coefficient IVREF+ = const with 0 mA ≤IVREF+ ≤1 mA 3 V ±100 °C

Settling time of internal IVREF+ = 0.5 mA, REF2_5V = 0,

tREFON reference voltage to 99.9% 3.6 V 30 µs

REFON = 0 →1

VREF IVREF+ = 0.5 mA,

Settling time of reference

tREFBURST REF2_5V = 1, REFON = 1, 3 V 2 µs

buffer to 99.9% VREF REFBURST = 1, ADC10SR = 0

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10-Bit ADC, External Reference(1) (MSP430G2x33 Only)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

VEREF+ >VEREF–,1.4 VCC

SREF1 = 1, SREF0 = 0

Positive external reference input

VEREF+ V

voltage range (2) VEREF– ≤ VEREF+ ≤VCC –0.15 V, 1.4 3

SREF1 = 1, SREF0 = 1 (3)

Negative external reference input

VEREF–VEREF+ >VEREF–0 1.2 V

voltage range (4)

Differential external reference

ΔVEREF input voltage range, VEREF+ >VEREF–(5) 1.4 VCC V

ΔVEREF = VEREF+ –VEREF–

0 V ≤VEREF+ ≤VCC,3 V ±1

SREF1 = 1, SREF0 = 0

IVEREF+ Static input current into VEREF+ µA

0 V ≤VEREF+ ≤VCC –0.15 V ≤3 V, 3 V 0

SREF1 = 1, SREF0 = 1(3)

IVEREF–Static input current into VEREF–0 V ≤VEREF– ≤ VCC 3 V ±1µA

(1) The external reference is used during conversion to charge and discharge the capacitance array. The input capacitance, CI, is also the

dynamic load for an external reference during conversion. The dynamic impedance of the reference supply should follow the

recommendations on analog-source impedance to allow the charge to settle for 10-bit accuracy.

(2) The accuracy limits the minimum positive external reference voltage. Lower reference voltage levels may be applied with reduced

accuracy requirements.

(3) Under this condition the external reference is internally buffered. The reference buffer is active and requires the reference buffer supply

current IREFB. The current consumption can be limited to the sample and conversion period with REBURST = 1.

(4) The accuracy limits the maximum negative external reference voltage. Higher reference voltage levels may be applied with reduced

accuracy requirements.

(5) The accuracy limits the minimum external differential reference voltage. Lower differential reference voltage levels may be applied with

reduced accuracy requirements.

10-Bit ADC, Timing Parameters (MSP430G2x33 Only)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

ADC10SR = 0 0.45 6.3

ADC10 input clock For specified performance of

fADC10CLK 3 V MHz

frequency ADC10 linearity parameters ADC10SR = 1 0.45 1.5

ADC10 built-in oscillator ADC10DIVx = 0, ADC10SSELx = 0,

fADC10OSC 3 V 3.7 6.3 MHz

frequency fADC10CLK = fADC10OSC

ADC10 built-in oscillator, ADC10SSELx = 0, 3 V 2.06 3.51

fADC10CLK = fADC10OSC

tCONVERT Conversion time µs

13 ×

fADC10CLK from ACLK, MCLK, or SMCLK: ADC10DIV ×

ADC10SSELx ≠01/fADC10CLK

Turn-on settling time of

tADC10ON (1) 100 ns

the ADC

(1) The condition is that the error in a conversion started after tADC10ON is less than ±0.5 LSB. The reference and input signal are already

settled.

10-Bit ADC, Linearity Parameters (MSP430G2x33 Only)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

EIIntegral linearity error 3 V ±1 LSB

EDDifferential linearity error 3 V ±1 LSB

EOOffset error Source impedance RS<100 Ω3 V ±1 LSB

EGGain error 3 V ±1.1 ±2 LSB

ETTotal unadjusted error 3 V ±2±5 LSB

MSP430G2x33

MSP430G2x03

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SLAS734D –APRIL 2011–REVISED NOVEMBER 2011

10-Bit ADC, Temperature Sensor and Built-In VMID (MSP430G2x33 Only)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

Temperature sensor supply REFON = 0, INCHx = 0Ah,

ISENSOR 3 V 60 µA

current(1) TA= 25°C

TCSENSOR ADC10ON = 1, INCHx = 0Ah (2) 3 V 3.55 mV/°C

Sample time required if channel ADC10ON = 1, INCHx = 0Ah,

tSensor(sample) 3 V 30 µs

10 is selected (3) Error of conversion result ≤1 LSB

IVMID Current into divider at channel 11 ADC10ON = 1, INCHx = 0Bh 3 V (4) µA

ADC10ON = 1, INCHx = 0Bh,

VMID VCC divider at channel 11 3 V 1.5 V

VMID ≉0.5 ×VCC

Sample time required if channel ADC10ON = 1, INCHx = 0Bh,

tVMID(sample) 3 V 1220 ns

11 is selected (5) Error of conversion result ≤1 LSB

(1) The sensor current ISENSOR is consumed if (ADC10ON = 1 and REFON = 1) or (ADC10ON = 1 and INCH = 0Ah and sample signal is

high). When REFON = 1, ISENSOR is included in IREF+. When REFON = 0, ISENSOR applies during conversion of the temperature sensor

input (INCH = 0Ah).

(2) The following formula can be used to calculate the temperature sensor output voltage:

VSensor,typ = TCSensor (273 + T [°C] ) + VOffset,sensor [mV] or

VSensor,typ = TCSensor T [°C] + VSensor(TA= 0°C) [mV]

(3) The typical equivalent impedance of the sensor is 51 kΩ. The sample time required includes the sensor-on time tSENSOR(on).

(4) No additional current is needed. The VMID is used during sampling.

(5) The on-time tVMID(on) is included in the sampling time tVMID(sample); no additional on time is needed.

Flash Memory

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST VCC MIN TYP MAX UNIT

CONDITIONS

VCC(PGM/ERASE) Program and erase supply voltage 2.2 3.6 V

fFTG Flash timing generator frequency 257 476 kHz

IPGM Supply current from VCC during program 2.2 V/3.6 V 1 5 mA

IERASE Supply current from VCC during erase 2.2 V/3.6 V 1 7 mA

tCPT Cumulative program time(1) 2.2 V/3.6 V 10 ms

tCMErase Cumulative mass erase time 2.2 V/3.6 V 20 ms

Program/erase endurance 104105cycles

tRetention Data retention duration TJ= 25°C 100 years

tWord Word or byte program time (2) 30 tFTG

tBlock, 0 Block program time for first byte or word (2) 25 tFTG

Block program time for each additional byte or

tBlock, 1-63 (2) 18 tFTG

word

tBlock, End Block program end-sequence wait time (2) 6 tFTG

tMass Erase Mass erase time (2) 10593 tFTG

tSeg Erase Segment erase time (2) 4819 tFTG

(1) The cumulative program time must not be exceeded when writing to a 64-byte flash block. This parameter applies to all programming

methods: individual word/byte write and block write modes.

(2) These values are hardwired into the Flash Controller's state machine (tFTG = 1/fFTG).

MSP430G2x33

MSP430G2x03

SLAS734D –APRIL 2011–REVISED NOVEMBER 2011

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RAM

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN MAX UNIT

V(RAMh) RAM retention supply voltage (1) CPU halted 1.6 V

(1) This parameter defines the minimum supply voltage VCC when the data in RAM remains unchanged. No program execution should

happen during this supply voltage condition.

JTAG and Spy-Bi-Wire Interface

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT

fSBW Spy-Bi-Wire input frequency 2.2 V 0 20 MHz

tSBW,Low Spy-Bi-Wire low clock pulse length 2.2 V 0.025 15 µs

Spy-Bi-Wire enable time

tSBW,En 2.2 V 1 µs

(TEST high to acceptance of first clock edge(1))

tSBW,Ret Spy-Bi-Wire return to normal operation time 2.2 V 15 100 µs

fTCK TCK input frequency(2) 2.2 V 0 5 MHz

RInternal Internal pulldown resistance on TEST 2.2 V 25 60 90 kΩ

(1) Tools accessing the Spy-Bi-Wire interface need to wait for the maximum tSBW,En time after pulling the TEST/SBWCLK pin high before

applying the first SBWCLK clock edge.

(2) fTCK may be restricted to meet the timing requirements of the module selected.

JTAG Fuse(1)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN MAX UNIT

VCC(FB) Supply voltage during fuse-blow condition TA= 25°C 2.5 V

VFB Voltage level on TEST for fuse blow 6 7 V

IFB Supply current into TEST during fuse blow 100 mA

tFB Time to blow fuse 1 ms

(1) Once the fuse is blown, no further access to the JTAG/Test, Spy-Bi-Wire, and emulation feature is possible, and JTAG is switched to

bypass mode.

PxDIR.y

From Timer

P1.0/TA0CLK/ ACLK/A0*

P1.1/TA0.0/

UCA0RXD/UCA0SOMI/A1*

P1.2/TA0.1/

UCA0TXD/UCA0SIMO/A2*

From USCI

* Note: MSP430G2x33 devices only. MSP430G2x03 devices have no ADC10.

To Module

From Timer

PxOUT.y

DVSS

DVCC 1

TAx.y

TAxCLK

Bus

Keeper

PxIN.y

PxSEL.y

PxREN.y

PxSEL2.y

INCHx = y *

ADC10AE0.y *

To ADC10 *

PxSEL.y

PxSEL2.y

PxIRQ.y

PxIE.y

Set

Interrupt

Edge

Select

PxSEL.y

PxIES.y

PxIFG.y

Direction

0: Input

1: Output

PxSEL.y

PxSEL2.y

MSP430G2x33

MSP430G2x03

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SLAS734D –APRIL 2011–REVISED NOVEMBER 2011

PORT SCHEMATICS

Port P1 Pin Schematic: P1.0 to P1.2, Input/Output With Schmitt Trigger

MSP430G2x33

MSP430G2x03

SLAS734D –APRIL 2011–REVISED NOVEMBER 2011

www.ti.com

Table 16. Port P1 (P1.0 to P1.2) Pin Functions

CONTROL BITS / SIGNALS(1)

PIN NAME x FUNCTION ADC10AE.x

(P1.x) P1DIR.x P1SEL.x P1SEL2.x (INCH.y = 1)(2)

P1.0/ P1.x (I/O) I: 0; O: 1 0 0 0

TA0CLK/ TA0.TACLK 0 1 0 0

ACLK/ 0 ACLK 1 1 0 0

A0(2)/ A0 X X X 1 (y = 0)

Pin Osc Capacitive sensing X 0 1 0

P1.1/ P1.x (I/O) I: 0; O: 1 0 0 0

TA0.0/ TA0.0 1 1 0 0

TA0.CCI0A 0 1 0 0

UCA0RXD/ 1 UCA0RXD from USCI 1 1 0

UCA0SOMI/ UCA0SOMI from USCI 1 1 0

A1(2)/ A1 X X X 1 (y = 1)

Pin Osc Capacitive sensing X 0 1 0

P1.2/ P1.x (I/O) I: 0; O: 1 0 0 0

TA0.1/ TA0.1 1 1 0 0

TA0.CCI1A 0 1 0 0

UCA0TXD/ 2 UCA0TXD from USCI 1 1 0

UCA0SIMO/ UCA0SIMO from USCI 1 1 0

A2(2)/ A2 X X X 1 (y = 2)

Pin Osc Capacitive sensing X 0 1 0

(1) X = don't care

(2) MSP430G2x33 devices only

* Note: MSP430G2x33 devices only. MSP430G2x03 devices have no ADC10.

P1.3/ADC10CLK*/

A3*/VREF-*/VEREF-*

Direction

0: Input

1: Output

To Module

From ADC10 *

PxOUT.y

DVSS

DVCC 1

TAx.y

TAxCLK

Bus

Keeper

PxIN.y

PxSEL.y

PxREN.y

PxDIR.y

0,2,3

PxSEL2.y

PxSEL.y

INCHx = y *

To ADC10 *

To ADC10 VREF- * 1

0VSS

SREF2 *

PxSEL.y

PxSEL2.y

PxIRQ.y

PxIE.y

Set

Interrupt

Edge

Select

PxSEL.y

PxIES.y

PxIFG.y

ADC10AE0.y *

PxSEL2.y

MSP430G2x33

MSP430G2x03

www.ti.com

SLAS734D –APRIL 2011–REVISED NOVEMBER 2011

Port P1 Pin Schematic: P1.3, Input/Output With Schmitt Trigger

MSP430G2x33

MSP430G2x03

SLAS734D –APRIL 2011–REVISED NOVEMBER 2011

www.ti.com

Table 17. Port P1 (P1.3) Pin Functions

CONTROL BITS / SIGNALS(1)

PIN NAME x FUNCTION ADC10AE.x

(P1.x) P1DIR.x P1SEL.x P1SEL2.x (INCH.x = 1)(2)

P1.3/ P1.x (I/O) I: 0; O: 1 0 0 0

ADC10CLK(2)/ ADC10CLK 1 1 0 0

A3(2)/ A3 X X X 1 (y = 3)

VREF-(2)/ VREF- X X X 1

VEREF-(2)/ VEREF- X X X 1

Pin Osc Capacitive sensing X 0 1 0

(1) X = don't care

(2) MSP430G2x33 devices only

P1.4/SMCLK/UCB0STE/UCA0CLK/

VREF+/VEREF+/A4/TCK

Direction

0: Input

1: Output

To Module

SMCLK

PxOUT.y

DVSS

DVCC 1

TAx.y

TAxCLK

Bus

Keeper

PxIN.y

PxSEL.y

PxREN.y

PxDIR.y

PxSEL2.y

PxSEL.y

INCHx = y *

To ADC10 *

From/To ADC10 Ref+ *

PxSEL.y

PxSEL2.y

From JTAG

To JTAG

PxIRQ.y

PxIE.y

Set

Interrupt

Edge

Select

PxSEL.y

PxIES.y

PxIFG.y

ADC10AE0.y *

* Note: MSP430G2x33 devices only. MSP430G2x03 devices have no ADC10.

from Module

MSP430G2x33

MSP430G2x03

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SLAS734D –APRIL 2011–REVISED NOVEMBER 2011

Port P1 Pin Schematic: P1.4, Input/Output With Schmitt Trigger

MSP430G2x33

MSP430G2x03

SLAS734D –APRIL 2011–REVISED NOVEMBER 2011

www.ti.com

Table 18. Port P1 (P1.4) Pin Functions

CONTROL BITS / SIGNALS(1)

PIN NAME ADC10AE.x

x FUNCTION

(P1.x) P1DIR.x P1SEL.x P1SEL2.x (INCH.x = JTAG Mode

1)(2)

P1.4/ P1.x (I/O) I: 0; O: 1 0 0 0 0

SMCLK/ SMCLK 1 1 0 0 0

UCB0STE/ UCB0STE from USCI 1 1 0 0

UCA0CLK/ UCA0CLK from USCI 1 1 0 0

VREF+(2)/ 4 VREF+ X X X 1 0

VEREF+(2)/ VEREF+ X X X 1 0

A4(2)/ A4 X X X 1 (y = 4) 0

TCK/ TCK X X X 0 1

Pin Osc Capacitive sensing X 0 1 0 0

(1) X = don't care

(2) MSP430G2x33 devices only

P1.5/TA0.0/UCB0CLK/

UCA0STE/A5*/TMS

P1.6/TA0.1/UCB0SOMI/

UCB0SCL/A6*/TDI/TCLK

P1.7/CAOUT/UCB0SIMO/

UCB0SDA/A7*/TDO/TDI

From Module

* Note: MSP430G2x33 devices only. MSP430G2x03 devices have no ADC10.

To Module

From Module

PxOUT.y

DVSS

DVCC 1

TAx.y

TAxCLK

Bus

Keeper

PxIN.y

PxSEL.y

PxREN.y

PxSEL2.y

INCHx = y *

To ADC10 *

PxSEL.y

PxSEL2.y

From JTAG

To JTAG

PxIRQ.y

PxIE.y

Set

Interrupt

Edge

Select

PxSEL.y

PxIES.y

PxIFG.y

Direction

0: Input

1: Output

PxDIR.y

From Module

PxSEL.y

PxSEL2.y

ADC10AE0.y *

MSP430G2x33

MSP430G2x03

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SLAS734D –APRIL 2011–REVISED NOVEMBER 2011

Port P1 Pin Schematic: P1.5 to P1.7, Input/Output With Schmitt Trigger

MSP430G2x33

MSP430G2x03

SLAS734D –APRIL 2011–REVISED NOVEMBER 2011

www.ti.com

Table 19. Port P1 (P1.5 to P1.7) Pin Functions

CONTROL BITS / SIGNALS(1)

PIN NAME ADC10AE.x

x FUNCTION

(P1.x) P1DIR.x P1SEL.x P1SEL2.x (INCH.x = JTAG Mode

1)(2)

P1.5/ P1.x (I/O) I: 0; O: 1 0 0 0 0

TA0.0/ TA0.0 1 1 0 0 0

UCB0CLK/ UCB0CLK from USCI 1 1 0 0

UCA0STE/ 5 UCA0STE from USCI 1 1 0 0

A5(2)/ A5 X X X 1 (y = 5) 0

TMS TMS X X X 0 1

Pin Osc Capacitive sensing X 0 1 0 0

P1.6/ P1.x (I/O) I: 0; O: 1 0 0 0 0

TA0.1/ TA0.1 1 1 0 0 0

UCB0SOMI/ UCB0SOMI from USCI 1 1 0 0

UCB0SCL/ 6 UCB0SCL from USCI 1 1 0 0

A6(2)/ A6 X X X 1 (y = 6) 0

TDI/TCLK/ TDI/TCLK X X X 0 1

Pin Osc Capacitive sensing X 0 1 0 0

P1.7/ P1.x (I/O) I: 0; O: 1 0 0 0 0

UCB0SIMO/ UCB0SIMO from USCI 1 1 0 0

UCB0SDA/ UCB0SDA from USCI 1 1 0 0

A7(2)/ A7 X X X 1 (y = 7) 0

TDO/TDI/ TDO/TDI X X X 0 1

Pin Osc Capacitive sensing X 0 1 0 0

(1) X = don't care

(2) MSP430G2x33 devices only

P2.0/TA1.0

P2.1/TA1.1

P2.2/TA1.1

P2.3/TA1.0

P2.4/TA1.2

P2.5/TA1.2

From Timer

Direction

0: Input

1: Output

To Module

PxOUT.y

DVSS

DVCC 1

TAx.y

TAxCLK

PxIN.y

PxSEL.y

PxREN.y

PxSEL2.y

PxSEL.y

PxSEL2.y

PxIRQ.y

PxIE.y

Set

Interrupt

Edge

Select

PxSEL.y

PxIES.y

PxIFG.y

PxDIR.y

PxSEL.y

MSP430G2x33

MSP430G2x03

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SLAS734D –APRIL 2011–REVISED NOVEMBER 2011

Port P2 Pin Schematic: P2.0 to P2.5, Input/Output With Schmitt Trigger

MSP430G2x33

MSP430G2x03

SLAS734D –APRIL 2011–REVISED NOVEMBER 2011

www.ti.com

Table 20. Port P2 (P2.0 to P2.5) Pin Functions

CONTROL BITS / SIGNALS(1)

PIN NAME x FUNCTION

(P2.x) P2DIR.x P2SEL.x P2SEL2.x

P2.0/ P2.x (I/O) I: 0; O: 1 0 0

TA1.0/ Timer1_A3.CCI0A 0 1 0

0Timer1_A3.TA0 1 1 0

Pin Osc Capacitive sensing X 0 1

P2.1/ P2.x (I/O) I: 0; O: 1 0 0

TA1.1/ Timer1_A3.CCI1A 0 1 0

1Timer1_A3.TA1 1 1 0

Pin Osc Capacitive sensing X 0 1

P2.2/ P2.x (I/O) I: 0; O: 1 0 0

TA1.1/ Timer1_A3.CCI1B 0 1 0

2Timer1_A3.TA1 1 1 0

Pin Osc Capacitive sensing X 0 1

P2.3/ P2.x (I/O) I: 0; O: 1 0 0

TA1.0/ Timer1_A3.CCI0B 0 1 0

3Timer1_A3.TA0 1 1 0

Pin Osc Capacitive sensing X 0 1

P2.4/ P2.x (I/O) I: 0; O: 1 0 0

TA1.2/ Timer1_A3.CCI2A 0 1 0

4Timer1_A3.TA2 1 1 0

Pin Osc Capacitive sensing X 0 1

P2.5/ P2.x (I/O) I: 0; O: 1 0 0

TA1.2/ Timer1_A3.CCI2B 0 1 0

5Timer1_A3.TA2 1 1 0

Pin Osc Capacitive sensing X 0 1

(1) X = don't care

XIN/P2.6/TA0.1

Direction

0: Input

1: Output

To Module

From Module

PxOUT.y

DVSS

DVCC 1

TAx.y

TAxCLK

PxIN.y

PxSEL.y

PxREN.y

PxDIR.y

PxSEL2.y

PxSEL.y

PxSEL2.y

PxIRQ.y

PxIE.y

Set

Interrupt

Edge

Select

PxSEL.y

PxIES.y

PxIFG.y

XOUT/P2.7

LF off

LFXT1CLK

PxSEL.6, PxSEL.7

BCSCTL3.LFXT1Sx = 11

MSP430G2x33

MSP430G2x03

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SLAS734D –APRIL 2011–REVISED NOVEMBER 2011

Port P2 Pin Schematic: P2.6, Input/Output With Schmitt Trigger

MSP430G2x33

MSP430G2x03

SLAS734D –APRIL 2011–REVISED NOVEMBER 2011

www.ti.com

Table 21. Port P2 (P2.6) Pin Functions

CONTROL BITS / SIGNALS(1)

PIN NAME x FUNCTION P2SEL.6 P2SEL2.6

(P2.x) P2DIR.x P2SEL.7 P2SEL2.7

1 0

XIN XIN 0 1 0

0 0

P2.6 P2.x (I/O) I: 0; O: 1 X 0

61 0

TA0.1 Timer0_A3.TA1 1 0 0

0 1

Pin Osc Capacitive sensing X X X

(1) X = don't care

XOUT/P2.7

Direction

0: Input

1: Output

To Module

From Module

PxOUT.y

DVSS

DVCC 1

TAx.y

TAxCLK

PxIN.y

PxSEL.y

PxREN.y

PxDIR.y

PxSEL2.y

PxSEL.y

PxSEL2.y

PxIRQ.y

PxIE.y

Set

Interrupt

Edge

Select

PxSEL.y

PxIES.y

PxIFG.y

XIN

LF off

LFXT1CLK

PxSEL.6, PxSEL.7

BCSCTL3.LFXT1Sx = 11

from P2.6

MSP430G2x33

MSP430G2x03

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SLAS734D –APRIL 2011–REVISED NOVEMBER 2011

Port P2 Pin Schematic: P2.7, Input/Output With Schmitt Trigger

MSP430G2x33

MSP430G2x03

SLAS734D –APRIL 2011–REVISED NOVEMBER 2011

www.ti.com

Table 22. Port P2 (P2.7) Pin Functions

CONTROL BITS / SIGNALS(1)

PIN NAME x FUNCTION P2SEL.6 P2SEL2.6

(P2.x) P2DIR.x P2SEL.7 P2SEL2.7

1 0

XOUT/ XOUT 1 1 0

0 0

P2.7/ 7 P2.x (I/O) I: 0; O: 1 X 0

0 1

Pin Osc Capacitive sensing X X X

(1) X = don't care

P3.0/TA0.2

P3.1/TA1.0

P3.2/TA1.1

P3.3/TA1.2

P3.4/TA0.0

P3.5/TA0.1

P3.6/TA0.2

P3.7/TA1CLK/CAOUT

Direction

0: Input

1: Output

To Module

From Module

PxOUT.y

DVSS

DVCC 1

TAx.y

TAxCLK

PxIN.y

PxSEL.y

PxREN.y

PxDIR.y

PxSEL2.y

PxSEL.y

PxSEL2.y

MSP430G2x33

MSP430G2x03

www.ti.com

SLAS734D –APRIL 2011–REVISED NOVEMBER 2011

Port P3 Pin Schematic: P3.0 to P3.7, Input/Output With Schmitt Trigger (RHB Package Only)

MSP430G2x33

MSP430G2x03

SLAS734D –APRIL 2011–REVISED NOVEMBER 2011

www.ti.com

Table 23. Port P3 (P3.0 to P3.7) Pin Functions (RHB Package Only)

CONTROL BITS / SIGNALS(1)

PIN NAME x FUNCTION

(P3.x) P3DIR.x P3SEL.x P3SEL2.x

P3.0/ P3.x (I/O) I: 0; O: 1 0 0

TA0.2/ Timer0_A3.CCI2A 0 1 0

0Timer0_A3.TA2 1 1 0

Pin Osc Capacitive sensing X 0 1

P3.1/ P3.x (I/O) I: 0; O: 1 0 0

TA1.0/ 1 Timer1_A3.TA0 1 1 0

Pin Osc Capacitive sensing X 0 1

P3.2/ P3.x (I/O) I: 0; O: 1 0 0

TA1.1/ 2 Timer1_A3.TA1 1 1 0

Pin Osc Capacitive sensing X 0 1

P3.3/ P3.x (I/O) I: 0; O: 1 0 0

TA1.2/ 3 Timer1_A3.TA2 1 1 0

Pin Osc Capacitive sensing X 0 1

P3.4/ P3.x (I/O) I: 0; O: 1 0 0

TA0.0/ 4 Timer0_A3.TA0 1 1 0

Pin Osc Capacitive sensing X 0 1

P3.5/ P3.x (I/O) I: 0; O: 1 0 0

TA0.1/ 5 Timer0_A3.TA1 1 1 0

Pin Osc Capacitive sensing X 0 1

P3.6/ P3.x (I/O) I: 0; O: 1 0 0

TA0.2/ 6 Timer0_A3.TA2 1 1 0

Pin Osc Capacitive sensing X 0 1

P3.7/ P3.x (I/O) I: 0; O: 1 0 0

TA1CLK/ 7 Timer1_A3.TACLK 0 1 0

Pin Osc Capacitive sensing X 0 1

(1) X = don't care

MSP430G2x33

MSP430G2x03

www.ti.com

SLAS734D –APRIL 2011–REVISED NOVEMBER 2011

REVISION HISTORY

REVISION DESCRIPTION

SLAS734 Production Data release

Corrections to Control Bits / Signals column in Table 18

SLAS734A Corrections to Pin Name and Function columns in Table 23

Changed Storage temperature range limit in Absolute Maximum Ratings

SLAS734B Added BSL functions to P1.1 and P1.5 in Table 2

Port P1 Pin Schematic, corrected pin name

Changed Tstg, Programmed device, to -55°C to 150°C in Absolute Maximum Ratings.

SLAS734C Changed TAG_ADC10_1 value to 0x10 in Table 10.

Added AVCC (RHB package only, pin 29) to Table 2 Terminal Functions.

Correct typo in P3.7/TA1CLK description in Table 2.

SLAS734D Corrected pin number for PW28 Input and Output columns in Table 13.

Changed all port schematics (added buffer after PxOUT.y mux) in Port Schematics.

PACKAGE OPTION ADDENDUM

www.ti.com 14-Sep-2011

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

MSP430G2203IN20 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM

MSP430G2203IPW20 ACTIVE TSSOP PW 20 70 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

MSP430G2203IPW20R ACTIVE TSSOP PW 20 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

MSP430G2203IPW28 ACTIVE TSSOP PW 28 50 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

MSP430G2203IPW28R ACTIVE TSSOP PW 28 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

MSP430G2203IRHB32R ACTIVE QFN RHB 32 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

MSP430G2203IRHB32T ACTIVE QFN RHB 32 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

MSP430G2233IN20 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM

MSP430G2233IPW20 ACTIVE TSSOP PW 20 70 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

MSP430G2233IPW20R ACTIVE TSSOP PW 20 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

MSP430G2233IPW28 ACTIVE TSSOP PW 28 50 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

MSP430G2233IPW28R ACTIVE TSSOP PW 28 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

MSP430G2233IRHB32R ACTIVE QFN RHB 32 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

MSP430G2233IRHB32T ACTIVE QFN RHB 32 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

MSP430G2303IN20 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM

MSP430G2303IPW20 ACTIVE TSSOP PW 20 70 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

MSP430G2303IPW20R ACTIVE TSSOP PW 20 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

MSP430G2303IPW28 ACTIVE TSSOP PW 28 50 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

PACKAGE OPTION ADDENDUM

www.ti.com 14-Sep-2011

Addendum-Page 2

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

MSP430G2303IPW28R ACTIVE TSSOP PW 28 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

MSP430G2303IRHB32R ACTIVE QFN RHB 32 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

MSP430G2303IRHB32T ACTIVE QFN RHB 32 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

MSP430G2333IN20 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM

MSP430G2333IPW20 ACTIVE TSSOP PW 20 70 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

MSP430G2333IPW20R ACTIVE TSSOP PW 20 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

MSP430G2333IPW28 ACTIVE TSSOP PW 28 50 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

MSP430G2333IPW28R ACTIVE TSSOP PW 28 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

MSP430G2333IRHB32R ACTIVE QFN RHB 32 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

MSP430G2333IRHB32T ACTIVE QFN RHB 32 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

MSP430G2403IN20 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM

MSP430G2403IPW20 ACTIVE TSSOP PW 20 70 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

MSP430G2403IPW20R ACTIVE TSSOP PW 20 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

MSP430G2403IPW28 ACTIVE TSSOP PW 28 50 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

MSP430G2403IPW28R ACTIVE TSSOP PW 28 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

MSP430G2403IRHB32R ACTIVE QFN RHB 32 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

MSP430G2403IRHB32T ACTIVE QFN RHB 32 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

MSP430G2433IN20 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM

MSP430G2433IPW20 ACTIVE TSSOP PW 20 70 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

PACKAGE OPTION ADDENDUM

www.ti.com 14-Sep-2011

Addendum-Page 3

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

MSP430G2433IPW20R ACTIVE TSSOP PW 20 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

MSP430G2433IPW28 ACTIVE TSSOP PW 28 50 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

MSP430G2433IPW28R ACTIVE TSSOP PW 28 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

MSP430G2433IRHB32R ACTIVE QFN RHB 32 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

MSP430G2433IRHB32T ACTIVE QFN RHB 32 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

MSP430G2533IN20 ACTIVE PDIP N 20 20 Pb-Free (RoHS) CU NIPDAU Level-1-260C-UNLIM

MSP430G2533IPW20 ACTIVE TSSOP PW 20 70 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

MSP430G2533IPW20R ACTIVE TSSOP PW 20 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

MSP430G2533IPW28 ACTIVE TSSOP PW 28 50 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

MSP430G2533IPW28R ACTIVE TSSOP PW 28 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM

MSP430G2533IRHB32R ACTIVE QFN RHB 32 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

MSP430G2533IRHB32T ACTIVE QFN RHB 32 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

PACKAGE OPTION ADDENDUM

www.ti.com 14-Sep-2011

Addendum-Page 4

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

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