1
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Doc. No. 1115, Rev. C
CAT24C01/02/04/08/16
1-Kb, 2-Kb, 4-Kb, 8-Kb and 16-Kb CMOS Serial EEPROM
PIN CONFIGURATION FUNCTIONAL SYMBOL
FEATURES
■ Supports Standard and Fast I2C Protocol
■ 1.8 V to 5.5 V Supply Voltage Range
■ 16-Byte Page Write Buffer
■ Hardware Write Protection for entire memory
■ Schmitt Triggers and Noise Suppression Filters
on I2C Bus Inputs (SCL and SDA).
■ Low power CMOS technology
■ 1,000,000 program/erase cycles
■ 100 year data retention
■ Industrial temperature range
■ RoHS-compliant 8-lead PDIP, SOIC, MSOP
and TSSOP, 8-pad TDFN and 5-lead TSOT-23
packages.
PDIP (L)
SOIC (W)
TSSOP (Y)
MSOP (Z)
TDFN (VP2)
VCC
VSS
SD
A
SCL
WP
CAT24Cxx
A2, A1, A0
DEVICE DESCRIPTION
The CAT24C01/02/04/08/16 are 1-Kb, 2-Kb, 4-Kb,
8-Kb and 16-Kb respectively CMOS Serial EEPROM
devices organized internally as 8/16/32/64 and 128
pages respectively of 16 bytes each. All devices support
both the Standard (100 kHz) as well as Fast (400 kHz)
I2C protocol.
Data is written by providing a starting address, then
loading 1 to 16 contiguous bytes into a Page Write
Buffer, and then writing all data to non-volatile memory
in one internal write cycle. Data is read by providing a
starting address and then shifting out data serially while
automatically incrementing the internal address count.
External address pins make it possible to address
up to eight CAT24C01 or CAT24C02, four CAT24C04,
two CAT24C08 and one CAT24C16 device on the
same bus.
8
7
6
5
VCC
WP
SCL
SDA
NC / A2 / A2 / A2 / A2
NC / NC / NC / A0 / A0
CAT24C16 / 08 / 04 / 02 / 01
NC / NC / A1 / A1 / A1
VSS
1
2
3
4
For the location of Pin 1, please consult the corresponding package drawing.
PIN FUNCTIONS
A0, A1, A2Device Address Inputs
SDA Serial Data Input/Output
SCL Serial Clock Input
WP Write Protect Input
VCC Power Supply
VSS Ground
NC No Connect * Catalyst carries the I2C protocol under a license from the Philips Corporation.
TSOT-23 (TD)
5
4
WP
VCC
SCL
VSS
SDA
1
2
3
For Ordering Information details, see page 16.
CAT24C01/02/04/08/16
2
Doc. No. 1115, Rev. C © 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
ABSOLUTE MAXIMUM RATINGS(1)
Storage Temperature -65°C to +150°C
Voltage on Any Pin with Respect to Ground(2) -0.5 V to +6.5 V
RELIABILITY CHARACTERISTICS(3)
Symbol Parameter Min Units
NEND(4) Endurance 1,000,000 Program/ Erase Cycles
TDR Data Retention 100 Years
D.C. OPERATING CHARACTERISTICS
VCC = 1.8 V to 5.5 V, TA = -40°C to 85°C, unless otherwise specified.
Symbol Parameter Test Conditions Min Max Units
ICCR Read Current Read, fSCL = 400 kHz 1 mA
ICCW Write Current Write, fSCL = 400 kHz 1 mA
ISB Standby Current All I/O Pins at GND or VCC 1μA
ILI/O Pin Leakage Pin at GND or VCC 1μA
VIL Input Low Voltage -0.5 VCC x 0.3 V
VIH Input High Voltage VCC x 0.7 VCC + 0.5 V
VOL1 Output Low Voltage VCC ≥ 2.5 V, IOL = 3.0 mA 0.4 V
VOL2 Output Low Voltage VCC < 2.5 V, IOL = 1.0 mA 0.2 V
PIN IMPEDANCE CHARACTERISTICS
VCC = 1.8 V to 5.5 V, TA = -40°C to 85°C, unless otherwise specified.
Symbol Parameter Conditions Max Units
CIN(3) SDA I/O Pin Capacitance VIN = 0 V 8 pF
CIN(3) Input Capacitance (other pins) VIN = 0 V 6 pF
IWP(5) WP Input Current VIN < VIH, VCC = 5.5 V 200
μA
VIN < VIH, VCC = 3.3 V 150
VIN < VIH, VCC = 1.8 V 100
VIN > VIH 1
Note:
(1) Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this speci-
fication is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
(2) The DC input voltage on any pin should not be lower than -0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than -1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns.
(3) These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC-Q100
and JEDEC test methods.
(4) Page Mode, VCC = 5 V, 25°C
(5) When not driven, the WP pin is pulled down to GND internally. For improved noise immunity, the internal pull-down is relatively strong;
therefore the external driver must be able to supply the pull-down current when attempting to drive the input HIGH. To conserve power,
as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull-down reverts to a weak current source.
CAT24C01/02/04/08/16
3Doc No. 1115, Rev. C
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
A.C. CHARACTERISTICS(1)
VCC = 1.8 V to 5.5 V, TA = -40°C to 85°C.
Symbol Parameter
Standard Fast
UnitsMin Max Min Max
FSCL Clock Frequency 100 400 kHz
tHD:STA START Condition Hold Time 4 0.6 μs
tLOW Low Period of SCL Clock 4.7 1.3 μs
tHIGH High Period of SCL Clock 4 0.6 μs
tSU:STA START Condition Setup Time 4.7 0.6 μs
tHD:DAT Data In Hold Time 0 0 μs
tSU:DAT Data In Setup Time 250 100 ns
tRSDA and SCL Rise Time 1000 300 ns
tF(2) SDA and SCL Fall Time 300 300 ns
tSU:STO STOP Condition Setup Time 4 0.6 μs
tBUF Bus Free Time Between STOP and START 4.7 1.3 μs
tAA SCL Low to Data Out Valid 3.5 0.9 μs
tDH Data Out Hold Time 100 100 ns
Ti(2) Noise Pulse Filtered at SCL and SDA Inputs 100 100 ns
tSU:WP WP Setup Time 0 0 μs
tHD:WP WP Hold Time 2.5 2.5 μs
tWR Write Cycle Time 5 5 ms
tPU(2, 3) Power-up to Ready Mode 1 1 ms
Note:
(1) Test conditions according to “A.C. Test Conditions” table.
(2) Tested initially and after a design or process change that affects this parameter.
(3) tPU is the delay between the time VCC is stable and the device is ready to accept commands.
A.C. TEST CONDITIONS
Input Levels 0.2 x VCC to 0.8 x VCC
Input Rise and Fall Times ≤ 50 ns
Input Reference Levels 0.3 x VCC, 0.7 x VCC
Output Reference Levels 0.5 x VCC
Output Load Current Source: IOL = 3 mA (VCC ≥ 2.5 V); IOL = 1 mA (VCC < 2.5 V); CL = 100 pF
CAT24C01/02/04/08/16
4
Doc. No. 1115, Rev. C © 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
POWER-ON RESET (POR)
Each CAT24Cxx* incorporates Power-On Reset (POR)
circuitry which protects the internal logic against
powering up in the wrong state.
A CAT24Cxx device will power up into Standby mode
after VCC exceeds the POR trigger level and will power
down into Reset mode when VCC drops below the POR
trigger level. This bi-directional POR feature protects
the device against ‘brown-out’ failure following a
temporary loss of power.
* For common features, the CAT24C01/02/04/08/16 will be refered
to as CAT24Cxx
PIN DESCRIPTION
SCL: The Serial Clock input pin accepts the Serial Clock
generated by the Master.
SDA: The Serial Data I/O pin receives input data and
transmits data stored in EEPROM. In transmit mode, this
pin is open drain. Data is acquired on the positive edge,
and is delivered on the negative edge of SCL.
A0, A1 and A2: The Address inputs set the device ad-
dress when cascading multiple devices. When not driven,
these pins are pulled LOW internally.
WP: The Write Protect input pin inhibits all write opera-
tions, when pulled HIGH. When not driven, this pin is
pulled LOW internally.
FUNCTIONAL DESCRIPTION
The CAT24Cxx supports the Inter-Integrated Circuit (I2C)
Bus data transmission protocol, which defines a device
that sends data to the bus as a transmitter and a device
receiving data as a receiver. Data flow is controlled by
a Master device, which generates the serial clock and
all START and STOP conditions. The CAT24Cxx acts
as a Slave device. Master and Slave alternate as either
transmitter or receiver.
I2C BUS PROTOCOL
The I2C bus consists of two ‘wires’, SCL and SDA. The
two wires are connected to the VCC supply via pull-up
resistors. Master and Slave devices connect to the 2-
wire bus via their respective SCL and SDA pins. The
transmitting device pulls down the SDA line to ‘transmit’
a ‘0’ and releases it to ‘transmit’ a ‘1’.
Data transfer may be initiated only when the bus is not
busy (see A.C. Characteristics).
During data transfer, the SDA line must remain stable
while the SCL line is HIGH. An SDA transition while
SCL is HIGH will be interpreted as a START or STOP
condition (Figure 1). The START condition precedes all
commands. It consists of a HIGH to LOW transition on
SDA while SCL is HIGH. The START acts as a ‘wake-up’
call to all receivers. Absent a START, a Slave will not
respond to commands. The STOP condition completes
all commands. It consists of a LOW to HIGH transition
on SDA while SCL is HIGH.
Device Addressing
The Master initiates data transfer by creating a START
condition on the bus. The Master then broadcasts an
8-bit serial Slave address. For normal Read/Write opera-
tions, the first 4 bits of the Slave address are fixed at
1010 (Ah). The next 3 bits are used as programmable
address bits when cascading multiple devices and/or as
internal address bits. The last bit of the slave address,
R/W, specifies whether a Read (1) or Write (0) operation
is to be performed. The 3 address space extension bits
are assigned as illustrated in Figure 2. A2, A1 and A0
must match the state of the external address pins, and
a10, a9 and a8 are internal address bits.
Acknowledge
After processing the Slave address, the Slave responds
with an acknowledge (ACK) by pulling down the SDA
line during the 9th clock cycle (Figure 3). The Slave will
also acknowledge the address byte and every data byte
presented in Write mode. In Read mode the Slave shifts
out a data byte, and then releases the SDA line during
the 9th clock cycle. As long as the Master acknowledges
the data, the Slave will continue transmitting. The Master
terminates the session by not acknowledging the last
data byte (NoACK) and by issuing a STOP condition.
Bus timing is illustrated in Figure 4.
CAT24C01/02/04/08/16
5Doc No. 1115, Rev. C
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Figure 3. Acknowledge Timing
Figure 2. Slave Address Bits
1 8 9
START
SCL FROM
MASTER
BUS RELEASE DELAY (TRANSMITTER) BUS RELEASE DELAY (RECEIVER)
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
ACK DELAY (≤ tAA)
ACK SETUP (≥ tSU:DAT)
START
CONDITION
STOP
CONDITION
SDA
SCL
Figure 1. START/STOP Conditions
Figure 4. Bus Timing
tHIGH
SCL
SDA IN
SDA OUT
tLOW
tF
tLOW
tR
tBUF
tSU:STO
tSU:DAT
tHD:DAT
tHD:STA
tSU:STA
tAA
tDH
1 0 1 0 a10 a9a8R/W CAT24C16
1 0 1 0
A2a9a8R/W CAT24C08
1 0 1 0
A2A1a8R/W CAT24C04
1 0 1 0 A2A1A0R/W CAT24C01 and CAT24C02
CAT24C01/02/04/08/16
6
Doc. No. 1115, Rev. C © 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
WRITE OPERATIONS
Byte Write
In Byte Write mode, the Master sends the START condi-
tion and the Slave address with the R/W bit set to zero
to the Slave. After the Slave generates an acknowledge,
the Master sends the byte address that is to be written
into the address pointer of the CAT24Cxx. After receiv-
ing another acknowledge from the Slave, the Master
transmits the data byte to be written into the addressed
memory location. The CAT24Cxx device will acknowl-
edge the data byte and the Master generates the STOP
condition, at which time the device begins its internal
Write cycle to nonvolatile memory (Figure 5). While this
internal cycle is in progress (tWR), the SDA output will
be tri-stated and the CAT24Cxx will not respond to any
request from the Master device (Figure 6).
Page Write
The CAT24Cxx writes up to 16 bytes of data in a single
write cycle, using the Page Write operation (Figure 7).
The Page Write operation is initiated in the same manner
as the Byte Write operation, however instead of termi-
nating after the data byte is transmitted, the Master is
allowed to send up to fifteen additional bytes. After each
byte has been transmitted the CAT24Cxx will respond
with an acknowledge and internally increments the four
low order address bits. The high order bits that define
the page address remain unchanged. If the Master
transmits more than sixteen bytes prior to sending the
STOP condition, the address counter ‘wraps around’ to
the beginning of page and previously transmitted data
will be overwritten. Once all sixteen bytes are received
and the STOP condition has been sent by the Master,
the internal Write cycle begins. At this point all received
data is written to the CAT24Cxx in a single write cycle.
Acknowledge Polling
The acknowledge (ACK) polling routine can be used to
take advantage of the typical write cycle time. Once the
stop condition is issued to indicate the end of the host’s
write operation, the CAT24Cxx initiates the internal write
cycle. The ACK polling can be initiated immediately. This
involves issuing the start condition followed by the slave
address for a write operation. If the CAT24Cxx is still
busy with the write operation, NoACK will be returned. If
the CAT24Cxx has completed the internal write operation,
an ACK will be returned and the host can then proceed
with the next read or write operation.
Hardware Write Protection
With the WP pin held HIGH, the entire memory is protected
against Write operations. If the WP pin is left floating or
is grounded, it has no impact on the operation of the
CAT24Cxx. The state of the WP pin is strobed on the
last falling edge of SCL immediately preceding the first
data byte (Figure 8). If the WP pin is HIGH during the
strobe interval, the CAT24Cxx will not acknowledge the
data byte and the Write request will be rejected.
Delivery State
The CAT24Cxx is shipped erased, i.e., all bytes are
FFh.
CAT24C01/02/04/08/16
7Doc No. 1115, Rev. C
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Figure 7. Page Write Sequence
Figure 6. Write Cycle Timing
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
ACK8th Bit
Byte n
SCL
SDA
Figure 5. Byte Write Sequence
ADDRESS
BYTE
DATA
BYTE
SLAVE
ADDRESS
S
A
C
K
A
C
K
A
C
K
S
T
O
P
P
S
T
A
R
T
BUS ACTIVITY:
MASTER
SLAVE
* For the CAT24C01 a7 = 0
a7 ÷ a0d7 ÷ d0
Figure 8. WP Timing
1 8 9 1 8
a7a0d7d0
tSU:WP
tHD:WP
ADDRESS
BYTE
DATA
BYTE
SCL
SDA
WP
CAT24C01/02/04/08/16
8
Doc. No. 1115, Rev. C © 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
READ OPERATIONS
Immediate Read
Upon receiving a Slave address with the R/W bit set
to ‘1’, the CAT24Cxx will interpret this as a request for
data residing at the current byte address in memory.
The CAT24Cxx will acknowledge the Slave address,
will immediately shift out the data residing at the current
address, and will then wait for the Master to respond.
If the Master does not acknowledge the data (NoACK)
and then follows up with a STOP condition (Figure 9),
the CAT24Cxx returns to Standby mode.
Selective Read
Selective Read operations allow the Master device to
select at random any memory location for a read opera-
tion. The Master device first performs a ‘dummy’ write
operation by sending the START condition, slave ad-
dress and byte address of the location it wishes to read.
After the CAT24Cxx acknowledges the byte address,
the Master device resends the START condition and
the slave address, this time with the R/W bit set to one.
The CAT24Cxx then responds with its acknowledge and
sends the requested data byte. The Master device does
not acknowledge the data (NoACK) but will generate a
STOP condition (Figure 10).
Sequential Read
If during a Read session, the Master acknowledges the 1st
data byte, then the CAT24Cxx will continue transmitting
data residing at subsequent locations until the Master
responds with a NoACK, followed by a STOP (Figure
11). In contrast to Page Write, during Sequential Read
the address count will automatically increment to and
then wrap-around at end of memory (rather than end
of page). In the CAT24C01, the internal address count
will not wrap around at the end of the 128 byte memory
space.
CAT24C01/02/04/08/16
9Doc No. 1115, Rev. C
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
Figure 11. Sequential Read Sequence
A
C
K
A
C
K
A
C
K
S
T
O
P
N
O
A
C
K
A
C
K
P
SLAVE
ADDRESS
DATA
BYTE
n
DATA
BYTE
n+1
DATA
BYTE
n+2
DATA
BYTE
n+x
BUS ACTIVITY:
MASTER
SLAVE
Figure 10. Selective Read Sequence
SLAVE
S
A
C
K
N
O
A
C
K
S
T
O
P
P
S
T
A
R
T
S
A
C
K
SLAVE
ADDRESS
A
C
K
S
T
A
R
T
DATA
BYTE
ADDRESS
BYTEADDRESS
BUS ACTIVITY:
MASTER
SLAVE
Figure 9. Immediate Read Sequence and Timing
SCL
SDA 8th Bit
STOPNO ACKDATA OUT
8 9
SLAVE
ADDRESS
S
A
C
K
DATA
BYTE
N
O
A
C
K
S
T
O
P
P
S
T
A
R
T
BUS ACTIVITY:
MASTER
SLAVE
CAT24C01/02/04/08/16
10
Doc. No. 1115, Rev. C © 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
PACKAGE OUTLINE
8-lead 300 MIL Wide Plastic DIP (L)
A
e
b
E1
b2
L
A2
A1
E
D
eB
24C16_8-LEAD_DIP_(300P).eps
SYMBOL
A
A1
b
b2
D
E
E1
e
eB
L
MIN
0.38
0.36
9.02
7.62
6.09 6.35
7.87
0.115 0.130 0.150
NOM
0.46
1.771.14
7.87
2.54 BSC
MAX
4.57
A2 3.05 3.81
0.56
10.16
8.25
7.11
9.65
Notes:
(1) All dimensions are in millimeters. Angels in degrees.
(2) Complies with JEDEC Standard MS001.
(3) Dimensioning and tolerancing per ANSI Y14.5M-1982
CAT24C01/02/04/08/16
11 Doc No. 1115, Rev. C
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
8-lead 150 Mil Wide Soic (W)
24C16_8-LEAD_SOIC.eps
SYMBOL
A1
A
b
C
D
E
E1
h
L
MIN
0.10
1.35
0.33
4.80
5.80
3.80
0.25
0.40
NOM
0.250.19
MAX
0.25
1.75
0.51
5.00
6.20
4.00
e 1.27 BSC
0.50
1.27
θ
1 0°8°
E
E1
D
A1
e
L
θ1
C
b
h x 45
A
Notes:
(1) All dimensions are in millimeters. Angels in degrees.
(2) Complies with JEDEC specification MS-012 dimensions.
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
CAT24C01/02/04/08/16
12
Doc. No. 1115, Rev. C © 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
8-Lead TSSOP (Y)
85
14
E E1
E/2
PIN #1 IDENT.
D
b
L
θ1
e
A
A1
A2
SEE DETAIL A
SEE DETAIL A
SEATING PLANE
c
GAGE PLANE
0.25
SYMBOL
A
A1
A2
b
c
D
E
E1
e
L
θ
1
MIN
0.05
0.80
0.09
2.90
6.30 6.4
4.30
0.00 8.00
NOM
0.90
0.300.19
3.00
4.40
0.60 0.750.50
MAX
1.20
0.15
1.05
0.20
3.10
6.50
4.50
0.65 BSC
Notes:
(1) All dimensions are in millimeters. Angels in degrees.
(2) Complies with JEDEC specification MO-153.
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
CAT24C01/02/04/08/16
13 Doc No. 1115, Rev. C
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
8-Lead MSOP (Z)
c
E
E1
e
b
D
A2 A
A1
L2
GAUGE
PLANE
L
L1
SYMBOL MIN NOM MAX
A 1.1
A1 0.05 0.10 0.15
A2 0.75 0.85 0.95
b 0.28 0.33 0.38
c
D 2.90 3.00 3.10
E 4.80 4.90 5.00
E1 2.90 3.00 3.10
e 0.65 BSC
L 0.35 0.45 0.55
L1
L2
0° 6°
8-lead_MSOP.eps
Notes:
(1) All dimensions are in millimeters. Angels in degrees.
(2) Complies with JEDEC specification MS-187.
(3) Stand off height/coplanarity are considered as special characteristics.
For current Tape and Reel information,
download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
CAT24C01/02/04/08/16
14
Doc. No. 1115, Rev. C © 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
8-PAD TDFN 2X3 PACKAGE (VP2)
E2
A2
E
PIN 1 INDEX AREA
L
TDFN2X3
(
03
)
.e
ps
A3
PIN 1 ID
e
b
A1
3 x e
D2
D
A
SYMBOL
A
A1
A2
A3
b
D
D2
E
E2
e
L
MIN
0.70
0.00
0.45
0.20
1.90
1.30 1.40
2.90
1.20
0.20 0.30 0.40
NOM
0.75
0.02
0.55
0.20 REF
0.25
2.00
3.00
0.50 TYP
MAX
0.80
0.05
0.65
0.30
2.10
1.50
3.10
1.401.30
Notes:
(1) All dimensions are in millimeters. Angels in degrees.
(2) Complies with JEDEC specification MO-229.
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
CAT24C01/02/04/08/16
15 Doc No. 1115, Rev. C
© 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
5-Lead TSOT-23 (TD)
A2 A
A1
D
e
b
E
E1
e1
e
E1
L2
GAUGE
PLANE
L
L1
c
5 LEAD TSOT-23 PACKAGE
MAX
1.0
0.1
0.9
0.45
0.20
0.50
8°
θ
NOM
—
0.05
0.87
—
0.15
2.90 BSC
2.80 BSC
1.60 BSC
1.90 BSC
0.40
0.25 BSC
MIN
—
0.01
0.80
0.30
0.12
0.30
0°
SYMBOL
A
A1
A2
b
c
D
E
E1
0.95 BSCe
e1
L
0.60 REFL1
L2
θ
Notes:
(1) All dimensions are in millimeters. Angels in degrees.
(2) Complies with JEDEC specification MO-193.
For current Tape and Reel information, download the PDF file from:
http://www.catsemi.com/documents/tapeandreel.pdf.
CAT24C01/02/04/08/16
16
Doc. No. 1115, Rev. C © 2006 by Catalyst Semiconductor, Inc.
Characteristics subject to change without notice
EXAMPLE OF ORDERING INFORMATION
Notes:
(1) All packages are RoHS-compliant (Lead-free, Halogen-free).
(2) The standard lead finish is NiPdAu pre-plated (PPF) lead frames.
(3) The device used in the above example is a CAT24C16YI-GT3 (TSSOP, Industrial Temperature, NiPdAu, Tape & Reel).
(4) For availability, please contact your nearest Catalyst Semiconductor Sales Office.
(5) For additional package and temperature options, please contact your nearest Catalyst Semiconductor Sales office.
Prefix Device # Suffix
24C16 Y I T3
Product Number
24C01
24C02
24C04
24C08
24C16
G–CAT
Temperature Range
I = Industrial (-40°C to +85°C)
Company ID T: Tape & Reel
3: 3000/Reel
Package
L: PDIP
W: SOIC, JEDEC
Y: TSSOP
Z: MSOP (4)
VP2: TDFN
TD: TSOT
Lead Finish
G: NiPdAu
Blank: Matte-Tin
Catalyst Semiconductor, Inc.
Corporate Headquarters
2975 Stender Way
Santa Clara, CA 95054
Phone: 408.542.1000
Fax: 408.542.1200
www.catsemi.com
Publication #: 1115
Revison: C
Issue date: 11/29/06
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Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:
AE2 ™, Beyond Memory ™, DPP ™, EZDim ™, MiniPot™ and Quad-Mode ™
Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products.
CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS
PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE
RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING
OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.
Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or
other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a
situation where personal injury or death may occur.
Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets
labeled “Advance Information” or “Preliminary” and other products described herein may not be in production or offered for sale.
Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate
typical semiconductor applications and may not be complete.
REVISION HISTORY
Date Revision Comments
07/18/06 A Combine 5 data sheets into one data sheet.
07/31/06 B Update Package Marking
11/29/06 C Update Features
Update Pin Configuration
Update Functional Symbol
Added 8-Lead MSOP Package Outline
Remove Package Marking
Update Example of Ordering Information