ANALOG DEVICES FEATURES Ultra-High Linearity (Nontinearity <+1 Count) Output Versatility With External Counters and Registers High Resolution Up to 1:40,000 (ADC1105K) Up to 1:4,000 (ADC1105J) Excellent Zero Stability User Choice of Input Ranges Accepts Unipolar or Bipolar Inputs Low Profile 2 x 4 x 0.6" Module Special Mounting Card Available Ratiometric Capability Automatic Sample Capability GENERAL DESCRIPTION The ADC1105 is a precision dual slope anzlog-to-digital con- verter which is designed for use with external counters and registers. With this product, the designer can build conversion systems which utilize any desired counting scheme and which have resolutions up to and including 4 BCI) digits (or 14 binary bits) plus 100% overrange plus sign. This versatility is particularly useful in instrumentation applications where it is desired to have outputs scaled directly in terms of engi- neering or physical units (e.g. pounds and ounces). Performance specifications for the ADC1105 include 2uV/C zero stability, 5ppm/C gain temperature coefficient, and +0.0015%/%Vzs power supply sensitivity. The ADC1105 is compatible with TTL/DTL as well as certain older RTL systems. It can be configured to perform conver- sions on command or automatically at a rete controlled by simple external circuitry. The ADC1105 a so offers both a +10V and a +1V input range, each with 100% overrange capability. BASIC OPERATION As a dual slope converter, the ADC1105 produces a pulse train output, the number of pulses in which is proportional to the analog input voltage. It also provides all of the signals needed to properly control the external counters and registers. A simple parallel output analog-to-digital con- verter built around the ADC1105 is shown in Figure 1. Although this represents a typical arrangement it is by no means the only one possible. Detailed timing diagrams and High Linearity, High Resolution, Dual Slope A/D Converter descriptions of terminal input/output characteristics will be presen<ed in a later section to aid the designer in adapting the ADC1105 to his systems particular requirements. POLARITY ANALOG _] OVERRANGE INPUT MSB PULSE REGISTER ee TRAIN COUNTER ACC1105 LsB RESET } CARRY CONVERT COMMAND LATCH Figure 1. Basic Converter Block Diagram The conversion cycle begins when the convert command is applied. The counter is reset to zero, input integration begins, and output pulses are generated. When the counter reaches full scale, a carry signal is sent back to the ADC1105 to initiate reference integration. When the integrator voltage returns to zero, the pulse train stops and the output register is strobed. The polarity signal is generated at the end of the input inte- gration period; the overrange signal is generated during the reference integration period and is valid at the end of conversion. A/D CONVERTERS 441SPECIFICATIONS (typical @ +25C and nominal supply voltages, unless otherwise noted) MODEL RESOLUTION NON-LINEARITY? ANALOG INPUT RANGES! INPUT IMPEDANCE TEMPERATURE COEFFICIENTS Gain? Offset Reference CONVERSION TIME CONVERSION RATE ADC1105J Up to 3%BCD Digits or 10 Binary Bits Plus Sign <+t1 Count 1V Full Scale +10V Full Scale 100kQ2/Vclt +1% +10ppm/C max +2nV/C max; 1V Range +20uV C max; 10V Range +20ppm/C max See Table ?? See Table 2 ADC1105K Up to 44%BCD Digits or 14 Binary Bits Plus Sign <+1 Count * * * +5ppm/C max * * +5ppm/C max * ae REFERENCE VOLTAGE Fixed Reference +6.2V $5% * Ratiometric +20V max * CLOCK FREQUENCY 200kHz +10% * Adjustment Range +10kHz * DIGITAL INPUTS See Digital Input Characteristics Text DIGITAL OUTPUTS See Digital Output Characteristics Text POWER SUPPLY REQUIREMENTS +5V +5% @ 120mMA +15V 5% @ 45mA -15V 45% @ 35mMA * * * POWER SUPPLY SENSITIVITY +0.0015%/%V5 * TEMPERATURE RANGE Operating Storage 0 to +50C -25C to +85C MTBF (CALCULATED) 70,000 Hours *Same as ADC 1105). 1 Each input range has 100% overrange capability, thereby permitting inputs of +2V and 20V respectively. 7Exclusive of reference. 3 Difference between the actual input-output transfer function and the theoretically perfect straight-line through zero and + cr ~ full scale. Specifications subject to change without notice. BLOCK DIAGRAM AND PIN DESIGNATIONS PULSE TRAIN 1 CONVERT COMMAND 4 OVERRANGE IN B OVERRANGE QUT 9 OVERRANGE Our 12 CTR.CARAY 13 POLARITY {117 POLARITY (45 13 RAMP DOWN 20 G) REF 23 REF ANALOG GND 26 ND SQUHCE (-) REE 78 6.20 ()INREE 29 620 ke bv 34 CHIN REF 35 INTERNAL clock CONTROL roGic 71 45v 70 OIG. GND 69 SAMP. RATE ADJ. 68 FREQ. CONTROL 63 END OF CONV. 62 CTR. RESET 61 EXT CLKIN TO ANALOG SITCHES. +15V INTEGRATOR ne | oan tisy DRIFT :ORRECT SWUT THES 111kS2 40 RANGE SELECT 39 ZERO ADJ. 38 ANALOG IN INPUT SWITCH REFERENCE SWITCHES 442 A/D CONVERTERS OUTLINE DIMENSIONS Dimensions shown in inches and (mm). = 2.01 MAX 61.0) 0.81 MAX (15.5) q 0.2 MIN 6.1) 4.03 MAX 1102.4} BOTTOM VIEW GRID 0,1 (2.5) NOTE: Terminal pins installed only in shaded hole locations. Module weight: 4 ounces (114 grams). All pins are gold-plated half-hard brass plated per MIL-G-45204; 0.019 +0.001 dia. (0.48mm +0.03mm). ORDERING GUIDE: ADC1105J (Module Only) ADC1105K (Module Only) ANDC1105J/AC1547J (Module Mounted on Card) ADC1105K/AC1547K (Module Mounted on Card)CONVERSION SEQUENCE Figures 2a and 2b below illustrate the interaction of the ADC1105s various inputs and outputs during two conversion cycles. Figure 2a shows the sequence of eve:1ts for a negative polarity, overrange input of -12V while Figure 2b shows the sequence for a positive, in-range input of +8V. Both examples assume that the 10V range of the ADC1105 is selected and that a 4 digit BCD counter with a full scale count of 9999 is being used. CONVERT 1 COMMAND 0 uU J COUNTER 1 RESET 0 J SL THAIN gE EEE EEE EEE SIH meanaron J ee VOLTAGE ov ee i COUNTER 1 CARRY o LJ | | END OF 1 CONVERSION 0 ia overrance | | | OVERAANGE b l POLARITY (+) VD i POLARITY [-) q ee nn 9 RAMP 1 _ DOWN, oT mm LT to u te Figure 2a. Timing Diagram CONVERT 1 COMMAND o U uU COUNTER 1 RESET 0 1 fk s 1 TRAIN 9 SE EEE EE ov - a - ae INTEGRATOR VOLTAGE ; ee COUNTER 1 CARRY LJ lL. END OF 1 CONVERSION 0 Y OVERRANGE , 1 OVERRANGE } J POLARITY (4) ; J POLARITY {-) 3 L RAMP 1 = DOWN 0 _. a | L Figure 2b. Timing Diagram At time tg a conversion is commanded by the 1 to 0 transition of the CONVERT COMMAND input (Pin 4). This causes a lus positive pulse to be generated at the COUNTER RESET terminal (Pin 62) which sets the counter to 0000. After the counter is reset, a 200kHz pulse signal is generated at the PULSE TRAIN OUTPUT terminal (Pin 1), the integrator comes out of drift correct, and input integration begins. The pulse train causes the counter to increment upwards and when the transition from 9999 to 0000 finally occurs, a O to 1 transition is sensed at the COUNTER CARRY INPUT ter- minal (Pin 13). This causes reference integration to begin. Since the input signal was negative, the POLARITY (+) output (Pin 19) goes to a O and the POLARITY () output (Pin 17) goes to a 1 at this time. The RAMP DOWN output (Pin 20) also goes to a 1 indicating that reference integration is in progress. Because the input signal exceeds -10V, the integrator does not fully discharge before the counter reaches 3999. Therefore, when the counter goes from 9999 to 0000, a 0 to 1 transition is sensed at the OVERRANGE IN terminal (Pin 8) causing the OVERRANGE output (Pin 9) to go to a 1 and the OVERRANGE output (Pin 12) to go to a QO. At time ty, the integrator finally discharges and a 1s negative pulse is generated at the END OF CONVERSION output (Pin 63). The pulse train stops and the RAMP DOWN output returns to 0. At time tz another conversion is commanded with the analog input at +8V. The events which occur are identical to those of the previous conversion except that on the 1 to O transi- tion of zhe CONVERT COMMAND input, the OVERRANGE and the POLARITY (+) are reset to 1 and the OVERRANGE and the POLARITY (-) are reset to 0. Because the input sig- nal is positive, the POLARITY (+) and POLARITY (-) outputs do not change state at the start of reference integration and since the integrator fully discharges before the external counter state. CONVERSION TIME The conversion time of the ADC1105 consists principally of the input and reference integration periods. The length of the input integration period (T,,) depends on the clock frequency (f.) and the counters full scale setting (Cpg) as expressed by the following equation: _&s__ f,, (kHz) The following table, Table 1, lists input integration periods for various counter configurations at the nominal 200kHz clock frequency. Tpy (ms) = Counter Size Input Integration Period 8 Bit Binary 1.28ms 10 Bit Binary 5.12ms 12 Bit Binary 20.48ms 14 Bit Binary 81.92ms 3 Digit BCD 5.00ms 4 Digit BCD 50.00ms Table 1. Input Integration Period Note that because of the OVERRANGE and POLARITY out- puts, the total converter resolution will be greater than the counter size. For example, a converter using an 8 bit binary counter can have a 10 bit sign-magnitude binary coded output. The reference integration period (Tpyp) is related to the input integration period (T,,,) by the following expression: x Vin . Vin = analog input in volts Ves Ves = 10V or 1V (depending on the range selected) Because the 100% overrange condition represents the maximum permissible input level, the maximum reference integration period is twice the input integration period. Table 2 below lists the maximum total conversion times and resulting mini- mum conversion rates for various counter configurations at the nominal 200kHz clock frequency TREF (ns) = Tyy Counter Size Total Conversion Time Conversion Rate 8 Bit Binary 3.84ms 260/sec 10 Bit Binary 15.36ms 65/sec 12 Bit Binary 61.44ms 16/sec 14 Bit Binary 245.76ms 4/sec 3 Digit BCD 15.00ms 66/sec 4 Digit BCD 150.00ms 6/sec Table 2. Maximum Total Conversion Time and Minimum Conversion Rates A/D CONVERTERS 443DIGITAL INPUT CHARACTERISTICS Convert Command (Pin 4) A 1 to OQ transition with a 2us max fa/l time initiates con- version. The O state must be held for at least 100ns. If con- versions are to be commanded by the automatic sample rate circuitry, this input must be tied to ground. 1TTL load (max). Counter Carry (Pin 13) A 0 to 1 transition at this terminal indicates that the ex- ternal counter has reached full scale and returned to zero. The 1 state must be held for at least 30ns. 2TTL loads (max). Overrange In (Pin 8) A 0 to 1 transition at this terminal indicates that the ex- ternal counter has reached full scale and returned to zero. It is used to determine if an overrange condition has occurred and in normal operation is jumpered to Pin 13. 2TTL loads (max). External Clock In (Pin 61) An external clock with a maximum frequency of 250kHz will override the internal clock when connected to this terminal. In this mode of operation the convert command must be syn- chronized to the 1 to 0 transition of the clock pulse. 1TTL load (max). DIGITAL OUTPUT CHARACTERISTICS Gated Pulse Train (Pin 1) This is a 200kHz (nominal) positive pulse cutput with a 1ys pulse duration. It is capable of driving 10T TL loads (min). Counter Reset Output (Pin 62) This is a lus positive pulse which is used to reset the counter at the start of conversion. The output circuit consists of an NPN emitter-follower with a 392 series resistor which is capable of supplying 40mA (max). When a 270Q, resistor is connected between this pin and ground, ore standard TTL load can be driven. End of Conversion (Pin 63) This is a 1s negative pulse which is used to signal the end of conversion and/or strobe an external register. The output cir- cuit consists of an NPN emitter follower with a 220 series resistor which is capable of supplying 40m.4 (max). When a 270Q resistor is connected between this pia and ground, one standard TTL load can be driven. Polarity (-) (Pin 17) This output is set to a O each time a conversion is com- manded. If the analog input signal is negative it will go to 1 at the start of reference integration and rernain there until the next conversion. This output is capable of driving 8TTL loads (min). Polarity (+) (Pin 19) This is the complement of the signal at Pin 19. It is also capable of driving 8TTL loads (min). Overrange (Pin 9) This output is set to 0 each time a conversion is commanded. If an overrange condition is detected during reference integra- tion it will go to a 1 and remain there until the next conver- sion. This output is capable of driving 10T'TL loads (min). Overrange (Pin 12) This is the complement of the signal at Pin 9. It is also capable of driving 1OTTL loads (min). Ramp Down (Pin 20) This output goes from a 0 to a 1 at the end of input inte- gration and returns to 0 at the end of conversion. It is capable of driving 4TTL loads (min). The '1 state indicates that reference integration is in progress. 444 A/D CONVERTERS OTHER EXTERNAL CONNECTIONS Sample Rate Control The AMC1105 will automatically perform conversions at a rate which can be varied from 0.2 to 260 conversions per second if the external circuitry of Figure 3 is connected. SAMPLE RATE CONTROL (PIN 69} O ay 100kS2 Vvaw 45V (PIN71) OO'C + she 10uF IM22 7 oisv 1/2W DIGITAL GROUND (PIN 70) Q-_______] Figure 3. External Sample Rate Control Circuit Range Selection The nominal +1V and +10V input ranges will accept inputs of +2V max and 20V max because of their 100% overrange capability. Figure 4 shows a switching arrangement which allows selection of either input range. ANALOG ANALOG INPUT {PIN 38) O- INPUT Ww RANGE . SELECT (PIN 40) Q RANGE ANALOG ; 10V GROUND (PIN 26) RANGE Figure 4. Range Selection Circuit Clock frequency Adjustment The internal clock runs at 200kHz +10%. If the external cir- cuitry of Figure 5 is connected, this clock frequency can be varied 3y as much as +10kHz. +5V (PIN 71) OQ CLOCK cw FREQ. ADJ. (PIN 68) 0 10kQ. DIGITAL GROUND (PIN 70) O~ Figure 5. Clock Frequency Adjust Circuit Zero Adjustment The circuit of Figure 6 is used to precisely adjust the zero point. A detailed description of the adjustment procedure follows in a later section. + REF PIN 23 O---_ ZERO cw Se ADJUST PIN 39 Q<_ 100k ] 20 TURN ~ REF PIN 28 Figure 6. Zero Adjust Circuit Gain Adjustment The circuit of Figure 7 is used to set the +FS and -FS points once the zero point has been adjusted. A detailed description of the adjustment procedure follows in a later section. <) PIN 28 - REF +REF PIN 23 | > Ss 2k {MODEL K) cw 4 20k (MODEL J) cw + REF q 20 TURN REF PIN 35 INPUT PIN 29 O-__~ INPUT A WV Figure 7. Gain Adjust Circuits External Reference Connections As shown in Figure 8, external reference sources may be used in place of the ADC1105s internal references. These external sources must supply +6.2V +5% @ +10uA and -6.2V 5% @ -10uA respectively.EXTERNAL EXTERNAL REFERENCE O--- REFERENCE SOURCE (+) [ SOURCE (-) 2. s 2ks2 (MODEL XK) > cw 4 20k (MODEL J) | cw TURN | + REF 5 zor P - REF INPUT {PIN 29) _-4 L_--= (PIN 35) INPUT Figure 8. External Reference Connections Two quadrant ratiometric operation is achieved by applying any voltage between 0 and +20V to the EXTERNAL REFER- ENCE SOURCE (+) input of Figure 8 while the same voitage is applied with opposite polarity to the EXTERNAL REFER- ENCE SOURCE (-) input. The converters output (Coy) in this case is related to the analog input (V,,) and the magnitude of the reference signal (Vppy) by the following equations: Cour = 6-2 VIN. for the 1V OUT = -4Cps XG ; for the range REF Vin = 0.62Cpg x - ;for the 10V range VREF Where Cgsg is the counters full scale count. In no case should values of Vpy and Vpgp be applied which would result in a Cour which exceeds 2 CruL SCALE: A typical external circuit used to implement ratiometric opera- tion is shown below in Figure 9. EXT REF R SO IRCE (+) o td vw . o EXT REF (vin 2 0) SOURCE (-) LC UNITY GAIN = BUFFER Figure 9. Additional Circuit for 2-Quadrant Ratiometric Operation Power Supply Connections The power supplies should be connected as shown below in Figure 10. +15V PIN 45 Q__ | -15V | 215V PIN 34 O-_ supp. RETURN (ANALOG GROUND) PIN 26 JUMPER CONNECTED CLOSE TO THE MODULE TIZRMINALS RETURN {DIGITAL GROUND) PIN 70 +5V +5V PIN710 SUPPLY Figure 10. Power Supply Connections Appropriate bypass capacitors have been included to reduce the effects of stray high frequency noise on the power supply busses. THE AC1547 MOUNTING CARD The AC1547 is an optional 4.50 x 2.77 printed circuit mounting card which has been specifically designed for use with the ADC1105 module. This card contains the three re- quired adjustment potentiometers (+Gain, ~Gain, and Zero), plated-through holes which are drilled out if external refer- ences are used, and a capacitor which simplifies connection of the external sample rate control circuit. When both an ADC1105 and an AC1547 are ordered, the module and card are soldered together and shipped as a single unit. Connec- tions te the card are made with a Cinch 25 1-22-30-160 (or equivalent) dual 22 pin edge connector. The pin designa- tions are listed below in Table 3. Card Module Card Module Pin Function Pin Pin Function Pin 1 END OF CONVERSION 63 A POLARITY (-) 17 2 COUNTER CARRY 13 B NC - 3 NC - Cc POLARITY (-) 17 4 NC - D CLOCK FREQ. ADJ. 68 5 (OVERRANGE IN 8 E EXT. CLOCK IN 61 6 (OVERRANGE OUT 9 F CONVERT COMMAND 4 7 (QVERRANGE OUT 12 H RAMP DOWN 20 8 (GATED PULSE TRAIN 1 J NC - 9 JIGITAL GROUND 70 K DIGITAL GROUND 70 10 hiv 71 L 45V 71 11 SAMPLE RATE CONTROL] 69 M POLARITY (+) 19 12 -15V 34 N -15V 34 13 rISV 45 P 4+15V 45 14-20] NC - R COUNTER RESET 62 21 + REF 23 s-W NC - 22 - REF 28 xX ANALOG INPUT 38 Y RANGE SELECT 40 Zz ANALOG GROUND 26 Table 3. Pin Designations The two plated-through holes located between the +Gain and -Gain potentiometers must be drilled out to disconnect the modules internal references if external reference sources are to be used. When this is done, the circuit of Figure 8 results, with mounting card pins 21 and 22 representing the External Reference Source (+) and External Reference Source (-) in- puts respectively. The external sample rate control circuit may be configured in several ways. If the circuit of Figure 3 is connected external to the mounting card, the sample rate can be varied from 4 conversions per minute to 86 conversions per second. If this same circuit is used but the +15V rather than the +5V supply is used, the sample rate can be varied from 0.2 to 260 conver- sions per second. If a fixed sample rate is desired, mounting card pin 11 is connected to the +5V supply and a 1/4W resis- tor is sabstituted for the jumper which is physically located between the zero adjust pot and the 10uF capacitor. A resis- tance clecade box can be used to empirically determine the value of resistance needed to achieve the desired sample rate. Figure 11 below shows the outline dimensions and layout of the AC1547 mounting card. 277 (70.4) 3 (7.6) PLATED-THROUGH |. HOLES {DRILLED OUT WHEN EXTERNAL REFERENCES ARE USED) 4.50 (114.3} ADC1105 MODULE _ 2260 {90 4) JUMPER (CAN BE REPLACED BY A I. RESISTOR FOR _d | ON-THE-CARD c . SAMPLE RATE 7 2.00 (60.8) CONTROL} | - 0.850 E Sc ~T (21.61 O.225 | (87) OA70 (149) en) 4 Figure 11. AC1547 Mounting Board Outline Dimensions Dirnensions Shown in Inches and (mm) A/D CONVERTERS 445ADJUSTMENT PROCEDURE The adjusement procedure described in this section should be carefully followed to take full advantage of the ADC1105s high degree of resolution and accuracy. The voltage standard used in this procedure must be capable of providing stable outputs with #1/10LSD resolution and accuracy in the region of ZERO, +FULL SCALE, and -FULL SCALE. To adjust the zero point, apply a small positive signal to the analog input (e.g., +1mV for the 1V scale of a 4% digit BCD converter). Use the zero adjust potentiometer to increase the counter output until it just changes to the correct value. Re- verse the analog input polarity and observe that the polarity output has changed and that the counter output is within one count of the previous reading. Apply small adjustments to the zero adjust potentiometer as necessary until the counter output is the same for the positive and negative inputs. Once the zero point has been adjusted, apply a +FULL SCALE analog input. Use the +GAIN adjustment potentiometer to in- crease the counter output until it just changes to one count above +FULL SCALE. Reverse the analog input polarity and repeat the procedure this time using the -GAIN potentiometer. APPLICATIONS Several converter configurations are shown below to demon- strate the versatility of the ADC1105. Because so many dif- ferent TTL counters and registers are available, each one having its own interface requirements, block diagrams rather than schematics are used. Figure 12 below shows the ADC1105 connected as a 14-bit sign- magnitude binary coded converter. Because of the nature of sign-magnitude code, the POLARITY (+) output is equivalent to the MSB. The OVERRANGE output is used as the next least significant bit and three 4-bit binary counters are used for the remaining 12 bits. A simple flip-flop is used to indicate the status of the digital output. The CONVERT COMMAND sets the STATUS output to a 1 and the END OF CONVER- SION pulse resets it to a 0. The digital output is only valid while the STATUS output is low. - BIT 1 (MSB) -o BIT2 a z gf; oss c2 ef Polat 4 Bo S19 -o'aIT s 8 5:2 -o airs xz POLARITY (+) bm } OVERRANGE 5 COUNTER CARRY Q > De 2g -onr7 5 Qe es -O 8IT 8 2 3, Sue -feoeis mis CONVERT a a Qt BIT 10 COMMAND COUNTER RESET x PULSE TRAIN END OF CONV. } Oo 5 ais -o BIT 11 22 eh fos Bo 49 boars 8 5st -o BIT 14 (LSB) R 12 -o@ STATUS Af-~o1 STATUS: L384Hd YTD Figure 12. 14-Bit Sign-Magnitude Binary Converter 446 A/D CONVERTERS The converter of Figure 13 demonstrates how the external counter can be configured to give outputs expressed directly in engineering units. In this case the ADC1105 is used in a simple weighing system to receive analog inputs from a load cell and send latched BCD outputs (199 Ibs. 15 oz. max) toa display. The 0 to 15 count which corresponds to the number of ounces is implemented with a 4-bit binary counter and a Binary-:0-BCD converter. The 2% digits corresponding to the number of pounds are generated by two decade counters and the OVERRANGE output. In this type of application the ex- ternal sample rate control circuit would be used to provide automatic repetitive conversions. ool 420719 AWYYo W31NNOO aavo3q OL zor 08 saNnnod 490719 AHNYD yaLNnoo qqvoad L2re OVERRANGE COUNTER CARRY sousay wva13 49079 ABHYD w3iNN09 Nig ad ANOD G98 OL AYWNIG z2eeB Oo 839NN0 1 COUNTER RESET PULSE TRAIN END OF CONVER. Figure 13. Simple Weighing System Note that exclusive of polarity, the ADC1105K can resolve up to one part in 20,000 while the ADC1105J can resolve up to one part in 2000. When designing 2 converter which uses a specialized counting scheme, the number of possible counter states must be computed to determine which version to use. In the above example, the full scale count was 199:15 and, therefore, the number of possible states is 200 x 16 = 3200. It is clear that the ADC1105K would be the proper model to choose.