W83601R/G/W83602R/G W83601R/W83601G/ W83602R/W83602G Winbond GPI/O IC -1- Publication Release Date: May 26, 2005 Revision 1.0 W83601R/G/W83602R/G Table of Contents1. GENERAL DESCRIPTION ......................................................................................................... 3 2. FEATURES ................................................................................................................................. 3 3. PACKAGE ................................................................................................................................... 3 5. PIN CONFIGURATION FOR W83601R/602R............................................................................ 4 6.1 7. 8. REGISTERS ............................................................................................................................... 7 7.1 Brief of register contents................................................................................................. 7 7.2 W83601R/G/W83602R/G Registers Descriptions .......................................................... 8 FUNCTION DESCRIPTIONS.................................................................................................... 12 8.1 9. W83602R/G Universal General Purpose I/O Port for I2C BUS & ACPI Power Control . 6 ACCESS INTERFACE.................................................................................................. 12 8.1.1 Write a data into W83601R/G/W83602R/G register .......................................................12 8.1.2 Read a data from W83601R/G/W83602R/G register......................................................12 8.2 CTLSTRV Timing Waveforms (Only for W83602R/G) ................................................. 13 8.3 CTL3VSB Timing Waveforms (Only for W83602R/G).................................................. 13 8.4 GPI/O Output Mode : .................................................................................................... 14 8.4.1 GPO output ....................................................................................................................14 8.4.2 INT output.......................................................................................................................14 8.4.3 GPI interrupt status.........................................................................................................14 DC AND AC SPECIFICATION.................................................................................................. 15 9.1 Absolute Maximum Ratings .......................................................................................... 15 9.2 DC Characteristics ........................................................................................................ 15 9.3 AC Characteristics ........................................................................................................ 16 9.3.1 Serial Bus Timing Diagram.............................................................................................16 10. PACKAGE DRAWING AND DIMENSIONS.............................................................................. 17 11. REVISION HISTORY ................................................................................................................ 21 -2- W83601R/G/W83602R/G 1. GENERAL DESCRIPTION W83601R/G/W83602R/G are general purpose input/output ICs with SMBusTM( I2C ). W83601R/G provides 15 GPI/O pins. W83602R/G provides 10 GPI/O pins and ACPI power control function for STR. W83601R/G/W83602R/G both provides SMBusTM (I2C) address setting pins to set the address during power- on reset or from external reset. W83601R/G SMBusTM Address is: 0 0 1 1 A2 A1 A0 R/W W83602R/G SMBusTM Address is: 0 0 1 1 0 A1 A0 R/W W83601R/G/W83602R/G also provides a interrupt to inform system that a transition occurs on General Purpose (GP) input pins. 2. FEATURES y SMBus compliance with 3.3V voltage levels y Two ports GPI/O which provides more flexibility y Issue interrupts to notify system that an event occurs y GP output can be level or pulse mode y Interrupt output can be level or pulse mode y Internal power-on reset or external RST# pin reset y Programmable POWER LED output y ACPI power management for Suspend to Ram (STR) (only for W83602R/G) 3. PACKAGE y 20-pin SSOP 4. 4. KEY SPECIFICATIONS y Supply Voltage y Operating Supply Current 1 mA typ. y Operating Temperature 0 - 70 C 5V -3- Publication Release Date: May 26, 2005 Revision 1.0 W83601R/G/W83602R/G 5. PIN CONFIGURATION FOR W83601R/602R W83601R SCLK SDAT GP20/A0 GP21/A1 GP22/A2 GP10 GP11 GP23 GP24 VSS 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 W83602R VDD RST# GP17/INT GP16 GP15 GP14 GP13 GP12 GP26/INT GP25 SCLK SDAT GP20/A0 GP21/A1 CTL3VSB GP10 GP11 CTLSTRV S5IN# VSS 20SSOP 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 20SSOP -4- VDD RST# GP17/INT GP16 GP15 GP14 GP13 GP12 PWCTLIN# PS_ON# W83601R/G/W83602R/G 6. PIN DESCRIPTION I/OD24t I/OD12ts I/O21 INt INcd INts OD24 - TTL level bi-directional pin open drain output with 24 mA sink capability - TTL level bi-directional pin open drain output with 12 mA sink capability and schmitt-trigger level input - CMOS level bi-directional pin with 21 mA source-sink capability - TTL level input pin - CMOS level input pin with internal pull down resistor - TTL level Schmitt-trigger input pin - Open drain output pin with 24 mA sink capability W83601R/G PIN Universal General Purpose I/O Port for I2C BUS SYMBOL I/O FUNCTION 2 1 SCL INts 2 SDA I/OD12ts GP20 I/O21 A0 INcd GP21 I/O21 A1 INcd GP22 I/O21 A2 INcd 6 GP10 I/OD24t General Purpose I/O default input. 7 GP11 I/OD24t General Purpose I/O default input. 8 GP23 I/OD24t General Purpose I/O default input. 9 GP24 I/OD24t General Purpose I/O default input. 10 VSS PWR 11 GP25 I/OD24t GP26 I/OD24t INT OD24 13 GP12 I/OD24t General Purpose I/O default input. 14 GP13 I/OD24t General Purpose I/O default input. 15 GP14 I/OD24t General Purpose I/O default input. 16 GP15 I/OD24t General Purpose I/O default input. 17 GP16 I/OD24t General Purpose I/O default input. GP17 I/OD24t INT OD24 19 RST# Ints 20 VDD PWR 3 4 5 12 18 SMBus Clock. (I C clock) SMBus bi-directional Data.(I2C data) General Purpose I/O. This pin is a setting pin for SMBus (I2C) address bit 0 during power-on reset or RST# pin reset. General Purpose I/O. This pin is a setting pin for SMBus (I2C) address bit 1 during power-on reset or RST# pin reset. General Purpose I/O. This pin is a setting pin for SMBus (I2C) address bit 2 during power-on reset or RST# pin reset. Ground Pin. General Purpose I/O default input. General Purpose I/O default input. Auto-generate Interrupt signal when detecting a transition on GPI inputs. This interrupt is either on pin12 or pin18. General Purpose I/O default input. Auto-generate Interrupt signal when detecting a transition on GPI inputs. This interrupt is either on pin12 or pin18 Reset signal input. Power Pin. -5- Publication Release Date: May 26, 2005 Revision 1.0 W83601R/G/W83602R/G 6.1 PIN W83602R/G Universal General Purpose I/O Port for I2C BUS & ACPI Power Control SYMBOL I/O FUNCTION 2 1 SCL INts 2 SDA I/OD12ts 3 GP20 I/O21 A0 INcd GP21 I/O21 A1 INcd 5 CTL3VSB OD24 Control 3VSB and 3VCC power source for ACPI features. 6 GP10 I/OD24t General Purpose I/O default input. 7 GP11 I/OD24t General Purpose I/O default input. 8 CTLSTR OD24 Suspend to RAM power control output. 9 S5IN# INt 10 VSS PWR Ground Pin. 11 PS_ON# OD24 ATX power on_off control. 12 PWCTLIN# INt 13 GP12 I/OD24t General Purpose I/O default input. 14 GP13 I/OD24t General Purpose I/O default input. 15 GP14 I/OD24t General Purpose I/O default input. 16 GP15 I/OD24t General Purpose I/O default input. 17 GP16 I/OD24t General Purpose I/O default input. 18 GP17 I/OD24t General Purpose I/O default input. INT OD24 19 RST# INts 20 VDD PWR 4 SMBus Clock. (I C clock) SMBus bi-directional Data.(I2C data) General Purpose I/O. This pin is a setting pin for SMBus (I2C) address bit 0 during power-on reset or RST# pin reset. General Purpose I/O. This pin is a setting pin for SMBus (I2C) address bit 1 during power-on reset or RST# pin reset. S5# signal input. Connected to W83627F/HF power control output. Auto-generate Interrupt signal when detecting a transition on GPI inputs. Reset signal input. Power Pin. -6- W83601R/G/W83602R/G 7. REGISTERS 7.1 Brief of register contents INDEX R/W DEFAULT REGISTERS DESCRIPTION 00h R - 01h R/W 00 GP Port 1: Output Port Data Register 02h R/W f0 GP Port 1: Polarity Inversion Register 03h R/W ff GP Port 1: Input/Output Configuration Register 04h R/W 00 GP Port 1: Output style control Register. 05h R - GP Port 1: Input Latched Data Register. 06-07h - - Reserved Register 08h R - GP Port 2: Input Port Register 09h R/W 00 GP Port 2: Output Port Register 0Ah R/W 70 GP Port 2: Polarity Inversion Register 0Bh R/W 7f GP Port 2: Input/Output Configuration Register 0Ch R/W 00 GP Port 2: Output style control Register. 0Dh R - GP Port 2: Input Latched Data Register. 0E-0F h - - Reserved Register 10h R 00 GP Port 1: Interrupt Status Register. 11h R 00 GP Port 2: Interrupt Status Register 12h R/W 00 GP Port 1: Interrupt Enable Register 13h R/W 00 GP Port 2: Interrupt Enable Register 14h R/W 00 Mode Configuration Register 15h R/W 00 Power LED Configuration Register 16-1F h - - 20h R 60 Chip ID High Byte Register 21h R 12 Chip ID Low Byte Register (W83601R/G) 22 Chip ID Low Byte Register (W83602R/G) GP Port 1: Input Port Data Register Reserved Register -7- Publication Release Date: May 26, 2005 Revision 1.0 W83601R/G/W83602R/G 7.2 W83601R/G/W83602R/G Registers Descriptions CR00 (GP Port 1: Input port Data Register, Default 0x--, Read Only) This register is a data port for input only. It reflects the incoming logic levels of the pins whether the pin is defined as an input mode by CR03. It will be inverted data by CR02. Bit 7 ~ 0: GP17 ~ GP10 Input Data Port. CR01 (GP Port 1: Output port Data Register, Default 0x00, Read/Write) This register is a data port for output only. It reflects the outgoing logic levels of the pins whether the pin is defined as an output mode by CR03. This register will reflect the value of output Flip-flop while read access. The output data will be inverted or changed output style by CR02 or CR04. Bit 7 ~ 0: GP17 ~ GP10 Output Data Port. CR02 (GP Port 1: Polarity Inversion Register, Default 0xf0, Read / Write) This register enables polarity inversion of pins defined as input or output by CR03. When set to a "1", the incoming/outgoing port value is inverted. When set to a "0", the incoming/outgoing port value is the same as in data register. Bit 7 ~ 0: GP17 ~ GP10 Polarity Iversion Register. CR03 (GP Port 1: Input/Output Configuration Register, Default 0xff, Read / Write) This register selects Input or Output mode of pins. When set to a "1", respective GPIO port is programmed as an input port. When set to a "0", respective GPIO port is programmed as an output port. Bit 7 ~ 0: GP17 ~ GP10 Input/Output Configuration Register. CR04 (GP Port 1: Output Style Control Register, Default 0x00, Read / Write) This register selects Output style of pins as level or pulse. When set to a "1", respective GPIO port is programmed as a pulse signal. When set to a "0", respective GPIO port is programmed as a level signal. Bit 7 ~ 0: GP17 ~ GP10 Output Style Control Register. CR05 (GP Port 1: Input latched data Register, Default 0x--, Read Only) This register will latch Port 1 data while power on or RST# pin low, which is controlled by CR14h bit 0. Bit 7 ~ 0: GP17 ~ GP10 Input latched data. CR06-07 Reserved Register -8- W83601R/G/W83602R/G CR08 (GP Port 2: Input port Data Register, Default 0x--, Read Only) This register is a data port for input only. It reflects the incoming logic levels of the pins whether the pin is defined as an input mode by CR0B. It will be inverted data by CR0A. Bit 7: Reserved. Bit 6 ~ 0: GP26 ~ GP20 Input Data Port. CR09 (GP Port 2: Output port Data Register, Default 0x00, Read / Write) This register is a data port for output only. It reflects the outgoing logic levels of the pins whether the pin is defined as an output mode by CR0B. This register will reflect the value of output Flip-flop while read access. The output data will be inverted or changed output style by CR0A or CR0C. Bit 7: Reserved. Bit 7 ~ 0: GP26 ~ GP20 Output Data Port. CR0A (GP Port 2: Polarity Inversion Register, Default 0x70, Read / Write) This register enables polarity inversion of pins defined as input or output by CR0B. When set to a "1", the incoming/outgoing port value is inverted. When set to a "0", the incoming/outgoing port value is the same as in data register. Bit 7: Reserved. Bit 6 ~ 0: GP26 ~ GP20 Polarity Inversion Register. CR0B (GP Port 2: Input/Output Configuration Register, Default 0x7f, Read / Write) This register selects Input or Output mode of pins. When set to a "1", respective GPIO port is programmed as an input port. When set to a "0", respective GPIO port is programmed as an output port. Bit 7: Reserved. Bit 6 ~ 0: GP26 ~ GP20 Input/Output Configuration Register. CR0C (GP Port 2: Output Style Control Register, Default 0x00, Read / Write) This register selects Output style of pins as level or pulse. When set to a "1", respective GPIO port is programmed as a pulse signal. When set to a "0", respective GPIO port is programmed as a level signal. Bit 7: Reserved. Bit 6 ~ 0: GP26 ~ GP20 Output Style Control Register. CR0D (GP Port 2: Input latched data Register, Default 0x--, Read Only) This register will latch Port 2 data while power on or RST# pin low, which is controlled by CR14h bit 1. Bit 7: Reserved. Bit 6 ~ 0: GP26 ~ GP20 Input latched data, which bit 2-0 are SMBus address bit A2-A0. CR0E-0F Reserved Register -9- Publication Release Date: May 26, 2005 Revision 1.0 W83601R/G/W83602R/G CR10 (GP Port1: Interrupt Status Register, Default 0x00, Read Only) Bit 7-0: = 1, a transition occurs at pin GP17-GP10. If GP17/INT is selected as interrupt function, bit 7 of this register will always be 0. A read to this register will clear this register. CR11 (GP Port2: Interrupt Status Register, Default 0x00, Read Only) Bit 7: = Reserved. Bit 6-0: = 1, a transition occurs at pin GP26-GP20. If GP26/INT is selected as interrupt function, bit 6 of this register will always be 0. A read to this register will clear this register. CR12 (GP Port 1: Interrupt Enable Register, Default 0x00, Read / Write) Bit 7-0: = 0, disable GP17-GP10 interrupt output when interrupt function is selected. CR13 (GP Port 2: Interrupt Enable Register, Default 0x00, Read / Write) Bit 7-5: = Reserved. Bit 6-0: = 0, disable GP26-GP20 interrupt output when interrupt function is selected. CR14 Mode Configuration Register (Default 0x00, Read / Write) Bit 7: = 1, Set GP/INT pin as INT function. 0, Set GP/INT pin as GP function. Bit 6: = 1, Set INT function at GP26 (pin 12). 0, Set INT function at GP17 (pin 18). W83602R/G INT function is only at GP17. Bit 5: = 1, Set INT output pin as pulse mode. 0, set INT output pin as level mode. Bit 4: = 1, Set INT output pin polarity is 1 (normal high) . 0, set INT output pin polarity is 0 (normal low). This bit is only for W83601R. Bit 3: = 1, Port 2 (CR09h-CR0Ch, CR11h, CR13h) registers can be reset to default data by RST# pin. 0 Port 2 (CR09h-CR0Ch) can not be reset by RST# pin. Bit 2: = 1, Port 1 (CR01h-CR04h, CR10h, CR12h) registers can be reset to default data by RST# pin. 0, Port 1 (CR01h-CR04h) can not be reset by RST# pin. Bit 1: = 1, Port 2 CR0Dh can be latched not only by RST# pin but also power-on period. 0, Port 2 CR0Dh can only be latched by power-on period. Bit 0: = 1, Port 1 CR05h can be latched not only by RST# pin but also power-on period. 0, Port 1 CR05h can only be latched by power-on period. - 10 - W83601R/G/W83602R/G CR15 Power LED Configuration Register (Default 0x00, Read/Write) Priority of LED function is highest. Bit 7: = 1, Enable LED function. 0, Disable LED funciton. When LED function is enabled, GP function is ignored despite of input or output. Bit 6-4: LED frequency selection. = 111, LED pin is tri-state (OD pin) or drived high (O pin). = 110, LED pin is a 1 Hz toggle pulse with 50 duty cycle. = 101, LED pin is a 1/2 Hz toggle pulse with 50 duty cycle. = 100, LED pin is a 1/4 Hz toggle pulse with 50 duty cycle. = 000, LED pin is drived low. Bit 3: GP port selection. 0, Select GP port 1 as LED function if bit 7 is set to 1. 1, Select GP port 2 as LED function if bit 7 is set to 1. As W83602R/G, setting this bit 1 is meaningless. Bit 2-0: GP pin selection. =110-000, GP16-GP10 can be selected as LED output when bit 3 is 0. =101-011, GP25-GP23 can be selected as LED output when bit 3 is 1. As W83602R/G, only GP16-GP10 can be selected as LED output. CR16-1F Reserved Register CR20 (Chip ID High Byte, Read Only) Bit 7-0: = 0x60. CR21 (Chip ID Low Byte, Read Only) Bit 7-0: = 0x13 (for W83601R/G). = 0x23 (for W83602R/G). NOTE: W83602R/G has no GP22-GP26. All the corresponding register has no effect on W83602R/G. - 11 - Publication Release Date: May 26, 2005 Revision 1.0 W83601R/G/W83602R/G 8. FUNCTION DESCRIPTIONS 8.1 ACCESS INTERFACE W83601R/G/W83602R/G provides a two-wired serial interface which is compliant with SMBusTM 1.0 Write Byte and Read Byte protocol. 8.1.1 Write a data into W83601R/G/W83602R/G register 0 7 8 0 7 8 SCL 0 SDA 0 Start By Master 1 1 A2 A1 A0 R/W 0 Frame 1 Serial Bus Address Byte D7 D6 Ack by 601R D5 D4 D3 D2 D1 D0 Ack by 601R Frame 2 Internal Index Register Byte 7 8 SCL (Continued) SDA (Continued) D7 D6 D5 D4 D3 D2 D1 D0 Ack by 601R Stop by Master Frame 3 Data Byte 8.1.2 Read a data from W83601R/G/W83602R/G register 0 7 8 7 4 0 8 SCL ... SDA 0 0 Start By Master 1 1 A2 A1 A0 Frame 1 Serial Bus Address Byte 0 7 R/W D7 0 Ack by 601R 8 0 D6 D5 D4 D3 D2 D1 ... D0 Ack by 601R Frame 2 Pointer Byte 7 8 SCL (Cont..) SDA (Cont..) 0 Repea Start By Master 0 1 1 A2 A1 Frame 3 Serial Bus Address Byte A0 R/W 1 D7 Ack by 601R - 12 - D6 D5 D4 Frame 4 MSB Data Byte D3 D2 D1 D0 No Ack by Master Stop by Master W83601R/G/W83602R/G 8.2 CTLSTRV Timing Waveforms (Only for W83602R/G) FIRST AC ON POWER ON ~ S5 STATE ~ ~ S0 STATE ~ SUSPEND RESUME to RAM from S3 ~ S3 STATE ~ SOFT OFF ~ S5 STATE ~ ~ S0 STATE ~ 5VSB S5IN# POWER * NOTE1 PWRCTL# STR *NOTE2 T1= 5+1MS T1=5+1MS PS_ON# T2=500+125MS CTLSTRV DRAM_VOLTAG 3VCC 3VSB 3VCC *NOTE 1: IT CAN WAKE UP POWER FROM POWER BUTTON, KEYBOARD/MOUSE, *NOTE 2: IT CAN SUSPEND TO RAM BY OS OR SPECIAL DEFINED 8.3 CTL3VSB Timing Waveforms (Only for W83602R/G) First AC On ~ S5 state ~ Power On ~ S0 state ~ Suspend to RAM Resume from S3 ~ S3 STATE ~ ~ S0 state ~ Soft OFF ~ S5 state ~ 5VSB PWRCTL# t1= 5+1ms t1= 5+1ms PS_ON# T2=500+125MS T2=500+125MS CTL3VSB 3VSB_Voltage 3VSB 3VCC - 13 - 3VSB 3VCC 3VSB Publication Release Date: May 26, 2005 Revision 1.0 W83601R/G/W83602R/G 8.4 8.4.1 GPI/O Output Mode : GPO output Tow output modes for GPO. One is LEVEL and the other is PULSE. GPO OUTPUT STYLE POLARITY OUTPUT PORT REGISTER OUTPUT VALUE AT PIN 0 0 0 1 1 0 1 1 0 0 write 1 Active 1 write 1 Active Level Pulse 8.4.2 1 WAVE INT output Two output modes for INT pin. One is LEVEL mode and the other is PULSE. INT OUTPUT MODE POLARITY OUTPUT Level 0(normal low) 1 1(normal high) 0 0(normal low) High Pulse 1(normal high) Low Pulse Pulse WAVE In Level mode, if INT is activated, it will be de-activated when interrupt status registers are read. In Pulse mode, interrupt will be activated again unless all enabled interrupt status registers are read. 8.4.3 GPI interrupt status Once a transition occurs at GPI input pins, interrupt status registers (CR10, CR11) will be set. At the mean time, if interrupt function is enable, INT pin will generate an interrupt. Reading these interrupt registers will clear themselves and reset interrupt. If an interrupt occurs but no read to interrupt status registers, interrupt will not be generated again. - 14 - W83601R/G/W83602R/G 9. DC AND AC SPECIFICATION 9.1 Absolute Maximum Ratings PARAMETER RATING UNIT Power Supply Voltage -0.5 to 7.0 V Input Voltage -0.5 to VDD+0.5 V Operating Temperature 0 to +70 C Storage Temperature -55 to +150 C Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device. 9.2 DC Characteristics (Ta = 0 C to 70 C, VDD = 5V 10%, VSS = 0V) PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS I/OD12ts - TTL level bi-directional pin open drain with source-sink capability of 12 mA and schmitt-trigger level input Input Low Threshold Voltage Vt- 0.5 0.8 1.1 V VDD = 5 V Input High Threshold Voltage Vt+ 1.6 2.0 2.4 V VDD = 5 V Hysteresis VTH 0.5 1.2 V VDD = 5 V Output Low Voltage VOL 0.4 V IOL = 12 mA Input High Leakage ILIH +10 A VIN = VDD Input Low Leakage ILIL -10 A VIN = 0V Input Low Voltage VIL 0.8 V Input High Voltage VIH Input High Leakage ILIH +10 A VIN = VDD Input Low Leakage ILIL -10 A VIN = 0 V INt - TTL level input pin INts 2.0 V - TTL level Schmitt-triggered input pin Input Low Threshold Voltage Vt- 0.5 0.8 1.1 V VDD = 5 V Input High Threshold Voltage Vt+ 1.6 2.0 2.4 V VDD = 5 V Hysteresis VTH 0.5 1.2 V VDD = 5 V Input High Leakage ILIH +10 A VIN = VDD Input Low Leakage ILIL -10 A VIN = 0 V - 15 - Publication Release Date: May 26, 2005 Revision 1.0 W83601R/G/W83602R/G DC Characteristics, continued PARAMETER SYM. MIN. TYP. MAX. UNIT CONDITIONS 0.3 VDD V VDD = 5 V V VDD = 5 V INcd - CMOS level input pin with internal pull down Input Low Voltage VIL Input High Voltage VIH Input High Leakage ILIH +10 A VIN = VDD Input Low Leakage ILIL -10 A VIN = 0 V V VDD = 5 V V VDD = 5 V V IOL = 21 mA V IOH = 21 mA 0.7VDD I/O21 - CMOS level bi-direction pin with 21mA source-sink capability Input Low Voltage VIL 0.3 VDD Input High Voltage VIH Output Low Voltage VOL Output High Voltage VOH Input High Leakage ILIH +10 A VIN = VDD Input Low Leakage ILIL -10 A VIN = 0 V 0.7VDD 0.4 3.5 I/OD24t - TTL level bi-direction pin open-drain output with 24mA sink capability Input Low Voltage VIL 0.8 V Input High Voltage VIH Output Low Voltage VOL 0.4 V IOL = 24 mA Input High Leakage ILIH +10 A VIN = 5 V Input Low Leakage ILIL -10 A VIN = 0 V 0.4 V IOL = 24 mA 2.0 V OD24 - open-drain output pin with 24mA sink capability Input Low Voltage 9.3 VIL AC Characteristics 9.3.1 Serial Bus Timing Diagram t SCL tR t F SCL t HD;STA SDA IN t SU;DAT VALID DATA t HD;DAT SDA OUT Serial Bus Timing Diagram - 16 - t SU;STO W83601R/G/W83602R/G Serial Bus Timing PARAMETER SYMBOL MIN. - SCL clock period MAX. UNIT t SCL 10 uS Start condition hold time tHD;STA 4.7 uS Stop condition setup-up time tSU;STO 4.7 uS DATA to SCL setup time tSU;DAT 120 nS DATA to SCL hold time tHD;DAT 5 nS SCL and SDA rise time tR 1.0 uS SCL and SDA fall time tF 300 nS 10. PACKAGE DRAWING AND DIMENSIONS 20 SSOP-209 mil D 11 2 DIMENSION IN MM SYMBOL DTEAIL A HE E A A1 A2 b c D E HE e L L1 10 1 MIN. SEATING PLANE Y e b DETAIL A SEATING PLANE MAX. DIMENSION IN INCH MIN. NOM 0.05 1.65 0.22 0.09 6.90 5.00 1.75 1.85 7.20 5.30 0.38 0.25 7.50 5.60 7.40 7.80 0.65 0.55 0.75 1.25 0 8.20 MAX. 0.079 2.00 Y A2 A NOM 0.002 0.065 0.069 0.073 0.015 0.010 0.283 0.209 0.307 0.0256 0.030 0.050 0.295 0.220 0.323 0.009 0.004 0.272 0.197 0.291 0.95 0.021 0.10 8 0 0.037 0.004 8 L L1 A1 - 17 - Publication Release Date: May 26, 2005 Revision 1.0 W83601R/G/W83602R/G W83602R/G Example Application Circuit R10 SCL SDA Diagnostic LEDs R9 C1 C2 D1 VCC R12 1 2 3 4 5 5VSB Reserved for needed U2 PCIRST# GP17 GP16 D4 100 VCC GP15 GP14 GP13 GP12 PWRCTL# From W83627F/HF power control Pull-up resistors PS_ON# Q9 1 10K This reset signal can be from system reset or GPO signal 2 R2 D3 D5 20 19 18 17 16 15 14 13 12 11 3 R1 10K CTL3VSB GP10 GP11 CTLSTRV SLP_S5# VCC RST# GP17/INT GP16 GP15 GP14 GP13 GP12 GP26/INT/PWCTLIN# GP25/PS_ON# SCLK SDAT GP20/A0 GP21/A1 GP22/A2/CTL3VSB GP10 GP11 GP23/CTLSTRV GP24/S5IN# VSS 4 GP20 GP21 1 2 3 4 5 6 7 8 9 10 5 Note 1. D2 10 9 8 7 6 2N3904 R11 4.7K To Power Supply PS_ON# signal 10 9 8 7 6 W83601R/602R Q10 SMBus Address 30 2N3904 GP10 GP11 GP12 GP13 GP14 12VCC 5VSB 5VSB 5VCC 5VSB 5VCC R8 4.7K R10 R11 1K 4.7K R12 4.7K G s D Q4 NPN 3904 Q11 2N3904 G Q1 R13 GP22 CTL3VSB R9 1K Q3 S Q5 Q2 PMOS IRF9531 D NPN 3904 Q12 PWRGOOD 2N3904 NMOS H603AL 330 NPN 3904 From system power good signal. This signal should be +5V high level. U1 3 VIN 2 VOUT Q13 1 ADJ 2N3904 R14 R LT1084_M VCC3_3VSB C6 CAP R15 R JP10 1 2 HEADER2 5VSB 5VSB 5VCC R16 R17 1K 4.7K S G Q6 R18 GP23 Q7 NPN 3904 CTLSTRV D17 PMOS IRF9531 D 1N5817 330 U3 VIN VOUT ADJ 3 2 VRAM 1 VRAM voltage is for RAM module VCC. R20 R LT1084_M JP13 1 2 C7 CAP R21 R HEADER2 Note 1. : Be sure that during Power-On reset or RST# reset, GP20 and GP21 will not receive signal which will affect Winbond Electronic Corp. the SMBus address setting. Title W83601R/602R Example Application Circuit Size Document Number Custom 602ap.sch Date: - 18 - Friday, December 24, 1999 Rev 0.3 Sheet 1 of 1 W83601R/G/W83602R/G REV Decription 0.1 First Publication 0.2 Change CTL3VSB, CTLSTRV Schematic 0.3 Change PMOS source,drain direction Winbond Electronic Corp. Title W83601R/602R Example Application Circuit Size Document Number Custom 602ap.sch Date: - 19 - Rev 0.3 Friday, December 24, 1999 Sheet 2 of 1 Publication Release Date: May 26, 2005 Revision 1.0 W83601R/G/W83602R/G 11. REVISION HISTORY VERSION DATE PAGE DESCRIPTION n.a. All the version before 0.30 are for internal use. First publication. 0.3 99/08 n.a. 0.31 99/08 P.4,5 Change Pin Description of W83601R pin 3,4,5. P.6 Change Pin Description of W83602R pin 3,4. P.10 Update Register Table. P.13 CR16 is a reserved register. Please ignore it. Change INT output description. 0.32 99/09 P.10 CR15 bit 3 description. 0.33 01/02 P.11 Insert 8.1 section - Access interface 0.34 01/02 P.10 Update CR21 Chip ID. 0.35 01/03 P.4 Update pin characteristic. Update application schematic to version 0.3. 0.4 01/06 P.15 Add chapter 9 DC and AC specification. 0.5 01/08 P.15 Update chapter 9.2 DC specification 0.6 05/04 n.a. Add Pb-free package 1.0 May 26, 2005 20 ADD Important Notice Important Notice Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales. - 20 - W83601R/G/W83602R/G - 21 - Publication Release Date: May 26, 2005 Revision 1.0