Integrated Circuit Systems, Inc. ICS9158 Integrated Buffer and Motherboard Frequency Generator General Description The ICS9158 is a low cost frequency generator designed specifically for desktop and notebook PC applications. Eight high drive, skew-controlled copies of the CPU clock are avail- able, eliminating the need for an external buffer. Each high drive (SOmA) output is capable of driving a 30pf load and has a typical duty cycle of 50/50, The CPU clock outputs are skew-controlled to within 250ps. The CPU clocks provide all necessary frequencies for 286, 386. 486 and Pen- tium systems, including support for the latest speeds of proc- essors. The CPU clock offers the unique feature of smooth, glitch-free transitions from one frequency to the next, making this the ideal device to use whenever slowing the CPU speeds. The ICS9158 makes a gradual transition between frequencies so that it meets the Intel cycle-to-cycle timing specification for 486 systems. ICS has been shipping Motherboard Frequency Generators since April 1990, and is the leader in the area of multiple output Features e Eight skew-free, high drive CPU clock outputs e Upto 100 MHz output at 5V e +250ps skew between CPU and 2XCPU outputs e Outputs can drive up to 30pf load e 50mA output drivers e =6Typical 50/50 duty cycle e Compatible with 486 and Pentium CPUs e Glitch-free start and stop clock option e Optional power-down mode supports Energy Star (green) PCs e On-chip loop filter components e Low power, high speed 0.8, CMOS technology e 24-pin PDIP or SOIC package Clock Table (in MHz) clocks on a single chip. The [CS9158 is a third generation Clock ICS9158-01 device, and uses ICSs patented analog CMOS Phase-Locked BUSCLK 16 Loop technology for low phase jitter. ICS offers a broad family _ | FDCLK 24 of frequency generators for motherboards, graphics and other 14.318 1 43 18 applications. including cost effective versions with only one or - : two output clocks. Consult ICS for all of yourclock generation = |CPUCLK 4,8,30,20,25,33.3.40, or 50 needs. 2XCPUCLK 8,16,60,40,50,66.6,80. or 100 Block Diagram 3 poor nm ee ee rr | SO - S2 > as 2XCPU CPU > OUTPUT | CLOCK | > BUFFER {| _t_s cpy 1,2,3,4,5,6,7 14.318 MHz -14 Crystal Cl | | REFERENCE + | CLOCK OE 14.318 MHz < | | ) + . 7 | '| PERIPHERAL | output BUSCLK CLOCKS BUFFERS | " t+_+-> FDCLK | | VDD GND AGND ICS9158-01RevA112294 C-89ICS9158 Pin Configuration cPu2 1 24 so X140UT 2 23 _ $1 X14IN 3 22 = CPUI VDD 4 ys 21 f 2XCPU GND 5 20 Im VDD 16 MHz 6 @ 19 f= GND 24 MHz 7 2 18 f= 14.318 MHz CPU3 8 & 17 CPU4 AGND 9 16 fF aAvDD OE 310 OG 15 be se CPUS 11 14 fF CPU6 GND 12 13 = CPU7 24-Pin PDIP or SOIC K-5, K-7 Pin Descriptions for ICS9158-01 PIN N' UMBER | PIN NAME TYPE DESCRIPTION 1 ICPU2 Output _|CPU clock output 2 X140UT - Crystal connection 3 X14IN - Crystal connection 4 VDD - Digital POWER SUPPLY (+5V) 5 GND - Digital GROUND 6 16 MHz Output 16 MHz clock output 7 24 MHz Output 24 MHz floppy disk/combination I/O clock output 8 CPU3 Output [CPU clock output 9 AGND - ANALOG GROUND 10 OE Input OUTPUT ENABLE. Tristates all outputs when low. ll CPUS Output CPU clock output 12 GND - Digital GROUND 13 CPU7 Output CPU clock output 14 CPU6 Output CPU clock output 15 $2 Input CPU clock frequency select 2 _ 16 AVDD - ANALOG power supply (+5V) _ 17 CPU4 Output CPU clock output 18 14.318 MHz Output 14.318 MHz clock output 19 GND - Digital GROUND 20 VDD - Digital POWER SUPPLY (+5V) | _al 2XCPU Output 2X CPU clock output 22 CPU Output CPU clock output | 23 Ny Input CPU clock frequency select #1 24 SO Input CPU clock frequency select #0 C-90ICS9158 Absolute Maximum Ratings AVDD, VDD referenced toGND ............... TV Operating temperature under bias ............... OC to +70C Storage temperature .............0....000 eevee -40C to +150C Voltage on I/O pins referenced to GND........... GND -0.5V to VDD +0.5V Power dissipation ........... 0.000. epee eee eae 0.5 Watts Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics at 5V Vpp = +5 V+410%, Ta=0C to 70C unless otherwise stated DC Characteristics PARAMETER SYMBOL | TEST CONDITIONS MIN TYP MAX UNITS Input Low Voltage VIL 0.8 Vv Input High Voltage VIH 2.0 Vv Input Low Current In [Vin=0V -5 5 HA Input High Current Tre | VIN=VDD -5 5 LA Output Low Voltage VOL foL=20.0mA 0.25 0.4 Vv Output High Voltage (Note 1) Vou Ion=-30mA 2.4 3.5 v Output Low Current (Note 1) lo. VoL=0.8V 45 65 mA Output High Current (Note 1) Tou VoH=2.0V -55 -35 mA Supply Current Ipp No load, 80 MHz 43 65 mA Output Frequency Change over Fp With respect to typical 0.002 0.01 % Supply and Temperature (Note 1) frequency Short circuit current (Note 1) Isc Each output clock 25 56 mA Pull-up resistor value (Note 1) Repu Input pin 680 kQ Input Capacitance (Note 1) Ci Except X1, X2 8 pf Load Capacitance (Note 1) CL Pins X1, X2 20 pf Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production. C-91ICS9158 Electrical Characteristics (continued) Vpp = +5V+10%, Ta=0C to 70C unless otherwise stated AC Characteristics PARAMETER SYMBOL | TESTCONDITIONS | MIN TYP | MAX [| UNITS Output Rise time, 0.8 to 2.0V tr |30pf toad | - 1 2 | ons (Note 1) | fo Rise time, 20% to 80% Vpp tr 30pf load - 2.5 3 ns (Note 1) eee jf Output Fall time, 2.0 to 0.8V te 30pf load - 0.5 | 1 ns (Note 1) a Fall time, 80% to 20% Vpp | tf 30pf load - 1.5 2 ns (Note Duty cycle (Note 1) dt 30pf load Jitter, one sigma (Note 1) | _tils As compared with Jitter, absolute | __tiab clock period Jitter, absolute tab 16-100 MHz clocks | Input Frequency | fj | Clock skew betweenCPUand | Tsc | 2XCPU outputs | Frequency Transition time | tit |From 4 to 50 MHz \eNote D oe | Note 1: Parameter is guaranteed by design and characterization. Not 100% tested in production. C-92ICS9158 ICS9158-01 CPU Clock Decoding Table (using 14.318 MHz input. All frequencies in MHz) CLOCK#2 CPU and 2XCPU Peripheral Clocks $2 Sl SO 2XCPU BUSCLK FDCLK (Pin 15) (Pin 23) (Pin 24)! (Pin 21) cPu (Pin6) | Pin) 0 0 0 7.580 3.790 16.002 24,003 0 0 1 15.511 7.756 " 0 1 0 59.875 29.938 0 1 1 40.090 20.045 1 0 0 50.113 25.057 Reference Clock 1 0 1 66.476 33.238 REFCLK1 1 1 0 79.772* 39.886* (Pin 18) 1 1 1 100.226* 50.113* 14.318 *5V only Frequency Transitions A key feature of the ICS9158 is its ability to provide smooth, glitch-free frequency transitions on the CPU and 2XCPU clocks when the frequency select pins are changed. The fre- quency transition rate does not violate the Intel 486 or Pentium specification of less than 0.1% frequency change per clock period. Using an Input Clock as a Reference The ICS9158 is designed to accept a 14.318 MHz crystal as the input reference. With some external changes, it is possible to use a crystal oscillator or other clock sources. Please see application note AANO4 for details on driving the ICS9158 with a clock. CPUCLK Stop Clock Feature (Optional Mask Version) The ICS9158 incorporates a unique stop clock feature compat- ible with static logic processors. When the stop clock pin goes low, the CPUCLK will go low after the next occurring falling edge. When STOPCLK again goes high, CPUCLK resumes on the next rising edge of the internal clock. This feature enables fast, glitch-free starts and stops of the CPUCLK and is useful in Energy Start motherboard applications. STOPCLK Za a C-93ICS9158 Ordering Information ICS9158-01N Example: ICS XXXX-PPP M Package Type N=DIP (Plastic) Pattern Number (2 or 3 digit number for parts with ROM code patterns) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV=Standard Device; GSP=Genlock Device 1CS9158-01M Example: ICS XXXX-PPP M Package Type M=SOIC Pattern Number (2 or 3 digit number for parts with ROM code patterns) Device Type (consists of 3 or 4 digit numbers) Prefix ICS, AV=Standard Device. GSP=Genlock Device C-94