TPS23751 TPS23752 www.ti.com SLVSB97B - JULY 2012 - REVISED JULY 2013 IEEE 802.3at PoE Interface with Wide Range High Efficiency DC-DC Controller Check for Samples: TPS23751 , TPS23752 FEATURES DESCRIPTION * * The TPS23751 is a 16-pin integrated circuit that combines a Power-over-Ethernet (PoE) powered device (PD) interface and a current-mode DC-DC controller optimized specifically for applications requiring high efficiency over a wide load range. 1 The DC-DC controller features internal soft-start, a bootstrap startup current source, current-mode control with slope compensation, blanking, and current limiting. Efficiency is enhanced at light loads by disabling synchronous rectification and entering variable frequency operation (VFO). APPLICATIONS The TPS23752 is a 20-pin extended version of the TPS23751 with the addition of a Sleep Mode feature. Sleep Mode disables the converter to minimize power consumption while still generating the Maintain Power Signature (MPS) required by IEEE802.3at. IEEE 802.3at-Compliant Devices Video and VoIP Telephones Multiband Access Points Security Cameras Pico-Base Stations From Ethernet Pairs 1,2 VDD RSRD RSRT1 M2 OPTO2 ROB CVC OPTO1 RSRT2 ARTN OPTO1 Type 2 PSE Indicator M1 VOUT CVB RT CCTL SRT GATE CS SRD OPTO3 DVC1 RVC VC VB TPS23751 58V RCTL RAPD2 Adapter RAPD1 VB DOUT T2P RT2P CLS PAD VSS APD CTL RT RCLS 0.1uF From Ethernet Pairs 3,4 DA CIN OPTO3 DEN VOUT CIO OPTO2 CIZ TLV431 RFBU RDEN T1 RTN * * * * * RFBL * The PoE interface implements type-2 hardware classification per IEEE 802.3at. It also includes an auxiliary power detect (APD) input and a disable function (DEN). A 0.5 , 100 V pass MOSFET minimizes heat dissipation and maximizes power utilization. COUT * * * * * * * * IEEE 802.3at Classification with Status Flag High Efficiency Solutions over Wide Load Range Powers up to 25.5 W PDs Robust 100 V, 0.5 Hotswap MOSFET Synchronous Rectifier Disable Signal PowerPADTM TSSOP Packages Complete PoE Interface Plus DC-DC Controller Adapter ORing Support Programmable Frequency TPS23752 Supports Ultra-Low Power Sleep Modes -40C to 125C Junction Temperature Range RCS 2 Figure 1. Typical Application Circuit 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PowerPAD is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 2012-2013, Texas Instruments Incorporated TPS23751 TPS23752 SLVSB97B - JULY 2012 - REVISED JULY 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. PRODUCT INFORMATION (1) DEVICE TPS23751 TPS23752 (1) TA -40C to 85C FEATURE PACKAGE Standard TSSOP-16 PowerPADTM MARKING 23751 Sleep Mode TSSOP-20 PowerPADTM TPS23752 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com. ABSOLUTE MAXIMUM RATINGS (1) (2) Voltage with respect to VSS (unless otherwise noted) VALUE Voltage DEN, VDD -0.3 to 100 ARTN (2), RTN (3) -0.6 to 100 CLS (4) -0.3 to 6.5 [CTL, MODE, RT, SLPb, SRT, VB (4), WAKE] to ARTN -0.3 to 6.5 CS to ARTN -0.3 to VB [LED, APD SRD, T2P, VC] to ARTN Current, sinking Current, sourcing Current, average sourcing or sinking ESD -0.3 to (VC+0.3) RTN (5) Internally limited LED 15 T2P, SRD 5 DEN 1 CLS 65 VC Internally limited VB Internally limited 2 mA mA GATE 25 mARMS Human body model (HBM) 2 kV 500 V 8/15 kV Internally limited C Charged device model (CDM) System level (contact/air) at RJ-45 (2) (3) (4) (5) (6) V -0.3 to 18 GATE (4) to ARTN (6) TJMAX (1) UNIT Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. ARTN must be connected to RTN. With IRTN = 0. Do not apply voltages to these pins. SOA limited to RTN = 80 V at 1.2 A. ESD per EN61000-4-2. A power supply containing the TPS23751 or TPS23752 was subjected to the highest test levels in the standard. Refer to the ESD section. Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: TPS23751 TPS23752 TPS23751 TPS23752 www.ti.com SLVSB97B - JULY 2012 - REVISED JULY 2013 THERMAL INFORMATION THERMAL METRIC (1) TPS23751 TPS23752 TSSOP-16 TSSOP-20 JA Junction-to-ambient thermal resistance 39.5 38.5 JCtop Junction-to-case (top) thermal resistance 25.9 23.8 JB Junction-to-board thermal resistance 21.1 25.6 JT Junction-to-top characterization parameter 0.7 0.7 JB Junction-to-board characterization parameter 20.8 20.3 JCbot Junction-to-case (bottom) thermal resistance 2.0 1.6 (1) UNITS C/W For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953. spacer, so notes in Thermal Table do not sit on top of the ROC title RECOMMENDED OPERATING CONDITIONS (1) Voltages with respect to VSS (unless otherwise noted) MIN NOM Input voltage range 0 57 [LED, APD ,SRD, T2P, VC] to ARTN 0 18 [CTL,CS, MODE, SLPb, SRT, WAKE] to ARTN 0 VB 0.5 1.5 SRT to ARTN RTN Sinking current MAX ARTN, RTN, VDD 1.2 SRD, T2P 2 LED 10 UNIT V A mA VB (2) 5 mA Continuous RTN current (TJ 125C) (3) 825 mA 392 k Sourcing current Resistance Capacitance RCLS (2) VB (2) 0.08 Junction temperature (1) (2) (3) 60 RWAKE -40 F 125 C ARTN tied to RTN Do not apply voltage supply to these pins. This is minimum current-limit value. Viable systems will be designed for maximum currents below this value with reasonable margin. IEEE 802.3at permits 600mA continuous loading. Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: TPS23751 TPS23752 Submit Documentation Feedback 3 TPS23751 TPS23752 SLVSB97B - JULY 2012 - REVISED JULY 2013 www.ti.com ELECTRICAL CHARACTERISTICS Unless otherwise noted, 40 V VDD 57 V; VCTL = VMODE = VSLPb = VB; VSRT = 0.5 V; VAPD = VCS = VARTN = VRTN; CLS, GATE, LED, SRD, T2P open; RWAKE = 392 k; RDEN = 24.9 k; RT = 34 k; CVB = CVC = 0.1 F; -40 TJ 125C. Typical values are at 25C. All voltages referred to VSS. CONTROLLER SECTION VC = 12 V, VDEN = VVSS, VARTN = VRTN = VSS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VVDD = 48 V, Sleep mode 12 12.8 13.8 V VVDD = 48 V, VC = 0 V 1.1 1.5 2.1 VVDD = 10.9 V, VC = 8.6 V 0.9 1.3 1.8 VC (GATE DRIVE SUPPLY) Output voltage; TPS23752 only IVC_ST Startup source current IVC_OP Operating current VVC = 12 V, VCTL = VB 0.9 1.8 3.0 mA tST Bootstrap start up time, CVC = 22 F VVDD = 48 V, measure time from VVC (0) VCUV 103 155 203 ms VVC rising until VSRD 8.6 8.9 9.2 3 3.2 3.4 7.5 V VVC 18 V, 0 IVB 5 mA 4.75 5.00 5.25 VAPD , measure with respect to ARTN 1.43 1.50 1.57 Hysteresis 0.28 0.30 0.32 VCUV UVLO threshold VCUVH Hysteresis mA V VB (BIAS SUPPLY) Output voltage V APD (AUXILIARY POWER DETECT) VAPDEN APD threshold voltage VAPDH Leakage current VAPD = 18 V V 10 A RT (OSCILLATOR) FSW Switching frequency in PWM mode RT = 34.0 k. Measure at GATE 226 251 276 kHz FVFO Switching frequency in VFO mode VCTL = 1.75 V, RT = 34.0 k. Measure at GATE 105 135 165 kHz DMAX Maximum duty cycle VCTL = VB, Measure at GATE 75% 80% 85% 1.90 2.00 2.10 2.15 2.25 CTL (CONTROL - PWM INPUT) VSRT = 0.5V VCTL_VFO VCTL at PWM/VFO transition point VSRT = 1.0 V TSSD Internal soft start delay time VCTL until VSRD Hysteresis (1) VCTL until VSRD Hysteresis 35 (1) VCTL = 3.5 V, measure from switching start to VCSMAX Input resistance V mV 2.35 40.50 V mV 1.87 3.01 5.09 ms 70 105 145 k V VZF Zero frequency threshold (ZF) VCTL until GATE stops switching 1.40 1.50 1.60 VZDC Zero duty cycle (ZDC) threshold (VFO disabled) VSRT = VARTN, VCTL until GATE stops switching 1.55 1.75 1.95 Gain, VCS to VCTL (1) 5.0 V V/V CS (CURRENT SENSE) VCSMAX VCS until VGATE Maximum threshold voltage 0.22 0.25 0.28 1.60V VCTL 1.90V, VSRT = 0.5 V, VCS until VGATE 40 50 60 mV V VCS_VFO Peak VCS in VFO mode 1.85V VCTL 2.15V, VSRT = 1.0 V, VCS until VGATE 85 100 115 mV VPK Internal slope compensation voltage, see Figure 2 D = DMAX 32 40 50 mV ICS_RAMP Ramp component of ICS D = DMAX 12 16 25 A ICSDC DC component of ICS 1 2 3 A DSLOPE_ST Slope compensation ramp start relative to switching period. Refer to Figure 2 30% 34% 39% t1 Turn off delay 50 90 ns tBLNK Blanking period 100 150 200 ns 290 500 VCS = 0.3 V, measure tprf50-50, see Figure 3 Off state pull-down resistance (1) 4 Parameters provided for reference only, and do not constitute part of TI published specifications for purposes of TI product warranty. Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: TPS23751 TPS23752 TPS23751 TPS23752 www.ti.com SLVSB97B - JULY 2012 - REVISED JULY 2013 CONTROLLER SECTION (continued) VC = 12 V, VDEN = VVSS, VARTN = VRTN = VSS PARAMETER TEST CONDITIONS MIN TYP MAX UNIT A GATE (GATE DRIVER) Peak source current GATE high, pulsed measurement 0.35 0.60 1.00 Peak sink current GATE low, pulsed measurement 0.70 1.00 1.40 Rise time Fall time (2) (2) tprr10-90, CGATE = 1 nF; see Figure 4 40 tpff90-10, CGATE = 1 nF; see Figure 4 27 A ns ns Pull-up resistance 20 Pull-down resistance 10 SRD (SYNCHRONOUS RECTIFIER DISABLE) Output low voltage ISRD = 2 mA sinking Leakage current VCTL = 1.75 V, VSRD = 18 V 0.25 0.45 V 10 A 1 A 155 C SRT (SYNCHRONOUS RECTIFIER THRESHOLD) 0 V VSRT 5 V Leakage current THERMAL SHUTDOWN Shutdown TJ rising 135 Hysteresis (2) (2) 145 20 C Parameters provided for reference only, and do not constitute part of TI published specifications for purposes of TI product warranty. SLEEP MODE (TPS23752 ONLY) VDD = 48 V, VAPD = VARTN = VRTN = VVSS, VVC = 13 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 1.10 1.66 2.10 V 4 5.7 8 A 1.10 1.66 2.10 V SLPb VSLPb falling until ILED SLPb threshold Input pull-up current MODE MODE falling unti ILED MODE threshold MODE hysteresis (1) 1.6 Input pullup current V 4 5.7 8 A 2.43 2.50 2.57 V 3.95 5.33 6.88 k 0.60 0.90 1.50 V 10 A 0.5 1 mA WAKE Output voltage RWKPLUP Sleep mode Pull-up resistance LED Output low voltage SLPb , ILED = 10 mA Leakage current VLED = 18 V SLEEP SUPPLY CURRENT Sleep supply current when VAPD = 2 V; SLPb , measure IVDD APD is enabled MPS supply current Pulsed mode: VMODE = 0 V; SLPb , Measure IVDD 0 ILED 10 mA 10.0 10.6 11.5 mApk DC mode: VMODE = VB, then SLPb , Measure IVDD 0 ILED 10 mA 10.0 10.6 11.5 mA 28.80% 28.88% 28.95% 75 87.5 MPS pulsed current duty cycle MPS pulsed mode duty cycle MPS pulsed current ON time MPS pulsed current OFF time (1) 215 ms 250 ms Parameters provided for reference only, and do not constitute part of TI published specifications for purposes of TI product warranty. Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: TPS23751 TPS23752 Submit Documentation Feedback 5 TPS23751 TPS23752 SLVSB97B - JULY 2012 - REVISED JULY 2013 www.ti.com PoE INTERFACE SECTION Unless otherwise noted, VVC = VAPD = VCS = VARTN = VRTN. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 3 5 12 A 0.1 5 A DEN (DETECTION AND ENABLE) Bias current DEN open, IVDD + IDEN + IRTN, VVDD = 10.1 V, not in mark DEN leakage current VDEN = VVDD = 57 V Detection current Disable threshold VPD_DIS IVDD + IDEN + IRTN, VVDD = 1.4 V 53.8 56.5 58.3 IVDD + IDEN + IRTN, VVDD = 10.1 V 395 410 417 3 3.6 5 50 113 200 1.80 2.17 2.60 RCLS = 243 9.90 10.60 11.20 RCLS = 137 17.60 18.60 19.40 RCLS = 90.9 26.50 27.90 29.30 RCLS = 63.4 38.00 39.90 42.00 11.9 12.5 13 1.4 1.6 1.7 DEN falling Hysteresis A V mV CLS (CLASSIFICATION) 13 V VVDD 21 V, Measure IVDD + IDEN + IRTN RCLS = 1270 ICLS Classification current VVDD rising, VCLS VCL_ON VCL_H Class lower threshold VCU_OFF VCU_H Class upper threshold VMSR Mark reset threshold Mark state resistance Leakage current VVDD = 57 V, VCLS = 0 V, measure ICLS Hysteresis VVDD rising, VCLS mA V 21 22 23 0.50 0.75 0.90 VVDD falling 3 3.9 5 V 2-point measurement at 5 V and 10.1 V 6 9.1 12 k 1 A Hysteresis V RTN (PASS DEVICE) rDS(on) On resistance VVC = VAPD = VARTN = VCS = VVDD 0.20 0.45 0.75 Current limit VVC = VAPD = VARTN = VCS = VVDD, VRTN =1.5 V, Measure IRTN 0.85 1.00 1.20 A Inrush current VVC = VAPD = VARTN = VCS = VDD, VRTN = 2 V, VDD = 20 V 48 V 100 140 180 mA Inrush termination Percentage of inrush current 80% 90% 99% Foldback threshold VRTN 11.0 12.3 13.6 V Foldback deglitch time VRTN rising to when current limit changes to inrush current limit 500 800 1500 s Input bias current VVDD = VRTN = 30 V, Measure IRTN 30 A RTN leakage current VRTN = VVDD = 100 V, VDEN = VVSS 50 A 0.26 0.60 V 4.3 0 ms 10 A T2P (TYPE 2 PSE INDICATION) VT2P Output low voltage IT2P = 2 mA, after 2-event classification and softstart is complete, VVC = 12 V, VCTL = 3 V, VARTN = VVSS tT2P T2P startup delay VCTL = 3 V, VAPD = 2 V, Measure from switching start to VT2P Leakage current VT2P = 18 V, VARTN = VVSS 2 PoE - PD UVLO VUVLO_R UVLO rising threshold 36.3 38.1 40 UVLO falling threshold 30.5 32.0 33.6 210 500 A 300 A V SUPPLY CURRENT 6 Operating current Measure IVDD, VVDD = 48 V, 40 V VVDD 57 V Off-state current ARTN and VVC open, VVDD = 30 V, Measure IVDD Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: TPS23751 TPS23752 TPS23751 TPS23752 www.ti.com SLVSB97B - JULY 2012 - REVISED JULY 2013 PoE INTERFACE SECTION (continued) Unless otherwise noted, VVC = VAPD = VCS = VARTN = VRTN. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 135 145 155 C THERMAL SHUTDOWN Shutdown Hysteresis (1) TJ rising (1) 20 C Parameters provided for reference only, and do not constitute part of TI published specifications for purposes of TI product warranty. VSLOPE = VPK / (DMAX DSLOPE_ST) VSLOPE Voltage added to current sense VPK 1 DM T _S PE LO AX DS 0 0, Time normalized to one switching cycle Figure 2. Current Mode Compensation Ramp VGATE 50% 0 Time VCS 50% 0 Time tprf50-50 Figure 3. Time Delay from VCS to VGATE VGATE tprr10-90 tpff90-10 90% 90% 10% 10% Time 0 Figure 4. Rise Time and Fall Time of VGATE DEVICE INFORMATION Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: TPS23751 TPS23752 Submit Documentation Feedback 7 TPS23751 TPS23752 SLVSB97B - JULY 2012 - REVISED JULY 2013 www.ti.com TPS23752 PWP PACKAGE (TOP VIEW) TPS23751 PWP PACKAGE (TOP VIEW) VDD DEN 1 16 2 15 VSS RTN VDD DEN 1 20 2 19 VSS RTN CLS 3 14 ARTN CLS 3 18 ARTN APD 4 13 GATE APD 4 17 RT 5 12 VC RT 5 16 GATE VC T2P 6 11 CS T2P 6 15 CS SRD 7 10 VB SRD 7 14 CTL 8 13 VB SRT LED 9 12 MODE 10 11 SLPb Thermal Pad 8 CTL 9 SRT P0047-02 WAKE Thermal Pad P0021-04 PIN FUNCTIONS NAME PIN I/O DESCRIPTION TPS23751 TPS23752 VDD 1 1 I DEN 2 2 I/O Connect 24.9 k to VDD for detection. Pull to VSS to disable pass MOSFET. CLS 3 3 I/O Connect resistor from CLS to VSS to program classification current. APD 4 4 I Raise 1.5 V above ARTN to disable pass MOSFET and force T2P active. RT 5 5 I Connect a resistor from RT to ARTN to set switching frequency. T2P 6 6 O Active low indicates type-2 PSE connected or APD active. SRD 7 7 O Disable external synchronous rectifiers in VFO Mode. CTL 8 8 I Control loop input to PWM LED 9 O Open-drain drive for external LED controlled by SLPb, MODE, and WAKE. WAKE 10 I/O Pull WAKE low to re-enable the DC-DC converter from Sleep Mode. SLPb 11 I Pull low during normal operation to enter Sleep Mode. MODE 12 I Enables pulsed MPS when entering Sleep Mode. Control LED in normal operation. I Set the threshold of PWM to VFO transition Connect to positive PoE input power rail. Bypass with 0.1 F to VSS. SRT 9 13 VB 10 14 O 5 V bias supply. Bypass with a minimum of 0.1 F to ARTN. CS 11 15 I/O Current sense input. Connect to ARTN-referenced current sense resistor. VC 12 16 I/O DC-DC converter bias voltage. Bypass with 0.47 F or more to ARTN directly at pin. GATE 13 17 O Gate driver output for DC-DC converter switching MOSFET. ARTN 14 18 RTN 15 19 VSS 16 20 PWR DC-DC converter analog return. Connect to RTN. O Pad 8 Drain of PoE pass MOSFET. Connect to ARTN. PWR Connect to negative power rail derived from PoE source. Always connect PowerPADTM to VSS. A large fill area is required to assist in heat dissipation. Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: TPS23751 TPS23752 TPS23751 TPS23752 www.ti.com SLVSB97B - JULY 2012 - REVISED JULY 2013 DEVICE FUNCTIONAL BLOCK DIAGRAMS DC-DC CONTROLLER SLEEP Voltage Regulator (TPS23752 only) VDD VC VB Regulator OSTD SLEEP Control CONV.ON Reference CONV.OFF VC RT VOSC Oscillator GATE 0 1 VOSC CTL 1 D Q CK CLR VFO ARTN ZDC COMP VFO COMP 80k VFO VZDC,VFO VFO. OFF 20k 0 VCS,VFO 1 PWM COMP VFO Soft Start ISLOPE 0.35 V VFO 0.35 V 1 Blanking Circuit 1 ILIMIT COMP 0.25 V 0 CS ARTN SRD RSLOPE 0 VFO GATE Soft Start Complete ARTN T2P VFO Reference Generator SRT VCS,VFO VZDC,VFO t2 T2P Logic CTL VFO. OFF APD ARTN 0.25 V Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: TPS23751 TPS23752 Submit Documentation Feedback 9 TPS23751 TPS23752 SLVSB97B - JULY 2012 - REVISED JULY 2013 www.ti.com PoE 12V & 10V VDD 22V & 21.25V 5V & 4V Detection Comp. Class Comp. 4V Class Comp. VSS Mark Comp. 2.5V REG. 800Ps 800Ps 12V APD Comp. APD DEN CLS VSS RTN Mark Comp Output 1.5V & 1.2V UVLO Comp Output ARTN S R Q Type 2 State Eng. 1 = inrush 0 = current limit R Inrush latch S 38.1V & 32V OTSD UVLO Comp. t2 Inrush limit 1 threshold Current limit 0 threshold Q CONV.OFF 1 0 High if over temperauture IRTN sense VSS RTN Signals referenced to VSS unless otherwise noted Hotswap MOSFET IRTN sense,1 if < 90% of inrush and current limit 10 Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: TPS23751 TPS23752 TPS23751 TPS23752 www.ti.com SLVSB97B - JULY 2012 - REVISED JULY 2013 SLEEP MODE FUNCTIONALITY (TPS23752 ONLY) VB 1 D SLPb Q Sleep CLK D CLR Q Q MPS CLK CLR Q MODE LED 1 Sleep D Q CLK Iref RWKPLUP VB Sleep VC CLR Q Sleep WAKE Oscillator Soft Start Complete Frequency Divider MPS Sleep VREF MPS Regulator + Sleep APD MPS ARTN PIN DESCRIPTION The following descriptions refer to the schematic of Figure 1 and the Functional Block Diagrams. APD: (Auxiliary Power Detect): The APD pin is used in applications that may draw power either from the Ethernet cable or from an auxiliary power source. A voltage of more than about 1.5 V on the APD pin relative to RTN turns off the internal pass MOSFET, disables the CLS output, and enables the T2P output. A resistor divider (RAPD1-RAPD2 in Figure 1) provides system-level ESD protection for the APD pin, discharges leakage from the blocking diode (DA in Figure 1), and provides input voltage supervision to ensure that switch-over to the auxiliary voltage source does not occur at excessively low voltages. If not used, connect APD to ARTN. When the TPS23752 operates in Sleep Mode, holding APD higher than its rising threshold, VAPDEN, disables the maintain power signature (MPS). ARTN: The ARTN pin is the local ground return for the DC-DC controller. Connections to the ARTN pin should return to a local ground plane beneath the DC-DC converter primary circuitry. For most applications, this ground plane should also connect to RTN. CLS: An external resistor (RCLS in Figure 1) connected between the CLS pin and VSS provides a classification signature to the PSE. The controller places a voltage of approximately 2.5 V across the external resistor whenever the voltage differential between VDD and VSS lies between about 10.9 V and 22 V. The current drawn by this resistor, combined with the internal current drain of the controller and any leakage through the internal pass MOSFET, creates the classification current. Table 1 lists the external resistor values required for each of the PD power ranges defined by IEEE802.3at. The maximum average power drawn by the PD, including all losses within the DC-DC converter as well as power supplied to the downstream load, should not exceed the maximum power indicated in Table 1. Holding APD high disables the classification signature. High-power PSEs may perform two classification cycles if Class 4 is presented on the first cycle. Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: TPS23751 TPS23752 Submit Documentation Feedback 11 TPS23751 TPS23752 SLVSB97B - JULY 2012 - REVISED JULY 2013 www.ti.com Table 1. Class Resistor Selection CLASS MINIMUM POWER at PD (W) MAXIMUM POWER at PD (W) RESISTOR RCLS () 0 0.44 12.95 1270 1 0.44 3.84 243 2 3.84 6.49 137 3 6.49 12.95 90.9 4 12.95 25.5 63.4 CS (Current Sense): The CS pin serves as the current sense input for the DC-DC controller. The CS pin senses the voltage at the high side of the current sense resistor (RCS in Figure 1). This voltage drives the current limit comparator and the PWM comparator (see Block Diagram of DC-DC controller). A leading-edge blanking circuit prevents MOSFET turn-on transients from falsely triggering either of these comparators. During the off time, and also during the blanking time that immediately follows, the CS pin is pulled to ARTN through an internal pulldown resistor. The current limit comparator terminates the on-time portion of the switching cycle as soon as VCS exceeds approximately 250 mV and the leading edge blanking interval has expired. If the converter is not in current limit, then either the PWM comparator or the maximum duty cycle limiting circuit terminates the on time. An internal slope compensation circuit generates a current that imposes a voltage ramp at the positive input of the PWM comparator to suppress sub-harmonic oscillations. This current flows out of the CS pin. If desired, the magnitude of the slope compensation can be increased by the addition of an external resistor in series with the CS pin. The beginning of the slope compensation ramp is delayed to provide a smoother transition from PWM to VFO mode, as shown in Figure 2. Slope compensation, including that generated by any external resistance, is disabled in VFO mode. CTL (Control): The CTL pin receives the control voltage from the external error amplifier. Typically this error amplifier consists of a TL431 shunt regulator driving an optocoupler, but other configurations are possible. The voltage differential between CTL and ARTN regulates power flow through the DC-DC converter. The voltage VCTL_VFO set by the SRT pin represents the boundary between PWM and VFO mode. In the PWM mode of operation, the CTL voltage determines the threshold at which the PWM comparator terminates the on-time interval. During VFO mode, the inductor peak current is fixed and the CTL voltage varies the switching frequency. During PWM mode the switching frequency is fixed and the CTL voltage varies the duty cycle. DEN (Detection and Enable): The DEN pin implements two separate functions. A resistor (RDEN in Figure 1) connected between VDD and DEN generates a detection signature whenever the voltage differential between VDD and VSS lies between approximately 1.4 and 10.9V. Beyond this range, the controller disconnects this resistor to save power. For applications that wish to comply with the requirements of IEEE802.3at, the external resistance should equal 24.9 k. If the resistance connected between VDD and DEN is divided into two roughly equal portions, then the application circuit can disable the PD by grounding the tap point between the two resistances. This action simultaneously spoils the detection signature and thereby signals the PSE that the PD no longer requires power. GATE: The gate drive pin drives the main switching MOSFET of the DC-DC converter. The internal gate driver circuitry draws power from VC and returns it to ARTN. GATE is held low whenever the converter is disabled. LED (TPS23752 only): The LED pin drives an external status LED. Connect the LED and its series currentlimiting resistor from VC to the LED pin. While in Sleep Mode, the controller pulls the LED pin to ARTN. The LED pin is also pulled low during normal operation after the soft start is complete whenever the MODE pin is low. The LED pin should draw as little current as possible to help minimize the power consumed by the PD in Sleep Mode. If a status LED is not required, leave this pin open. MODE (TPS23752 only): The MODE pin in combination with the SLPb pin sets the type of MPS (DC or pulsed) during Sleep Mode. Holding this pin high when the SLPb pin transitions low causes the TPS23752 to generate a DC MPS by drawing a total of 10.6 mA (typical) from the Ethernet cable. Holding this pin low when the SLPb pin transitions low causes the TPS23752 to generate a pulsed MPS. Either MPS ensures that the PSE does not disconnect power from the PD while it is asleep. An MPS is not generated if the APD pin is held high (> 1.5 V). During normal operation, pulling MODE low causes the LED pin to pull low. 12 Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: TPS23751 TPS23752 TPS23751 TPS23752 www.ti.com SLVSB97B - JULY 2012 - REVISED JULY 2013 RT (Timing Resistor): A timing resistor (RT in Figure 1) connected between this pin and ARTN sets the PWM switching frequency fSW according to Equation 1. | SW = 8.5 109 W Hz RT (1) The switching frequency remains constant during PWM operation, but decreases as VCTL falls below VCTL_VFO. RT is a high impedance pin. Keep the connections short and isolate them from potential noise sources. RTN: The RTN pin provides the negative power return path for the converter. Once VDD exceeds the UVLO threshold (VUVLO_R), the internal pass MOSFET pulls RTN to VSS. Inrush limiting prevents the RTN current from exceeding about 140 mA until the bulk capacitance (CIN in Figure 1) is fully charged. Inrush ends and the converter begins operating when the RTN current drops below about 125 mA. The RTN current is subsequently limited to about 1 A. If RTN ever exceeds about 12 V, then the controller returns to inrush limiting. RTN should be connected to ARTN for most applications. SLPb: (TPS23752 only): The SLPb pin controls entry into Sleep Mode. A falling-edge transition applied to this pin during normal operation initiates Sleep Mode. This mode of operation disables converter switching, increases the current limit of the internal VC regulator, and pulls the LED output low. Cycling VDD or pulling the WAKE pin low terminates the Sleep Mode and restores normal operation. SRD (Synchronous Rectifier Disable): This open-drain output pulls to ARTN whenever the DC-DC converter is enabled, inrush and soft start are complete, and the voltage at the CTL pin exceeds the threshold VCTL_VFO set by the SRT pin. A low voltage on the SRD pin signals the synchronous rectifier to begin operation. If the CTL pin voltage drops below VCTL_VFO, then the SRD output goes high impedance to disable the synchronous rectifier. This action ensures that the synchronous rectifier does not operate during VFO mode. SRT (Synchronous Rectifier Threshold): The SRT pin sets the thresholds VCTL_VFO and VCS_VFO, at which the DCDC converter switches between PWM and VFO. The application circuit normally uses a resistor divider (RSRT1-RSRT2 in Figure 1) to generate a voltage of 0.5 to 1.5 V at the SRT pin. When the voltage on the CTL pin exceeds VCTL_VFO, the converter operates in PWM mode and the SRD pin is pulled low to enable the synchronous rectifier. When the voltage on CTL falls below VCTL_VFO, the converter operates in VFO and the SRD pin goes high impedance to disable the synchronous rectifier. Tying SRT to ARTN disables the VFO mode. T2P (Type-2 PSE Indicator): The controller pulls this pin to ARTN whenever type-2 hardware classification has been observed; or the APD pin is pulled high, after the internal T2P delay is complete, and VCTL 4 V. Once T2P is valid, VCTL has no effect on the status of T2P. The T2P output will return to a high-impedance state if the part enters thermal shutdown, the pass MOSFET enters inrush limiting, or if a type-2 PSE was not detected and the voltage on APD drops below its threshold. The circuitry that watches for type-2 hardware classification latches its result when the V(VDD-VSS) voltage differential rises above the upper classification threshold. This circuit resets when the V(VDD-VSS) voltage differential drops below the mark threshold. The T2P pin can be left unconnected if it is not used. VB (Bias Voltage): The VB pin is the output of an internal 5 V regulator fed from VC. A ceramic bypass capacitor with a minimum capacitance of no less than 80 nF must connect from VB to ARTN. VB may be used to bias the feedback optocoupler. For the TPS23752, VB may also bias pullups for SLPb and MODE. VC (Controller Voltage): The VC pin connects to the auxiliary bias supply for the DC-DC controller. The MOSFET gate driver draws current directly from VC. VB is regulated down from VC to provide power for the rest of the internal control circuitry. A startup current source from VDD to VC controlled by a comparator with hysteresis implements the converter bootstrap startup. VC must receive power from an auxiliary source, such as an auxiliary winding on the flyback transformer, to sustain normal operation after startup. A low-ESR bypass capacitor, such as a ceramic capacitor, must connect from VC to ARTN to supply the gate drive current required to drive the external switching MOSFET. The TPS23752 regulates VC to 12.8 V while in Sleep Mode to regulate the brightness of the Sleep-Mode LED. The Sleep Mode output voltage is high enough to drive at least three LED's in series when additional brightness is required. This reduces the required value of RLED and associated power consumption for a given LED bias current. VDD: The VDD pin connects to the positive side of the input supply. The VDD pin provides operating power to the PD controller, allows this circuit to monitor the input line voltage, and serves as the source for DC-DC startup current. In the TPS23752, it also supplies the LED and MPS current during Sleep-Mode operation Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: TPS23751 TPS23752 Submit Documentation Feedback 13 TPS23751 TPS23752 SLVSB97B - JULY 2012 - REVISED JULY 2013 www.ti.com VSS: The VSS pin connects to the negative rail of the input supply. It serves as a local ground for the PD control circuitry. The PowerPADTM must connect to VSS to ensure proper operation. WAKE (TPS23752 only): The WAKE pin performs several functions. During Sleep Mode, it outputs a currentlimited 2.5V. Pushing the external pushbutton (SWAKE in Figure 29) during Sleep Mode connects the WAKE pin to optocoupler, OPTO6. An internal current comparator detects this excess current drawn by OPTO6 and reenables the DC-DC converter out of Sleep Mode. The WAKE pin now connects back to the internal pull-up resistor (RWKPLUP in the Sleep Mode block diagram) to provide bias current for OPTO6. The optocoupler alerts the system controller that the button has been pressed during sleep operation. Circuit board routing should protect WAKE from noise sources on the board. 14 Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: TPS23751 TPS23752 TPS23751 TPS23752 www.ti.com SLVSB97B - JULY 2012 - REVISED JULY 2013 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs SUPPLY VOLTAGE DEN BIAS CURRENT vs SUPPLY VOLTAGE 450 7 TA = -40C TA = 25C TA = 125C 350 300 250 200 150 100 5 4 3 2 1 24 29 34 39 44 VDD (V) 49 54 0 57 2 4 6 8 G002 Figure 5. Figure 6. CS VFO PEAK VOLTAGE vs SRT VOLTAGE VC OPERATING CURRENT vs VC VOLTAGE 6.2 TA = 25C 130 120 110 100 90 80 70 10 VDD (V) VC Operating Current (mA) 140 0 G001 150 CS VFO Peak Voltage (mV) TA = -40C TA = 25C TA = 125C 6 DEN Blas Current (A) IDD, Supply Current (A) 400 RT = 16.9 k RT = 34 k RT = 169 k 5.2 TA = 25C 4.2 3.2 2.2 1.2 60 50 0.5 0.7 0.9 1.1 1.3 VSRT (V) 0.2 1.5 11 12 13 14 VC (V) 15 16 17 18 G004 Figure 8. CS RAMP CURRENT vs TEMPERATURE VC VOLTAGE in SLEEP MODE vs TEMPERATUE 13.6 VC Voltage in Sleep Mode (V) 17.5 ICS_RAMP Current (A) 10 Figure 7. 18 17 16.5 16 15.5 15 14.5 14 -40 9 G003 -20 0 20 40 60 Temperature (C) 80 100 120 13.4 13.2 13 12.8 12.6 12.4 -40 -20 G005 Figure 9. 0 20 40 60 Temperature (C) 80 100 120 G006 Figure 10. Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: TPS23751 TPS23752 Submit Documentation Feedback 15 TPS23751 TPS23752 SLVSB97B - JULY 2012 - REVISED JULY 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) VC BOOTSTRAP CURRENT SOURCE vs SUPPLY VOLTAGE CTL PWM/VFO THRESHOLD vs SRT VOLTAGE TA = 25C CTL PWM/VFO Threshold (V) TA = -40C TA = 25C TA = 125C 1.28 1.26 1.24 1.22 1.2 1.18 Switching Frequency (kHz) 2.6 VC = 8.6 V 12 16 20 24 28 32 VDD (V) 36 40 44 2.4 2.3 2.2 2.1 G008 SWITCHING FREQUENCY vs PROGRAMMABLE CONDUCTANCE 900 400 RT = 16.9 k RT = 34 k RT = 169 k 350 300 250 200 150 100 Actual Ideal 800 700 600 500 400 300 200 100 -20 0 20 40 60 Temperature (C) 80 100 0 120 5 G009 30 55 80 105 Programmable Conductance, 106/RT (-1) Figure 13. Figure 14. VFO FREQUENCY vs CTL VOLTAGE BLANKING PERIOD vs TEMPERATURE 250 125 G010 180 SRT = 0.5 V RT = 34 k TJ = 25C Blanking Period (ns) 170 150 100 50 160 150 140 130 1.6 1.7 1.8 VCTL (V) 1.9 2 120 -40 -20 G011 Figure 15. 16 1.5 SWITCHING FREQUENCY vs TEMPERATURE 1000 0 1.5 1.25 Figure 12. 450 200 1 VSRT (V) Figure 11. 500 0 -40 0.75 G007 50 VFO Frequency (kHz) 2.5 2 0.5 48 Switching Frequency (kHz) VC Bootstrap Current Source (mA) 1.3 Submit Documentation Feedback 0 20 40 60 Temperature (C) 80 100 120 G012 Figure 16. Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: TPS23751 TPS23752 TPS23751 TPS23752 www.ti.com SLVSB97B - JULY 2012 - REVISED JULY 2013 TYPICAL CHARACTERISTICS (continued) rDS(on) vs TEMPERATURE MPS SUPPLY CURRENT vs LED CURRENT 10.8 10.75 MPS Supply Current (mA) 0.7 0.65 0.6 rDS(on) () 0.55 0.5 0.45 0.4 0.35 0.3 10.7 10.65 10.6 10.55 10.5 10.45 0.25 0.2 -40 TA = -40C TA = 25C TA = 125C 10.4 -20 0 20 40 60 Temperature (C) 80 100 10.35 120 0 2 4 6 8 ILED (mA) G013 Figure 17. 10 G014 Figure 18. MPS SUPPLY CURRENT vs SUPPLY VOLTAGE 10.9 TA = -40C TA = 25C TA = 125C MPS Supply Current (mA) 10.85 10.8 10.75 10.7 10.65 10.6 10.55 10.5 10.45 10.4 39 44 49 VDD (V) 54 G015 Figure 19. DETAILED DESCRIPTION PoE OVERVIEW The following text is intended as an aid in understanding the operation of the TPS23751 and TPS23752 but not as a substitute for the IEEE 802.3at standard. The IEEE 802.3at standard is an update to IEEE 802.3-2008 clause 33 (PoE), adding high-power options and enhanced classification. Generally speaking, a device compliant to IEEE 802.3-2008 is referred to as a type 1 device, and devices with high power and enhanced classification are referred to as type 2 devices. Standards change and should always be referenced when making design decisions. The IEEE 802.3at standard defines a method of safely powering a PD (powered device) over a cable by power sourcing equipment (PSE), and then removing power if a PD is disconnected. The process proceeds through an idle state and three operational states of detection, classification, and operation. The PSE leaves the cable unpowered (idle state) while it periodically looks to see if something has been plugged in; this operation is referred to as detection. The low power levels used during detection are unlikely to damage devices not designed for PoE. If a valid PD signature is present, the PSE may inquire how much power the PD requires; this operation is referred to as classification. The PSE may then power the PD if it has adequate capacity. Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: TPS23751 TPS23752 Submit Documentation Feedback 17 TPS23751 TPS23752 SLVSB97B - JULY 2012 - REVISED JULY 2013 www.ti.com Type 2 PSEs are required to do type 1 hardware classification plus a (new) data-layer classification, or an enhanced type 2 hardware classification. Type 1 PSEs are not required to do hardware or data link layer (DLL) classification. A type 2 PD must do type 2 hardware classification as well as DLL classification. The PD may return the default, 13W current-encoded class, or one of four other choices. DLL classification occurs after power-on and the Ethernet data link has been established. 0 10.1 14.5 20.5 30 Maximum Input Voltage Must Turn On by- Voltage Rising Lower Limit -Operating Range Must Turn Off by - Voltage Falling Shutdown Classify Detect 6.9 2.7 Classification Upper Limit Classification Lower Limit Detection Upper Limit Detection Lower Limit IEEE 802.3-2008 Once started, the PD must present a Maintain Power Signature (MPS) to assure the PSE that it is still present. The PSE monitors its output for a valid MPS and turns the port off if it loses the MPS. Loss of the MPS returns the PSE to the idle state. Figure 20 shows the operational states as a function of PD input voltage. The upper half is for IEEE 802.3-2008, and the lower half shows specific differences for IEEE 802.3at. The dashed lines in the lower half indicate these states are the same (e.g., Detect and Class) for both. Normal Operation 42.5 37 57 42 250s Transient Lower Limit - 13W Op. Class-Mark Transition T2 Reset Range IEEE 802.3at PI Voltage (V) Normal Operation Mark Figure 20. Threshold Voltages The PD input, typically an RJ-45 eight-lead connector, is referred to as the power interface (PI). PD input requirements differ from PSE output requirements to account for voltage drops and operating margin. The standard allots the maximum loss to the cable regardless of the actual installation to simplify implementation. IEEE 802.3-2008 was designed to run over infrastructure including ISO/IEC 11801 class C (CAT3 per TIA/EIA568) that may have had AWG 26 conductors. IEEE 802.3at type 2 cabling power loss allotments and voltage drops have been adjusted for 12.5 power loops per ISO/IEC11801 class D (CAT5 or higher per TIA/EIA-568, typically AWG 24 conductors). Table 2 shows key operational limits broken out for the two revisions of the standard. 18 Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: TPS23751 TPS23752 TPS23751 TPS23752 www.ti.com SLVSB97B - JULY 2012 - REVISED JULY 2013 Table 2. Comparison of Operational Limits Standard Power Loop Resistance (max) PSE Output Power (min) PSE Static Output Voltage (min) PD Input Power (max) Static PD Input Voltage Power 12.95W Power > 12.95W IEEE802.3at-2008 802.3at (Type 1) 20 15.4W 44V 12.95W 37V - 57V N/A 802.3at (Type 2) 12.5 30W 50V 25.5W 37V - 57V 42.5V - 57V The PSE can apply voltage either between the RX and TX pairs (pins 1 - 2 and 3 - 6 for 10baseT or 100baseT), or between the two spare pairs (4 - 5 and 7 - 8). Power application to the same pin combinations in 1000baseT systems is recognized in IEEE 802.3at. 1000baseT systems can handle data on all pairs, eliminating the spare pair terminology. The PSE may only apply voltage to one set of pairs at a time. The PD uses input diode bridges to accept power from any of the possible PSE configurations. The voltage drops associated with the input bridges create a difference between the standard limits at the PI and the TPS23751 and TPS23752 specifications. A compliant type 2 PD has power management requirements not present with a type 1 PD. These requirements include the following: 1. Must interpret type 2 hardware classification, 2. Must present hardware class 4, 3. Must implement DLL negotiation, 4. Must behave like a type 1 PD during inrush and startup, 5. Must not draw more than 13W for 80ms after the PSE applies operating voltage (power-up), 6. Must not draw more than 13W if it has not received a type 2 hardware classification or received permission through DLL, 7. Must meet various operating and transient templates, and 8. Optionally monitor for the presence or absence of an adapter (assume high power). As a result of these requirements, the PD must be able to dynamically control its loading, and monitor T2P for changes. In cases where the design needs to know specifically if an adapter is plugged in and operational, the adapter should be individually monitored, typically with an optocoupler. Threshold Voltages PD Powered Idle Classification Type 1 Type 2 Functional State The TPS23751 and TPS23752 have a number of internal comparators with hysteresis for stable switching between the various states. Figure 21 relates the parameters in the Electrical Characteristics section to the PoE states. The mode labeled Idle between Classification and Operation implies that the DEN, CLS, and RTN pins are all high impedance. The state labeled Mark, which is drawn in dashed lines, is part of the new type 2 hardware class state machine. Mark Detection VDD-VSS VCL_H VCL_ON VCU_H VUVLO_H VCU_OFF VUVLO_R VMSR NOTE: Variable names refer to Electrical Characteristic table parameters Figure 21. Threshold Voltages Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: TPS23751 TPS23752 Submit Documentation Feedback 19 TPS23751 TPS23752 SLVSB97B - JULY 2012 - REVISED JULY 2013 www.ti.com PoE Startup Sequence The waveforms of Figure 22 demonstrate detection, classification, and startup from a PSE with type 2 hardware classification. The key waveforms shown are V(VDD-VSS), V(RTN-VSS), and IPI. IEEE 802.3at requires a minimum of two detection levels, two class and mark cycles, and startup from the second mark event. VRTN to VSS falls as the TPS23751 or TPS23752 charges CIN following application of full voltage. Subsequently, the converter starts up, drawing current as seen in the IPI waveform. Converter Starts Inrush IPI 100mA/div V(VDD-VSS) Class Mark Detect V(RTN-VSS) 10V/div Time: 50ms/div Figure 22. Startup Detection The TPS23751 or TPS23752 pulls DEN to VSS whenever V(VDD-VSS) is below the lower classification threshold. When the input voltage rises above VCL-ON, the DEN pin goes to an open-drain condition to conserve power. While in detection, RTN is high impedance, and almost all the internal circuits are disabled. An RDEN of 24.9 k (1%), presents the correct signature. It may be a small, low-power resistor since it only sees a stress of about 5 mW. A valid PD detection signature is an incremental resistance ( V/I ) between 23.75 k and 26.25 k at the PI. The detection resistance seen by the PSE at the PI is the result of the input bridge resistance in series with the parallel combination of RDEN and internal VDD loading. The incremental resistance of the input diode bridge may be hundreds of ohms at the very low currents drawn when 2.7 V is applied to the PI. The input bridge resistance is partially compensated by the TPS23751 or TPS23752 effective resistance during detection. The type 2 hardware classification protocol of IEEE 802.3at specifies that a type 2 PSE drops its output voltage into the detection range during the classification sequence. The PD is required to have an incorrect detection signature in this condition, which is referred to as a mark event (see Figure 22). After the first mark event, the TPS23751 or TPS23752 presents a signature less than 12 k until it has experienced a V(VDD-VSS) voltage below the mark reset threshold (VMSR). This operation is explained more fully in the Hardware Classification section. 20 Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: TPS23751 TPS23752 TPS23751 TPS23752 www.ti.com SLVSB97B - JULY 2012 - REVISED JULY 2013 Hardware Classification Hardware classification allows a PSE to determine the power requirements of a PD before powering, and helps with power management once power is applied. Type 2 hardware classification permits high power PSEs and PDs to determine whether the connected device can support high-power operation. A type 2 PD presents class 4 in hardware to indicate that it is a high-power device. A type 1 PSE treats a class 4 device like a class 0 device, allotting 13 W if it chooses to power the PD. A PD that receives a 2-event class understands that it is powered from a high-power PSE and it may draw up to 25.5 W immediately after the 80 ms startup period completes. A type 2 PD that does not receive a 2-event hardware classification may choose to not start, or must start in a 13 W condition and request more power through the DLL after startup. The standard requires a type 2 PD to indicate that it is underpowered if this occurs. Startup of a high-power PD under 13 W implicitly requires some form of powering down sections of the application circuits. The maximum power entries in Table 1 determine the class the PD must advertise. The PSE may disconnect a PD if it draws more than its stated Class power, which may be the hardware class or a lower DLL-derived power level. The standard permits the PD to draw limited current peaks that increase the instantaneous power above the Table 1 limit, however the average power requirement always applies. The TPS23751 and TPS23752 implement two-event classification. Selecting an RCLS of 63.4 provides a valid type 2 signature. A TPS23751 or TPS23752 may be used as a compatible type 1 device simply by programming class 0-3 per Table 1. DLL communication is implemented by the Ethernet communication system in the PD and is not implemented by the TPS23751 or TPS23752. The TPS23751 and TPS23752 disable classification above VCU_OFF to avoid excessive power dissipation. CLS voltage is turned off during PD thermal limiting or when DEN is active. The CLS output is inherently current limited, but should not be shorted to VSS for long periods of time. Figure 23 shows how classification works for the TPS23751 and TPS23752. Transition from state-to-state occurs when comparator thresholds are crossed (see Figure 20 and Figure 21). These comparators have hysteresis, which adds inherent memory to the machine. Operation begins at idle (unpowered by PSE) and proceeds with increasing voltage from left to right. A 2-event classification follows the (heavy lined) path towards the bottom, ending up with a latched type 2 decode along the lower branch that is highlighted. This state results in a low T2P during normal operation. Once the valid path to type 2 PSE detection is broken, the input voltage must transition below the mark reset threshold to start anew. Idle Detect Mark Reset Mark Class Between Ranges Class Between Ranges Class Between Ranges UVLO Falling UVLO Rising Operating T2P Open-Drain TYPE 1 PSE Hardware Class PoE Startup Sequence Mark Class Between Ranges UVLO Rising Operating T2P Low TYPE 2 PSE Hardware Class UVLO Falling Figure 23. Two-Event Class Internal States Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: TPS23751 TPS23752 Submit Documentation Feedback 21 TPS23751 TPS23752 SLVSB97B - JULY 2012 - REVISED JULY 2013 www.ti.com Inrush and Startup IEEE 802.3at has a startup current and time limitation, providing type 2 PSE compatibility for type 1 PDs. A type 2 PSE limits output current to between 400 mA and 450 mA for up to 75 ms after power-up (applying "48 V" to the PI) in order to mirror type 1 PSE functionality. The type 2 PSE supports higher output current after 75 ms. The TPS23751 and TPS23752 implement a 140 mA inrush current, which is compatible with all PSE types. A high-power PD must limit its converter startup peak current. The operational current cannot exceed 400 mA for a period of 80 ms or longer. The TPS23751 and TPS23752 internal soft-start permits control of the converter startup, however the application circuits must assure that their power draw does not cause the PD to exceed the current and time limitation. This requirement implicitly requires some form of powering down sections of the application circuits. T2P becomes valid within tT2P after switching starts, or if an adapter is plugged in while the PD is operating from a PSE. Maintain Power Signature The MPS is an electrical signature presented by the PD to assure the PSE that it is still present after operating voltage is applied. A valid MPS consists of a minimum dc current of 10 mA (or a 10 mA pulsed current for at least 75 ms every 325 ms) and an ac impedance lower than 26.3 k in parallel with 0.05 F. The ac impedance is usually accomplished by the minimum operating CIN requirement of 5 F. When DEN is used to force the hotswap switch off, the dc MPS is not met. A PSE that monitors the dc MPS removes power from the PD when this occurs. A PSE that monitors only the ac MPS may remove power from the PD. Additional TPS23752 MPS features are supported as described in the Sleep Mode section. Startup and Converter Operation The internal PoE UVLO (Under Voltage Lock Out) circuit holds the hotswap switch off before the PSE provides full voltage to the PD. This prevents the converter circuits from loading the PoE input during detection and classification. The converter circuits discharge CIN, Cvc, and Cvb while the PD is unpowered. Thus V(VDD-RTN) is a small voltage just after applying full voltage to the PD, as seen in Figure 22. The PSE drives the PI voltage to the operating range once the PSE has decided to power up the PD. When VVDD rises above the UVLO turn-on threshold (VUVLO-R, approximately 38 V) with RTN high, the TPS23751 and TPS23752 enable the hotswap MOSFET with approximately 140 mA (inrush) current limit as seen in Figure 24. Converter switching is disabled while CIN charges and VRTN falls from VVDD to nearly VVSS, however the converter startup circuit is allowed to charge CVC (the bootstrap startup capacitor). Converter switching is allowed if the PD is not in inrush, OTSD is not active, and the VC UVLO permits it. Once the inrush current falls about 10% below the inrush current limit, the PD current limit switches to the operational level (approximately 1000 mA). Continuing the startup sequence shown in Figure 24, VVC continues to rise until the startup threshold (VCUV approximately 8.9 V) is exceeded, turning the startup source off and enabling switching. The VB regulator is always active, powering the internal converter circuits as VVC rises. There is a slight delay between the removal of charge current and the start of switching as the softstart ramp sweeps above the VZDC threshold. VVC falls as it powers both the internal circuits and the switching MOSFET gates. If the converter control bias output rises to support VVC before it falls to VCUV - VCUVH (approximately 5.7 V), a successful startup occurs. In Figure 24, T2P is active if a type 2 PSE is plugged in. 22 Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: TPS23751 TPS23752 TPS23751 TPS23752 www.ti.com SLVSB97B - JULY 2012 - REVISED JULY 2013 V(VDD-RTN) 50V/div Converter Starts Inrush IPI 100mA/div PI Powered V(VC-RTN) 5V/div OUTPUT VOLTAGE 5V/div Type 1 PSE T2P @ OUTPUT 5V/div Type 2 PSE Time: 20ms/div Figure 24. Power Up and Start If VVDD- VVSS drops below the lower PoE UVLO (VUVLO-R - VUVLO-H, approximately 32 V), the hotswap MOSFET is turned off, but the converter still runs. The converter stops if VVC falls below the converter UVLO (VCUV - VCUVH, approximately 5.7 V), the hotswap is in inrush current limit, 0% duty cycle is demanded by VCTL (VCTL < VZDC, approximately 1.75 V), or the converter is in thermal shutdown. PD Hotswap Operation IEEE 802.3at has taken a new approach to PSE output limiting. A type 2 PSE must meet an output current versus time template with specified minimum and maximum sourcing boundaries. The peak output current may be as high as 50 A for 10 s or 1.75 A for 75 ms. This makes robust protection of the PD device even more important than it was in IEEE 802.3-2008. The internal hotswap MOSFET is protected against output faults and input voltage steps with a current limit and deglitched (time-delay filtered) foldback. An overload on the pass MOSFET engages the current limit, with VRTNVVSS rising as a result. If VRTN rises above approximately 12 V for longer than approximately 800 s, the current limit reverts to the inrush value, and turns the converter off. The 800 s deglitch feature prevents momentary transients from causing a PD reset, provided that recovery lies within the bounds of the hotswap and PSE protection. Figure 25 shows an example of recovery from a 16 V PSE rising voltage step. The hotswap MOSFET goes into current limit, overshooting to a relatively low current, recovers to approximately 1000 mA full current limit and charges the input capacitor while the converter continues to run. The MOSFET did not go into foldback because VRTN-VVSS was below 12 V after the 800 s deglitch. Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: TPS23751 TPS23752 Submit Documentation Feedback 23 TPS23751 TPS23752 SLVSB97B - JULY 2012 - REVISED JULY 2013 www.ti.com Recovery from PI Dropout V(VDD-VSS) 20V/div CIN Completes Charge While Converter Operates IPI 500mA/div 16-V Input Step VRTN < 12V @ 800s V(RTN-VSS) 10V/div Time: 200s/div Figure 25. Response to Output Short Circuit The PD control has a thermal sensor that protects the internal hotswap MOSFET. Conditions like startup or operation into a VDD-to-RTN short cause high power dissipation in the MOSFET. An over-temperature shutdown (OTSD) turns off the hotswap MOSFET and class regulator, which are restarted after the device cools. The hotswap MOSFET is re-enabled with the inrush current limit when exiting from an over-temperature event. Pulling DEN to VSS during powered operation causes the internal hotswap MOSFET to turn off. The hotswap switch is forced off under the following conditions: 1. VAPD above VAPDEN (approximately 1.5V) 2. V(DEN -VSS) < VPD_DIS when VVDD- VVSS is in the operational range, 3. PD OTSD is active, or 4. V(DEN -VSS) < PoE UVLO falling threshold (approximately 32 V). Sleep Mode Operation (TPS23752 only) These features implement a Sleep Mode, permitting power savings at night (or some other system-driven criteria) by turning the active load circuits off while maintaining enough functionality for the PD to respond to a local power-up request. The Sleep Mode is initiated by command of a local device controller (microprocessor) when the SLPb input is driven low. Sleep Mode is latched by this event, the converter is disabled, VDD regulates VC to 12.8V, and the LED output is active. The LED output sinks current to light an LED biased from the VC pin with RLED as shown in Figure 29. LED can alert a local user that Sleep Mode is active. The TPS23752 signals the PSE that it wants to remain powered during sleep by drawing enough current to satisfy the IEEE 802.3at DC MPS requirements. If MODE was low when SLPb fell, a pulsed VDD current-draw scheme is implemented; otherwise a DC current is drawn. The input current consists of the TPS23752 bias currents and the LED sink current, assuming no additional loading on VC or VB. The MPS current draw is inhibited when APD is active. A local pushbutton switch 24 Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: TPS23751 TPS23752 TPS23751 TPS23752 www.ti.com SLVSB97B - JULY 2012 - REVISED JULY 2013 (SWAKE in Figure 29) is monitored by the WAKE pin and the latched sleep state exits when the button is pressed. The button is connected to ARTN through an optocoupler LED (OPTO6 in Figure 29) that alerts the device controller the button was pushed during normal operation. The MODE pin also has a second function, serving to activate the LED output when driven low during normal converter operation. For more information regarding the TPS23752 Sleep Mode Feature, see TPS23752 Maintain Power Signature Operation In Sleep Mode (SLVA588). Converter Controller Features The TPS23751 and TPS23752 DC-DC controller implements typical current-mode control as well as variable frequency operation for light load efficiency optimization as shown in the Functional Block Diagram. Features include programmable oscillator, over-current, PWM, VFO, and ZDC comparators, current-sense blanker, softstart, and gate driver. In addition, an internal slope-compensation ramp generator, thermal shutdown, and startup current source with control are provided. The TPS23751 and TPS23752 are targeted at high efficiency, current mode, synchronous, flyback converters incorporating an external error amplifier. In PWM mode, the external error amplifier and optocoupler drives the CTL pin to demand current from the PWM. The internal current sense to control (CS to CTL pin) gain is 5V/V. VFO mode can be enabled using a voltage divider on the SRT pin. The TPS23751 and TPS23752 enter VFO mode when VCTL falls below VSRT/2 + 1.75V. PWM and VFO Operation; CTL, SRT, and SRD Pin Relationships to Output Load Current As the TPS23751 and TPS23752 transition from PWM to VFO mode with decreasing output load current, several things happen to help reduce the light load losses of the DC-DC converter. A summary is shown in Table 3. Table 3. Comparison of PWM and VFO Modes MODE SWITCHING FREQUENCY INDUCTOR PEAK CURRENT SYNCHRONOUS RECTIFIER (control with SRD pin) INTERNAL SLOPE COMPENSATION PWM Constant; set by RT Variable, set by VCTL Enabled (SRD = LOW) Enabled VFO Variable; set by VCTL Constant, clamped by VSRT Disabled (SRD = OPEN) Disabled The state of the SRD pin depends on the internal operating mode (PWM or VFO) and is used to enable or disable the synchronous rectifier. In addition to disabling the synchronous rectifier, the TPS23751 and TPS23752 reduce the switching frequency in VFO mode to maintain output regulation. Synchronous rectification provides an efficiency advantage over a standard diode rectifier at medium to heavy loads, but not at lighter loads. The SRD feature can provide a means to recover the light load losses by disabling the synchronous rectifier and allowing the standard diode rectifier to take over as illustrated in Figure 26 by the VFO/PWM mode efficiency curve. Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: TPS23751 TPS23752 Submit Documentation Feedback 25 TPS23751 TPS23752 SLVSB97B - JULY 2012 - REVISED JULY 2013 www.ti.com 90 VFO/PWM Mode 85 80 Efficiency (%) 75 70 PWM Mode Only 65 60 55 50 45 40 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 Load Current (A) Figure 26. TPS23751 and TPS23752 Light Load Efficiency versus Mode Figure 27 illustrates operation through the VFO to PWM to VFO transitions. As load current increases, so does VCTL. When VCTL exceeds the rising threshold, the TPS23751 and TPS23752 transition from VFO to PWM mode, and SRD goes low. The converter now operates with fixed frequency and current demand set by VCTL. As load current decreases, so does VCTL. When VCTL decays below the falling threshold, the TPS23751 and TPS23752 transition from PWM to VFO mode, and SRD goes high. The converter now operates with variable frequency set by VCTL, and fixed current demand set by VSRT. 26 Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: TPS23751 TPS23752 TPS23751 TPS23752 www.ti.com SLVSB97B - JULY 2012 - REVISED JULY 2013 ILOAD Natural Hysteresis 1A/div VCTL VFO Mode PWM Mode VFO Mode 500mV/div VSRD 10V/div Time: 5ms/div Figure 27. Converter Mode Transition There is a natural load current hysteresis for ILOAD which can be seen in Figure 27 between the transition points. For increasing ILOAD, the transition current is slightly higher than for decreasing ILOAD. This condition is due partially to CTL pin hysteresis (approximately 35mV) and partially due to CTL pin operating point versus mode. VCTL is slightly higher in PWM mode than in VFO mode for given output load at or near the transition point. Bootstrap Topology The internal startup current source (IVC_ST) and control logic implement a bootstrap-type startup as discussed in the Startup and Converter Operation section. The startup current source charges CVC from VDD when the converter is disabled (either by the PD control or the VC control) to store enough energy to start the converter. Steady-state operating power must come from a converter (bias winding) output or other source. Loading on VC and VB must be minimal while CVC charges, otherwise the converter may never start. The optocoupler does not load VB when the converter is off for most situations, however care should be taken in ORing topologies where the output is powered when PoE is off. The converter shuts off when VC falls below its lower UVLO. This can happen when power is removed from the PD, or during a fault on a converter output rail. When one output is shorted, all the output voltages fall including the one that powers VC. The control circuit discharges VC until it hits the lower UVLO and turns off. A restart is initiated as described in the Startup and Converter Operation section if the converter turns off and there is sufficient VDD voltage. This type of operation is sometimes referred to as hiccup mode which provides robust output short protection by providing time-average heating reduction of the output rectifier. Below VCUV, the bootstrap control logic disables most of the converter controller circuits except the VB regulator and internal reference. GATE is low when the converter is disabled. The bootstrap source provides reliable startup from widely varying input voltages, and eliminates the continual power loss of external resistors. The startup current source does not charge above the maximum recommended VVC if the converter is disabled and there is sufficient VDD to charge higher. Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: TPS23751 TPS23752 Submit Documentation Feedback 27 TPS23751 TPS23752 SLVSB97B - JULY 2012 - REVISED JULY 2013 www.ti.com Current Slope Compensation and Current Limit Current-mode control requires addition of a compensation ramp to the sensed inductive (transformer or inductor) current for stability at duty cycles near and over 50%. The TPS23751 and TPS23752 have a maximum duty cycle limit of 80%, permitting the design of wide input-range converters with lower voltage stress on the output rectifiers. While the maximum duty cycle is 80%, converters may be designed that run at duty cycles well below this for a narrower, 36 V to 57 V PI range. The TPS23751 and TPS23752 provide fixed internal slope compensation which suffices for most applications. The TPS23751 and TPS23752 provide internal, frequency independent, slope compensation (VPK = 40 mV at DMAX) starting from DSLOPE_ST to the PWM comparator input for current-mode control-loop stability. This voltage is not applied to the current-limit comparator whose threshold is 0.25 V (VCSMAX). If the provided slope is not sufficient, the effective slope may be increased by addition of RS per Figure 30. The additional slope voltage is provided by (ICS_RAMP x RS). There is also a small dc offset caused by the ICSDC (approximately 2.0 A) current. The peak current limit does not have duty cycle dependency unless RS is used which is easier designing the current limit to a fixed value. See the Current Slope Compensation section for more information. The internal comparators monitoring CS are isolated from the CS pin by the blanking circuits while GATE is low, and for a short time (blanking period) just after GATE switches high. A 500 (max) equivalent pull-down resistor on CS is applied while GATE is low. RT The RT pin programs the (free-running) oscillator frequency of the TPS23751 and TPS23752 in PWM mode. The internal oscillator sets the maximum duty cycle at 80% and controls the slope-compensation ramp circuit. In VFO mode, the RT pin is driven by VCTL. T2P, Startup and Power Management T2P (type 2 PSE) is an active-low multifunction pin that indicates if [(PSE = Type_2) + (VAPD > 1.5V) + (VCTL < 4 V) x (PD current limit Inrush)]. The term with VCTL prevents an optocoupler connected to the secondary-side from loading VC before the converter is started. The APD term allows the PD to operate from an adapter at high-power if a type 2 PSE is not present, assuming the adapter has sufficient capacity. Applications must monitor the state of T2P to detect power source transitions. Transitions could occur when a local power supply is added or dropped or when a PSE is enabled on the far end. The PD may be required to adjust the load appropriately. The usage of T2P is demonstrated in Figure 1. In order for a type 2 PD to operate at less than 13W the first 80ms after power application, the various delays must be estimated and used by the application controller to meet the requirement. The bootup time of many applications processors may be long enough to eliminate the need to do any timing. Figure 24 illustrates the T2P delay after the converter starts. Thermal Shutdown The DC-DC controller has an OTSD that can be triggered by heat sources including the VB regulator, GATE driver, bootstrap current source, and bias currents. The controller OTSD turns off VB, the GATE driver, and forces the VC control into an under-voltage state. Adapter ORing Many PoE-capable devices are designed to operate from either a wall adapter or PoE power. A local power solution adds cost and complexity, but allows a product to be used if PoE is not available in a particular installation. While most applications only require that the PD operate when both sources are present, the TPS23751 and TPS23752 supports forced operation from either of the power sources. Figure 28 illustrates three options for diode ORing external power into a PD. Only one option would be used in any particular design. Option 1 applies power to the TPS23751 and TPS23752 PoE input, option 2 applies power between the TPS23751 and TPS23752 PoE section and the power circuit, and option 3 applies power to the output side of the converter. Each of these options has advantages and disadvantages. Many of the basic ORing configurations and much of the discussion contained in the application note Advanced Adapter ORing Solutions using the TPS23753 (literature number SLVA306), apply to the TPS23751 and TPS23752. 28 Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: TPS23751 TPS23752 TPS23751 TPS23752 SLVSB97B - JULY 2012 - REVISED JULY 2013 VPOE VDD RDEN + Low Voltage Output DEN CLS VSS Power Circuit TPS23751/2 RCLS D1 C1 From Spare Pairs From Ethernet or Transformers Transformers www.ti.com RTN Adapter Option 1 Adapter Option 2 Adapter Option 3 Figure 28. Oring Configurations The IEEE standards require that the Ethernet cable be isolated from ground and all other system potentials. The adapter must meet a minimum 1500 Vac dielectric withstand test between the output and all other connections for ORing options 1 and 2. The adapter only needs this isolation for option 3 if it is not provided by the converter. Adapter ORing diodes are shown for all the options to protect against a reverse voltage adapter, a short on the adapter input pins, or damage to a low-voltage adapter. ORing is sometimes accomplished with a MOSFET in option 3. Using DEN to Disable PoE The DEN pin may be used to turn the PoE hotswap switch off by pulling it to VSS while in the operational state, or to prevent detection when in the idle state. A low voltage on DEN forces the hotswap MOSFET off during normal operation. ORing Challenges Preference of one power source presents a number of challenges. Combinations of adapter output voltage (nominal and tolerance), power insertion point, and which source is preferred determine solution complexity. Several factors adding to the complexity are the natural high-voltage selection of diode ORing (the simplest method of combining sources), the current limit implicit in the PSE, and PD inrush and protection circuits (necessary for operation and reliability). Creating simple and seamless solutions is difficult, if not impossible, for many of the combinations. However, the TPS23751 and TPS23752 offer several built-in features that simplify some combinations. Several examples demonstrate the limitations inherent in ORing solutions. Diode ORing a 48 V adapter with PoE (option 1) presents the problem that either source may have the higher voltage. A blocking switch would be required to assure that one source dominates. A second example combines a 12 V adapter with PoE using option 2. The converter draws approximately four times the current at 12 V from the adapter than it does from PoE at 48 V. Transition from adapter power to PoE may demand more current than can be supplied by the PSE. The converter must be turned off while the CIN capacitance charges, with a subsequent converter restart at the higher voltage and lower input current. A third example involves the loss of the MPS when running from the adapter, causing the PSE to remove power from the PD. If ac power is then lost, the PD stops operating until the PSE detects and powers the PD. Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: TPS23751 TPS23752 Submit Documentation Feedback 29 TPS23751 TPS23752 SLVSB97B - JULY 2012 - REVISED JULY 2013 www.ti.com APPLICATION INFORMATION From Ethernet Pairs 1,2 The TPS23751 and TPS23752 support power supply topologies that require a single PWM gate drive with current-mode control. Figure 29 provides an example of a synchronous rectifier flyback converter. Selecting a converter topology along with a design procedure is beyond the scope of this applications section. Examples to help in programming the TPS23751 and TPS23752 are shown below. Additional special topics are included to explain the ORing capabilities, frequency dithering, and other design considerations. For more specific converter design examples refer to the following application notes: * Designing with the TPS23753 Powered Device and Power Supply Controller, SLVA305 * Advanced Adapter ORing Solutions using the TPS23753, SLVA306A * TPS23751EVM-104 EVM: Evaluation Module for TPS23751, SLVU754 * TPS23752EVM-145 EVM: Evaluation Module for TPS23752, SLVU753 RT2P RSRD RSRT1 M2 OPTO1 TLV431 OPTO2 VB RWAKE WAKE RSL MODE VOUT OPTO4 RPB SLPb RMODE RLED LED TPS23752 P 2/2 VC SLPb RSLN OPTO5 MODE SWAKE RMPS OPTO6 PBb Sleep Mode Processor Control Interface CIO CIZ RFBL ROB RFBU OPTO2 VOUT CVC OPTO1 Type 2 PSE Indicator M1 RSRT2 ARTN TPS23752 P 1/2 SRT GATE CS SRD OPTO3 DVC1 RVC VC VB CVB RT CCTL RCTL RTN VSS APD CTL RT DOUT RCS VDD 58V CLS PAD VB RAPD2 Adapter RAPD1 DEN RCLS 0.1uF From Ethernet Pairs 3,4 DA CIN OPTO3 T2P VOUT COUT RDEN T1 Figure 29. TPS23752 Application Circuit Input Bridges and Schottky Diodes Using Schottky diodes instead of PN junction diodes for the PoE input bridges reduces the power dissipation in these devices by about 30%. There are, however, some things to consider when using them. The IEEE standard specifies a maximum backfeed voltage of 2.8 V. A 100 k resistor is placed between the unpowered pairs and the voltage is measured across the resistor. Schottky diodes often have a higher reverse leakage current than PN diodes, making this a harder requirement to meet. To compensate, use conservative design for diode operating temperature, select lower-leakage devices where possible, and match leakage and temperatures by using packaged bridges. Schottky diode leakage currents and lower dynamic resistances can impact the detection signature. Setting reasonable expectations for the temperature range over which the detection signature is accurate is the simplest solution. Increasing RDEN slightly may also help meet the requirement. Schottky diodes have proven less robust to the stresses of ESD transients than PN junction diodes. After exposure to ESD, Schottky diodes may become shorted or leak. Care must be taken to provide adequate protection in line with the exposure levels. This protection may be as simple as ferrite beads and capacitors. As a general recommendation, use 1 A or 2 A, 100 V rated discrete or bridge diodes for the input rectifiers. 30 Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: TPS23751 TPS23752 TPS23751 TPS23752 www.ti.com SLVSB97B - JULY 2012 - REVISED JULY 2013 Protection, D1 A TVS, D1, across the rectified PoE voltage per Figure 1 must be used. A SMAJ58A, or equivalent, is recommended for general indoor applications. Adequate capacitive filtering or a TVS must limit input transient voltage to within the absolute maximum ratings. Outdoor transient levels or special applications require additional protection. Capacitor, C1 The IEEE 802.3at standard specifies an input bypass capacitor (from VDD to VSS) of 0.05 F to 0.12 F. Typically a 0.1 F, 100 V, 10% ceramic capacitor is used. Detection Resistor, RDEN The IEEE 802.3at standard specifies a detection signature resistance, RDEN between 23.75 k and 26.25 k, or 25 k 5%. A resistor of 24.9 k 1% is recommended for RDEN. Classification Resistor, RCLS Connect a resistor from CLS to VSS to program the classification current according to the IEEE 802.3at standard. The class power assigned should correspond to the maximum average power drawn by the PD during operation. Select RCLS according to Table 1. For a high power design, choose class 4 and RCLS = 63.4 . APD Pin Divider Network, RAPD1, RAPD2 The APD pin can be used to disable the TPS23751 and TPS23752 internal hotswap MOSFET, giving the adapter source priority over the PoE. For an example calculation, see literature number SLVA306A. Setting the PWM-VFO Threshold using the SRT pin The TPS23751 and TPS23752 internally compares modified voltages at the SRT and CTL pins to determine the operating mode. The designer should consider the light load operating point (considering the value of VCTL) where synchronous rectifier (M2 in Figure 29) gate drive and switching losses nearly match conduction losses of the rectifier diode (DOUT in Figure 29). Typically, the designer characterizes circuit efficiency, output load, and control pin (VCTL) voltage and then select the transition point. Both VFO PWM (occurs at higher load current due to natural hysteresis) and PWM VFO (occurs at slightly lower load current) transitions should be considered when choosing the VSRT setpoint. As an example: 1. Assume that the desired efficiency transition threshold occurs at 18% of full load and VCTL = 2.0 V 2. Determine where to set VSRT. Transition to VFO mode when VCTL = 2.0 V VSRT = 2 VCTL - 3.5 V = 2 2.0 V - 3.5 V = 0.5 V (2) 3. Set VSRT using a voltage divider from VB to ARTN as shown in Figure 29. 4. Choose RSRT1 = 100 k and then calculate RSRT2 as follows: R V 100 k W 0.5 V RSRT2 = SRT1 SRT = = 11.1 kW VB - VSRT 5 V - 0.5 V (3) 5. Select 11 k for RSRT2. Setting Frequency (RT) The converter switching frequency in PWM mode is set by connecting resistor, RT from the RT pin to ARTN (see Figure 29). The frequency may be set as high as 1 MHz with some loss in programming accuracy as well as converter efficiency. As an example: 1. Assume a desired switching frequency (fSW) of 250 kHz. 2. Compute RT: RT = 8.5 109 W 8.5 109 W = = 34000 W | SW (Hz) 250000 (4) 3. Select 34 k for RT. Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: TPS23751 TPS23752 Submit Documentation Feedback 31 TPS23751 TPS23752 SLVSB97B - JULY 2012 - REVISED JULY 2013 www.ti.com Current Slope Compensation The TPS23751 and TPS23752 provide a fixed internal compensation ramp that suffices for most applications. RS (see Figure 30) may be used if the internally provided slope compensation is not enough. Most current-mode control papers and application notes define the slope values in terms of VPP/TS (peak ramp voltage / switching period). Assuming that the desired slope, VSLOPE_D (in mV/period), as shown in Figure 2, is based on the full period, compute RS per the following equation where VPK and ICS_RAMP are from the electrical characteristics table with voltages in mV and current in A. VPK (mV) VSLOPE _ D (mV) DMAX - DSLOPE _ ST RS ( W ) = 1000 ICS _ RAMP (mA) ( ) (DMAX - DSLOPE _ ST ) (5) VDD RVFF ARTN RTN GATE CS RS CS RCS Figure 30. Additional Slope Compensation CS may be required if the presence of RS causes increased noise, due to adjacent signals like the gate drive, to appear at the CS pin. Voltage Feed-Forward Compensation Voltage feed-forward compensation can provide additional benefits including a flatter output fold-back current limit characteristic (versus input voltage), and a reduction of voltage stress on the primary switching MOSFET at high line and output overload. Voltage feed-forward can simply be applied by adding a resistor, RVFF between VDD and CS as shown in Figure 30. The current through RVFF and RS provides a small dc offset on the CS pin which reduces the output fold back current limit. A simple way to choose RVFF is to first determine the natural circuit output fold back current at minimum line input voltage. For example, if the circuit requirements are to deliver a regulated 5 V output at 5 A from a 24 V dc adapter, then low line input could be as low as 21.6 V including tolerance. RVFF must be set large enough to allow the required current to be delivered prior to output voltage fold back. Natural circuit output fold back current and primary MOSFET voltage stress should also be characterized at high line in order to assess the improvement provided by the addition of RVFF. For a given SRT setpoint, the addition of RVFF reduces the output current at which the VFO to PWM (and PWM to VFO) transition occurs. This requires that the designer increase VSRT to account for the reduction due to RVFF. Estimating Bias Supply Requirements and Cvc The bias supply (VC) power requirements determine CVC sizing and hiccup frequency during a fault. The first step is to determine the power and current requirements of the power supply control circuitry, then select CVC. The following example assumes that control current draw is constant with voltage with no loading by the feedback and T2P optocouplers to simplify the process: 1. Let VQG be the gate voltage swing that the MOSFET QG is rated to (often 10 V). ae V o PGATE = VC | SW c QGATE C / c VQG /o e (6) 32 Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: TPS23751 TPS23752 TPS23751 TPS23752 www.ti.com SLVSB97B - JULY 2012 - REVISED JULY 2013 Compute gate drive power if VC is 12 V and QGATE is 17 nC 12 PGATE = 12 V 250kHz 17nC = 61.2mW 10 (7) This equation illustrates why MOSFET QG should be an important consideration in selecting the switching MOSFETs. 2. Estimate the required bias current at some intermediate voltage during the CVC discharge. For the TPS23751 and TPS23752, 12 V provides a reasonable estimate. Add the operating bias current to the gate drive current. P 61.2mW IDRIVE = GATE = = 5.1mA VC 12 V ITOTAL = IDRIVE + IVC _ OP = 5.1mA + 1.8mA = 6.9mA (8) 3. Compute the required CVC based on startup within the typical softstart delay of 3.01 ms. T I 3.01ms 6.9mA CVC1 + CVC2 = SSD TOTAL = = 6.49F VCUVH 3.2 V (9) 4. Choose a 10 F electrolytic and 0.47 F ceramic capacitor each rated for 16 V (minimum). Compute the initial time to start the converter when operating from PoE. Using a typical bootstrap current of 1.5 mA, compute the time to startup. TST = (CVC1 + CVC2 ) VCUV IVC _ ST = 10.47 mF 8.9 V = 62.1ms 1.5mA (10) 5. Compute the fault duty cycle and hiccup frequency TRECHARGE = TDISCHARGE = (CVC1 + CVC2 ) VCUVH (10 mF + 0.47 mF 3.2 V ) = IVC _ ST (CVC1 + CVC2 ) VCUVH ITOTAL = 1.5mA (11) (10 mF + 0.47 mF ) 3.2 V 6.9mA = 22.3ms = 4.9ms (12) TDISCHARGE 4.9ms Duty Cycle : D = = = 18.0% TDISCHARGE + TRECHARGE 4.9ms + 22.3ms (13) 1 1 = = 37Hz Hiccup Frequency : F = TDISCHARGE + TRECHARGE 4.9ms + 22.3 ms (14) Switching Transformer Considerations and RVC Care in design of the transformer and VC bias circuit is required to obtain hiccup overload protection. Leadingedge voltage overshoot on the bias winding may cause VC to peak-charge, preventing the expected tracking with output voltage. Some method of controlling overshoot is usually required. The method may be as simple as a series resistor, or an R-C filter in front of DVC1. Good transformer bias-to-output-winding coupling results in reduced overshoot and better voltage tracking. RVC VC DVC1 CVC T1 Bias WInding ARTN Figure 31. VC Pin Interface RVC as shown in Figure 31 helps to reduce peak charging from the bias winding. Reduced peak charging becomes especially important when tuning hiccup mode operation during output overload. Typical values for RVC are between 10 and 100 . Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: TPS23751 TPS23752 Submit Documentation Feedback 33 TPS23751 TPS23752 SLVSB97B - JULY 2012 - REVISED JULY 2013 www.ti.com T2P Pin Interface The T2P pin is an active-low, open-drain output which indicates that a high power source is available. An optocoupler can interface the T2P pin to circuitry on the secondary side of the converter. A high-gain optocoupler and a high-impedance (for example, CMOS) receiver are recommended. Design of the T2P optocoupler interface can be accomplished as follows: VOUT RT2P IT2P-OUT IT2P VC RT2P-OUT VT2P-OUT VT2P Low Indicates Type 2 T2P From TPS23751/2 Figure 32. T2P Interface 1. As shown in Figure 32, let VC = 12 V, VOUT = 5 V, RT2P-OUT = 10 k, VT2P = 260 mV, VT2P-OUT = 400 mV. V - VT2P -OUT 5 - 0.4 IT2P -OUT = OUT = = 0.46 mA RT2P -OUT 10000 (15) 2. The optocoupler current transfer ratio, CTR, is not needed to determine RT2P. A device with a minimum CTR of 100% at 1 mA LED bias current, IT2P, is selected. Note that in practice, CTR varies with temperature, LED bias current, and aging. These variations may require some iteration using the CTR-versus- IDIODE curve on the optocoupler data sheet. a. The approximate forward voltage of the optocoupler diode, VFWLED , is 1.1 V from the data sheet. IT2P-MIN = IT2P-OUT 0.46mA = = 0.46mA, Select IT2P = 1mA CTR 1.00 b. RT2P = VC - VT2P - VFWLED 12 V - 0.26 V - 1.1V = 10.6kW = 1mA IT2P c. Select a 10.7 kW resistor. (16) Softstart Converters require a softstart on the voltage error amplifier to prevent output overshoot on startup. Figure 33 shows a common implementation of a secondary-side softstart that works with the typical TL431 error amplifier. The softstart components consist of DSS, RSS, and CSS. They serve to control the output rate-of-rise by pulling VCTL down as CSS charges through ROB, the optocoupler, and DSS. This has the added advantage that the TL431 output and CIZ are preset to the proper value as the output voltage reaches the regulated value, preventing voltage overshoot due to the error amplifier recovery. The secondary-side error amplifier does not become active until there is sufficient voltage on the secondary. The TPS23751 and TPS23752 provide a primary-side softstart which persists long enough (approximately 3ms) for secondary side voltage-loop softstart to take over. The primary-side current-loop softstart controls the switching MOSFET peak current by applying a slowly rising ramp voltage to a second PWM control input. The PWM is controlled by the lower of the softstart ramp or the CTLderived current demand. The actual output voltage rise time is usually much shorter than the internal softstart period. Initially the internal softstart ramp limits the maximum current demand as a function of time. The current limit, secondary-side softstart, or output regulation assume control of the PWM before the internal softstart period is over. 34 Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: TPS23751 TPS23752 TPS23751 TPS23752 www.ti.com SLVSB97B - JULY 2012 - REVISED JULY 2013 From Regulated Output Voltage ROB RSS RFBU CIZ DSS CSS RFBL TLV431 Figure 33. Error Amplifier Soft Start Special Switching MOSFET Considerations Special care must be used in selecting the converter switching MOSFET. The TPS23751 and TPS23752 minimum switching MOSFET VGATE is approximately 5.5 V, which is due to the VC lower threshold. This condition occurs during an output overload, or towards the end of a (failed) bootstrap startup. The MOSFET must be able to carry the anticipated peak fault current at this gate voltage. Thermal Considerations and OTSD Sources of nearby local PCB heating should be considered during the thermal design. Typical calculations assume that the TPS23751 and TPS23752 are the only heat sources contributing to the PCB temperature rise. It is possible for a normally operating TPS23751 or TPS23752 device to experience an OTSD event if it is excessively heated by a nearby device. ESD ESD requirements for a unit that incorporates the TPS23751 or TPS23752 have a much broader scope and operational implications than are used in TI testing. Unit-level requirements should not be confused with reference design testing that only validates the ruggedness of the TPS23751 and TPS23752. Layout Printed circuit board layout recommendations are provided in the evaluation module (EVM) documentation available for the devices. Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: TPS23751 TPS23752 Submit Documentation Feedback 35 TPS23751 TPS23752 SLVSB97B - JULY 2012 - REVISED JULY 2013 www.ti.com REVISION HISTORY Changes from Original (July 2012) to Revision A * Page Changed from PRODUCT PREVIEW to PRODUCTION DATA ........................................................................................... 1 Changes from Revision A (August 2012) to Revision B Page * Added "THERMAL SHUTDOWN" to the CONTROLLER SECTION .................................................................................... 5 * Added text to the VC Pin Description: "The Sleep Mode output voltage is high enough to drive..." ................................... 13 * Added text to the Sleep Mode Operation (TPS23752 only) " For more information regarding ..." ..................................... 24 36 Submit Documentation Feedback Copyright (c) 2012-2013, Texas Instruments Incorporated Product Folder Links: TPS23751 TPS23752 PACKAGE OPTION ADDENDUM www.ti.com 24-Jun-2013 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish (2) MSL Peak Temp Op Temp (C) Device Marking (3) (4/5) TPS23751PWP ACTIVE HTSSOP PWP 16 90 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 23751 TPS23751PWPR ACTIVE HTSSOP PWP 16 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 23751 TPS23752PWP ACTIVE HTSSOP PWP 20 70 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS23752 TPS23752PWPR ACTIVE HTSSOP PWP 20 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS23752 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 24-Jun-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. 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Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 26-Nov-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device TPS23751PWPR Package Package Pins Type Drawing SPQ HTSSOP 2000 PWP 16 Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 330.0 12.4 Pack Materials-Page 1 6.9 B0 (mm) K0 (mm) P1 (mm) 5.6 1.6 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 26-Nov-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS23751PWPR HTSSOP PWP 16 2000 367.0 367.0 35.0 Pack Materials-Page 2 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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