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The Leader in High Temperature
Semiconductor Solutions
CHT-RHEA
DATASHEET
Version: 2.4
12-Nov-13
(Last Modification Date)
General Description
The CHT-RHEA is a high-temperature, high
reliability integrated circuit that implements
a dual-channel full duplex isolated data
transceiver. It can be used in any applica-
tion where there is a need to galvanically
isolate a digital data line. The galvanic iso-
lation is achieved by means of an external
pulse transformer for each digital signal.
The CHT-RHEA integrates in a single
package 2 transceivers (2 transmit and 2
receive channels). A complete 4 lines data
transmission (2 full duplex channels) re-
quires 2 instances of CHT-RHEA, one be-
ing connected to the primary side of the
transformers and one to the secondary
side.
Each transmit channel (Tx) implements a
modulation block using a circuit’s built-in
clock generator, which frequency can be
programmed with one among 7 different
values inside the range [5.9-15.3 Mhz].
Each receive channel (Rx) demodulates the
signal coming from the transformer. The
data transmission rate is up to 2 Mbit/s.
During power-up of the circuit, the output
signals can be forced to the 0 state through
the control input pin ENABLE.
CHT-RHEA offers state-of-the-art digital
signal isolation with substantial advantages
over opto-couplers such as lower transmis-
sion delay, high reliability, lower power
consumption, high immunity to dV/dt and
operation in extreme temperature condi-
tions.
The solution can be used anywhere there is
a need to isolate control lines or status/
fault reporting lines in high voltage systems
or to communicate data in sensing sys-
tems.
The complete solution is optimized to mini-
mize the size of the transformer, the num-
ber of external components, the transmis-
sion delay (<100ns) and to maximize the
noise margin, even in harsh dV/dt condi-
tions (50kV/µs).
Features
Operating junction temperature:
from -55°C to +225°C
2 transmit (Tx) and 2 receive (Rx)
channels
Data rate up to 2 Mbits/sec per chan-
nel
Transmission delay: max 100 ns
Jitter (RMS cycle-2-cycle) : max 21 ns
Power supply: 5V
Low power consumption: 50 mW per
channel (1 MHz NRZ input signal)
Hysteresis on digital input for noise
immunity
Isolation: 10 MΩ @2500V
High common mode transient immuni-
ty: 50KV/µS
ENABLE control signal on both TX and
RX functions
On-Off Keying modulation
Programmable modulation frequency
(to manage EMC requirements of spe-
cific applications)
Modulation polarity change by configu-
ration
Validated at 225°C for 10000 hours
(and still on-going)
Package: CSOIC28
Applications
Isolated gate drive for IGBT, MOSFET,
JFET and SiC Transistors
Isolated sensor interfaces
Galvanic isolation of A-D converters
Galvanic isolation of standard RS-232 /
RS-422 / RS-485 / I2C transmission
links
Industrial field bus isolation
Industrial power inverters
Motor drives and battery management
in EV / HEV
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Functional Block Diagram
TXAP
VSS
CHT-RHEA
TXAN
OSCILLATOR
DINA
TX Channel A
ENABLETX
TX Channel B TXBP
TXBN
VCC
RX Channel B RXBP
RXBN
RX Channel A RXAP
RXAN
DINB
DOUTB
DOUTA
RXFB
RXFA
SETMODTXA
TXAP
VSS CHT-RHEA
TXAN
OSCILLATOR
DINA
TX Channel A
ENABLETX
TX Channel B
TXBP
TXBN
VCC
RX Channel B
RXBP
RXBN
RX Channel A
RXAP
RXAN
DINB
DOUTB
DOUTA
RXFB
RXFA
SETMODTXA
RTXAN
RX
DEMOD
+
CONTROL
LOGIC
RFextA
VSS
TX
MODULATOR
+
CONTROL
LOGIC
TXAP
Driver
TXAN
Driver
TXTRIM2
TXTRIM1
TXTRIM0
SETMODTXB
TRIM2
TRIM1
TRIM0
SETMODTXB
ENABLERX
ENABLERX
SETMODRXB
SETMODRXA
SETMODRXB
SETMODRXA
RTXAP
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Package configuration and Pin Description
SOIC28
26
25
24
23
22
21
8
1
2
3
4
5
6
7
28
27
TXTRIM1
DINA
TXAP
TXAN
ENABLETX
SETMODTXA
DINB
SETMODRXA
TXBP
TXBN
TXTRIM0
SETMODRXB
SETMODTXB
VSS
TXTRIM2
VCC
14
9
10
11
12
13
DOUTB
RXFB
RXAN
DOUTA
RXAP
RXFA
18
17
16
15
20
19
NC
VCC
ENABLERX
NC
RXBN
RXBP
Pin #
Pin Name
Pin type
Pin Description
1
TXAP
Output
Positive differential output of TX channel A; to be connected to the prima-
ry of the transformer.
2
TXAN
Output
Negative differential output of TX channel A; to be connected to the pri-
mary of the transformer.
3
ENABLETX
Input
Controls the activation of the 2 TX channels; while at logical zero, both
TX channels are disabled and TXAP/TXAN, TXBP/TXBN are forced to
VSS level
4
VCC
Power supply
Positive power supply
5
DINA
Input
Schmitt trigger input of TX channel A
6
DINB
Input
Schmitt trigger input of TX channel B
7
SETMODTXA
Input
Controls the “polarity” of the modulation of TX channel A; cfr TX channel
true table for more information
8
SETMODRXA
Input
Controls the “polarity” of the RX channel A demodulation
9
RXFB
Input/
Output
Connected to the internal demodulation node of RX channel B; Re-
sistance RFextB to be connected between this node and VSS
10
RXFA
Input/
Output
Connected to the internal demodulation node of RX channel A; Re-
sistance RfextA to be connected between this node and VSS
11
DOUTB
Output
Output of RX channel B
12
DOUTA
Output
Output of RX channel A
13
RXAN
Input
Negative differential input of RX channel A; to be connected to the sec-
ondary of the transformer.
14
RXAP
Input
Positive differential input of RX channel A; to be connected to the sec-
ondary of the transformer.
15
RXBP
Input
Positive differential input of RX channel B; to be connected to the sec-
ondary of the transformer.
16
RXBN
Input
Negative differential input of RX channel B; to be connected to the sec-
ondary of the transformer.
17
NC
Input
Not connected
18
NC
Input
Not connected
19
ENABLERX
Input
Controls the output of the 2 RX channels; while at logical zero, both RX
channel outputs (DOUTA and DOUTB) are forced to VSS level
20
VCC
Input
Positive power supply
21
VSS
Power supply
Negative power supply
22
SETMODRXB
Input
Controls the “polarity” of the RX channel B demodulation
23
SETMODTXB
Input
Controls the “polarity” of the modulation of TX channel B; cfr TX channel
true table for more information
24
TXTRIM2
Input
Control bit of the internal oscillator clock divider
25
TXTRIM1
Input
Control bit of the internal oscillator clock divider
26
TXTRIM0
Input
Control bit of the internal oscillator clock divider
27
TXBN
Output
Negative differential output of TX channel B; to be connected to the pri-
mary of the transformer.
28
TXBP
Output
Positive differential output of TX channel B; to be connected to the prima-
ry of the transformer.
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CHT-RHEA: Absolute Maximum Ratings
These ratings are considered individually (not in combination). If not specified, voltages are
related to VSS.
Parameter
Min.
Max.
Units
(VCC-VSS)
-0.5
5.5
V
Junction Temperature
225
°C
ESD Rating (Human Body Model) (expected)
2
kV
Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating
and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is
not implied. Frequent or extended exposure to absolute maximum rating conditions or above may affect device reliability.
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Electrical Characteristics
Unless otherwise stated: Tj=25°C. Bold underlined values indicate values
over the whole temperature range (-55°C < Tj < +225°C).
Parameter
Condition
Min
Typ
Max
Units
Supply voltage (VCC)
4.5
5.5
V
Supply current (1 TX + RX
path)
DINx = all ‘0’ (duty cycle = 0%);
CDOUT = 50 pF;
TXTRIM[2..0] = ‘000
SETMODxxx = ‘0’’
1.28
mA
DINx = all ‘1’ (duty cycle = 100%) ;
CDOUT = 50 pF;
TXTRIM[2..0] = ‘000’
SETMODxxx = ‘0’
18
mA
DINx = 1 MHz NRZ signal (duty cycle
= 50%);
CDOUT = 50 pF;
TXTRIM[2..0] = ‘000’
SETMODxxx = ‘0’
10
mA
Supply quiescent current
ENABLETX=0; ENABLERX=0
135
230
µA
Maximum data rate
2
Mbps
Modulation frequency
Using TXTRIM[2-0] control signals
Discrete steps (cfr next section)
5.9
15.3
MHz
Modulation frequency varia-
tion
Includes process/temperature/power
supply variations
-35
+40
%
Modulation frequency duty
cycle
Includes process/temperature/power
supply variations
48.5
51.5
%
Propagation delay
TXTRIM[2..0]= ‘0xx’
100
ns
Jitter (RMS cycle-2-cycle)
TXTRIM[2..0]= ‘0xx’
21
ns
Start-up time
When ENABLE goes to 1
100
ns
Isolation
At 2500V
10
M
Common mode transient
immunity
50
KV/µS
TX Channel
High state output resistance
On each TX output
9
Low state output resistance
On each TX output
6.7
Propagation delay
Input rising (DINA->TXAP/N)
RTXAP+RTXAN =50Ohms
20
ns
Input falling (DINA->TXAP/N)
RTXAP+RTXAN =50Ohms
20
ns
Minimum HIGH voltage
level for digital inputs
Applies to:DINA, DINB, ENABLEx,
SETMODx, TXTRIMx
3.84
V
Maximum LOW voltage
level for digital inputs
Applies to:DINA, DINB, ENABLEx,
SETMODx, TXTRIMx
1.1
V
Hysteresis
1.68
2.07
2.39
V
RX Channel
External resistor RFEXTx
1100
Ohms
Minimum HIGH level output
voltage VOH
IOH < 8mA (source); applies to
DOUTA & DOUTB
4.4
V
Maximum LOW level output
voltage VOL
Iol < 8mA (sink); applies to DOUTA &
DOUTB
0.63
V
Output Rise/Fall Time (10%
to 90%)
On 50 pF external capacitance
3
ns
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Typical Performance Characteristics
Unless otherwise stated: VCC = 5V.
Figure 1: Propagation delay (rising edge)
vs. TXTRIM[2..0] configuration bits and
temperature
Figure 2: Propagation delay (falling edge)
vs. TXTRIM[2..0] configuration bits and
temperature
Figure 3: Jitter (peak-2-peak) (rising edge)
vs. TXTRIM[2..0] configuration bits and
temperature
Figure 4: Jitter (peak-2-peak) (falling
edge) vs. TXTRIM[2..0] configuration bits
and temperature
Figure 5 : TX Oscillator Frequency vs.
TXTRIM[2..0] configuration bits and tem-
perature
Figure 6 : Consumption vs. TXTRIM[2..0]
configuration bits and temperature (all
channels active, Input= 1MHz NRZ, DOUT
load = 50 pF, SETMODTX/RX = ‘0’)
70.00
75.00
80.00
85.00
90.00
95.00
000
001
010
011
100
101
110
111
Propagation delay (rising edge) (ns)
TXTRIM[2..0]
-55°C
25°C
125°C
175°C
70.00
75.00
80.00
85.00
90.00
95.00
100.00
000
001
010
011
100
101
110
111
Propagation delay (falling edge) (ns)
TXTRIM[2..0]
-55°C
25°C
125°C
175°C
0.00
5.00
10.00
15.00
20.00
25.00
000
001
010
011
100
101
110
111
Jitter (peak-2-peak) (rising edge) (ns)
TXTRIM[2..0]
-55°C
25°C
125°C
175°C
0.00
5.00
10.00
15.00
20.00
25.00
000
001
010
011
100
101
110
111
Jitter (peak-2-peak) (falling edge) (ns)
TXTRIM[2..0]
-55°C
25°C
125°C
175°C
0
2
4
6
8
10
12
14
16
18
000
001
010
011
100
101
110
111
TX Oscillator Frequency [MHz]
TXTRIM[2..0]
-55°C
25°C
125°C
175°C
225°C
0
5
10
15
20
25
000
001
010
011
100
101
110
111
Current Consumption [mA]
TXTRIM[2..0]
-55°C
25°C
125°C
175°C
225°C
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General description
Transmit Block functionalities
The Transmit channel uses an internally
generated clock to modulate the input sig-
nal and to generate 2 complementary out-
puts.
The 2 outputs drive the primary side of the
pulse transformer in a differential manner.
Care has been taken in the component
design to achieve 50% duty cycle on the
TX outputs and so to avoid creating DC
current inside the transformer.
For proper operation, RTXAN and RTXAP
should be set to 5Ω.
The TX channel modulation clock frequen-
cy can be selected (7 discrete values) in
the range [5.9Mhz-15.3Mhz]. Table below
provides the modulation frequency in func-
tion of the 3 control signals (TXTRIM[2..0])
at 25°C.
TXTRIM [2..0]
Typ. Clock freq (MHz)
000
15.3
001
13.8
010
11.3
011
10.2
100
8.21
101
6.86
110
5.91
111
forbidden
This function can be used to manage po-
tential electromagnetic compatibility issues
at system level by moving the modulation
clock frequency outside of system critical
frequency bands.
ENABLETX signal offers the capability to
tie down the 2 outputs of both channels.
This signal is active high. In a typical ap-
plication, this signal could be connected to
the system power-on reset to ensure that
no spurious transmission is taking place till
system power-up is completed.
Finally, with SETMODTXA/B signal, one
can invert the polarity of the Transmit
Channel. Combined with the equivalent
function on the Receive Block, the polarity
of the modulation can be inverted while
maintaining a non-inverting polarity end-to-
end. This feature can be used to optimize
the power dissipation of the isolated data
transmission function.
The table below provides the complete
logical truth table of the TX block.
CLK
DINx
ENABLE
TX
SETMOD
TXx
TXAP
TXAN
1
1
1
0
1
0
0
1
1
0
0
1
1
0
1
0
0
0
0
0
1
0
0
0
1
X
0
0
0
0
0
X
0
0
0
0
1
1
1
1
0
0
0
1
1
1
0
0
1
0
1
1
1
0
0
0
1
1
0
1
1
X
0
1
0
0
0
X
0
1
0
0
Receive Block functionalities
The Receive Block demodulates the dif-
ferential signal sent through the pulse
transformer by the Transmit Block.
The 2 differential inputs of each Receive
Block are connected to the secondary of
the transformer. RFextA/B resistance con-
trols the demodulation function.
ENABLERX signal offers the capability to
tie down the RX channel output. This sig-
nal is active high. In a typical application,
this signal could be connected to the sys-
tem power-on reset to ensure that no spu-
rious transmission is taking place till sys-
tem power-up is completed.
Finally, with SETMODRXA/B signal, one
can invert the polarity of the Receive
Channel. Combined with the equivalent
function on the Transmit Block, the polarity
of the modulation can be inverted while
maintaining a non-inverting polarity end-to-
end.
This feature can be used to optimize the
power dissipation of the isolated data
transmission function.
The table below provides the complete
logical truth table of the RX block.
RX demodu-
lated signal
ENABLE
RX
SETMOD
RXx
DOUTx
X
0
X
0
1
1
0
1
0
1
0
0
1
1
1
0
0
1
1
1
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Power dissipation
The supply current of RHEA is a function
of the supply voltage, the input data rate,
the input data “duty cycle” (the average
percentage of “1” in the input data stream),
the settings SETMODTX/SETMODRX, the
TX oscillator frequency and the load on
DOUT.
The graph below provides supply current
information for a complete TX+RX channel
in function of TX oscillator frequency and
input data “duty cycle” (0% = all “0” signal ,
100% = all “1” signal, 50% = standard NRZ
signal, Supply Voltage= 5V, DOUT load =
50 pF, SETMODTX/RX = ‘0’).
Influence of the input data rate can be
considered as marginal compared to the
other parameters.
Transformer
The transformer design has to cope with
following constraints:
- Minimize parasitic capacitance
(Cp) between Primary and Sec-
ondary; ideally Cp should be lower
than 0.5 pF
- Respect isolation requirements
- Minimize core size
- Maximum current on primary side
of 20 mA (CHT-RHEA drive capa-
bility)
- Primary driver power supply: 5V
- Maximum switching frequency: 20
MHz
- Secondary to primary ratio of
about 1.1 (ideally 1 but needs to
be slightly higher to compensate
transformer losses)
The selected transformer has an equiva-
lent electrical model as shown in figure
below. The winding ratio (P/S) is 13/15.
0
2
4
6
8
10
12
14
16
18
20
0.00% 10.00% 20.00% 30 .00% 40.00% 50.00% 6 0.00% 70.00 % 80.00% 90.00 % 10 0.00%
Current Consumption [mA]
Duty Cycle
15MHz
12MHz
6MHz
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Package Drawing
4.70
17.90
9.90
6.75
7.45
1.27 0.42
0.42
7.45
0.20
4.70
0.55
2.15
Min 8.50 / Max 9.00
0.5-1.25
Min 10.00 / Max 11.00
CSOIC 28 Drawing (mm +/- 10%)
Ordering Information
Ordering Reference
Package
Temperature Range
Marking
CHT-TIT4750G-CSOIC28-T
CSOIC28
-55°C to +225°C
CHT-TIT4750G
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Contact & Ordering
CISSOID S.A.
Headquarters and
contact EMEA:
CISSOID S.A. – Rue Francqui, 3 – 1435 Mont Saint Guibert - Belgium
T : +32 10 48 92 10 – F : +32 10 88 98 75
Email : sales@cissoid.com
Sales
Representatives:
Visit our website: http://www.cissoid.com
Disclaimer
Neither CISSOID, nor any of its directors, employees or affiliates make any representations or extend any warranties
of any kind, either express or implied, including but not limited to warranties of merchantability, fitness for a particular
purpose, and the absence of latent or other defects, whether or not discoverable. In no event shall CISSOID, its di-
rectors, employees and affiliates be liable for direct, indirect, special, incidental or consequential damages of any kind
arising out of the use of its circuits and their documentation, even if they have been advised of the possibility of such
a damage. The circuits are provided “as is”. CISSOID has no obligation to provide maintenance, support, updates, or
modifications.