ASM1232LPNF - ON Semiconductor L.L.C.

August, 2011 − Rev. 3

1Publication Order Number:

ASM1232LP/D

ASM1232LP, ASM1232LPS

5 V mP Power Supply

Monitor and Reset Circuit

Description

The ASM1232LP/LPS is a fully integrated microprocessor

Supervisor. It can halt and restart a “hung−up” microprocessor, restart

a microprocessor after a power failure. It has a watchdog timer and

external reset override.

A precision temperature−compensated reference and comparator

circuits monitor the 5 V, VCC input voltage status. During power−up or

when the VCC power supply falls outside selectable tolerance limits,

both RESET and RESET become active. When VCC rises above the

threshold voltage, the reset signals remain active for an additional

250 ms minimum, allowing the power supply and system

microprocessor to stabilize. The trip point tolerance signal, TOL,

selects the trip level tolerance to be either 5% or 10%.

Each device has both a push−pull, active HIGH reset output and an

open drain active LOW reset output. A debounced manual reset input,

PBRST, activates the reset outputs for a minimum period of 250 ms.

There is a watchdog timer to stop and restart a microprocessor that is

“hung−up”. The watchdog timeouts periods are selectable: 150 ms,

610 ms and 1200 ms. If the ST input is not strobed LOW before the

time−out period expires, a reset is generated.

Devices are available in 8−pin DIP, 16−pin SO and compact 8−pin

MicroSO packages.

Features

•5 V Supply Monitor

•Selectable Watchdog Period

•Debounce Manual Push−button Reset Input

•Precision Temperature−compensated Voltage Reference and

Comparator

•Power−up, Power−down and Brown Out Detection

•250 ms Minimum Reset Time

•Active LOW Open Drain Reset Output and Active HIGH Push−pull

Output

•Selectable Trip Point Tolerance: 5% or 10%

•Low−cost Surface Mount Packages: 8−pin/16−pin SO, 8−pin DIP and

8−pin Micro SO Packages

•Wide Operating Temperature −40°C to +85°C (N Suffixed Devices)

Applications

•Microprocessor Systems

•Computers

•Controllers

•Portable Equipment

•Intelligent Instruments

•Automotive Systems

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PIN CONFIGURATIONS

See detailed ordering and shipping information in the package

dimensions section on page 12 of this data sheet.

ORDERING INFORMATION

PDIP−8

P SUFFIX

CASE 646AA

SOIC−8

S SUFFIX

CASE 751BD

PBRST

TOL

GND

VCC

RESET

ASM1232LP

ASM1232LPS−2

ASM1232LPU

DIP/SO/MicroSO

(Top View)

MICRO−8

U SUFFIX

CASE 846AA

(Top View)

SOIC−16

S SUFFIX

CASE 751BG

ASM1232LPS

VCC

RESET

PBRST

TOL

GND

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Figure 1. Typical Operating Circuit

Figure 2. Block Diagram

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Table 1. PIN DESCRIPTION

Pin #

8−Pin Package

Pin #

16−Pin Package

Name Function

1 2 PBRST Debounced manual pushbutton RESET input.

2 4 TDWatchdog time delay selection. (tTD = 150 ms for TD = GND, tTD = 610 ms

for TD = Open, and tTD = 1200 ms for TD = VCC).

3 6 TOL Selects 5% (TOL connected to GND) or 10% (TOL connected to VCC) trip

point tolerance.

4 8 GND Ground.

5 9 RESET Active HIGH reset output. RESET is active:

1. If VCC falls below the reset voltage trip point.

2. If PBRST is LOW.

3. If ST is not strobed LOW before the timeout period set by TD expires.

4. During power−up.

611 RESET Active LOW reset output. (See RESET).

7 13 ST Strobe input.

8 15 VCC 5 V power.

1,3,5,7,10,12,14,16 NC No internal connection.

Table 2. ABSOLUTE MAXIMUM RATINGS

Parameter Min Max Unit

Voltage on VCC (Note 1) −0.5 7 V

Voltage on ST, TD (Note 1) −0.5 VCC + 0.5 V

Voltage on PBRST, RESET, RESET (Note 1) −0.5 VCC + 0.5 V

Operating Temperature Range (N suffixed devices) −40 +85 °C

Operating Temperature Range (others) 0 70 °C

Soldering Temperature (for 10 sec) +260 °C

Storage Temperature −55 +125 °C

ESD rating HBM 2 KV

MM 200 V

Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the

Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect

device reliability.

1. Voltages are measured with respect to ground

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Table 3. DC ELECTRICAL CHARACTERISTICS (Unless otherwise stated, 4.5 V ≤ VCC ≤ 5.5 V and over the operating

temperature range of 0°C to 70°C (−40°C to +85°C. for N devices). All Voltages are referenced to ground.)

Parameter Symbol Conditions Min Typ Max Unit

Supply Voltage VCC 4.5 5.5 V

ST and PBRST Input High Level VIH 2 VCC + 0.3 V

ST and PBRST Input Low Level VIL −0.3 0.8 V

VCC Trip Point (TOL = GND) VCCTP 4.50 4.62 4.74 V

VCC Trip Point (TOL = VCC) VCCTP 4.25 4.37 4.49 V

Watchdog Timeout Period tTD TD = GND 62.5 150 250 ms

Watchdog Timeout Period tTD TD = VCC 500 1200 2000 ms

Watchdog Timeout Period tTD TD Floating 250 610 1000 ms

Output Voltage VOH I = −500 mA

(Note 4)

VCC − 0.5 VCC − 0.1 V

Output Current IOH Output = 2.4 V

(Note 3)

−8−10 mA

Output Current IOL Output = 0.4 V 10 mA

Input Leakage IIL (Note 2) −1.0 1.0 mA

RESET Low Level VOL (Note 4) 0.4 V

Internal Pull−up Resistor (Note 2) 40 kW

Operating Current (CMOS) ICC1 30 mA

Input Capacitance CIN 5 pF

Output Capacitance COUT 10 pF

PBRST Manual Reset

Minimum Low Time

tPB PBRST = VIL

Reset Active Time tRST 250 610 1000 ms

ST Pulse Width tST (Note 5) 20 ns

VCC Fail Detect to RESET or RESET tRPD 5 8 ms

VCC Slew Rate tF4.75 V to 4.25 V 300 ms

PBRST Stable LOW to RESET and

RESET Active

tPDLY 20 ms

VCC Detect to RESET or RESET inactive tRPU tRISE = 5 ms250 610 1000 ms

VCC Slew Rate tR4.25 V to 4.75 V 0 ns

2. PBRST is internally pulled HIGH to VCC through a nominal 40 kW resistor.

3. RESET is an open drain output.

4. RESET remains within 0.5 V of VCC on power−down until VCC falls below 2 V. RESET remains within 0.5 V of ground on power−down until

VCC falls below 2.0 V.

5. Must not exceed the minimum watchdog time−out period (tTD). The watchdog circuit cannot be disabled. To avoid a reset, ST must be strobed.

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Detailed Description

The ASM1232LP/LPS monitors the microprocessor or

micro controller power supply and generates reset signal,

both active HIGH and Active LOW, that halt processor

operation whenever the power supply voltage levels are

outside a predetermined tolerance.

RESET and RESET outputs

RESET is an active HIGH signal developed by a CMOS

push−pull output stage and is the logical opposite to RESET.

RESET is an active LOW signal. It is developed with an

open drain driver. A pull up resistor of typical value 10 kW

to 50 kW is required to connect with the output.

Trip Point Tolerance Selection

The TOL input is used to determine the level VCC can vary

below 5 V without asserting a reset. With TOL connected to

VCC, RESET and RESET become active whenever VCC

falls below 4.5 V. RESET and RESET become active when

the VCC falls below 4.75 V if TOL is connected to ground.

After VCC has risen above the trip point set by TOL,

RESET and RESET remain active for a minimum time

period of 250 ms. On power−down, once VCC falls below the

reset threshold RESET stays LOW and is guaranteed to be

0.4 V or less until VCC drops below 1.2 V. The active HIGH

reset signal is valid down to a VCC level of 1.2 V also.

Tolerance Select Tolerance

TRIP Point Voltage (V)

Min Nom Max

TOL = VCC 10% 4.25 4.37 4.49

TOL = GND 5% 4.5 4.62 4.74

Figure 3. Timing Diagram: Power Up

Figure 4. Timing Diagram: Power Down

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Application Information

Manual Reset Operation

Push−button switch input, PBRST, allows the user to

override the internal trip point detection circuits and issue

reset signals. The pushbutton input is debounced and is

pulled HIGH through an internal 40 kW resistor.

When PBRST is held LOW for the minimum time tPB,

both resets become active and remain active for a minimum

time period of 250 ms after PBRST returns HIGH.

The debounced input is guaranteed to recognize pulses

greater than 20 ms. No external pull−up resistor is required,

since PBRST is pulled HIGH by an internal 40 kW resistor.

The PBRST can be driven from a TTL or CMOS logic line

or shorted to ground with a mechanical switch.

Figure 5. Timing Diagram: Pushbutton Reset

Figure 6. Application Circuit: Pushbutton Reset

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Watchdog Timer and ST Input

A watchdog timer stops and restarts a microprocessor that

is “hung−up”. The mP must toggle the ST input within a set

period (as selectable through TD input) to verify proper

software execution. If the ST is not toggled low within the

minimum timeout period, reset signals become active. In

power−up after the supply voltage returns to an in−tolerance

condition, the reset signal remains active for 250 ms

minimum, allowing the power supply and system

microprocessor to stabilize. ST pulses as short as 20 ns can

be detected.

Figure 7. Timing Diagram: Strobe Input

Timeouts periods of approximately 150 ms, 610 ms or 1,200 ms are selected through the TD pin.

TD Voltage level

Watchdog Time−out Period (ms)

Min Nom Max

GND 62.5 150 250

Floating 250 610 1000

VCC 500 1200 2000

The watchdog timer cannot be disabled. It must be strobed with a high−to−low transition to avoid watchdog timeout and reset.

Figure 8. Application Circuit: Watchdog Timer

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PACKAGE DIMENSIONS

Micro8t/TSSOP8 3x3

CASE 846AA−01

ISSUE O

0.08 (0.003) A S

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE

BURRS. MOLD FLASH, PROTRUSIONS OR GATE BURRS SHALL NOT EXCEED

0.15 (0.006) PER SIDE.

4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION.

INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE.

5. 846A-01 OBSOLETE, NEW STANDARD 846A-02.

PIN 1 ID

8 PL

0.038 (0.0015)

−T−

SEATING

PLANE

A1 cL

*For additional information on our Pb−Free strategy and soldering

details, please download the ON Semiconductor Soldering and

Mounting Techniques Reference Manual, SOLDERRM/D.

SOLDERING FOOTPRINT*

8X 8X

6X ǒmm

inchesǓ

SCALE 8:1

1.04

0.041

0.38

0.015

5.28

0.208

4.24

0.167

3.20

0.126

0.65

0.0256

DIM

MIN NOM MAX MIN

MILLIMETERS

−− −− 1.10 −−

INCHES

A1 0.05 0.08 0.15 0.002

b0.25 0.33 0.40 0.010

c0.13 0.18 0.23 0.005

D2.90 3.00 3.10 0.114

E2.90 3.00 3.10 0.114

e0.65 BSC

L0.40 0.55 0.70 0.016

−− 0.043

0.003 0.006

0.013 0.016

0.007 0.009

0.118 0.122

0.026 BSC

0.021 0.028

NOM MAX

4.75 4.90 5.05 0.187 0.193 0.199

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PACKAGE DIMENSIONS

PDIP−8, 300 mils

CASE 646AA−01

ISSUE A

TOP VIEW

SIDE VIEW END VIEW

PIN # 1

IDENTIFICATION

Notes:

(1) All dimensions are in millimeters.

(2) Complies with JEDEC MS-001.

SYMBOL MIN NOM MAX

0.38

2.92

0.36

6.10

1.14

0.20

9.02

2.54 BSC

3.30

5.33

4.95

0.56

7.11

1.78

0.36

10.16

eB 7.87 10.92

E 7.62 8.25

2.92 3.80

3.30

0.46

6.35

1.52

0.25

9.27

7.87

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PACKAGE DIMENSIONS

SOIC 8, 150 mils

CASE 751BD−01

ISSUE O

E1 E

PIN # 1

IDENTIFICATION

TOP VIEW

SIDE VIEW END VIEW

Notes:

(1) All dimensions are in millimeters. Angles in degrees.

(2) Complies with JEDEC MS-012.

SYMBOL MIN NOM MAX

0º 8º

0.10

0.33

0.19

0.25

4.80

5.80

3.80

1.27 BSC

1.75

0.25

0.51

0.25

0.50

5.00

6.20

4.00

L0.40 1.27

1.35

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PACKAGE DIMENSIONS

SOIC−16, 150 mils

CASE 751BG−01

ISSUE O

TOP VIEW

PIN#1 IDENTIFICATION

ebA1 L

SIDE VIEW END VIEW

Notes:

(1) All dimensions are in millimeters. Angles in degrees.

(2) Complies with JEDEC MS-012.

SYMBOL MIN NOM MAX

0º 8º

0.10

0.33

0.19

0.25

9.80

5.80

3.80

1.27 BSC

1.75

0.25

0.51

0.25

0.50

10.00

6.20

4.00

L0.40 1.27

1.35

9.90

6.00

3.90

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Table 4. ORDERING INFORMATION

Part Number (Note 6) Package

Operating

Temperature

Range

Maximum

Supply

Current (mA)

Voltage

Monitoring

Application Package Marking

TIN−LEAD DEVICES

ASM1232LP 8L PDIP 0°C to +70°C 30 5 V ASM1232LP

ASM1232LPN 8L PDIP −40°C to +85°C 30 5 V ASM1232LPN

ASM1232LPS 16L SOIC 0°C to +70°C 30 5 V ASM1232LPS

ASM1232LPS−28L SOIC 0°C to +70°C 30 5 V ASM1232LPS−2

ASM1232LPSN 16L SOIC −40°C to +85°C 30 5 V ASM1232LPSN

ASM1232LPSN−28L SOIC −40°C to +85°C 30 5 V ASM1232LPSN−2

ASM1232LPU 8L MSOP 0°C to +70°C 30 5 V ASM1232LP

ASM1232LPUN 8L MSOP −40°C to +85°C 30 5 V ASM1232LPN

LEAD FREE DEVICES

ASM1232LPF 8L PDIP 0°C to +70°C 30 5 V ASM1232LPF

ASM1232LPNF 8L PDIP −40°C to +85°C 30 5 V ASM1232LPNF

ASM1232LPS−2F 8L SOIC 0°C to +70°C 30 5 V ASM1232LPS−2F

ASM1232LPSF 16L SOIC 0°C to +70°C 30 5 V ASM1232LPSF

ASM1232LPSN−2F 8L SOIC −40°C to +85°C 30 5 V ASM1232LPSN−2F

ASM1232LPSNF 16L SOIC −40°C to +85°C 30 5 V ASM1232LPSNF

ASM1232LPUF 8L MSOP 0°C to +70°C 30 5 V ASM1232LPF

ASM1232LPUNF 8L MSOP −40°C to +85°C 30 5 V ASM1232LPNF

6. For parts to be packed in Tape and Reel, add “−T” at the end of the part number.

ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice

to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.

“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All

operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights

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ASM1232LP/D

PUBLICATION ORDERING INFORMATION

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USA/Canada

Europe, Middle East and Africa Technical Support:

Phone: 421 33 790 2910

Japan Customer Focus Center

Phone: 81−3−5773−3850

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