HCF4021 Asynchronous parallel input or synchronous serial-in/serial-out 8-stage static shift register Datasheet - production data Description PDIP-16 The HCF4021 is a monolithic integrated circuit fabricated in metal oxide semiconductor technology available in PDIP-16 and SO-16 packages. SO-16 Features Medium speed operation: 12 MHz (typ.) clock rate at VDD - VSS = 10 V Fully static operation 8 master-slave flip-flops plus output buffering and control gating Quiescent current specified up to 20 V 5 V, 10 V, and 15 V parametric ratings Input leakage current II = 100 nA (max.) at VDD = 18 V, TA = 25 C 100% tested for quiescent current ESD performance - CDM: 1 kV - HBM: 2 kV - MM: 200 V Applications This device is an 8-stage parallel or serialinput/serial-output register having common clock and parallel/serial control inputs, a single serial data input, and individual parallel "jam" inputs to each register stage. Each register stage is a Dtype, master-slave flip-flop in addition to an output from stage 8. "Q" outputs are also available from stages 6 and 7. Serial entry is synchronous with the clock but parallel entry is asynchronous. In this device, entry is controlled by the parallel/serial control input. When the parallel/serial control input is low, data are serially shifted into the 8-stage register synchronously with the positive transition of the clock line. When the parallel/serial control input is high, data are jammed into the 8-stage register via the parallel input lines and synchronous with the positive transition of the clock line. The clock input of the internal stage is "forced" when asynchronous parallel entry is made. Register expansion using multiple packages is permitted. Automotive Industrial Computer Consumer Table 1. Device summary Order code Temperature range Package HCF4021M013TR -55 C to +125 C SO-16 Packing Marking HCF4021 HCF4021YM013TR(1) -40 C to +125 C SO-16 (automotive grade)(1) Tape & reel HCF4021BEY -55 C to +125 C PDIP-16 Tube HCF4021Y HCF4021BE 1. Qualification and characterization according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC Q001 & Q002 or equivalent. September 2013 This is information on a product in full production. DocID008216 Rev 3 1/13 www.st.com Contents HCF4021 Contents 1 Pin information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.1 PDIP-16 (0.25) package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.2 SO-16 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 5 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2/13 DocID008216 Rev 3 HCF4021 1 Pin information Pin information Figure 1. Pin connections (top view) 3, 9'' 4 3, 4 3, 3, 3, 3, 4 3, 6(5,$/,1 3, &/2&. 966 3$5$//(/6(5,$/&21752/ *$06&% Table 2. Pin description Pin number Symbol Name and function 7, 6, 5, 4, 13, 14, 15, 1 PI-1 to PI-8 Parallel input 11 SERIAL IN Serial input 9 PARALLEL/SERIAL CONTROL Parallel/serial input control 10 CLOCK Clock input 2, 3, 12 Q6, Q7, Q8 Buffered outputs 8 VSS Negative supply voltage 16 VDD Positive supply voltage DocID008216 Rev 3 3/13 13 Functional description 2 HCF4021 Functional description Figure 2. Logic diagram 6HULDOLQSXW 3 3 3 3 3 3 3 3 3 ' &/ 36 &ORFN 4 3 ' &/ 4 ' &/ 36 3 4 36 3 ' &/ 4 3 ' &/ 36 4 ' &/ 36 3 4 ' &/ 36 3 4 ' &/ 36 3 4 36 3DUDOOHOVHULDOFRQWURO &/ 3 &/ ' 3 S Q 4 &/ ' 36 4 4 4 &/ i &/ 36 &/ S Q S Q &/ S Q &/ 4 &/ &/ S Q S Q &/ &/ *$06&% Table 3. Truth table Clock Serial input Parallel/serial control PI-1 PI-n Q1 (internal) Qn X(1) X(1) 1 0 0 0 0 X(1) X(1) 1 0 1 0 1 (1) X(1) 1 1 0 1 0 (1) X(1) 1 1 1 1 1 0 0 X (1) X(1) 0 Qn-1 1 0 X(1) X(1) 1 Qn-1 X(1) X(1) X(1) X(1) Q1 Qn X X 1. Don't care Figure 3. Input equivalent circuit 9'' ,1387 966 *$06&% 4/13 DocID008216 Rev 3 HCF4021 3 Electrical characteristics Electrical characteristics Absolute maximum ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltage values are referred to VSS pin voltage. Table 4. Absolute maximum ratings (AMR) Symbol Parameter Value VDD Supply voltage -0.5 to +22 VI DC input voltage -0.5 to VDD + 0.5 II DC input current 10 Power dissipation per package 200 Power dissipation per output transistor 100 Top Operating temperature -55 to +125 Tstg Storage temperature -65 to +150 PD Unit V mA mW C Table 5. Recommended operating conditions Symbol Parameter Value VDD Supply voltage 3 to 20 VI Input voltage 0 to VDD Top Operating temperature -55 to 125 DocID008216 Rev 3 Unit V C 5/13 13 Electrical characteristics HCF4021 Table 6. DC specifications(1) Test condition Value TA = 25 C Sym. Parameter VI (V) IL VOH VOL VIH VIL IOH IOL Quiescent current High-level output voltage Low-level output voltage II Input leakage current CI Input capacitance Min. Typ. Max. -40 to 85 C -55 to 125C Unit Min. Min. Max. 5 0/10 10 0/15 15 0/20 20 0/5 5 4.95 4.95 4.95 10 9.95 9.95 9.95 0/15 15 14.95 14.95 14.95 5/0 5 0/10 <1 10/0 <1 15/0 0.08 10 5 150 150 10 300 300 20 600 600 100 3000 3000 0.05 0.05 3.5 3.5 10 7 7 7 1.5/13.5 15 11 11 11 4.5/0.5 5 1.5 1.5 1.5 10 3 3 3 15 4 4 4 9/1 <1 13.5/1.5 2.5 4.6 -1.36 -3.2 -1.1 -1.1 -0.44 -1 -0.36 -0.36 10 -1.1 -2.6 -0.9 -0.9 5 <1 0/10 9.5 0/15 13.5 15 -3.0 -6.8 -2.4 -2.4 0/5 0.4 5 0.44 1 0.36 0.36 0/10 0.5 10 1.1 2.6 0.9 0.9 0/15 1.5 15 3.0 6.8 2.4 2.4 0/18 V 3.5 <1 <1 Any input 18 10-5 0.1 Any input 5 1 mA 1 7.5 1. The noise margin for both level "1" and "0" is: 1 V min. with VDD = 5 V, 2 V min. with VDD = 10 V, and 2.5 V min. with VDD = 15 V. 6/13 DocID008216 Rev 3 A 0.05 5 1/9 0/5 0.04 Max. 15 0.5/4.5 Low-level input voltage Output sink current |IO| (A) VDD(V) 0/5 High-level input voltage Output drive current VO (V) A pF HCF4021 Electrical characteristics Table 7. Dynamic electrical characteristics (Tamb = 25 C, CL = 50 pF, RL = 200 k, tr = tf = 20 ns) Value(1) Test condition Symbol VDD (V) tPLH, tPHL tTHL, tTLH fCL(2) tw Unit Parameter Propagation delay time Transition time Maximum clock input frequency Clock pulse width Min. Typ. Max. 5 160 320 10 80 160 15 60 120 5 100 200 10 50 100 15 40 80 5 3 6 10 6 12 15 8.5 17 5 180 90 10 80 40 15 50 25 ns MHz ns 5 tr , tf Clock input rise or fall time 10 15 s 15 Minimum setup time, serial input tH 200 ns (ref to CL) ts Minimum setup time, parallel inputs tH 200 ns (ref to P/S) 5 120 60 10 80 40 15 60 30 5 50 25 10 30 15 15 20 10 5 th Hold time, serial in, parallel in, parallel/serial control 10 ns 0 15 tWH trem P/S pulse width P/S removal time ref to CL) 5 160 80 10 80 40 15 50 25 5 280 140 10 140 70 15 100 50 1. The typical temperature coefficient for all VDD values is 0.3 %/C. 2. If more than one unit is cascaded, trCL should be made less than or equal to the sum of the transition time and the fixed propagation delay of the output of the driving stage of the estimated capacitive load. DocID008216 Rev 3 7/13 13 Electrical characteristics HCF4021 Figure 4. Test circuit 9'' 3XOVHJHQHUDWRU '87 966 57 &/ 5/ *$06&% 1. Legend: CL = 50 pF or equivalent (includes jig and probe capacitance), RL = 200 KRT = ZOUT of pulse generator (typically 50 ) Figure 5. Waveform 1: propagation delay times, clock pulse width (f = 1 MHz; 50 % duty cycle) QV QV 9'' &/2&. 966 WZ WZ W3/+ W3+/ 92+ 4 W7/+ 92/ W7+/ *$06&% 8/13 DocID008216 Rev 3 HCF4021 Electrical characteristics Figure 6. Waveform 2: setup and hold times (SI to CLOCK) (f = 1 MHz; 50 % duty cycle) 9'' 6, 966 WV WK 9'' &/2&. 966 *$06&% Figure 7. Waveform 3: setup and hold time (PI to P/S) (f = 1 MHz; 50 % duty cycle) 9'' 3, 966 WV WK 9'' 36 966 *$06&% Figure 8. Waveform 4: pulse width and removal time (P/S to clock) (f = 1 MHz; 50 % duty cycle) 9'' 966 36 W:+ &/2&. WUHP *$06&% DocID008216 Rev 3 9/13 13 Package information 4 HCF4021 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. 4.1 PDIP-16 (0.25) package information Figure 9. PDIP-16 (0.25) package mechanical drawing D , E / E = % H ( H ' ) *$06&% Table 8. PDIP-16 (0.25) package mechanical data Dimensions Ref Millimeters Min. a1 0.51 B 0.77 Typ. Max. Min. Typ. Max. 0.020 1.65 0.030 0.065 b 0.5 0.020 b1 0.25 0.010 D 20 0.787 E 8.5 0.335 e 2.54 0.100 e3 17.78 0.700 F 7.1 0.280 I 5.1 0.201 L Z 10/13 Inches 3.3 1.27 0.130 1.27 DocID008216 Rev 3 0.050 0.050 HCF4021 4.2 Package information SO-16 package information Figure 10. SO-16 package mechanical drawing * / F & $ D E 6 H D E H ( ' 0 ) *$06&% Table 9. SO-16 package mechanical data Dimensions Ref Millimeters Min. Typ. A a1 Inches Max. Min. Typ. 1.75 0.1 0.2 a2 Max. 0.068 0.003 0.007 1.65 0.064 b 0.35 0.46 0.013 0.018 b1 0.19 0.25 0.007 0.010 C 0.5 0.019 c1 45 45 D 9.8 10 0.385 0.393 E 5.8 6.2 0.228 0.244 e 1.27 0.050 e3 8.89 0.350 F 3.8 4.0 0.149 0.157 G 4.6 5.3 0.181 0.208 L 0.5 1.27 0.019 0.050 M 0.62 0.024 S 8 8 DocID008216 Rev 3 11/13 13 Ordering information 5 HCF4021 Ordering information Table 10. Order codes Order code Temperature range Package HCF4021M013TR -55 C to +125 C SO-16 Packing Marking HCF4021 HCF4021YM013TR (1) -40 C to +125 C SO-16 (automotive grade)(1) Tape & reel HCF4021BEY -55 C to +125 C PDIP-16 Tube HCF4021Y HCF4021BE 1. Qualification and characterization according to AEC Q100 and Q003 or equivalent, advanced screening according to AEC Q001 & Q002 or equivalent. 6 Revision history Table 11. Document revision history 12/13 Date Revision Changes Sep-2001 1 Initial release. 18-Feb-2013 2 Document template and layout updated Removed "B" from part number Updated package names (PDIP-16 and SO-16 instead of DIP-16 and SOP-16). Added Applications Added Device summary Updated symbol names in Table 7 Added Section 5: Ordering information 12-Sep-2013 3 Added ESD performance to Features Updated footnote 1 of Table 1 Updated footnote 1 of Table 10 DocID008216 Rev 3 HCF4021 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. 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