1. Introduction
This document de scr ibe s th e fu nct ion a lity an d electrical specifications of the contactless
reader/writer IC CLRC663.
2. General description
The CLRC663 is a highly integrated transceiver IC for contactless communication at
13.56 MHz.
The CLRC663 transceiver IC supports the following operating modes
Read/write mode supporting ISO/IEC 14443A/MIFARE
Read/write mode supporting ISO/IEC 14443B
Read/write mode supporting JIS X 6319-4 (comparable with FeliCa1 (see
Section 21.5 scheme)
Passive initiator mode according to ISO/IEC 18092
Read/write mode supporting ISO/IEC 15693
Read/write mode supporting ICODE EPC UID/ EPC OTP
Read/write mode supporting ISO/IEC 18000-3 mode 3/ EPC Class-1 HF
The CLRC663’s internal transmitter is able to drive a reader/writer antenna designed to
communicate with ISO/IEC 14443A/MIFARE cards and transponders without additional
active circuitry. The digital module manages the complete ISO/IEC 14443A framing and
error detection functionality (parity and CRC).
The CLRC663 supports MIFARE Classic 1K, MIFARE Classic 4K, MIFARE Ultralight,
MIFARE Ultralight C, MIFARE PLUS and MIFARE DESFire products. The CLRC663
supports MIFARE higher transfer speeds of up to 848 kbit/s in both directions.
The CLRC663 supports layer 2 and 3 of the ISO/IEC 14443B reader/writer
communication scheme except anticollision. The anticollision needs to be implemented in
the firmware of th e ho st co nt ro ller as well as in th e uppe r lay er s.
The CLRC663 is able to demodulate and decode FeliCa coded signals.The FeliCa
receiver part provides the demodulation and decoding circuitry for FeliCa coded signals.
The CLRC663 handles the FeliCa framing and error detection such as CRC. The
CLRC663 supports FeliCa higher transfer speeds of up to 424 kbit/s in both directions.
CLRC663
Contactless reader IC
Rev. 3.4 — 17 July 2012
171134 Product data sheet
COMPANY PUBLIC
1. In the following the word FeliCa is used for JIS X 6319-4
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The CLRC663 is supporting the P2P passive initiator mode in accordance with
ISO/IEC 18092.
The CLRC663 supp o rts the vicinity pr ot oco l acc or din g to ISO/I EC1 56 9 3, EPC UID an d
ISO/IEC 18000-3 mode 3/ EPC Class-1 HF.
The following host interfaces are supported:
Serial Peripheral Interface (SPI)
Serial UART (similar to RS232 with voltage levels dependent on pin voltage supply)
I2C-bus interface (two versions are implemented: I2C and I2CL)
The CLRC663 supports the connection of a secure access module (SAM). A dedicated
separate I2C interface is imple mented for a connection of the SAM. The SAM can be used
for high secure key storage and acts as a very performant crypto coprocessor. A
dedicated SAM is available for connection to the CLRC663.
3. Features and benefits
High RF output power frontend IC for transfer speed up to 848 kbit/s
Supports ISO/IEC 14443 A/MIFARE, ISO/IEC 14443 B and FeliCa
P2P passive initiator mode in accordance with ISO/IEC 18092
Supports ISO/IEC15693, ICODE EPC UID and ISO/IEC 18000-3 mode 3/ EPC
Class-1 HF
Supports MIFARE Classic encryption in read/w rite mode
Low-Power Card Detection
Compliance to “EM V con tactless pr ot oc ol sp ecif ica tio n V 2.0.1 on RF lev el can be
achieved
Antenna connection with minimum number of external components
Supported host interfaces:
SPI up to 10 Mbit/s
I2C-bus interfaces up to 400 kBd in Fast mode, up to 1000 kBd in Fast mode plus
RS232 Serial UART up to 1228.8 kBd, with voltage levels dependent on pin
voltage supply
Separate I2C-bus interface for connection of a secure access module (SAM)
FIFO buffer with size of 512 byte for highest transaction performance
Flexible and efficient power saving modes including hard power down, standby and
low-power card detection
Cost saving by integrated PLL to derive system CPU clock from 27.12 MHz RF quartz
crystal
3.3 V to 5 V powe r su pp ly
Up to 8 free programmable input/output pins
Typical operating distance in read/write mode for communication to a
ISO/IEC 14443A/MIFARE Card up to 12 cm, depending on the antenna size and
tuning
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Contactless reader IC
4. Quick reference data
[1] VDD(PVDD) must always be the same or lower voltage than VDD.
[2] Ipd is the sum of all supply currents
[3] IDD(TVDD) depends on VDD(TVDD) and the external circuitry connected to TX1 and TX2.
[4] Typical value: Assumes the usage of a complementary driver configuration and an antenna matched to 40 between pins TX1, TX2 at
13.56 MHz.
5. Ordering information
[1] Delivered in one tray, CLRC66301HN/TRAYB.
[2] Delivered in five trays CLRC66301HN/TRAYBM.
Table 1. Quick reference data
Symbol Parameter Conditions Min Typ Max Unit
VDD supply voltage 3 5 5.5 V
VDD(TVDD) TVDD supply voltage [1] 355.5V
VDD(PVDD) PVDD supply voltage 3 5 5.5 V
Ipd power-down current PDOWN pin pulled HIGH [2] - 8 40 nA
IDD supply current - 17 20 mA
IDD(TVDD) TVDD supply current [3][4] - 100 200 mA
Tamb ambient temperature 25 +25 +85 C
Tstg storage temperature no supply voltage applied 40 +25 +100 C
Table 2. Ordering information
Type number Package
Name Description Version
CLRC66301HN[1] HVQFN32 plastic thermal enhanced very thin quad flat package; no leads;
32 terminals + 1 central ground; body 5 5 0.85 mm SOT617-1
CLRC66301HN[2]
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Contactless reader IC
6. Block diagram
The analog interface handle s the modulation an d demodulation of the antenna signals for
the contactless interface.
The contactless UART manages the protocol dependency of the contactless interface
settings managed by the host.
The FIFO buffer ensures fast and convenient data transfer between host and the
contactless UART.
The register bank contains the settings for the analog and digital functionality.
7. Pinning information
Fig 1. Simplified bloc k diagram of the CLRC663
001aaj627
HOST
ANTENNA FIFO
BUFFER
ANALOG
INTERFACE CONTACTLESS
UART SERIAL UART
SPI
I
2
C-BUS
REGISTER BANK
(1) Pin 33 VSS - heatsink connection
Fig 2. Pinning configuration HVQFN32 (SOT617-1)
001aam004
CLRC663
Transparent top view
TX1
(1)
DVDD
VDD
TVDD
SIGOUT XTAL1
SIGIN XTAL2
TCK PDOWN
TMS CLKOUT
TDI SCL
TDO SDA
AVDD
AUX1
AUX2
RXP
RXN
VMID
TX2
TVSS
IRQ
IF3
IF2
IF1
IF0
IFSEL1
IFSEL0
PVDD
817
718
619
520
421
322
223
124
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
terminal 1
index area
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7.1 Pin description
[1] This pin is used for connection of a buffer capacitor. Connection of a supply voltage might damage the device.
Table 3. Pin description
Pin Symbol Type Description
1 TDO O test data output for boundary scan interface
2 TDI I test data input boundary scan interface
3 TMS I test mode select boundary scan interface
4 TCK I test clock boundary scan interface
5 SIGIN I Contactless communication interface output.
6 SIGOUT O Contactless communication interface input.
7 DVDD PWR digital power supply buffer [1]
8 VDD PWR power supply
9 AVDD PWR analog power supply buffer [1]
10 AUX1 O auxiliary outputs: Pin is used for analog test signal
11 AUX2 O auxiliary outputs: Pin is used for analog test signal
12 RXP I receiver input pin for the received RF signal.
13 RXN I receiver input pin for the received RF signal.
14 VMID PWR internal receiver reference voltage [1]
15 TX2 O transmitter 2: delivers the modulated 13.56 MHz carrier
16 TVSS PWR transmitter ground, supplies the output stage of TX1, TX2
17 TX1 O transmitter 1: delivers the modulated 13.56 MHz carrier
18 TVDD PWR transmitter voltage supply
19 XTAL1 I crystal oscillator input: Input to the inverting amplifier of the oscillator . This is pin is also the
input for an externally generated clock (fosc = 27,12 MHz)
20 XTAL2 O crystal oscillator output: output of the inverting amplifier of the oscillator
21 PDOWN I Power Down
22 CLKOUT O clock output.
23 SCL O Serial Clock line
24 SDA I/O Serial Data Line
25 PVDD PWR pad power supply
26 IFSEL0 I host interface selecti on 0
27 IFSEL1 I host interface selecti on 1
28 IF0 I/O interfac e pi n , multifunct io n pi n: Can be assigned to host interface RS232, SPI, I2C, I2C-L
29 IF1 I/O interface pin, multifunction pin: Can be assigned to host interface SPI, I2C, I2C-L
30 IF2 I/O interfac e pi n , multifunct io n pi n: Can be assigned to host interface RS232, SPI, I2C, I2C-L
31 IF3 I/O interfac e pi n , multifunct io n pi n: Can be assigned to host interface RS232, SPI, I2C, I2C-L
32 IRQ O interrupt request: output to signal an interrupt event
33 VSS PWR ground and heatsink connection
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Contactless reader IC
8. Functional description
Fig 3. Detailed block di ag ram of the CLRC663
001aam005
I2C,
LOGICAL
FIFO
512 Bytes
REGISTERS
STATEMACHINES
EEPROM
8 kByte
SPI
SAM interface
VOLTAGE
REGULATOR
3/5 V =>
1.8 V
DVDD
POR
ADC PLLLPO
RX OSCTX
VOLTAGE
REGULATOR
3/5 V =>
1.8 V
AVDD
RNG
ANALOGUE FRONT-END
BOUNDARY
SCAN
IF0
IFSEL0
IFSEL1
IF1
IF2
IF3
TCK
TDI
TMS
TDO
RESET
LOGIC PDOWN
I2C
RS232
SPI
host interfaces
INTERRUPT
CONTROLLER
IRQ SIGIN
TIMER0..3
CRC
TIMER4
(WAKE-UP
TIMER)
SIGPRO
TX
CODEC
RX
DECOD
CL-
COPRO
SIGIN/
SIGOUT
CONTROL
SIGOUT VMID RXN
RXP
TX1
TX2
XTAL1
XTAL2
SDA
SCL
VDD
VSS
PVDD
TVDD
TVSS
AUX1
AUX2
AVDD
DVDD
CLKOUT
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8.1 Interrupt controller
The interrupt controller handles the enabling/disabling of interrupt requests. All of the
interrupts can be configured by firmware. Additionally, the firmware has possibilities to
trigger interrupts or clear pending interrupt requests. Two 8-bit interrupt registers IRQ0
and IRQ1 are implemented, accompanied by tw o 8- bit inter ru p t enab le re gisters IRQ0En
and IRQ1En. A dedicated functionality of bit 7 to set and clear bits 0 to 6 in this interrupt
controller registers is implemented.
The CLRC663 indicates certain events by setting bit IRQ in the register Status1Reg and
additionally, if activated, by pin IRQ. The signal on pin IRQ may be used to interrupt the
host using its interrupt handling capabilities. This allows the implementation of efficient
host software.
The following table shows the available interrupt bits, the corresponding source and the
condition for its activation. The interrupt bit TimernIrq in register IRQ1 indicates an
interrupt set by the timer unit. The setting is done if the timer underflows.
The TxIrq bit in register IRq0 indicates that the transmission is finished. If the state
changes from sending data to transmitting the end of the frame pattern, the transmitter
unit sets the interrupt bit automatically.
The bit RxIrq in register IRQ0 indicates an interrupt when the end of the received data is
detected.
The bit IdleIrq in register IRQ0 is set if a command finishes and the content of the
command register changes to idle.
The waterlevel defines both - minimum and maximum warning levels - counting from top
and from bottom of the FIFO by a single value.
The bit HiAlertIrq in register IRQ0 is set to logic 1 if the HiAlert bit is set to logic 1, that
means the FIFO data number has reached the top level as configured by the bit
WaterLevel.
The bit LoAlertIrq in register IRQ0 is set to logic 1 if the LoAlert bit is set to logic 1, that
means the FIFO data number has reached the bottom level as configured by the bit
WaterLevel.
The bit ErrIrq in register IRQ0 indicate s an error detected by the contactless UART during
receive. This is indicated by any bit set to logic 1 in regis te r Erro r.
The bit LPCDIrq in register IRQ0 indicates a card detected.
The bit RxSOFIrq in register IRQ0 indicates a detection of a SOF or a subcarrier by the
contactless UART during receiving.
The bit GlobalIRq in register IRQ1 indicates an interrupt occurring at any other interrupt
source when enabled.
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Ta ble 4. Interrupt sources
Interrupt bit Interrupt source Is set automatically, when
Timer0Irq Timer Unit the timer register T0 CounterVal underflows
Timer1Irq Timer Unit the timer register T1 CounterVal underflows
Timer2Irq Timer Unit the timer register T2 CounterVal underflows
Timer3Irq Timer Unit the timer register T3 CounterVal underflows
TxIrq Transmitter a transmitted data stream ends
RxIrq Receiver a received data stream ends
IdleIrq Command Register a command execution finishes
HiAlertIrq FIFO-buffer pointer the FIFO data number has reached the top level as
configured by the bit WaterLevel
LoAlertIrq FIFO-buffer pointer the FIFO data number has reached the bottom level as
configured by the bit WaterLevel
ErrIrq contactless UART a communication error had been detected
LPCDIrq LPCD a card was detected when in low-power card detection
mode
RxSOFIrq Receiver detection of a SOF or a subcarrier
GlobalIrq all interrupt sources will be set if another interrupt request source is set
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8.2 T imer module
Timer module overview
The CLRC663 implements five timers. Each of four timers Timer0 to Timer3 has an input
clock that can be configured by register T(x)Control to be 13.56 MHz, 212 kHz, (derived
from the 27.12 MHz quartz) or to be the underflow event of a Timer. Each timer
implements a counter register which is 16 bit wide. A reload value for the counter is
defined in a range of 0000h to FFFFh in the registers TxReloadHi and TxReloadLo. The
fourth timer Timer4 is intended to be used as a wakeup timer and is connected to the
internal LPO (Low-Power Oscillator) as input clock source.
The TControl regi ste r allows the glob al start and sto p of eac h of the fo ur time rs Timer0 to
T i mer3. Additio nally, this register indicate s if one o f the time rs is running o r stopped. Each
of the five timers implements an individual configuration register set defining timer reload
value (e.g. T0ReloadHi,T0ReloadLo), the timer value (e.g. T0CounterValHi,
T0CounterValLo) and the conditions which define start, stop and clockfrequency (e.g.
T0Control).
The external host may use these timers to manage timing relevant tasks. The timer unit
may be used in one of the following configurations:
Time-out counter
Watch-dog counter
Stop watch
Programmable one-shot timer
Periodical trigger
The timer unit can be used to measure the time interval between two events or to indicate
that a specific event has occurred after an elapsed time. The timer register content is
modified by the timer unit, which can be used to generate an interrupt to allow an host to
react on this event.
The counter value of the timer is available in the registers T(x)CounterValHi,
T(x)CounterValLo. The content of these registers is decremented at each timer clock.
If the counter value has reached a value of 0000h and the interrupts are enabled for this
specific timer, an interrupt will be generated as soon as the next clock is received.
If enabled, the timer event can be indicated on the pin IRQ (interrupt request). The bit
Timer(x)Irq can be set and reset by the host controller. Depending on the configuration,
the timer will stop counting at 0000h or restart with the value loaded from registers
T(x)ReloadHi, T(x)ReloadLo.
The counting of the timer is indicated by bit TControl.T(x)Running.
The timer can be started by setting bits TControl.T(x)Running and
TControl.T(x)StartStopNow or stopped by setting the bits TControl.T(x)StartStopNow and
clearing TControl.T(x)Running.
Another possibility to start the timer is to set the bit T(x)Mode.T(x)Start, this can be useful
if dedicated protocol requirements need to be fulfilled.
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8.2.1 Timer modes
8.2.1.1 Time-Out- and Watch-Dog-Counter
Having configured the timer by se tting register T(x)ReloadValue and st ar tin g the coun ting
of Timer(x) by setting bit TControl.T(x)StartStop and TControl.T(x)Running, the timer unit
decrements the T(x)CounterValue Register beginning with the configured start event. If
the configured stop event occurs before the Timer(x) underflows (e.g. a bit is received
from the card), the timer unit stops (no interrupt is generated).
If no stop event occurs, the timer unit continues to decreme nt the counter registers until
the content is zero and generates a timer interrupt request at the next clock cycle. This
allows to indicate to a ho st th at the event di d no t occur durin g th e conf igur ed time inter val .
8.2.1.2 Wake-up timer
The wake-up Timer4 allows to wakeup the system from standby after a predefined time.
The system can be configured in such a wa y t hat it is entering the standby mode again in
case no card had been detected.
This functionality ca n be use d to im ple m ent a low-power card detection (LPCD). For the
low-power card detection it is recommended to set T4Control.T4AutoWakeUp and
T4Control.T4AutoRestart, to activate the Timer4 and automat ically set the system in
standby. The internal low-power clock oscillator (LPO) is then used as input clock for this
Timer4. If a card is detected the host-communication can be started. If bit
T4Control.T4AutoW a keUp is not set, the CLRC663 will not enter the standby mode again
in case no card is detected but stays fully powered.
8.2.1.3 Stop watch
The elapsed time between a configured start- and stop event may be measured by the
CLRC663 timer unit. By setting the registers T(x)ReloadValueHi, T(x)reloadValueLo the
timer starts to decrement as soon as activated. If the configured stop even t oc cu rs, the
timers stops decrement ing . Th e elapsed time between start and stop event can then be
calculated by the host dependent on the timer interval TTimer:
(1)
If an underflow occurred which can be identified by evaluating the corresponding IRQ bit,
the performed time measurement according to the formula above is not correct.
8.2.1.4 P rogra mma bl e on e -s h ot timer
The host configures the interrupt and the timer, starts the timer and waits for the interrupt
event on pin IRQ. After the configured time the interrupt request will be raised.
8.2.1.5 Periodical trigger
If the bit T(x)Control.T(x)AutoRestart is set and the interrupt is activated, an interrupt
request will be indicated periodically after every elapsed timer period.

Timervaluevalue TTimerTreloadT *
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8.3 Contactless interface unit
The contactless in terface unit of the CLRC663 supp ort s the following read /write op erating
modes:
ISO/IEC14443A/MIFARE
ISO/IEC14443B
FeliCA
ISO/IEC15693/ICODE
ICODE EPC UID
ISO/IEC 18000-3 mode 3/ EPC Class-1 HF
A typical system using the CLRC663 is using a microcontroller to implement the higher
levels of the contactless communication protocol and a power supply (battery or external
supply).
8.3.1 ISO/IEC14443A/MIFARE functionality
The physical level of the communication is shown in Figure 5.
The physical parameters are described in Table 5.
Fig 4. Read/write mode
001aal996
BATTERY/POWER SUPPLY
reader/writer
MICROCONTROLLER
READER IC ISO/IEC 14443 A CARD
(1) Reader to Card 100 % ASK, Miller Coded, Transfer speed 106 kbit/s to 848 kbit/s
(2) Card to Reader, Subcarrier Load Modulation Manchester Coded or BPSK, transfer speed
106 kbit/s to 848 kbit/s
Fig 5. ISO/IEC 14443 A/MIFARE read/write mode communication diagram
(1)
(2)
001aam268
ISO/IEC 14443 A CARD
ISO/IEC 14443 A
READER
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The CLRC663 connection to a host is required to manage the complete
ISO/IEC 14443 A/MIFARE prot oco l. Figure 6 shows the data coding and framing
according to ISO/IEC 14443A /MIFARE.
The internal CRC coprocessor calculates the CRC value based on ISO/IEC 14443 A
part 3 and handles parity generation internally according to the transfer speed.
Table 5. Communication overview for ISO/IEC 14443 A/MIFARE reader/writer
Communication
direction Signal type Transfer speed
106 kbit/s 212 kbit/s 424 kbit/s 848 kbit/s
Reader to card (send
data from the CLRC663
to a card)
fc = 13.56 MHz
reader side
modulation 100 % ASK ASK ASK ASK
bit encoding modified Miller
encoding modified Miller
encoding modified Miller
encoding modified Miller
encoding
bit rate [kbit/s] fc / 128 fc / 64 fc / 32 fc / 16
Card to reader
(CLRC663 receives
data from a card)
card side
modulation subcarrier load
modulation subcarrier load
modulation subcarrier load
modulation subcarrier load
modulation
subcarrier
frequency fc/16fc/16fc /16fc/16
bit encodin g Manchester
encoding BPSK BPSK BPSK
Fig 6. Data coding and fram ing ac cor ding to ISO/IEC 14443 A
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8.3.2 ISO/IEC14443B functionality
The physical level of the communication is shown in Figure 7.
The physical parameters are described in Table 6.
The CLRC663 connecte d to a host is required to manag e the comple te ISO/IEC 14443 B
protocol. The following Figure 8 “SOF and EOF acco rding to ISO/IEC 14443 B shows the
ISO/IEC 14443B SOF and EOF.
(1) Reader to Card NRZ, Miller coded, transfer speed 106 kbit/s to 848 kbit/s
(2) Card to reader , Subcarrier Load Modulation Manchester Coded or BPSK, transfer speed 106 kbit/s
to 848 kbit/s
Fig 7. ISO/IEC 14443 A/MIFARE read/write mode communication diagram
(1)
(2)
001aal997
ISO/IEC 14443 B CARD
ISO/IEC 14443 B
READER
Table 6. Communication overview for ISO/IEC 14443 B reader/writer
Communication
direction Signal type Transfer speed
106 kbit/s 212 kbit/s 424 kbit/s 848 kbit/s
Reader to card (send
data from the CLRC663
to a card)
fc = 13.56 MHz
reader side
modulation 10 % ASK 10 % ASK 10 % ASK 10 % ASK
bit encodin g NRZ NRZ NRZ NRZ
bit rate [kbit/s] 128 / fc 64 / fc 32 / fc 16 / fc
Card to reader
(CLRC663 receives
data from a card)
card side
modulation subcarrier load
modulation subcarrier load
modulation subcarrier load
modulation subcarrier load
modulation
subcarrier
frequency fc/16 fc/16 fc /16 fc /16
bit encoding BPSK BPSK BPSK BPSK
Fig 8. SOF and EOF according to ISO/IEC 14443 B
001aam270
UNMODULATED (SUB)
CARRIER
Start of Frame (SOF)
sequence
9.44 µs
''0'' ''0'' ''0'' ''0'' ''0'' ''0'' ''0'' ''0'' ''0'' ''0'' ''1'' ''1'' DATA
LAST CHARACTER UNMODULATED (SUB)
CARRIER
End of Frame (EOF)
sequence
9.44 µs
''0'' ''0'' ''0'' ''0'' ''0'' ''0'' ''0'' ''0'' ''0'' ''0''
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8.3.3 FeliCa functionality
The FeliCa mode is the general reader/writer to card communication scheme according to
the FeliCa specification. The communication on a physical level is shown in Figure 9.
The physical parameters are described in Table 7.
The CLRC663 needs to be connected to a host to be able to suppor t the complete Fe liCa
protocol.
8.3.3.1 FeliCa framing and coding
To enable the FeliCa communication a 6 byte preamble (00h, 00h, 00h, 00h, 00h, 00h)
and 2 bytes sync bytes (B2h, 4Dh) are sent to synchronize the receiver.
The following Len byte indi cates the length of the sent data bytes plus the LEN byte itself.
The CRC calculation is done according to the FeliCa definitions with the MSB first.
To transmit data on the RF interface, the host controller has to send the Len- and data-
bytes to the CLRC663's FIFO-buffer. The preamble and the sync bytes are generated by
the CLRC663 automatically and must not be written to the FIFO by the host controller.
The CLRC663 performs internally the CRC calculation and adds the result to the data
frame.
8.3.4 ISO/IEC15693 functionality
The physical parameters are described in Table 9.
Fig 9. FeliCa read/write co mmuni c ati on dia gram
Ta ble 7. Communication overview for FeliCa reader/writer
Communication
direction Signal type Tr ansfer speed FeliCa FeliCa higher transfer
speeds
212 kbit/s 424 kbit/s
Reader to card (send
data from the CLRC663
to a card)
fc = 13.56 MHz
reader side
modulation 8 % to 30 % ASK 8 % to 30 % ASK
bit encoding Manchester encoding Manchester encoding
bit rate fc/64 fc/32
Card to reader (CLRC663
receives data from a
card)
card side load
modulation 30/H^1.2
(H = field strength [A/m]) 30/H^1.2
(H = field strength [A/m])
bit encoding Manchester encoding Manchester encoding
001aam271
FeliCa READER
(PCD)
FeliCa CARD
(PICC)
1. PCD to PICC 8-30 % ASK
Manchester Coded,
baudrate 212 to 424 kbaud
2. PICC to PCD, >12 % Loadmodulation
Manchester Coded,
baudrate 212 to 424 kbaud
Table 8. FeliCa fra ming and coding
Preamble (Hex.) Sync
(Hex.) Len n-Data CRC
00 00 00 00 00 00 B2 4D
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[1] Fast inventory (page) read command only (ICODE proprietary command).
Table 9. Communication overview for ISO/IEC 15693 reader/writer reader to label
Communication
direction Signal type Transfer speed
fc / 8192 kbit/s fc / 512 kbit/s
Reader to label (send
data from the
CLRC663 to a card)
reader side
modulation 10 % to 30 % ASK or
100 % ASK 10 % to 30 % ASK 90 %
to 100 % ASK
bit encoding 1/256 1/4
bit length 4.833 ms 302.08 ms
Table 10. Communication overview for ISO/IEC 1569 3 reader/writer label to reader
Communication
direction Signal type Transfer speed
6.62 (6.67) kbit/s 13.24
kbit/s[1] 26.48
(26.69) kbit/s 52.96 kbit/s
Label to reader
(CLRC663
receives data
from a card)
fc = 13.56 MHz
card side
modulation not supported not supported single (dual)
subcarrier
load
modulation
ASK
single
subcarrier
load
modulation
ASK
bit length
(ms) - - 37.76 (3.746) 18.88
bit encoding - - Manchester
coding Manchester
coding
subcarrier
frequency
[MHz]
--fc/32
(fc / 28) fc / 32
Fig 10. Data coding according to ISO/IEC 15693. standard mode reader to label
001aam272
pulse
modulated
carrier
~9.44 μs
01 2 3 4
~18.88 μs
. 2 . . . ..... . . . . . . . . . 22..... 2 2
25555
5~4,833 ms 3245
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8.3.5 EPC-UID/UID-OTP functionality
The physical parameters are described in Table 11.
Data coding and framing according to EPC global 13.56 MHz ISM (industrial, scientific
and medical) Band Class 1 Radio Frequency Identification Tag Interface Specification
(Candidate Recommendation, Version 1.0.0).
8.3.6 ISO/IEC 18000-3 mode 3/ EPC Class-1 HF functionality
The ISO/IEC 18000-3 mode 3/ EPC Class-1 HF is not described in this documen t. Fo r a
detailed explanation of the protocol, refer to the ISO/IEC 18000- 3 mode 3/ EPC Class-1
HF standard.
8.3.7 ISO/IEC 18092 mode
The CLRC663 supports Passive Initiator Communication mode at the transfer speeds
106 kbit/s, 212 kbit/s and 424 kbit/s as defined in the ISO/IEC 18092 standard.
Passive communication mode means th at the t arget answe rs to an initiato r command
in a load modulation scheme. The initiator is active in terms of genera ting the RF field.
Initiator: generates RF field at 13.56 MHz and starts the ISO/IEC 18092
communication.
Target: responds to initiator command either in a load modulation scheme in Passive
communication mode or using a self gener ated and self modu lated RF fiel d for Active
Communication mode.
Table 11. Communication overview for EPC/UID
Communication
direction Signal type Transfer speed
26.48 kbit/s 52.96 kbit/s
Reader to card (send
data from the
CLRC663 to a card)
reader side modulation 10 % to 30 % ASK
bit encoding RTZ
bit length 37.76 s
Card to reader
(CLRC663 receives
data from a card)
card side modulation single subcarrier load
modulation
bit length 18.88 ms
bit encoding Manchester coding
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8.3.7.1 Passive communication mode
Passive communication mode means that the t arget answers to an initiato r command in a
load modulation scheme. The initiator is active meaning generating the RF field.
The cont actless UART of CLRC663 and a dedicated ho st controller are required to ha ndle
the ISO/IEC 18092 passive initiator protocol.
Fig 11. Passive communication mode
Ta ble 12. Commun ication overview for Passive communication mode
Communication
direction 106 kbit/s 212 kbit/s 424 kbit/s
Initiator target According to
ISO/IEC 14443A
100 % ASK, Modified
Miller Coded
According to FeliCa, 8 % to 30 % ASK
Manchester Coded
Target initiator According to
ISO/IEC 14443A subcarrier
load modulation,
Manchester Coded
According to FeliCa, > 12 % ASK
Manchester Coded
host NFC INITIATOR
powered to
generate RF field
1. initiator starts communication
at selected transfer speed
2. targets answers using
load modulated data
at the same transfer speed
host
NFC TARGET
powered for
digital processing
001aan217
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8.3.7.2 ISO /IEC 18092 framing an d co di n g
The ISO/IEC 18092 framing and coding in Passive communication mode is defined in the
ISO/IEC 18092 standard.
8.3.7.3 ISO/IEC 18092 protocol support
The ISO/IEC 18092 proto col is not described in this documen t. For a det aile d explan ation
of the protocol, refer to the ISO/IEC 18092 standard.
8.3.8 EPC Class-1 HF and ICODE
8.3.8.1 Data encoding ICODE
The ICODE protocols have mainly three different methods of data encoding:
“1” out of “4” coding sch e me
“1” out of “256” coding scheme
“Return to Zero” (RZ) coding scheme.
Data encoding for all three coding schemes is done by the ICODE generator.
The supported EPC Class-1 HF modes are:
2 pulse for 424 Kbit subcarrier
4 pulse for 424 Kbit subcarrier
2 pulse for 848 Kbit subcarrier
4 pulse for 848 Kbit subcarrier
8.4 Host interfaces
8.4.1 Host interface configuration
The CLRC663 supports direct interfacing of various hosts as the SPI, I2C, I2CL and ser i al
UART interface type. The CLRC663 resets its interface and checks the current host
interface type automatically having performed a power-up or resuming from power down.
The CLRC663 identifies the host interface by the means of the logic levels on the control
pins after the Cold Reset Phase. This is done by a combination of fixed pin
connections.The following table shows the possible configurations defined by
IFSEL1,IFSEL0:
Table 13. Framing and coding overview
Transfer speed Framing and Coding
106 kbit/s According to the ISO/IEC 14443A/MIFARE scheme
212 kbit/s According to the FeliCa scheme
424 kbit/s According to the FeliCa scheme
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8.4.2 SPI interface
8.4.2.1 General
The CLRC663 acts as a slave during the SPI communication. The SPI clock SCK has to
be generated by the master. Data communication from the master to the slave uses the
Line MOSI. Line MISO is used to send data back from the CLRC663 to the master.
A serial peripheral interface (SPI compatible) is supported to enable high speed
communication to a host. The implemented SPI compatible interface is according to a
standard SPI in terface. The SPI interface can han dle dat a speed of up to 10 Mbit/s. In the
communication with a host CLRC663 acts as a slave receiving da ta from the external host
for register sett ing s an d to send and receive data relevant for the communication on the
RF interface.
On both data lines (MOSI, MISO) each data byte is sent by MSB first. Data on MOSI line
shall be stable on rising edge of the clock line (SCK) and is allowed to change on falling
edge. The sa me is valid for th e MISO line. Dat a is provided by the CLRC663 on the falling
edge and is stable on the rising edge.The polarity of the clock is low at SPI idle.
8.4.2.2 Read data
To read out data from the CLRC663 by using the SPI compatible interface the following
byte order has to be used.
The first byte that is sent defines the mode (LSB bit) and the address.
Table 14. Connection scheme for detecting the different interface types
Pin Pin Symbol UART SPI I2C I2C-L
28 IF0 RX MOSI ADR1 ADR1
29 IF1 - SCK SCL SCL
30 IF2 TX MISO ADR2 SDA
31 IF3 1 NSS SDA ADR2
26 IFSEL0 0 0 1 1
27 IFSEL1 0 1 0 1
Fig 12. Connection to host with S PI
001aal998
READER IC
IF1
SCK
IF0
MOSI
IF2
MISO
IF3
NSS
Table 15. Byte Order for MOSI and MISO
byte 0 byte 1 byte 2 byte 3 to n-1 byte n byte n+1
MOSI address 0 address 1 address 2 …….. address n 00h
MISO X data 0 data 1 …….. data n 1data n
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Remark: The Most Significant Bit (MSB) has to be sent first.
8.4.2.3 Write data
To write data to the CLRC663 using the SPI interface the following byte order has to be
used. It is possible to write more than one byte by sending a single address byte
(see.8.5.2.4).
The first send byte defines both, the mode itself and the address byte.
Remark: The Most Significant Bit (MSB) has to be sent first.
8.4.2.4 Addres s by t e
The address byte has to fulfil the following format:
The LSB bit of the first byte defines the used mode. To read data from the CLRC663 the
LSB bit is set to logic 1. To write data to the CLRC663 the LSB bit has to be cleared. The
bits 6 to 0 define the address byte.
NOTE: When writing the sequence [addre ss byte][data1][data2][data3]..., [dat a1] is written
to address [address byte], [data2] is written to address [address byte + 1] and [data3] is
written to [address byte + 2].
Exception: This auto increment of the address byte is not performed if data is written to
the FIFO address
8.4.2.5 Timing Specification SPI
The timing condition for SPI interface is as follows:
Table 16. Byte Order for MOSI and MISO
byte 0 byte 1 byte 2 3 to n-1 byte n byte n + 1
MOSI address 0 data 0 data 1 …….. data n 1 data n
MISOXXX…..XX
Table 17. Address byte 0 register; address MOSI
76543210
address 6 address 5 address 4 address 3 address 2 address 1 address 0 1 (read)
0 (write)
MSB LSB
Table 18. Timing conditions SPI
Symbol Parameter Min Typ Max Unit
tSCKL SCK LOW time 50 - - ns
tSCKH SCK HIGH time 50 - - ns
th(SCKH-D) SCK HIGH to data input hold time 25 - - ns
tsu(D-SCKH) data input to SCK HIGH set-up time 25 - - ns
th(SCKL-Q) SCK LOW to data output hold time - - 25 ns
t(SCKL-NSSH) SCK LOW to NSS HIGH time 0 - - ns
tNSSH NSS HIGH time 50 - - ns
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Remark: To send more bytes in one dat a stream the NSS signal must be LOW during the
send process. To send more than one dat a stream the NSS signal must be HIGH between
each data stream.
8.4.3 RS232 interface
8.4.3.1 Selection of the transfer speeds
The internal UART interface is compatible to a RS232 serial interface.
Table 20 “Selectable transfer speeds describes examples for different transfer speeds
and relevant register settings. The resulting transfer speed error is less than 1.5 % for all
described transfer speeds. The default transfer speed is 115.2 kbit/s.
To change the transfer speed, the host controller has to write a value for the new transfer
speed to the register SerialSpeedReg. The bits BR_T0 and BR_T1 define factors to set
the transfer speed in the SerialSpeedReg.
Table 19 “Settings of BR_T0 and BR_T1 describes the settings of BR_T0 and BR_T1.
Fig 13. Connection to host with SPI
001aaj641
tSCKL
tNSSH tSCKH tSCKL
th(SCKL-Q)
tsu(D-SCKH)
th(SCKH-D)
th(SCKL-Q)
t(SCKL-NSSH)
SCK
MOSI
MISO
MSB
MSB
LSB
LSB
NSS
Table 19. Settings of BR_T0 and BR_T1
BR_T001234567
factor BR_T011248163264
range BR_T1 1 to 32 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64 33 to 64
Ta ble 20. Selectable transfer speed s
Transfer speed (kbit/s) Serial SpeedReg Transfer speed accuracy (%)
(Hex.)
7.2 FA 0.25
9.6 EB 0.32
14.4 DA 0.25
19.2 CB 0.32
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The selectable transfer speeds as shown are calculated according to the following
formulas:
if BR_T0 = 0: transfer speed = 27.12 MHz / (BR_T1 + 1)
if BR_T0 > 0: transfer speed = 27.12 MHz / (BR_T1 + 33)/2(BR_T0 1)
Remark: Transfer speeds above 1228.8 KBits/s are not supported.
8.4.3.2 Framing
Remark: For data and address bytes the LSB bit has to be sent first. No parity bit is used
during transmission.
Read dat a: To read out dat a using the UAR T interface the flow described below has to be
used. The first send byte defines both the mode itself and the address.The Trigger on pin
IF3 has to be set, otherwise no read of data is possible.
38.4 AB 0.32
57.6 9A 0.25
115.2 7A 0.25
128 74 0.06
230.4 5A 0.25
460.8 3A 0.25
921.6 1C 1.45
1228.8 15 0.32
Ta ble 20. Selectable transfer speed s
Transfer speed (kbit/s) Serial SpeedReg Transfer speed accuracy (%)
(Hex.)
Ta ble 21. UART framing
Bit Length Value
Start bit (Sa) 1 bit 0
Data bits 8 bit Data
Stop bit (So) 1 bit 1
Ta ble 22. Byte Order to Read Data
Mode byte 0 byte 1
RX address -
TX - data 0
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Write data:
To write data to the CLRC663 using the UART interface the following sequence has to be
used.
The first send byte defines both, the mode itself and the address.
Remark: Data can be sent before address is received .
Fig 14. Timing Diagram for UART Read Data
001aam298
A0 A1Sa A2 A3
TX
RX A4 A5 A6 RD/
NWR So
D0
DATA
ADDRESS
D1Sa D2 D3 D4 D5 D6 D7 So
Ta ble 23. Byte Order to Write Data
Mode byte 0 byte 1
RX address 0 data 0
TX address 0
Fig 15. Timing diagram for UART write data
001aam299
A0 A1Sa A2 A3
TX
RX A4 A5 A6 RD/
NWR
So
A0
ADDRESS
ADDRESS
A1Sa A2 A3 A4 A5 A6 RD/
NWR
So
D0
DATA
D1Sa D2 D3 D4 D5 D6 D7 So
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8.4.4 I2C-bus interface
8.4.4.1 General
An Inter IC (I2C) bus interfac e is sup por ted to en ab le a low cost, low pin count serial bus
interface to the host. The impl emented I2C interface is mainly implemented accor ding the
NXP Semiconductors I2C interface specification, rev. 3.0, June 2007. The CLRC663 can
act as a slave receiver or slave transmitter in standard mode, fast mode and fast mode
plus.
The following features defined by the NXP Semiconductors I2C interface specification,
rev. 3.0, June 2007 are not supported:
The CLRC663 I2C interface does not stretch the clock
The CLRC663 I2C interface does not support the general call. This means that the
CLRC663 does not support a software reset
The CLRC663 does not support the I2C device ID
The implemented interface can o nly act in slave mo de. Therefore no clock genera tion
and access arbitration is implemented in the CLRC663.
High speed mode is not supported by the CLRC663
SDA is a bidirectional line, connected to a positive supply voltage via a pull-up resistor.
Both lines SDA and SCL are set to HIGH level if no data is transmitted. Data on the
I2C-bus can be transferred at data rates of up to 400 kbit/s in fast mode, up to 1 Mbit/s in
the fast mode+.
If the I2C interface is selected, a spike suppression according to the I2C interface
specification on SCL an d SDA is autom a tically act iva ted .
For timing requ ire m en ts refer to Table 248 “I2C-bus timing in fast mode and fast mode
plus
8.4.4.2 I2C Data validity
Data on the SDA line shall be stable during the HIGH period of the clock. The HIGH state
or LOW state of the data line shall only change when the clock signal on SCL is LOW.
Fig 16. I2C-bus interface
001aam000
READER IC
SDA
SCL
PULL-UP
NETWORK
PULL-UP
NETWORK
MICROCONTROLLER
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8.4.4.3 I2C START and STOP conditions
To handle the data transfer on the I2C-bus, unique START (S) and STOP (P) conditions
are defined.
A START condition is defined with a HIGH-to-LOW transition on the SDA line while SCL is
HIGH.
A STOP condition is defined with a LOW-to-HIGH transition on the SDA line while SCL is
HIGH.
The master always gener ates the START and ST OP co nditions. The bus is considered to
be busy after the START condition. The bus is considered to be free again a certain time
after the STOP condition.
The bus st ays busy if a repeated START (Sr) is generated instead of a ST OP condition. In
this respect, the ST AR T (S) and repeated START (Sr) conditions are functionally identical.
Therefore, the S symbol will be used as a generic term to represent both the START and
repeated START (Sr) conditions.
8.4.4.4 I2C byte format
Each byte has to be followed by an acknowledge bit. Data is transferred with the MSB
first, see Figure 18 “START and STOP conditions. The number of transmitted bytes
during one data transfer is unrestricted but shall fulfil the read/write cycle format.
Fig 17. Bit transfer on the I2C-bus.
001aam300
data line stable;
data valid
change
of data
allowed
SDA
SCL
Fig 18. START and STOP conditions
001aam301
START condition
S
SCL
SDA
SCL
SDA
STOP condition
P
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8.4.4.5 I2C Acknowledge
An acknowledge at the end of one data byte is mandator y. The acknowledge-related clock
pulse is generated by the ma ster. The transmitter of da ta, either master or slave, relea ses
the SDA line (HIGH) during the acknowledge clock pu lse. The receiver shall pull down th e
SDA line during the acknowledge clock pulse so that it remains stable LOW during the
HIGH period of this clock pulse.
The master can then generate either a STOP (P) condition to stop the transfer, or a
repeated START (Sr) condition to start a new transfer.
A master-receiver shall indi cate the end of dat a to the slave- transm itter by not generating
an acknowledge on the last byte that was clocked out by the slave. The slave-transmitter
shall release the da ta lin e to allow the master to g enerate a ST OP (P) or r epeated START
(Sr) condition.
8.4.4.6 I2C 7-bit addressing
During the I2C-bus addressing proced ur e, the fir st by te after the START co nditio n is used
to determine which slave will be selected by the master.
Fig 19. Acknowledge on the I2C- bus
Fig 20. Data transfer on the I2C- bus
001aam302
clock pulse for
acknowledgement
1
SCL FROM
MASTER
DATA OUTPUT
BY RECEIVERER
DATA OUTPUT
BY TRANSMITTER
289
acknowledge
START
condition
S
not acknowledge
001aam303
MSB acknowledgement
signal from slave acknowledgement
signal from receiver
clock line held low while
interrupts are serviced
byte complete,
interrupt within slave
12789 12 9
ACK ACK
3 - 8 Sr
or
P
P
Sr
S
or
Sr
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Alternatively the I2C address can be configured in the EEPROM. Several address
numbers are reserved for this purpose. During de vice configuration, the designer has to
ensure, that no collision with these reserved addresses in the system is possible. Check
the corresponding I2C specification for a complete list of reserved addresses.
For all CLRC663 devices the uppe r 5 bit s of th e device bus a ddress are rese rved by NXP
and set to 01010(bin). The remaining 2 bit s (ADR_2, ADR_1) of the slave address can be
freely configured by the customer in order to prevent collisions with other I2C devices by
using the interface pins (refer to Table 14) or the value of the I2C address EEPROM
register (refer to Table 34).
8.4.4.7 I2C-register write access
To write data from the host controller via I2C to a specific register of the CLRC663 the
following frame format shall be used.
The first byte of a frame indicates the device address according to the I2C rules. The
second byte indicates the register address followed by up to n-da ta bytes. In case the
address indicates the FIFO, in one frame all n-data bytes are written to the FIFO register
address. This enables for example a fast FIFO access. For any other address, the
address pointer is incremented automatically and data is written to the locations [address],
[address+1], [address+2]... [address+(n-1)]
The read/write bit shall be set to logic 0.
8.4.4.8 I2C-register read access
To read out data from a spe cific register ad dr ess of the CLRC66 3 th e h ost co ntro ller shall
use the proc ed ur e :
First a write access to the specific register address has to be performed as indicated in the
following frame:
The first byte of a frame indicates the device address according to the I2C rules. The
second byte indicates the register address. No data bytes are added.
The read/write bit shall be logic 0.
Having performed this write access, the read access starts. Th e host sends the device
address of the CLRC663. As an answer to this device address the CLRC663 responds
with the content of the addr essed register. In one frame n-data bytes could be read using
the same register address. The address pointing to the register is incremented
automatically (exception: FIFO register address is not incremented automatically). This
enables a fast transfer of register content. The address pointer is incremented
automatically and data is read from the locations [address], [address+1], [address+2]...
[address+(n-1)]
Fig 21. First byte following the START procedure
001aam304
Bit 6 Bit 5 Bit 4
slave address
Bit 3 Bit 2 Bit 1 Bit 0 R/W
MSB LSB
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In order to support a fast FIFO data transfer, the address pointer is not incremented
automatically in case the address is pointing to the FIFO.
The read/write bit shall be set to logic 1.
8.4.4.9 I2CL-bus interface
The CLRC663 provides an interface option according to of a logical handling of an I2C
interface. This logical interface fulfills the I2C specification, but the rise/fall timings will not
be according the I2C standard. Standard I/O pads are used for communication and the
communication speed is limited to 5 MBaud. The protocol itself is equivalent to the fast
mode protocol of I 2C. The address is 01010xxb, where the last two bits of the address can
be defined by the application. The definition of this bits can be done by two options. With a
pin, where the hig her bit is fixed to 0 or the configuration can be defined via EEPROM.
Refer to the EEPROM configuration in Section 8.7.
Fig 22. Register read and write access
001aam305
Ack
0
(W) Ack 0SA I2C slave address
A7-A0 CLRC663 register
address A6-A0 Ack
DATA
[7..0]
SO
SO
[0..n]
Ack
0
(W) Ack
Optional, if the previous access was on the same register address
Read Cycle
Write Cycle
0SA I2C slave address
A7-A0 CLRC663 register
address A6-A0
1
(R) AckSA
sent by master
sent by slave
I2C slave address
A7-A0 Ack
DATA
[7..0]
SO
[0..n]
0..n
Nack
DATA
[7..0]
Table 24. Timing parameter I2CL
Parameter Min Max Unit
fSCL 05MHz
tHD;STA 80 - ns
tLOW 100 - ns
tHIGH 100 - ns
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The pull-up resistor is not required for the I2CL interface. Instead, a on chip buskeeper is
implemented in the CLRC663 for SDA of the I2CL interface. This protoco l is intended to be
used for a point to point connection of devices over a short distance and does not support
a bus capability.The driver of the pin must force the line to the desired logic voltage. To
avoid that two drivers are pushing the line at the same time following regulations must be
fulfilled:
SCL: As there is no clock stretching, the SCL is always under control of the Master.
SDA: The SDA line is shared between master and slave. Therefore the master and the
slave must have the control over the own driver enable line of the SDA pin. The following
rules must be followed:
In the idle phase the SDA line is driven high by the master
In the time between st art and stop condition the SDA line is d riven by maste r or slave
when SCL is low. If SCL is high the SDA line is not driven by any device
To keep the value on the SDA line a on chip buskeeper str ucture is implemented for
the line
8.4.5 SAM interface I2C
8.4.5.1 SAM functionality
The CLRC663 implement s a dedicated I2C interfa ce to integrate a MIFARE SAM (Secure
Access Module) in a very convenient way into applications (e.g. a proximit y rea d er).
The SAM can be connected to the microcontroller to operate like a cryptographic
co-processor. For any cryptographic task, the microcontroller requests a operation from
the SAM, receives the answer and sends it over a host interface (e.g. I2C, SPI) interface
to the connected reader IC.
The MIFARE SAM supports a optimized method to integrate the SAM in a very efficient
way to reduce the protocol overhead. In this system configuration, the SAM is integrated
between the microprocessor and the reader IC, connected by one interface to the reader
IC and by another interface to the microcontroller. In this application the microcontroller
accesses the SAM using the T=1 protocol and the SAM accesses the reader IC using an
I2C interface. As the SAM is directly communicating with reader IC, the communication
overhead is reduced. In this configuration, a performance boost of up to 40% can be
achieved for a transaction time.
The MIFARE SAM supports applications using MIFARE cards. For multi application
purposes an architecture conn ecting th e micro controller additionally directly to the reader
IC is recommended. This is possible by connecting the CLRC663 on one interface (SAM
Interface SDA, SCL) with the MIFARE SAM AV2.6 (P5DF081XX/T1AR1070) and by
connecting the microcontroller to the S2C or SPI interface.
tSU;SDA 80 - ns
tHD;DAT 050ns
tSU;DAT 020ns
tSU;STO 80 - ns
tBUF 200 - ns
Table 24. Timing parameter I2CL
Parameter Min Max Unit
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8.4.5.2 SAM connection
The CLRC663 provides an interface to connect a SAM dedicated to the CLRC663. Both
interface options of the CLRC663, I 2C or I2CL can be used for this purpose . The interface
option of the SAM itself is configured by a host command sent from the host to the SAM.
The I2CL interface is in tended to be used as connection between two IC’s over a short
distance. The protocol fulfills the I2C specification, but does support a single device
connected to the bus only.
8.4.6 Boundary scan interface
The CLRC663 provides a boundary scan interface according the IEEE 1149.1. This
interface allows to test interconnections without using physical test probes. This is done
by test cells, assigned to each pin, which override the functionality of this pin.
To be able to program the test cells, the following commands are supported:
The S tandard IEEE 1149.1 describes the four basic blocks necessary to use this interface:
Test Access Port (TAP), TAP controller, TAP inst ru ctio n register, TAP da ta register;
Fig 23. I2C interface enables convenient MIFARE SAM integration
µC
Reader
I2C
I2C
aaa-002963
SAM
AV2.6
READER
IC
Table 25. Boundary scan command
Value
(decimal) Command Parameter in Parameter out
0 bypass - -
1 preload data (24) -
1 sample - data (24)
2 ID code (default) - data (32)
3 USER code - data (32)
4Clamp - -
5HIGH Z - -
7 extest data (24) data (24)
8 interface on/off interface (1) -
9 register access read address (7) data (8)
10 register access write address (7) - data (8) -
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8.4.6.1 Interface signals
The boundary scan inte rfa ce imp lem e nts a four line inter fac e be tween the chip and the
environment. There are three Inputs: Test Clock (TCK); Test Mode Select (TMS); Test
Data Input (TDI) and one output Test Data Output (TDO). TCK and TMS are broadcast
signals, TDI to TDO generate a serial line called Scan path.
Advantage o f this technique is that independent of the number s of boundary sca n devices
the complete path can be handled with four signal lines.
The signals TCK, TMS are directly connected with the boun dary scan contr oller. Because
these signals are responsible for the mode of the chip, all boundary scan devices in one
scan path will be in the same boundary scan mode.
8.4.6.2 Test Clock (TCK)
The TCK pin is the input clock fo r the module. If this clock is provided, the test logic is able
to operate independent of any other system clocks. In addition, it ensures that multiple
boundary scan controllers that are daisy-chained together can synchronously
communicate serial test data between components. During normal operation, TCK is
driven by a free-running clock. When necessary, TCK can be stopped at 0 or 1 for
extended periods of time. While TCK is stopped at 0 or 1, the state of the boundary scan
controller does not change and data in the Instruction and Data Registers is not lost.
The internal pull-up resistor on the TCK pin is enabled. This assures that no clocking
occurs if the pin is not driven from an external source.
8.4.6.3 Tes t Mo d e Sel ect (TMS)
The TMS pin selects the next state of the bou ndary scan controller. TMS is sampled on
the rising edge of TCK. Depending on the current boundary scan state and the sampled
value of TMS, the next state is entered. Because the TMS pin is sampled on the rising
edge of TCK, the IEEE Standard 1149.1 expects the value on TMS to change on the
falling edge of TCK.
Holding TMS high for five consecutive TCK cycles drives the boundary scan controller
state machine to the Test-Logic-Reset state. When the boundary scan controller enters
the Test-Logic-Reset state, the Instruction Register (IR) resets to the default instr uc tio n,
IDCODE. Therefore, this sequence can be used as a reset mechanism.
The internal pull-up resistor on the TMS pin is enabled.
8.4.6.4 Test Data Input (TDI)
The TDI pin provides a stream of serial information to the IR chain and the DR chai ns. TDI
is sampled on the rising edge of TCK and, depending on the current TAP state and the
current instruction, presents this data to the proper shift register chain. Because the TDI
pin is sampled on the rising edge of TCK, the IEEE Standard 1149.1 expects the value on
TDI to change on the falling edge of TCK.
The internal pull-up resistor on the TDI pin is enabled.
8.4.6.5 Test Data Output (TDO)
The TDO pin provides an output stream of serial information from the IR chain or the DR
chains. The value of TDO depends on the current TAP state, the current instruction, and
the data in the chain being accessed. In order to save power when the port is not being
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used, the TDO pin is placed in an inactive drive state when not actively shifting out data.
Because TDO can be connected to the TDI of another controller in a daisy-chain
configuration, the IEEE Standard 1149.1 expects the value on TDO to change on the
falling edge of TCK.
8.4.6.6 Data register
According to the IEEE1149.1 standard there are two types of data register defined:
bypass and boundary sca n
The bypass register enable the possibility to bypass a device when part of the scan
path.Serial dat a is allowed to be transferr ed through a device from the TDI pin to the TDO
pin without affecting the operation of the device.
The boundary scan register is the scan-chain of the boundary cells. The size of this
register is dependent on the command.
8.4.6.7 Boundary sc an ce ll
The boundary scan cell opens the possibility to control a hardware pin independent of its
normal use case. Basically the cell can only do one of the following: control, output and
input.
8.4.6.8 Boundary sc an path
This chapter shows the boundary scan path of the CLRC663.
Fig 24. Boundary scan cell path structure
001aam306
TAP
LOGIC
LOGIC
TAP
IC1 IC2
TCK TMS
TCK TMS
TDO
TDO
Boundary scan cell
TDI
TDI
Ta ble 26. Bo undary scan path of the CLRC663
Number (decimal) Cell Port Function
23 BC_1 - Control
22 BC_8 CLKOUT Bidir
21 BC_1 - Control
20 BC_8 SCL2 Bidir
19 BC_1 - Control
18 BC_8 SDA2 Bidir
17 BC_1 - Control
16 BC_8 IFSEL0 Bidir
15 BC_1 - Control
14 BC_8 IFSEL1 Bidir
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Refer to the CLRC663 BSDL file.
8.4.6.9 Boundary Scan Description Language (BSDL)
All of the boundary scan devices ha ve a un ique bo und ary structur e which is ne ce ssary to
know for operating the device. Important components of this language are:
available test bus signal
compliance pin s
command register
data register
boundary scan structure (number and types of the cells, their function and the
connection to the pins.)
The CLRC663 is using the cell BC_8 for the IO-Lines. The I2C Pin is using a BC_4 cell.
For all pad enable lines the cell BC1 is used.
The manufacturer's identification is 02Bh.
attribute IDCODEISTER of CLRC663: entity is "0001" and -- version
"0011110010000010b" and -- part number (3C82h)
"00000010101b" and -- manufacturer (02Bh)
"1b"; -- mandatory
The user code data is coded as followed:
product ID (3 bytes)
version
These four bytes are stored as the first four bytes in the EEPROM.
13 BC_1 - Control
12 BC_8 IF0 Bidir
11 BC_1 - Control
10 BC_8 IF1 Bidir
9 BC_1 - Control
8BC_8IF2Bidir
7 BC_1 IF2 Output2
6BC_4IF3Bidir
5 BC_1 - Control
4 BC_8 IRQ Bidir
3 BC_1 - Control
2 BC_8 SIGIN Bidir
1 BC_1 - Control
0 BC_8 SIGOUT Bidir
Ta ble 26. Bo undary scan path of the CLRC663
Number (decimal) Cell Port Function
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8.4.6.10 Non-IEEE1149.1 commands
Interface on/off: With this command the host/SAM interface can be deactivated and the
Read and Write command of the boundary scan interface is activated. (Data = 1). With
Update-DR the value is taken over.
Register Acce ss Rea d : At Capture-DR the actual address is read and stored in the DR.
Shifting the DR is shifting in a new address. With Update-DR this address is taken over
into the actual address.
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8.5 Buffer
8.5.1 Overview
An 512 8-bit FIFO buffer is imple mented in the CLRC6 63. It buf f ers the inp ut and outpu t
data stream between the host and the internal state machine of the CLRC663. Thus, it is
possible to handle data streams with lengths of up to 512 bytes without taking timing
constraints into account. The FIFO can also be limited to a size of 255 byte. In this case all
the parameters (FIFO length, Watermark...) require a single byte only for definition. In
case of a 512 byte FIFO length the definition of this values requires 2 bytes.
8.5.2 Accessing the FIFO buffer
When the -Controller starts a command, the CLRC663 may, while the command is in
progress, access the FIFO-buffer according to that command. Physically only one
FIFO-buffer is implemented, which can be used in input and output direction. Therefore
the -Controller has to take care, not to access the FIFO buffer in a way that corrupts the
FIFO data.
8.5.3 Controlling the FIFO buffer
Besides writing to and reading from the FIFO buffer, the FIFO-buffer pointers might be
reset by setting the bit FIFOFlush in FIFOControl to 1. Consequently, the FIFOLevel bits
are set to logic 0, the actually stored bytes are not accessible any more and the FIFO
buffer can be filled with another 512 bytes (or 255 bytes if the bit FIFOSize is set to 1)
again.
8.5.4 Status Information about the FIFO buffer
The host may obtain the following data about the FIFO-buffers status:
Number of bytes already stored in the FIFO-buffer. Writing increments, reading
decrements the FIFO level: FIFOLength in register FIFOLength (and FIFOControl
Register in 512 byte mode)
Warning, that the FIFO-buffer is almost full: HiAlert in register FIFOControl according
to the value of the water level in register WaterLevel (Registe r 02h bit [2], Register
03h bit[7:0])
Warning, that the FIFO-buffer is almost empty: LoAlert in register FIFOControl
according to the value of the water level in register WaterLevel (Register 02h bit [2],
Register 03h bit[7:0])
FIFOOvl bit indicates, that bytes were written to the FIFO buffer although it was
already full: ErrIrq in register Irq0.
WaterLevel is one single value defining both HiAlert (counting from the FIFO top) and
LoAlert (counting from the FIFO bottom). The CLRC663 can generate an interrupt signal
if:
LoAlertIRQEn in register IRQ0En is set to logic 1 it will activate pin IRQ when LoAlert
in the register FIFOControl changes to 1.
HiAlertIRQEN in register IRQ0En is set to logic 1 it will activate pin IRQ when HiAlert
in the register FIFOControl changes to 1.
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The bit HiAlert is set to logic 1 if maximum water level bytes (as set in register WaterLevel)
or less can be stored in the FIFO-buffer. It is generated according to the following
equation:
(2)
The bit LoAlert is set to logic 1 if water level bytes (as set in register WaterLevel) or less
are actually stored in the FIFO-buffer. It is generated according to the following equation:
(3)
HiAlert FiFoSize FiFoLengthWaterLevel=
LoAlert FIFOLength WaterLevel=
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8.6 Analog interface and contactless UART
8.6.1 General
The integrated cont actle ss UAR T suppo rt s the externa l host online with fr aming and e rror
checking of the protocol requirements up to 848 kbit/s. An external circuit can be
connected to the communication interface pins SIGIN and SIGOUT to modulate and
demodulate the data.
The cont actless UART handles th e protocol requirement s for the communi cation schemes
in co-operation with the h ost. The pr otocol han dling it self g enerates bit- and byte -oriente d
framing and handles error detection like Parity and CRC according to the different
contactless communication schemes.
The size, the tuning of the antenna, and the supply voltage of the output drivers have an
impact on the achievable field strength. The operating distance between reader and card
depends additionally on the type of card used.
8.6.2 TX transmitter
The signal delivered on pin TX 1 and pin TX 2 is the 13.5 6 MHz carrie r mo d ula te d by an
envelope signal for energy and data transmission. It can be used to drive an antenna
directly, using a few passive components for matching and filtering, see Section 14
Application information. The signal on TX1 and TX2 can be configured by the register
DrvMode, see Section 9.8.1 TxMode.
The modulation index can be set by the TxAmp.
Following figure shows the general relations during modulation
Note: When changing the continuous wave, the residual carrier also changes, while the
modulation index remains the same.
Fig 25. General depende nc e s of mo dulation
001aan355
time
influenced by set_clk_mode envelope
TX ASK100
1: Defined by set_cw_amplitude.
2: Defined by set_residual_carrier.
TX ASK10
(1)
(2)
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The registers Section 9.8 and Section 9.10 control the data rate, the framing during
transmission and the setting of the antenna driver to support the requirements at the
different specified modes and transfer speeds.
Register TXamp and the bits for set_residual_carrier can define the modulation index:
Table 27. Settings for TX1 and TX2
TxClkMode
(binary) Tx1 and TX2 output Remarks
000 High impedance -
001 0 output pulled to 0 in an y case
010 1 output pulled to 1 in an y case
110 RF high side push open drain, only high side (push) MOS supplied
with clock, clock p arity defined by invtx; low side
MOS is off
101 RF low side pull open drain, only low side (pull) MOS supplied
with clock, clock parity defined by invtx; high
side MOS is off
111 13.56 MHz clock derived
from 27.12 MHz quartz
divided by 2
push/pull Operation, clock polarity defined by
invtx; settin g for 10% modulation
Table 28. Setting residual carrier and modulation ind ex by TXamp.set_residual_carrier
set_residual_carrier (decimal) residual carrier [%] modulation index [%]
0990.5
1981.0
2962.0
3943.1
4914.7
5895.8
6877.0
7867.5
8858.1
9848.7
10 83 9.3
11 82 9.9
12 81 10.5
13 80 11.1
14 79 11.7
15 78 12.4
16 77 13.0
17 76 13.6
18 75 14.3
19 74 14.9
20 72 16.3
21 70 17.6
22 68 19.0
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Note: When VDD(TVDD) < 5 V it is not recommended to use a residual carrier < 50 %
8.6.2.1 Overshoot protection
The CLRC663 provides an overshoot protection for 100% ASK to avoid overshoots during
a PCD communication. Therefor e two timers ov ershoo t_t1 and over shoot_t2 can be used .
During the timer overshoot_t1 runs an amplitude defined by set_cw_amplitude bits is
provided to the output driver. Followed by an amplitude denoted by set_residual_carrier
bits with the duration of oversh oo t_ t2 .
23 65 21.2
24 60 25.0
25 55 29.0
26 50 33.3
27 45 37.9
28 40 42.9
29 35 48.1
30 30 53.8
31 25 60.0
Table 28. Setting residual carrier …continuedand modulation in dex by
set_residual_carrier (decimal) residual carrier [%] modulation index [%]
Fig 26. Example 1: overshoot_t1 = 2d ; overhoot_t2 = 5d.
001aan356
2.50 3.03 3.56 4.10
time (μs)
7.0
5.0
(V)
3.0
1.0
-1.0
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8.6.2.2 Bit generator
The default coding of a data stream is done by using the Bit-Generator. It is activated
when the value of TxFrameCon.DCodeType is set to 0000 (bin). The Bit-Generator
encodes the data stream byte-wise and can apply the following encoding steps to each
data byte.
1. Add a start-bit of specified type at beginning of every byte
2. Add a stop-bit and EGT bits of a specified type. The maximum number o f EGT bit is 6,
only full bits are supported
3. Add a parity-bit of a specified type
4. TxFirstBits (skips a given number of bits at the beginning of the first byte in a frame)
5. TxLastBits (skips a given number of bits at the end of the last byte in a frame)
6. Encrypt data-bit (MIFARE encryption)
TxFirstBits a nd TxLastBit s can be used at the same tim e. If only a single data byte is sent,
it must be ensured that the range of TxFirstBits and TxLastBits do not overlap. It is not
possible to skip more than 8 bit of a single byte! ( (8 - TxFirstBits) + (8 - TxLastBits) ) < 8
By default, dat a bytes are always treate d LSB first. To make use of a MSB first coding, the
TxMSBFirst in the register CLCON1 needs to be set.
8.6.3 Receiver circuitry
8.6.3.1 General
The CLRC663 features a versatile quadrature receiver architecture with fully differential
signal input at RXP and RXN. It can be configured to achieve optimum performance for
reception of various 13.56 MHz based protocols.
For all processing units various adjustments can be made to obtain optimum
performance.
Fig 27. Example 2: overshoot_t1 = 0d ; overhoot_t2 = 5d
0
-1.0 1234
t
1.0
3.0
5.0
(V)
7.0