Integrated Circuit Solution Inc. 1
SSR009-0B
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.
FEATURES
• Fast access time:
– 133, 117, 100 MHz; 6 ns (83 MHz);
7 ns (75 MHz); 8 ns (66 MHz)
• Internal self-timed write cycle
• Individual Byte Write Control and Global Write
• Clock controlled, registered address, data and
control
• Pentium™ or linear burst sequence control
using MODE input
• Five chip enables for simple depth expansion
and address pipelining
• Common data inputs and data outputs
• Power-down control by ZZ input
• JEDEC 128-Pin LQFP and PQFP 14mm x
20mm package
• Single +3.3V power supply
• Control pins mode upon power-up:
– MODE in interleave burst mode
– ZZ in normal operation mode
These control pins can be connected to GNDQ
or VCCQ to alter their power-up state
DESCRIPTION
The ICSI IS61SP6464 is a high-speed, low-power synchro-
nous static RAM designed to provide a burstable, high-perfor-
mance, secondary cache for the i486™, Pentium™, 680X0™,
and PowerPC™ microprocessors. It is organized as 65,536
words by 64 bits, fabricated with ICSI's advanced CMOS
technology. The device integrates a 2-bit burst counter, high-
speed SRAM core, and high-drive capability outputs into a
single monolithic circuit. All synchronous inputs pass through
registers controlled by a positive-edge-triggered single clock
input.
Write cycles are internally self-timed and are initiated by the
rising edge of the clock input. Write cycles can be from one to
eight bytes wide as controlled by the write control inputs.
Separate byte enables allow individual bytes to be written.
BW1 controls I/O1-I/O8, BW2 controls I/O9-I/O16, BW3 con-
trols I/O17-I/O24, BW4 controls I/O25-I/O32, BW5 controls
I/O33-I/O40, BW6 controls I/O41-I/O48, BW7 controls I/O49-
I/O56, BW8 controls I/O57-I/O64, conditioned by BWE being
LOW. A LOW on GW input would cause all bytes to be written.
Bursts can be initiated with either ADSP (Address Status
Processor) or ADSC (Address Status Cache Controller) input
pins. Subsequent burst addresses can be generated internally
by the IS61SP6464 and controlled by the ADV (burst address
advance) input pin.
Asynchronous signals include output enable (OE), sleep mode
input (ZZ), and burst mode input (MODE). A HIGH input on the
ZZ pin puts the SRAM in the power-down state. When ZZ is
pulled LOW (or no connect), the SRAM normally operates after
the wake-up period. A LOW input, i.e., GNDQ, on MODE pin
selects LINEAR Burst. A VCCQ (or no connect) on MODE pin
selects INTERLEAVED Burst.
IS61SP6464
64K x 64 SYNCHRONOUS
PIPELINE STATIC RAM
IS61SP6464
2Integrated Circuit Solution Inc.
SSR009-0B
BLOCK DIAGRAM
16
BINARY
COUNTER
A15-A0
BW1
GW
CLR
CE
CLK Q0
Q1
MODE
A0’
A0
A1 A1’
CLK
ADV
ADSC
ADSP
14 16
ADDRESS
REGISTER
CE
D
CLK
Q
DQ57-DQ64
BYTE WRITE
REGISTERS
D
CLK
Q
DQ8-DQ1
BYTE WRITE
REGISTERS
D
CLK
Q
ENABLE
REGISTER
CE
D
CLK
Q
ENABLE
DELAY
REGISTER
D
CLK
Q
BWE
BW8
CE
CE2
CE2
CE3
CE3
64K x 64
MEMORY
ARRAY
64
INPUT
REGISTERS
CLK
OUTPUT
REGISTERS
CLK
64
OE
864
OE DATA[64:1]
IS61SP6464
Integrated Circuit Solution Inc. S3-3
PIN CONFIGURATION
128-Pin LQFP and PQFP
VCCQ
I/O
32
I/O
31
I/O
30
I/O
29
I/O
28
I/O
27
I/O
26
I/O
25
I/O
24
I/O
23
I/O
22
GNDQ
VCCQ
I/O
21
I/O
20
I/O
19
I/O
18
I/O
17
I/O
16
I/O
15
I/O
14
I/O
13
I/O
12
GNDQ
VCCQ
I/O
11
I/O
10
I/O
9
I/O
8
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
I/O
2
I/O
1
GNDQ
VCCQ
CE3
CE2
CE3
CE2
GND
VCC
CE
BW8
BW7
BW6
BW5
OE
CLK
BWE
GW
BW4
BW3
GND
VCC
BW2
BW1
ADSC
ADSP
ADV
GNDQ
GNDQ
I/O
33
I/O
34
I/O
35
I/O
36
I/O
37
I/O
38
I/O
39
I/O
40
I/O
41
I/O
42
I/O
43
VCCQ
GNDQ
I/O
44
I/O
45
I/O
46
I/O
47
I/O
48
I/O
49
I/O
50
I/O
51
I/O
52
I/O
53
VCCQ
GNDQ
I/O
54
I/O
55
I/O
56
I/O
57
I/O
58
I/O
59
I/O
60
I/O
61
I/O
62
I/O
63
I/O
64
VCCQ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
GNDQ
NC
MODE
A15
A14
A13
VCC
GND
A12
A11
A10
A9
A8
NC
A7
A6
A5
A4
A3
VCC
GND
A2
A1
A0
ZZ
VCCQ
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
PIN DESCRIPTIONS
A0-A15 Address Inputs
CLK Clock
ADSP Processor Address Status
ADSC Controller Address Status
ADV Burst Address Advance
BW1-BW8 Synchronous Byte Write Enable
BWE Byte Write Enable
GW Global Write Enable
CE, CE2, CE2, Synchronous Chip Enable
CE3, CE3
OE Output Enable
I/O1-I/O64 Data Input/Output
ZZ Sleep Mode
MODE Burst Sequence Mode
VCC +3.3V Power Supply
GND Ground
VCCQ Isolated Output Buffer Supply:
+3.3V
NC No Connect
GNDQIsolated Output Buffer Ground
IS61SP6464
4Integrated Circuit Solution Inc.
SSR009-0B
TRUTH TABLE
ADDRESS
OPERATION USED CE3 CE2 CE3CE3
CE3CE3
CE3 CE2CE2
CE2CE2
CE2 CECE
CECE
CE ADSPADSP
ADSPADSP
ADSP ADSCADSC
ADSCADSC
ADSC ADVADV
ADVADV
ADV WRITEWRITE
WRITEWRITE
WRITE OEOE
OEOE
OE CLK I/O
Deselected, Power-down None X X X X H X L X X X L-H High-Z
Deselected, Power-down None L X X X L L XXXXL-HHigh-Z
Deselected, Power-down None X L X X L L XXXXL-HHigh-Z
Deselected, Power-down None X X H X L L XXXXL-HHigh-Z
Deselected, Power-down None X X X H L L XXXXL-HHigh-Z
Deselected, Power-down None L X X X L H L X X X L-H High-Z
Deselected, Power-down None X L X X L H L X X X L-H High-Z
Deselected, Power-down None X X H X L H L X X X L-H High-Z
Deselected, Power-down None X X X H L H L X X X L-H High-Z
Read Cycle, Begin Burst External H H L L L L X X X L L-H Dout
Read Cycle, Begin Burst External H H L L L L X X X H L-H High-Z
Write Cycle, Begin Burst External H H L L L H L X L X L-H Din
Read Cycle, Begin Burst External H H L L L H L X H L L-H Dout
Read Cycle, Begin Burst External H H L L L H L X H H L-H High-Z
Read Cycle, Continue Burst Next X X X X X H H L H L L-H Dout
Read Cycle, Continue Burst Next X X X X X H H L H H L-H High-Z
Read Cycle, Continue Burst Next X X X X H X H L H L L-H Dout
Read Cycle, Continue Burst Next X X X X H X H L H H L-H High-Z
Write Cycle, Continue Burst Next X X X X X H H L L X L-H Din
Write Cycle, Continue Burst Next X X X X H X H L L X L-H Din
Read Cycle, Suspend Burst Current X X X X X HHHHLL-HDout
Read Cycle, Suspend Burst Current X X X X X HHHHHL-HHigh-Z
Read Cycle, Suspend Burst Current X X X X H X H H H L L-H Dout
Read Cycle, Suspend Burst Current X X X X H X HHHHL-HHigh-Z
Write Cycle, Suspend Burst Current X X X X X H H H L X L-H Din
Write Cycle, Suspend Burst Current X X X X H X H H L X L-H Din
Notes:
1. All inputs except OE must meet setup and hold times for the Low-to-High transition of clock (CLK).
2. Wait states are inserted by suspending burst.
3. X means don't care. WRITE=L means any one or more byte write enable signals (BW1-BW8) and BWE are LOW or GW is
LOW. WRITE=H means all byte write enable signals are HIGH.
4. For a Write operation following a Read operation, OE must be HIGH before the input data required setup time and held HIGH
throughout the input data hold time.
5. ADSP LOW always initiates an internal READ at the Low-to-High edge of clock. A WRITE is performed by setting one or more
byte write enable signals and BWE LOW or GW LOW for the subsequent L-H edge of clock.
IS61SP6464
Integrated Circuit Solution Inc. S3-5
ASYNCHRONOUS TRUTH TABLE
Operation ZZ OEOE
OEOE
OE I/O STATUS
Pipelined Read L L Dout
Pipelined Read L H High-Z
Write L L High-Z
Write L H Din
Deselect L X High-Z
Sleep H X High-Z
WRITE TRUTH TABLE
Operation GWGW
GWGW
GW BWEBWE
BWEBWE
BWE BW8BW8
BW8BW8
BW8 BW7BW7
BW7BW7
BW7 BW6BW6
BW6BW6
BW6 BW5BW5
BW5BW5
BW5 BW4BW4
BW4BW4
BW4 BW3BW3
BW3BW3
BW3 BW2BW2
BW2BW2
BW2 BW1BW1
BW1BW1
BW1
Read H H X X X X X X X X
Read H L H H H H H H H H
Write all bytes H L L L L L L L L L
Write all bytes L X X X X X X X X X
Write Byte 1 H L H H H H H H H L
Write Byte 2 H L H H H H H H L H
Write Byte 3 H L H H H H H L H H
Write Byte 4 H L H H H H L H H H
Write Byte 5 H L H H H L H H H H
Write Byte 6 H L H H L H H H H H
Write Byte 7 H L H L H H H H H H
Write Byte 8 H L L H H H H H H H
INTERLEAVED BURST ADDRESS TABLE (MODE = VCC or No Connect)
External Address 1st Burst Address 2nd Burst Address 3rd Burst Address
A1 A0 A1 A0 A1 A0 A1 A0
00 01 10 11
01 00 11 10
10 11 00 01
11 10 01 00
IS61SP6464
6Integrated Circuit Solution Inc.
SSR009-0B
LINEAR BURST ADDRESS TABLE (MODE = GNDQ)
0,0
1,0
0,1A1’, A0’ = 1,1
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Parameter Value Unit
TBIAS Temperature Under Bias –10 to +85 °C
TSTG Storage Temperature –55 to +150 °C
PDPower Dissipation 1.0 W
IOUT Output Current (per I/O) 100 mA
VIN, VOUT Voltage Relative to GND for I/O Pins –0.5 to VCCQ + 0.3 V
VIN Voltage Relative to GND for –0.5 to 5.5 V
for Address and Control Inputs
VCC Voltage on Vcc Supply Relatiive to GND –0.5 to 4.6 V
Notes:
1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation of the
device at these or any other conditions above those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
2. This device contains circuity to protect the inputs against damage due to high static voltages
or electric fields; however, precautions may be taken to avoid application of any voltage
higher than maximum rated voltages to this high-impedance circuit.
3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
OPERATING RANGE
Range Ambient Temperature VCC
Commercial 0°C to +70°C 3.3V +10%, –5%
Industrial –40°C to +85°C 3.3V +10%, –5%
IS61SP6464
Integrated Circuit Solution Inc. S3-7
DC ELECTRICAL CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter Test Conditions Min. Max. Unit
VOH Output HIGH Voltage IOH = –4.0 mA 2.4 — V
VOL Output LOW Voltage IOL = 8 mA — 0.4 V
VIH Input HIGH Voltage 2.0 VCCQ + 0.3 V
VIL Input LOW Voltage –0.3 0.8 V
ILI Input Leakage Current GND < VIN < VCCQ(2) Com. –2 2 µA
Ind. –10 10
ILO Output Leakage Current GND < VOUT < VCCQ, OE = VIH Com. –2 2 µA
Ind. –10 10
CAPACITANCE(1,2)
Symbol Parameter Conditions Max. Unit
CIN Input Capacitance VIN = 0V 5 pF
COUT Input/Output Capacitance VOUT = 0V 7 pF
Notes:
1. Tested initially and after any design or process changes that may affect these parameters.
2. Test conditions: TA = 25°C, f = 1 MHz, Vcc = 3.3V.
AC TEST CONDITIONS
Parameter Unit
Input Pulse Level 0V to 3.0V
Input Rise and Fall Times 1.5 ns
Input and Output Timing 1.5V
and Reference Level
Output Load See Figures 1 and 2
AC TEST LOADS
Output
Buffer
Z
O
= 50Ω
1.5V
50Ω
30 pF
Figure 1 Figure 2
317 Ω
5 pF
Including
jig and
scope
351 Ω
OUTPUT
3.3V
IS61SP6464
8Integrated Circuit Solution Inc.
SSR009-0B
POWER SUPPLY CHARACTERISTICS (Over Operating Range)
-133 -117 -100 -6 -7 -8
Symbol Parameter Test Conditions
Max. Max. Max. Max. Max. Max. Uni
t
ICC AC Operating Device Selected, Com. 280 270 250 200 170 150 mA
Supply Current All Inputs = VIL or VIH Ind. — 290 270 220 190 170
OE = VIH,
Cycle Time > tKC min.
ISB1Standby Current Device Deselected, Com. 70 70 70 70 70 70 mA
TTL Inputs VCC = Max., Ind. — 80 80 80 80 80
All Inputs = VIH or VIL
CLK Cycle Time > tKC min.
ISB2Standby Current Device Deselected, Com. 20 20 20 20 20 20 mA
CMOS Inputs VCC = Max., Ind. — 30 30 30 30 30
VIN = VCC > 0.2V, or VIN < 0.2V
CLK Cycle Time > tKC min.
IZZ Power-Down Mode ZZ = VCCQ, CLK Running Com. 20 20 20 20 20 20 mA
Current All Inputs < GND + 0.2V Ind. — 30 30 30 30 30
or > VCC – 0.2V
Notes:
1. The MODE pin has an internal pullup. ZZ pin has an internal pull-down. This pin may be a No Connect, tied to GND, or tied to
VCCQ.
2. The MODE pin should be tied to Vcc or GND. It exhibits ±10 µA maximum leakage current when tied to < GND + 0.2V
or > Vcc – 0.2V.
IS61SP6464
Integrated Circuit Solution Inc. S3-9
READ CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-133 MHz -117 MHz -100 MHz
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tKC Cycle Time 7.5 — 8.5 — 10 — ns
tKH Clock High Time 3 — 3.4 — 4 — ns
tKL Clock Low Time 3 — 3.4 — 4 — ns
tKQ Clock Access Time — 5 — 5 — 5 ns
tKQX(1) Clock High to Output Invalid 1.5 — 1.5 — 2.5 — ns
tKQLZ(1,2) Clock High to Output Low-Z 0 — 0 — 0 — ns
tKQHZ(1,2) Clock High to Output High-Z 2 5 2 5 2 5 ns
tOEQ Output Enable to Output Valid — 5 — 5 — 5 ns
tOEQX(1) Output Disable to Output Invalid 0 — 0 — 0 — ns
tOELZ(1,2) Output Enable to Output Low-Z 0 — 0 — 0 — ns
tOEHZ(1,2) Output Disable to Output High-Z — — — — 2 5 ns
tAS Address Setup Time 2.5 — 2.5 — 2.5 — ns
tSS Address Status Setup Time 2.5 — 2.5 — 2.5 — ns
tWS Write Setup Time 2.5 — 2.5 — 2.5 — ns
tCES Chip Enable Setup Time 2.5 — 2.5 — 2.5 — ns
tAVS Address Advance Setup Time 2.5 — 2.5 — 2.5 — ns
tAH Address Hold Time 0.5 — 0.5 — 0.5 — ns
tSH Address Status Hold Time 0.5 — 0.5 — 0.5 — ns
tWH Write Hold Time 0.5 — 0.5 — 0.5 — ns
tCEH Chip Enable Hold Time 0.5 — 0.5 — 0.5 — ns
tAVH Address Advance Hold Time 0.5 — 0.5 — 0.5 — ns
Notes:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
IS61SP6464
10 Integrated Circuit Solution Inc.
SSR009-0B
READ CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-6 ns -7 ns -8 ns
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tKC Cycle Time 12 — 13 — 15 — ns
tKH Clock High Time 4.5 — 5 — 6 — ns
tKL Clock Low Time 4.5 — 5 — 6 — ns
tKQ Clock Access Time — 6 — 7 — 8 ns
tKQX(1) Clock High to Output Invalid 2.5 — 3 — 3 — ns
tKQLZ(1,2) Clock High to Output Low-Z 0 — 0 — 0 — ns
tKQHZ(1,2) Clock High to Output High-Z 2 5 2 5 2 6 ns
tOEQ Output Enable to Output Valid — 5 — 5 — 5 ns
tOEQX(1) Output Disable to Output Invalid 0 — 0 — 0 — ns
tOELZ(1,2) Output Enable to Output Low-Z 0 — 0 — 0 — ns
tOEHZ(1,2) Output Disable to Output High-Z 2 5 2 5 2 6 ns
tAS Address Setup Time 2.5 — 2.5 — 2.5 — ns
tSS Address Status Setup Time 2.5 — 2.5 — 2.5 — ns
tWS Write Setup Time 2.5 — 2.5 — 2.5 — ns
tCES Chip Enable Setup Time 2.5 — 2.5 — 2.5 — ns
tAVS Address Advance Setup Time 2.5 — 2.5 — 2.5 — ns
tAH Address Hold Time 0.5 — 0.5 — 0.5 — ns
tSH Address Status Hold Time 0.5 — 0.5 — 0.5 — ns
tWH Write Hold Time 0.5 — 0.5 — 0.5 — ns
tCEH Chip Enable Hold Time 0.5 — 0.5 — 0.5 — ns
tAVH Address Advance Hold Time 0.5 — 0.5 — 0.5 — ns
Notes:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
IS61SP6464
Integrated Circuit Solution Inc. S3-11
READ CYCLE TIMING
Single Read
High-Z
High-Z
DATA
OUT
DATA
IN
OE
CE2, CE3
CE2, CE3
CE
BW8-BW1
BWE
GW
A15-A0
ADV
ADSC
ADSP
CLK
RD1 RD2
1a 2c 2d 3a
Unselected
Burst Read
tKQX
tKC
tKLtKH
tSS tSH
tSS tSH
tAS tAH
tWS tWH
tWS tWH
RD3
tCES tCEH
tCES tCEH
tCES tCEH
CE3, CE2 and CE2, CE3 only sampled with ADSP or ADSC
CE Masks ADSP
Unselected with CE2, CE3
tOEQ
tOEQX
tOELZ
tKQLZ
tKQ
tOEHZ
tKQHZ
ADSC initiate read
ADSP is blocked by CE inactive
tAVH
tAVS Suspend Burst
Pipelined Read
2a 2b
IS61SP6464
12 Integrated Circuit Solution Inc.
SSR009-0B
WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-133 MHz -117 MHz -100 MHz
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tKC Cycle Time 7.5 — 8.5 — 10 — ns
tKH Clock High Time 3 — 3.4 — 4 — ns
tKL Clock Low Time 3 — 3.4 — 4 — ns
tAS Address Setup Time 2.5 — 2.5 — 2.5 — ns
tSS Address Status Setup Time 2.5 — 2.5 — 2.5 — ns
tWS Write Setup Time 2.5 — 2.5 — 2.5 — ns
tDS Data In Setup Time 2.5 — 2.5 — 2.5 — ns
tCES Chip Enable Setup Time 2.5 — 2.5 — 2.5 — ns
tAVS Address Advance Setup Time 2.5 — 2.5 — 2.5 — ns
tAH Address Hold Time 0.5 — 0.5 — 0.5 — ns
tSH Address Status Hold Time 0.5 — 0.5 — 0.5 — ns
tDH Data In Hold Time 0.5 — 0.5 — 0.5 — ns
tWH Write Hold Time 0.5 — 0.5 — 0.5 — ns
tCEH Chip Enable Hold Time 0.5 — 0.5 — 0.5 — ns
tAVH Address Advance Hold Time 0.5 — 0.5 — 0.5 — ns
WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-6 ns -7 ns -8 ns
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tKC Cycle Time 12 — 13 — 15 — ns
tKH Clock High Time 4.5 — 5 — 6 — ns
tKL Clock Low Time 4.5 — 5 — 6 — ns
tAS Address Setup Time 2.5 — 2.5 — 2.5 — ns
tSS Address Status Setup Time 2.5 — 2.5 — 2.5 — ns
tWS Write Setup Time 2.5 — 2.5 — 2.5 — ns
tDS Data In Setup Time 2.5 — 2.5 — 2.5 — ns
tCES Chip Enable Setup Time 2.5 — 2.5 — 2.5 — ns
tAVS Address Advance Setup Time 2.5 — 2.5 — 2.5 — ns
tAH Address Hold Time 0.5 — 0.5 — 0.5 — ns
tSH Address Status Hold Time 0.5 — 0.5 — 0.5 — ns
tDH Data In Hold Time 0.5 — 0.5 — 0.5 — ns
tWH Write Hold Time 0.5 — 0.5 — 0.5 — ns
tCEH Chip Enable Hold Time 0.5 — 0.5 — 0.5 — ns
tAVH Address Advance Hold Time 0.5 — 0.5 — 0.5 — ns
IS61SP6464
Integrated Circuit Solution Inc. S3-13
WRITE CYCLE TIMING
Single Write
DATA
OUT
DATA
IN
OE
CE2, CE3
CE2, CE3
CE
BW8-BW1
BWE
GW
A15-A0
ADV
ADSC
ADSP
CLK
WR1 WR2
Unselected
Burst Write
tKC
tKLtKH
tSS tSH
tAS tAH
tWS tWH
tWS tWH
WR3
tCES tCEH
tCES tCEH
tCES tCEH
CE3, CE2 and CE2, CE3 only sampled with ADSP or ADSC
CE Masks ADSP
Unselected with CE2, CE3
ADSC initiate Write
ADSP is blocked by CE inactive
tAVH
tAVS
ADV must be inactive for ADSP Write
WR1 WR2
tWS tWH
WR3
tWS tWH
High-Z
High-Z 1a 3a
tDS tDH
BW8-BW1 only are applied to first cycle of WR2
Write
2c 2d2b2a
IS61SP6464
14 Integrated Circuit Solution Inc.
SSR009-0B
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-133 MHz -117 MHz -100 MHz
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tKC Cycle Time 7.5 — 8.5 — 10 — ns
tKH Clock High Time 3 — 3.4 — 4. — ns
tKL Clock Low Time 3 — 3.4 — 4 — ns
tKQ Clock Access Time — 5 — 5 — 5 ns
tKQX(1) Clock High to Output Invalid 1.5 — 1.5 — 2.5 — ns
tKQLZ(1,2) Clock High to Output Low-Z 0 — 0 — 0 — ns
tKQHZ(1,2) Clock High to Output High-Z 1.5 7.5 1.5 8.5 2 5 ns
tOEQ Output Enable to Output Valid — 5 — 5 — 5 ns
tOEQX(1) Output Disable to Output Invalid 0 — 0 — 0 — ns
tOELZ(1,2) Output Enable to Output Low-Z 0 — 0 — 0 — ns
tOEHZ(1,2) Output Disable to Output High-Z — — — — 2 5 ns
tAS Address Setup Time 2.5 — 2.5 — 2.5 — ns
tSS Address Status Setup Time 2.5 — 2.5 — 2.5 — ns
tWS Write Setup Time 2.5 — 2.5 — 2.5 — ns
tCES Chip Enable Setup Time 2.5 — 2.5 — 2.5 — ns
tAH Address Hold Time 0.5 — 0.5 — 0.5 — ns
tSH Address Status Hold Time 0.5 — 0.5 — 0.5 — ns
tWH Write Hold Time 0.5 — 0.5 — 0.5 — ns
tCEH Chip Enable Hold Time 0.5 — 0.5 — 0.5 — ns
Note:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
IS61SP6464
Integrated Circuit Solution Inc. S3-15
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-6 ns -7 ns -8 ns
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tKC Cycle Time 12 — 13 — 15 — ns
tKH Clock High Time 4.5 — 5 — 6 — ns
tKL Clock Low Time 4.5 — 5 — 6 — ns
tKQ Clock Access Time — 6 — 7 — 8 ns
tKQX(1) Clock High to Output Invalid 2.5 — 3 — 3 — ns
tKQLZ(1,2) Clock High to Output Low-Z 0 — 0 — 0 — ns
tKQHZ(1,2) Clock High to Output High-Z 2 5 2 5 2 6 ns
tOEQ Output Enable to Output Valid — 5 — 5 — 5 ns
tOEQX(1) Output Disable to Output Invalid 0 — 0 — 0 — ns
tOELZ(1,2) Output Enable to Output Low-Z 0 — 0 — 0 — ns
tOEHZ(1,2) Output Disable to Output High-Z 2 5 2 5 2 6 ns
tAS Address Setup Time 2.5 — 2.5 — 2.5 — ns
tSS Address Status Setup Time 2.5 — 2.5 — 2.5 — ns
tWS Write Setup Time 2.5 — 2.5 — 2.5 — ns
tCES Chip Enable Setup Time 2.5 — 2.5 — 2.5 — ns
tAH Address Hold Time 0.5 — 0.5 — 0.5 — ns
tSH Address Status Hold Time 0.5 — 0.5 — 0.5 — ns
tWH Write Hold Time 0.5 — 0.5 — 0.5 — ns
tCEH Chip Enable Hold Time 0.5 — 0.5 — 0.5 — ns
Note:
1. Guaranteed but not 100% tested. This parameter is periodically sampled.
2. Tested with load in Figure 2.
IS61SP6464
16 Integrated Circuit Solution Inc.
SSR009-0B
READ/WRITE CYCLE TIMING
Single Read Single Write
High-Z
High-Z
DATA
OUT
DATA
IN
OE
CE2, CE3
CE2, CE3
CE
BW8-BW1
BWE
GW
A15-A0
ADV
ADSC
ADSP
CLK
RD1 WR1
WR1
1a
1a
2a 2b 2c 2d
Unselected
Burst Read
t
KQX
t
KC
t
KL
t
KH
t
SS
t
SH
ADSP is blocked by CE inactive
t
SS
t
SH
t
AS
t
AH
t
WS
t
WH
t
WS
t
WH
t
WS
t
WH
RD2 RD3
t
CES
t
CEH
t
CES
t
CEH
t
CES
t
CEH
CE2, CE3 and CE2, CE3 only sampled with ADSP or ADSC
CE Masks ADSP
Unselected with CE2, CE3
t
OEQ
t
OEQX
t
OELZ
t
KQLZ
t
KQ
t
OEHZ
t
KQX
t
KQHZ
t
DS
t
DH
t
KQHZ
IS61SP6464
Integrated Circuit Solution Inc. S3-17
SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-133 MHz -117 MHz -100 MHz
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tKC Cycle Time 7.5 — 8.5 — 10 — ns
tKH Clock High Time 3 — 3.4 — 4 — ns
tKL Clock Low Time 3 — 3.4 — 4 — ns
tKQ Clock Access Time — 5 — 5 — 5 ns
tKQX(3) Clock High to Output Invalid 0 — — — 2.5 — ns
tKQLZ(3,4) Clock High to Output Low-Z 0 — 0 — 0 — ns
tKQHZ(3,4) Clock High to Output High-Z 1.5 7.5 1.5 8.5 2 5 ns
tOEQ Output Enable to Output Valid — 5 — 4 — 5 ns
tOEQX(3) Output Disable to Output Invalid 0 — 0 — 0 — ns
tOELZ(3,4) Output Enable to Output Low-Z 0 — 0 — 0 — ns
tOEHZ(3,4) Output Disable to Output High-Z — — — — 2 5 ns
tAS Address Setup Time 2.5 — 2.5 — 2.5 — ns
tSS Address Status Setup Time 2.5 — 2.5 — 2.5 — ns
tCES Chip Enable Setup Time 2.5 — 2.5 — 2.5 — ns
tAH Address Hold Time 0.5 — 0.5 — 0.5 — ns
tSH Address Status Hold Time 0.5 — 0.5 — 0.5 — ns
tCEH Chip Enable Hold Time 0.5 — 0.5 — 0.5 — ns
tZZS ZZ Standby(1) 2— 2— 2—cyc
tZZREC ZZ Recovery(2) 2— 2— 2—cyc
Notes:
1. The assertion of ZZ allows the SRAM to enter a lower power state than when deselected within the time specified. Data
retention is guaranteed when ZZ is asserted and clock remains active.
2. ADSC and ADSP must not be asserted for at least 2 cyc after leaving ZZ state.
3. Guaranteed but not 100% tested. This parameter is periodically sampled.
4. Tested with load in Figure 2.
IS61SP6464
18 Integrated Circuit Solution Inc.
SSR009-0B
SNOOZE AND RECOVERY CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
-6 ns -7 ns -8 ns
Symbol Parameter Min. Max. Min. Max. Min. Max. Unit
tKC Cycle Time 12 — 13 — 15 — ns
tKH Clock High Time 4.5 — 5 — 6 — ns
tKL Clock Low Time 4.5 — 5 — 6 — ns
tKQ Clock Access Time — 6 — 7 — 8 ns
tKQX(3) Clock High to Output Invalid 2.5 — 3 — 3 — ns
tKQLZ(3,4) Clock High to Output Low-Z 0 — 0 — 0 — ns
tKQHZ(3,4) Clock High to Output High-Z 2 5 2 5 2 6 ns
tOEQ Output Enable to Output Valid — 5 — 5 — 5 ns
tOEQX(3) Output Disable to Output Invalid 0 — 0 — 0 — ns
tOELZ(3,4) Output Enable to Output Low-Z 0 — 0 — 0 — ns
tOEHZ(3,4) Output Disable to Output High-Z 2 5 2 5 2 6 ns
tAS Address Setup Time 2.5 — 2.5 — 2.5 — ns
tSS Address Status Setup Time 2.5 — 2.5 — 2.5 — ns
tCES Chip Enable Setup Time 2.5 — 2.5 — 2.5 — ns
tAH Address Hold Time 0.5 — 0.5 — 0.5 — ns
tSH Address Status Hold Time 0.5 — 0.5 — 0.5 — ns
tCEH Chip Enable Hold Time 0.5 — 0.5 — 0.5 — ns
tZZS ZZ Standby(1) 2— 2— 2—cyc
tZZREC ZZ Recovery(2) 2— 2— 2—cyc
Notes:
1. The assertion of ZZ allows the SRAM to enter a lower power state than when deselected within the time specified. Data
retention is guaranteed when ZZ is asserted and clock remains active.
2. ADSC and ADSP must not be asserted for at least 2 cyc after leaving ZZ state.
3. Guaranteed but not 100% tested. This parameter is periodically sampled.
4. Tested with load in Figure 2.
IS61SP6464
Integrated Circuit Solution Inc. S3-19
SNOOZE AND RECOVERY CYCLE TIMING
Single Read
High-Z
High-Z
DATAOUT
DATAIN
OE
CE2, CE3
CE2, CE3
CE
BW8-BW1
BWE
GW
A15-A0
ADV
ADSC
ADSP
CLK
RD1
1a
Read
Snooze with Data Retention
tKC
tKLtKH
tSS tSH
tAS tAH
RD2
tCES tCEH
tCES tCEH
tCES tCEH
tOEQ
tOEQX
tOELZ
tKQLZ
tKQ
tOEHZ
tKQX
tKQHZ
ZZ
tZZS tZZREC
IS61SP6464
20 Integrated Circuit Solution Inc.
SSR009-0B
ORDERING INFORMATION
Commercial Range: 0°C to +70°C
Speed Order Part Number Package
133 IS61SP6464-133TQ 14*20*1.4mm LQFP
IS61SP6464-133PQ 14*20*2.7mm PQFP
117 IS61SP6464-117TQ 14*20*1.4mm LQFP
IS61SP6464-117PQ 14*20*2.7mm PQFP
100 IS61SP6464-100TQ 14*20*1.4mm LQFP
IS61SP6464-100PQ 14*20*2.7mm PQFP
83 IS61SP6464-6TQ 14*20*1.4mm LQFP
IS61SP6464-6PQ 14*20*2.7mm PQFP
75 IS61SP6464-7TQ 14*20*1.4mm LQFP
IS61SP6464-7PQ 14*20*2.7mm PQFP
66 IS61SP6464-8TQ 14*20*1.4mm LQFP
IS61SP6464-8PQ 14*20*2.7mm PQFP
Integrated Circuit Solution Inc.
HEADQUARTER:
NO.2, TECHNOLOGY RD. V, SCIENCE-BASED INDUSTRIAL PARK,
HSIN-CHU, TAIWAN, R.O.C.
TEL: 886-3-5780333
Fax: 886-3-5783000
BRANCH OFFICE:
7F, NO. 106, SEC. 1, HSIN-TAI 5TH ROAD,
HSICHIH TAIPEI COUNTY, TAIWAN, R.O.C.
TEL: 886-2-26962140
FAX: 886-2-26962252
http://www.icsi.com.tw
