Data Sheet ADuM4135
Rev. C | Page 13 of 17
For the following design example, see the schematic shown in
Figure 28 along with the waveforms in Figure 21. Under normal
operation, during IGBT off times, the voltage across the IGBT,
VCE, rises to the rail voltage supplied to the system. In this case,
the blocking diode shuts off, protecting the ADuM4135 from
high voltages. During the off times, the internal desaturation
switch is on, accepting the current going through the RBLANK
resistor, which allows the CBLANK capacitor to remain at a low
voltage. For the first 300 ns of the IGBT on time, the DESAT
switch remains on, clamping the DESAT pin voltage low. After
the 300 ns delay time, the DESAT pin is released, and the DESAT
pin is allowed to rise towards VDD2 either by the internal current
source on the DESAT pin, or additionally with an optional external
pull-up, RBLANK, to increase the current drive if it is not clamped
by the collector or drain of the switch being driven. VRDESAT is
chosen to dampen the current at this time, usually selected around
100 Ω to 2 kΩ. Select the blocking diode to block above the
high rail voltage on the collector of the IGBT and to be a fast
recovery diode.
In the case of a desaturation event, VCE rises above the 9 V
threshold in the desaturation detection circuit. If no RBLANK resistor
is used to increase the blanking current, the voltage on the blanking
capacitor, CBLANK, rises at a rate of 500 µA (typical) divided by the
CBLANK capacitance. Depending on the IGBT specifications, a
blanking time of approximately 2 µs is a typical design choice.
When the DESAT pin rises above the 9 V threshold, a fault
registers, and within 200 ns, the gate output drives low. The
output is brought low using the N-FET fault MOSFET, which
is approximately 50 times more resistive than the internal gate
driver N-FET, to perform a soft shutdown to reduce the chance
of an overvoltage spike on the IGBT during an abrupt turn-off
event. Within 2 µs, the fault is communicated back to the primary
side FAULT pin. To clear the fault, a reset is required.
Miller Clamp
The ADuM4135 has an integrated Miller clamp to reduce voltage
spikes on the IGBT gate caused by the Miller capacitance during
shut-off of the IGBT. When the input gate signal calls for the IGBT
to turn off (driven low), the Miller clamp MOSFET is initially
off. When the voltage on the GATE_SENSE pin crosses the 2 V
internal voltage reference, as referenced to VSS2, the internal
Miller clamp latches on for the remainder of the off time of the
IGBT, creating a second low impedance current path for the gate
current to follow. The Miller clamp switch remains on until the
input drive signal changes from low to high. An example waveform
of the timings is shown in Figure 22.
ONOFF OFF
V
I
+
V
I
–
V
GATE_SENSE
V
DD2
V
SS2
2V
LATCH ON
MILLER
CLAMP
SWITCH
LATCH OFF
13082-022
Figure 22. Miller Clamp Example
Thermal Shutdown
If the internal temperature of the ADuM4135 exceeds 155°C
(typical), the device enters thermal shutdown (TSD). During
the thermal shutdown time, the READY pin is brought low
on the primary side, and the gate drive is disabled. When
TSD occurs, the device does not leave TSD until the internal
temperature drops below 125°C (typical), at which time the
READY pin returns to high, and the device exits shutdown.
Undervoltage Lockout (UVLO) Faults
UVLO faults occur when the supply voltages are below the
specified UVLO threshold values. During a UVLO event on either
the primary side or secondary side, the READY pin goes low, and
the gate drive is disabled. When the UVLO condition is removed,
the device resumes operation, and the READY pin goes high.
READY Pin
The open-drain READY pin is an output that confirms
communication between the primary to secondary sides is
active. The READY pin remains high when there are no UVLO
or TSD events present. When the READY pin is low, the IGBT
gate is driven low.
Table 11. READY Pin Logic Table
UVLO TSD READY Pin Output
No No High
Yes No Low
Yes Yes Low