TPS65023QRSBRQ1 - Texas Instruments

TPS65023-Q1

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SLVS927D –MARCH 2009–REVISED SEPTEMBER 2011

POWER MANAGEMENT IC FOR LI-ION POWERED SYSTEMS

Check for Samples: TPS65023-Q1

1FEATURES

23•Qualified for Automotive Applications •Separate Enable Pins for Inductive Converters

•1.5 A, 90% Efficient Step-Down Converter for •I2C™Compatible Serial Interface

Processor Core (VDCDC1) •85-μA Quiescent Current

•1.2 A, Up to 95% Efficient Step-Down •Low Ripple PFM Mode

Converter for System Voltage (VDCDC2) •Thermal Shutdown Protection

•1.0 A, 92% Efficient Step-Down Converter for •40-Pin 5-mmx5-mm QFN (RSB) or

Memory Voltage (VDCDC3) 6-mmx6-mm QFN (RHA) Package

•30 mA LDO/Switch for Real Time Clock (VRTC)

•2×200 mA General-Purpose LDO APPLICATIONS

•Dynamic Voltage Management for Processor •Digital Media Players

Core •Internet Audio Player

•Preselectable LDO Voltage Using Two Digital •Digital Still Camera

Input Pins •Digital Radio Player

•Externally Adjustable Reset Delay Time •Supply DaVinci™DSP Family Solutions

•Battery Backup Functionality

DESCRIPTION

The TPS65023 is an integrated Power Management IC for applications powered by one Li-Ion or Li-Polymer cell,

and which require multiple power rails. The TPS65023 provides three highly efficient, step-down converters

targeted at providing the core voltage, peripheral, I/O and memory rails in a processor based system. The core

converter allows for on-the-fly voltage changes via serial interface, allowing the system to implement dynamic

power savings. All three step-down converters enter a low-power mode at light load for maximum efficiency

across the widest possible range of load currents. The TPS65023 also integrates two general-purpose 200 mA

LDO voltage regulators, which are enabled with an external input pin. Each LDO operates with an input voltage

range between 1.5 V and 6.5 V, allowing them to be supplied from one of the step-down converters or directly

from the battery. The default output voltage of the LDOs can be digitally set to 4 different voltage combinations

using the DEFLDO1 and DEFLDO2 pins. The serial interface can be used for dynamic voltage scaling, masking

interrupts, or for dis/enabling and setting the LDO output voltages. The interface is compatible with the

Fast/Standard mode I2C specification, allowing transfers at up to 400 kHz. The TPS65023 is available in 40-pin

QFN packages (RHA and RSB), and operates over a free-air temperature of –40°C to 125°C.

ORDERING INFORMATION(1)

TAPACKAGE(2) ORDERABLE PART NUMBER TOP-SIDE MARKING

QFN –RSB Reel of 3000 TPS65023QRSBRQ1 TPS65023Q

–40°C to 125°CQFN –RHA Reel of 2500 TPS65023QRHARQ1 65023QRHA

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI

web site at www.ti.com.

(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2DaVinci, PowerPAD are trademarks of Texas Instruments.

3I2C is a trademark of Philips Electronics.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

TPS65023-Q1

SLVS927D –MARCH 2009–REVISED SEPTEMBER 2011

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This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

ABSOLUTE MAXIMUM RATINGS(1)

over operating free-air temperature range (unless otherwise noted)

VIInput voltage range on all pins except AGND and PGND pins with respect to AGND –0.3 V to 7 V

Current at VINDCDC1, L1, PGND1, VINDCDC2, L2, PGND2, VINDCDC3, L3, PGND3 2000 mA

Peak current at all other pins 1000 mA

Continuous total power dissipation See Dissipation Rating Table

TAOperating free-air temperature –40°C to 125°C

TJMaximum junction temperature 125°C

Tstg Storage temperature –65°C to 150°C

Human-body model (HBM) 2000 V

RHA package Machine model (MM) 50 V

Charged-device model (CDM) 750 V

ESD Electrostatic discharge protection Human-body model (HBM) 2000 V

RSB package Machine model (MM) 100 V

Charged-device model (CDM) 1000 V

(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings

only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating

conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability

THERMAL INFORMATION TPS65023-Q1

THERMAL METRIC(1) RHA UNITS

40 PINS

θJA Junction-to-ambient thermal resistance 31.6

θJCtop Junction-to-case (top) thermal resistance 18.2

θJB Junction-to-board thermal resistance 6.6 °C/W

ψJT Junction-to-top characterization parameter 0.2

ψJB Junction-to-board characterization parameter 6.5

θJCbot Junction-to-case (bottom) thermal resistance 1.7

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

DISSIPATION RATINGS THERMAL RESISTANCE,

TA≤25°C TA= 70°C TA= 85°C

PACKAGE JUNCTION TO AMBIENT

POWER RATING POWER RATING POWER RATING

(RθJA)

RSB(1) 2.65 W 39°C/W 1.41 W 1.025 W

RHA(2) 3.175 W 31.5°C/W 1.746 W 1.269 W

(1) The thermal resistance, junction-to-ambient (RθJA), of the RSB package is 39°C/W measured on a high-K board.

(2) The thermal resistance, junction-to-ambient (RθJA), of the RHA package is 31.5°C/W measured on a high-K board.

Product Folder Link(s): TPS65023-Q1

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SLVS927D –MARCH 2009–REVISED SEPTEMBER 2011

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT

Input voltage range step-down converters

VCC 2.5 6 V

(VINDCDC1, VINDCDC2, VINDCDC3)

Output voltage range for VDCDC1 step-down converter(1) 0.6 VINDCDC1

VOOutput voltage range for VDCDC2 step-down converter(1) 0.6 VINDCDC2 V

Output voltage range for VDCDC3 step-down converter(1) 0.6 VINDCDC3

VIInput voltage range for LDOs (VINLDO1, VINLDO2) 1.5 6.5 V

VOOutput voltage range for LDOs (VLDO1, VLDO2) 1 VINLDO1-2 V

IO(DCDC1) Output current at L1 1500 mA

Inductor at L1(2) 1.5 2.2 μH

CI(DCDC1) Input capacitor at VINDCDC1 (2) 10 μF

CO(DCDC1) Output capacitor at VDCDC1 (2) 10 22 μF

IO(DCDC2) Output current at L2 1200 mA

Inductor at L2 (2) 1.5 2.2 μH

CI(DCDC2) Input capacitor at VINDCDC2 (2) 10 μF

CO(DCDC2) Output capacitor at VDCDC2 (2) 10 22 μF

IO(DCDC3) Output current at L3 1000 mA

Inductor at L3 (2) 1.5 2.2 μH

CI(DCDC3) Input capacitor at VINDCDC3(2) 10 μF

CO(DCDC3) Output capacitor at VDCDC3 (2) 10 22 μF

CI(VCC) Input capacitor at VCC (2) 1μF

Ci(VINLDO) Input capacitor at VINLDO (2) 1μF

CO(VLDO1-2) Output capacitor at VLDO1, VLDO2 (2) 2.2 μF

IO(VLDO1-2) Output current at VLDO1, VLDO2 200 mA

CO(VRTC) Output capacitor at VRTC (2) 4.7 μF

TAOperating ambient temperature –40 125 °C

TJOperating junction temperature –40 125 °C

Resistor from VINDCDC3, VINDCDC2, VINDCDC1 to VCC used for filtering(3) 1 10 Ω

(1) When using an external resistor divider at DEFDCDC3, DEFDCDC2, DEFDCDC1

(2) See Applications Information section for more information.

(3) Up to 3 mA can flow into VCC when all three converters are running in PWM. This resistor causes the UVLO threshold to be shifted

accordingly.

Product Folder Link(s): TPS65023-Q1

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SLVS927D –MARCH 2009–REVISED SEPTEMBER 2011

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ELECTRICAL CHARACTERISTICS

VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA=–40°C to 125°C, typical values are

at TA= 25°C (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

CONTROL SIGNALS : SCLK, SDAT (input), DCDC1_EN, DCDC2_EN, DCDC3_EN, LDO_EN, DEFLDO1, DEFLDO2

Resistor pullup at SCLK and SDAT = 4.7 kΩ,

VIH High level input voltage 1.3 VCC V

pulled to VRTC

Resistor pullup at SCLK and SDAT = 4.7 kΩ,

VIH High level input voltage, SDAT 1.45 VCC V

pulled to VRTC

Resistor pullup at SCLK and SDAT = 4.7 kΩ,

VIL Low level input voltage 0 0.4 V

pulled to VRTC

IHInput bias current 0.01 0.1 μA

CONTROL SIGNALS : HOT_RESET

VIH High-level input voltage 1.3 VCC V

VIL Low-level input voltage 0 0.4 V

IIB Input bias current 0.01 0.1 μA

tglitch Deglitch time at HOT_RESET 25 30 35 ms

CONTROL SIGNALS : LOWBAT, PWRFAIL, RESPWRON, INT, SDAT (output)

VOH High-level output voltage 6 V

VOL Low-level output voltage IIL = 5 mA 0 0.3 V

Duration of low pulse at RESPWRON External capacitor 1 nF 100 ms

VRTC falling –3% 2.4 +3%

Reset power-on threshold V

VRTC rising –3% 2.52 +3%

Product Folder Link(s): TPS65023-Q1

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SLVS927D –MARCH 2009–REVISED SEPTEMBER 2011

ELECTRICAL CHARACTERISTICS

VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA=–40°C to 125°C, typical values are

at TA= 25°C (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SUPPLY PINS: VCC, VINDCDC1, VINDCDC2, VINDCDC3

All three dc-dc converters enabled, VCC = 3.6 V, VBACKUP = 3 V,

zero load, and no switching, LDOs 85 100

V(VSYSIN) = 0 V

enabled

All three dc-dc converters enabled, VCC = 3.6 V, VBACKUP = 3 V,

zero load, and no switching, LDOs 78 90

V(VSYSIN) = 0 V

Operating quiescent off

I(q) μA

current, PFM DCDC1 and DCDC2 converters VCC = 3.6 V, VBACKUP = 3 V,

enabled, zero load, and no 57 70

V(VSYSIN) = 0 V

switching, LDOs off

DCDC1 converter enabled, zero VCC = 3.6 V, VBACKUP = 3 V, 43 55

load, and no switching, LDOs off V(VSYSIN) = 0 V

All three dc-dc converters enabled VCC = 3.6 V, VBACKUP = 3 V, 2 3

and running in PWM, LDOs off V(VSYSIN) = 0 V

DCDC1 and DCDC2 converters

Current into VCC, VCC = 3.6 V, VBACKUP = 3 V,

IIenabled and running in PWM, 1.5 2.5 mA

PWM V(VSYSIN) = 0 V

LDOs off

DCDC1 converter enabled and VCC = 3.6 V, VBACKUP = 3 V, 0.85 2

running in PWM, LDOs off V(VSYSIN) = 0 V

VCC = 3.6 V, VBACKUP = 3 V, 23 33 μA

V(VSYSIN) = 0 V

VCC = 2.6 V, VBACKUP = 3 V,

I(q) Quiescent current All converters disabled, LDOs off 3.5 5 μA

V(VSYSIN) = 0 V

VCC = 3.6 V, VBACKUP = 0 V, 43 μA

V(VSYSIN) = 0 V

Product Folder Link(s): TPS65023-Q1

TPS65023-Q1

SLVS927D –MARCH 2009–REVISED SEPTEMBER 2011

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ELECTRICAL CHARACTERISTICS

VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA=–40°C to 125°C, typical values are

at TA= 25°C (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SUPPLY PINS: VBACKUP, VSYSIN, VRTC

VBACKUP = 3 V, VSYSIN = 0 V,

I(q) Operating quiescent current 20 33 μA

VCC = 2.6 V, current into VBACKUP

VBACKUP <V_VBACKUP, current into

I(SD) Operating quiescent current 2 3 μA

VBACKUP

VRTC LDO output voltage VSYSIN = VBACKUP = 0 V, IO= 0 mA 3 V

IOOutput current for VRTC VSYSIN <2.57 V and VBACKUP <2.57 V 30 mA

VRTC short-circuit current limit VRTC = GND, VSYSIN = VBACKUP = 0 V 100 mA

Maximum output current at VRTC for VRTC >2.6 V, VCC = 3 V, 30 mA

RESPWRON = 1 VSYSIN = VBACKUP = 0 V

VOOutput voltage accuracy for VRTC VSYSIN = VBACKUP = 0 V, IO= 0 mA –1% 1%

Line regulation for VRTC VCC = VRTC + 0.5 V to 6.5 V, IO= 5 mA –1% 1%

IO= 1 mA to 30 mA,

Load regulation VRTC –3% 1%

VSYSIN = VBACKUP = 0 V

Regulation time for VRTC Load change from 10% to 90% 10 μs

Ilkg Input leakage current at VSYSIN VSYSIN <V_VSYSIN 2 μA

rDS(on) of VSYSIN switch 12.5 Ω

rDS(on) of VBACKUP switch 12.5 Ω

Input voltage range at VBACKUP(1) 2.73 3.75 V

Input voltage range at VSYSIN(1) 2.73 3.75 V

VSYSIN threshold VSYSIN falling –3% 2.55 3% V

VSYSIN threshold VSYSIN rising –3% 2.65 3% V

VBACKUP threshold VBACKUP falling –3% 2.55 3% V

VBACKUP threshold VBACKUP falling –3% 2.65 3% V

SUPPLY PIN: VINLDO

I(q) Operating quiescent current Current per LDO into VINLDO 16 30 μA

Total current for both LDOs into VINLDO,

I(SD) Shutdown current 0.1 1 μA

VLDO = 0 V

(1) Based on the requirements for the Intel PXA270 processor.

Product Folder Link(s): TPS65023-Q1

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SLVS927D –MARCH 2009–REVISED SEPTEMBER 2011

ELECTRICAL CHARACTERISTICS

VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA=–40°C to 125°C, typical values are

at TA= 25°C (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VDCDC1 STEP-DOWN CONVERTER

VIInput voltage range, VINDCDC1 2.5 6 V

IOMaximum output current 1500 mA

I(SD) Shutdown supply current in VINDCDC1 DCDC1_EN = GND 0.1 1 μA

rDS(on) P-channel MOSFET on-resistance VINDCDC1 = V(GS) = 3.6 V 125 261 mΩ

Ilkg P-channel leakage current VINDCDC1 = 6 V 2 μA

rDS(on) N-channel MOSFET on-resistance VINDCDC1 = V(GS) = 3.6 V 130 260 mΩ

Ilkg N-channel leakage current V(DS) = 6 V 7 10 μA

Forward current limit 2.5 V <VI(MAIN) <6 V 1.9 2.19 2.6 A

(P-channel and N-channel)

fSOscillator frequency 1.95 2.25 2.55 MHz

Fixed output voltage VINDCDC1 = 2.5 V to 6 V, –2 2

FPWMDCDC1=0 0 mA ≤IO≤1.5 A

All VDCDC1 %

Fixed output voltage VINDCDC1 = 2.5 V to 6 V, –1 1

FPWMDCDC1=1 0 mA ≤IO≤1.5 A

Adjustable output voltage with resistor VINDCDC1 = VDCDC1 + 0.3 V (min 2.5 V) –2 2 %

divider at DEFDCDC1, FPWMDCDC1=0 to 6 V, 0 mA ≤IO≤1.2 A

Adjustable output voltage with resistor VINDCDC1 = VDCDC1 + 0.3 V (min 2.5 V) –1 1 %

divider at DEFDCDC1, FPWMDCDC1=1 to 6 V, 0 mA ≤IO≤1.2 A

VINDCDC1 = VDCDC1 + 0.3 V (min. 2.5 V)

Line Regulation 0 %/V

to 6 V, IO= 10 mA

Load Regulation IO= 10 mA to 1200 mA 0.25 %/A

VDCDC1 ramping from 5% to 95% of target

Soft start ramp time 750 μs

value

Internal resistance from L1 to GND 1 MΩ

VDCDC1 discharge resistance DCDC1 discharge = 1 300 Ω

Product Folder Link(s): TPS65023-Q1

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SLVS927D –MARCH 2009–REVISED SEPTEMBER 2011

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ELECTRICAL CHARACTERISTICS

VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA=–40°C to 125°C, typical values are

at TA= 25°C (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VDCDC2 STEP-DOWN CONVERTER

VIInput voltage range, VINDCDC2 2.5 6 V

DEFDCDC2 = GND 1200

IOMaximum output current mA

VINDCDC2 = 3.6 V, 1000

3.3 V - 1% ≤VDCDC2 ≤3.3 V + 1%

I(SD) Shutdown supply current in VINDCDC2 DCDC2_EN = GND 0.1 1 μA

rDS(on) P-channel MOSFET on-resistance VINDCDC2 = V(GS) = 3.6 V 140 300 mΩ

Ilkg P-channel leakage current VINDCDC2 = 6 V 2 μA

rDS(on) N-channel MOSFET on-resistance VINDCDC2 = V(GS) = 3.6 V 150 297 mΩ

Ilkg N-channel leakage current V(DS) = 6 V 7 10 μA

Forward current limit

ILIMF 2.5 V <VINDCDC2 <6 V 1.7 1.94 2.2 A

(P-channel and N-channel)

fSOscillator frequency 1.95 2.25 2.55 MHz

VINDCDC2 = 2.5 V to 6 V,

VDCDC2 = 1.8 V –2 2

0 mA ≤IO≤1.2 A

Fixed output voltage %

FPWMDCDC2=0 VINDCDC2 = 3.7 V to 6 V,

VDCDC2 = 3.3 V –1 1

0 mA ≤IO≤1.2 A

VINDCDC2 = 2.5 V to 6 V,

VDCDC2 = 1.8 V –2 2

0 mA ≤IO≤1.2 A

Fixed output voltage %

FPWMDCDC2=1 VINDCDC2 = 3.7 V to 6 V,

VDCDC2 = 3.3 V –1 1

0 mA ≤IO≤1.2 A

Adjustable output voltage with resistor VINDCDC2 = VDCDC2 + 0.3 V (min 2.5 V) –2% 2%

divider at DEFDCDC2 FPWMDCDC2=0 to 6 V, 0 mA ≤IO≤1 A

Adjustable output voltage with resistor VINDCDC2 = VDCDC2 + 0.3 V (min 2.5 V) –1% 1%

divider at DEFDCDC2, FPWMDCDC2=1 to 6 V, 0 mA ≤IO≤1 A

VINDCDC2 = VDCDC2 + 0.3 V (min. 2.5 V)

Line Regulation 0 %/V

to 6 V, IO= 10 mA

Load Regulation IO= 10 mA to 1000 mA 0.25 %/A

VDCDC2 ramping from 5% to 95% of target

Soft start ramp time 750 μs

value

Internal resistance from L2 to GND 1 MΩ

VDCDC2 discharge resistance DCDC2 discharge =1 300 Ω

Product Folder Link(s): TPS65023-Q1

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SLVS927D –MARCH 2009–REVISED SEPTEMBER 2011

ELECTRICAL CHARACTERISTICS

VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA=–40°C to 125°C, typical values are

at TA= 25°C (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VDCDC3 STEP-DOWN CONVERTER

VIInput voltage range, VINDCDC3 2.5 6 V

DEFDCDC3 = GND 1000

IOMaximum output current mA

VINDCDC3 = 3.6 V, 525

3.3 V - 1% ≤VDCDC3 ≤3.3 V + 1%

I(SD) Shutdown supply current in VINDCDC3 DCDC3_EN = GND 0.1 1 μA

rDS(on) P-channel MOSFET on-resistance VINDCDC3 = V(GS) = 3.6 V 310 698 mΩ

Ilkg P-channel leakage current VINDCDC3 = 6 V 0.1 2 μA

rDS(on) N-channel MOSFET on-resistance VINDCDC3 = V(GS) = 3.6 V 220 503 mΩ

Ilkg N-channel leakage current V(DS) = 6 V 7 10 μA

Forward current limit (P-channel and 2.5 V <VINDCDC3 <6 V 1.28 1.49 1.69 A

N-channel)

fSOscillator frequency 1.95 2.25 2.55 MHz

VINDCDC3 = 2.5 V to 6 V,

VDCDC3 = 1.8 V –2 2

0 mA ≤IO≤1 A

Fixed output voltage %

FPWMDCDC3=0 VINDCDC3 = 3.6 V to 6 V,

VDCDC3 = 3.3 V –1 1

0 mA ≤IO≤1 A

VINDCDC3 = 2.5 V to 6 V,

VDCDC3 = 1.8 V –2 2

0 mA ≤IO≤1 A

Fixed output voltage %

FPWMDCDC3=1 VINDCDC3 = 3.6 V to 6 V,

VDCDC3 = 3.3 V –1 1

0 mA ≤IO≤1 A

Adjustable output voltage with resistor VINDCDC3 = VDCDC3 + 0.5 V (min 2.5 V) –2% 2%

divider at DEFDCDC3 FPWMDCDC3=0 to 6 V, 0 mA ≤IO≤800 mA

Adjustable output voltage with resistor VINDCDC3 = VDCDC3 + 0.5 V (min 2.5 V) –1% 1%

divider at DEFDCDC3, FPWMDCDC3=1 to 6 V, 0 mA ≤IO≤800 mA

VINDCDC3 = VDCDC3 + 0.3 V (min. 2.5 V)

Line Regulation 0 %/V

to 6 V, IO= 10 mA

Load Regulation IO= 10 mA to 1000 mA 0.25 %/A

VDCDC3 ramping from 5% to 95% of target

Soft start ramp time 750 μs

value

Internal resistance from L3 to GND 1 MΩ

VDCDC3 discharge resistance DCDC3 discharge =1 300 Ω

Product Folder Link(s): TPS65023-Q1

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ELECTRICAL CHARACTERISTICS

VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA=–40°C to 125°C, typical values are

at TA= 25°C (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

VLDO1 and VLDO2 LOW DROPOUT REGULATORS

VIInput voltage range for LDO1, 2 1.5 6.5 V

VO(LD01) LDO1 output voltage range 1 3.15 V

VO(LDO2) LDO2 output voltage range 1 3.3 V

VI= 1.8 V, VO= 1.3 V 200

Maximum output current for LDO1,

IOmA

LDO2 VI= 1.5 V, VO= 1.3 V 120

LDO1 and LDO2 short circuit

I(SC) V(LDO1) = GND, V(LDO2) = GND 400 mA

current limit IO= 50 mA, VINLDO = 1.8 V 120

Minimum voltage drop at LDO1, IO= 50 mA, VINLDO = 1.5 V 65 150 mV

LDO2 IO= 200 mA, VINLDO = 1.8 V 300

Output voltage accuracy for LDO1, IO= 10 mA –2% 1%

LDO2 VINLDO1, 2 = VLDO1,2 + 0.5 V

Line regulation for LDO1, LDO2 –1% 1%

(min. 2.5 V) to 6.5 V, IO= 10 mA

Load regulation for LDO1, LDO2 IO= 0 mA to 50 mA –1% 1%

Regulation time for LDO1, LDO2 Load change from 10% to 90% 10 μs

ANALOG SIGNALS DEFDCDC1, DEFDCDC2, DEFDCDC3

VIH High-level input voltage 1.3 VCC V

VIL Low-level input voltage 0 0.1 V

Input bias current 0.001 0.05 μA

THERMAL SHUTDOWN

T(SD) Thermal shutdown Increasing junction temperature 160 °C

Thermal shutdown hysteresis Decreasing junction temperature 20 °C

INTERNAL UNDERVOLTAGE LOCK OUT

UVLO Internal UVLO VCC falling –2% 2.35 2% V

Internal UVLO comparator

V(UVLO_HYST) 120 mV

hysteresis

VOLTAGE DETECTOR COMPARATORS

Comparator threshold Falling threshold –2% 1 2% V

(PWRFAIL_SNS, LOWBAT_SNS)

Hysteresis 40 50 60 mV

Propagation delay 25-mV overdrive 10 μs

POWER GOOD

VDCDC1, VDCDC2, VDCDC3, VLDO1,

V(PGOODF) –12% –10% –8%

VLDO2, decreasing

VDCDC1, VDCDC2, VDCDC3, VLDO1,

V(PGOODR) –7% –5% –3%

VLDO2, increasing

Product Folder Link(s): TPS65023-Q1

11 12 13 14 15 16 17 18 19 20

40 39 38 37 36 35 34 33 32 31

DEFDCDC3

VDCDC3

PGND3

VINDCDC3

VINDCDC1

PGND1

VDCDC1

DEFDCDC1

HOT_RESET

DEFLDO1

DEFLDO2

VSYSIN

VBACKUP

VRTC

AGND2

VINLDO

VLDO1

VLDO2

SCLK

SDAT

INT

RESPWRON

TRESPWRON

DCDC1_EN

DCDC2_EN

DCDC3_EN

LDO_EN

LOWBAT

AGND1

LOWBAT_SNS

PWRFAIL_SNS

VCC

VINDCDC2

PGND2

VDCDC2

DEFDCDC2

PWRFAIL

TPS65023-Q1

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SLVS927D –MARCH 2009–REVISED SEPTEMBER 2011

PIN ASSIGNMENT

(TOP VIEW)

TERMINAL FUNCTIONS

TERMINAL I/O DESCRIPTION

NAME NO.

SWITCHING REGULATOR SECTION

AGND1 40 Analog ground. All analog ground pins are connected internally on the chip.

AGND2 17 Analog ground. All analog ground pins are connected internally on the chip.

PowerPAD™ – Connect the exposed thermal pad to analog ground.

Input voltage for VDCDC1 step-down converter. VINDCDC1 must be connected to the same voltage

VINDCDC1 6 I supply as VINDCDC2, VINDCDC3, and VCC.

L1 7 Switch pin of VDCDC1 converter. The VDCDC1 inductor is connected here.

VDCDC1 9 I VDCDC1 feedback voltage sense input. Connect directly to VDCDC1

PGND1 8 Power ground for VDCDC1 converter.

Input voltage for VDCDC2 step-down converter. VINDCDC2 must be connected to the same voltage

VINDCDC2 36 I supply as VINDCDC1, VINDCDC3, and VCC.

L2 35 Switch pin of VDCDC2 converter. The VDCDC2 inductor is connected here.

VDCDC2 33 I VDCDC2 feedback voltage sense input. Connect directly to VDCDC2

PGND2 34 Power ground for VDCDC2 converter

Input voltage for VDCDC3 step-down converter. VINDCDC3 must be connected to the same voltage

VINDCDC3 5 I supply as VINDCDC1, VINDCDC2, and VCC.

L3 4 Switch pin of VDCDC3 converter. The VDCDC3 inductor is connected here.

VDCDC3 2 I VDCDC3 feedback voltage sense input. Connect directly to VDCDC3

PGND3 3 Power ground for VDCDC3 converter.

Product Folder Link(s): TPS65023-Q1

TPS65023-Q1

SLVS927D –MARCH 2009–REVISED SEPTEMBER 2011

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TERMINAL FUNCTIONS (continued)

TERMINAL I/O DESCRIPTION

NAME NO.

Power supply for digital and analog circuitry of VDCDC1, VDCDC2, and VDCDC3 dc-dc converters.

VCC 37 I VCC must be connected to the same voltage supply as VINDCDC3, VINDCDC1, and VINDCDC2.

VCC also supplies serial interface block.

Input signal indicating default VDCDC1 voltage, 0 = 1.2 V, 1 = 1.6 V DEFDCDC1 can also be

DEFDCDC1 10 I connected to a resistor divider between VDCDC1 and GND, if the output voltage of the DCDC1

converter is set in a range from 0.6 V to VINDCDC1 V.

Input signal indicating default VDCDC2 voltage, 0 = 1.8 V, 1 = 3.3 V DEFDCDC2 can also be

DEFDCDC2 32 I connected to a resistor divider between VDCDC2 and GND, if the output voltage of the DCDC2

converter is set in a range from 0.6 V to VINDCDC2 V.

Input signal indicating default VDCDC3 voltage, 0 = 1.8 V, 1 = 3.3 V DEFDCDC3 can also be

DEFDCDC3 1 I connected to a resistor divider between VDCDC3 and GND, if the output voltage of the DCDC3

converter is set in a range from 0.6 V to VINDCDC3 V.

DCDC1_EN 25 I VDCDC1 enable pin. A logic high enables the regulator, a logic low disables the regulator.

DCDC2_EN 24 I VDCDC2 enable pin. A logic high enables the regulator, a logic low disables the regulator.

DCDC3_EN 23 I VDCDC3 enable pin. A logic high enables the regulator, a logic low disables the regulator.

LDO REGULATOR SECTION

VINLDO 19 I Input voltage for LDO1 and LDO2

VLDO1 20 O Output voltage of LDO1

VLDO2 18 O Output voltage of LDO2

LDO_EN 22 I Enable input for LDO1 and LDO2. A Logic high enables the LDOs, a logic low disables the LDOs.

VBACKUP 15 I Connect the backup battery to this input pin.

VRTC 16 O Output voltage of the LDO/switch for the real time clock.

VSYSIN 14 I Input of system voltage for VRTC switch.

DEFLD01 12 I Digital input. DEFLD01 sets the default output voltage of LDO1 and LDO2.

DEFLD02 13 I Digital input. DEFLD02 sets the default output voltage of LDO1 and LDO2.

CONTROL AND I2C SECTION

HOT_RESET 11 I Push button input that reboots or wakes up the processor via RESPWRON output pin.

TRESPWRON 26 I Connect the timing capacitor to TRESPWRON to set the reset delay time: 1 nF →100 ms.

RESPWRON 27 O Open drain system reset output.

PWRFAIL 31 O Open drain output. Active low when PWRFAIL comparator indicates low VBAT condition.

LOW_BAT 21 O Open drain output of LOW_BAT comparator.

INT 28 O Open drain output

SCLK 30 I Serial interface clock line

SDAT 29 I/O Serial interface data/address

PWRFAIL_SNS 38 I Input for the comparator driving the PWRFAIL output.

LOWBAT_SNS 39 I Input for the comparator driving the LOW_BAT output.

Product Folder Link(s): TPS65023-Q1

TPS65023

LOW_BATT

VCC

HOT_RESET

INT

RESPWRON

VINDCDC1

DCDC1_EN

PWRFAIL

BBAT

SWITCH

SerialInterface

CONTROL

UVLO

VREF

OSC

Thermal

Shutdown

DCDC1

BuckConverter

1500mA

DCDC2

BuckConverter

1200mA

DCDC3

BuckConverter

1000mA

LDO1

200mA

LDO2

200mA

Dynamic

Voltage

Management

VSYSIN

VBACKUP

VRTC

SCLK

SDAT

DCDC2_EN

DCDC3_EN

LDO_EN

LOWBAT_SNS

PWRFAIL_SNS

TRESPWRON

DEFLDO1

DEFLDO2

VDCDC1

DEFDCDC1

PGND1

VINDCDC2

VDCDC2

DEFDCDC2

PGND2

VINDCDC3

VDCDC3

DEFDCDC3

PGND3

AGND1

VLDO1

AGND2

VINLDO

VLDO2

TPS65023-Q1

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SLVS927D –MARCH 2009–REVISED SEPTEMBER 2011

FUNCTIONAL BLOCK DIAGRAM

Product Folder Link(s): TPS65023-Q1

100

0.01 0.1 1 10 100 1k 10k

I -OutputCurrent-mA

Efficiency-%

T =25°C

V =1.2V

PWM/PFMMode

V =4.2V

V =2.5V

V =3.6V

V =5V

100

0.01 0.1 1 10 100 1k 10k

I -OutputCurrent-mA

Efficiency-%

T =25°C

V =1.2V

PWMMode

V =4.2V

V =2.5V

V =3.6V

V =5V

TPS65023-Q1

SLVS927D –MARCH 2009–REVISED SEPTEMBER 2011

www.ti.com

TYPICAL CHARACTERISTICS

Graphs were taken using the EVM with the following inductor/output capacitor combinations:

CONVERTER INDUCTOR OUTPUT CAPACITOR OUTPUT CAPACITOR VALUE

VDCDC1 VLCF4020-2R2 C2012X5R0J106M 2 ×10 μF

VDCDC2 VLCF4020-2R2 C2012X5R0J106M 2 ×10 μF

VDCDC3 VLF4012AT-2R2M1R5 C2012X5R0J106M 2 ×10 μF

Table 1. Table of Graphs

FIGURE

ηEfficiency vs Output current 1, 2, 3, 4, 5, 6

Output voltage vs Output current @ 85°C 7, 8

Line transient response 9, 10, 11

Load transient response 12, 13, 14

VDCDC2 PFM operation 15

VDCDC2 low ripple PFM operation 16

VDCDC2 PWM operation 17

Startup VDCDC1, VDCDC2 and VDCDC3 18

Startup LDO1 and LDO2 19

Line transient response 20, 21, 22

Load transient response 23, 24, 25

DCDC1: EFFICIENCY DCDC1: EFFICIENCY

vs vs

OUTPUT CURRENT OUTPUT CURRENT

Figure 1. Figure 2.

Product Folder Link(s): TPS65023-Q1

100

0.01 0.1 1 10 100 1k 10k

I -OutputCurrent-mA

Efficiency-%

T =25°C

V =1.8V

PWM/PFMMode

V =4.2V

V =2.5V

V =3.6V

V =5V

100

0.01 0.1 1 10 100 1k 10k

I -OutputCurrent-mA

Efficiency-%

T =25°C

V =1.8V

PWMMode

V =4.2V

V =2.5V

V =3.6V

V =5V

100

0.01 0.1 1 10 100 1k 10k

I -OutputCurrent-mA

Efficiency-%

T =25°C

V =1.8V

PWM/PFMMode

V =4.2V

V =2.5V

V =3.6V

V =5V

100

0.01 0.1 1 10 100 1k 10k

I -OutputCurrent-mA

Efficiency-%

T =25°C

V =1.8V

PWMMode

V =4.2V

V =2.5V

V =3.6V

V =5V

TPS65023-Q1

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SLVS927D –MARCH 2009–REVISED SEPTEMBER 2011

DCDC2: EFFICIENCY DCDC2: EFFICIENCY

vs vs

OUTPUT CURRENT OUTPUT CURRENT

Figure 3. Figure 4.

DCDC3: EFFICIENCY DCDC3: EFFICIENCY

vs vs

OUTPUT CURRENT OUTPUT CURRENT

Figure 5. Figure 6.

Product Folder Link(s): TPS65023-Q1

3.234

3.254

3.274

3.294

3.314

3.334

3.354

0.1 110

I -OutputCurrent- A

V -OutputVoltage-V

T =85°C

DEFDCDC2=VINDCDC2

V =3.8V

V =3.7V

V =3.6V

V =3.5V

3.234

3.254

3.274

3.294

3.314

3.334

3.354

I -OutputCurrent- A

V -OutputVoltage-V

T =85°C

DEFDCDC3=VINDCDC3

V =3.8V

V =3.7V

V =3.6V

0.1 110

V =4V

V =3.9V

V =3.5V

C1High

4.71V

C1Low

3.68V

C2Pk-Pk

28.5mV

C2Mean

1.18925V

VINDCDC1

VDCDC1

I =100mA

VINDCDC1=3.7V-4.7V

DEFDCDC1=VINDCDC1

PWWMode

C2Pk-Pk

48.9mV

C2Mean

1.81053V

C1High

4.01V

C1Low

3.02V

VINDCDC2

VDCDC2

I =100mA

VINDCDC2=3V-4V

DEFDCDC2=GND

PWWMode

TPS65023-Q1

SLVS927D –MARCH 2009–REVISED SEPTEMBER 2011

www.ti.com

DCDC2: OUTPUT VOLTAGE DCDC3: OUTPUT VOLTAGE

vs vs

OUTPUT CURRENT at 85°C OUTPUT CURRENT at 85°C

Figure 7. Figure 8.

VDCDC1 LINE TRANSIENT RESPONSE VDCDC2 LINE TRANSIENT RESPONSE

Figure 9. Figure 10.

Product Folder Link(s): TPS65023-Q1

C1High

4.20V

C1Low

3.59V

C2Pk-Pk

60.4mV

C2Mean

3.28264V

VINDCDC3

VDCDC3

I =100mA

VINDCDC3=3.6V-4.2V

DEFDCDC3=VINDCDC3

PWWMode

VDCDC3=3.3V@50mV/Div

(ACCoupled)

ILOAD@500mA/Div

100mA

800mA

VIN=3.8V TIMESCALE=50 s/Divm

TPS65023-Q1

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SLVS927D –MARCH 2009–REVISED SEPTEMBER 2011

VDCDC3 LINE TRANSIENT RESPONSE VDCDC1 LOAD TRANSIENT RESPONSE

Figure 11. Figure 12.

VDCDC2 LOAD TRANSIENT RESPONSE VDCDC3 LOAD TRANSIENT RESPONSE

Figure 13. Figure 14.

Product Folder Link(s): TPS65023-Q1

TPS65023-Q1

SLVS927D –MARCH 2009–REVISED SEPTEMBER 2011

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VDCDC2 OUTPUT VOLTAGE RIPPLE VDCDC2 OUTPUT VOLTAGE RIPPLE

Figure 15. Figure 16.

VDCDC2 OUTPUT VOLTAGE RIPPLE STARTUP VDCDC1, VDCDC2, AND VDCDC3

Figure 17. Figure 18.

Product Folder Link(s): TPS65023-Q1

C1High

3.83V

C1Low

3.29V

C2PK-PK

6.2mV

C2Mean

1.09702V

=Ch1 V

Ch2 V

I =25mA

V =1.1V

T =25 C

ENABLE

LDO1

LDO2

C1High

3.82V

C1Low

3.28V

C2PK-PK

22.8mV

=Ch1 V

Ch2 V

I =10mA

V =3V

T =25 C

C2Mean

2.98454V

C1High

4.51V

C1Low

3.99V

C2PK-PK

6.1mV

=Ch1 V

Ch2 V

I =25mA

V =3.3V

T =25 C

C2Mean

3.29828V

TPS65023-Q1

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SLVS927D –MARCH 2009–REVISED SEPTEMBER 2011

STARTUP LDO1 AND LDO2 LDO1 LINE TRANSIENT RESPONSE

Figure 19. Figure 20.

LDO2 LINE TRANSIENT RESPONSE VRTC LINE TRANSIENT RESPONSE

Figure 21. Figure 22.

Product Folder Link(s): TPS65023-Q1

C4High

47.8mA

C4Low

-2.9mA

C2PK-PK

40.4mV

=Ch2 V

Ch4 I

=4V

V =3.3V

T =25 C

C2Mean

3.29821V

C4High

48.9mA

C4Low

2.1mA

C2PK-PK

42.5mV

=Ch2 V

Ch4

=I

=3.3V

V =1.1V

T =25 C

C2Mean

1.09664V

C4High

21.4mA

C4Low

-1.4mA

C2PK-PK

76mV

=Ch2 V

Ch4 I

=3.8V

V =3V

T =25 C

C2Mean

2.9762V

TPS65023-Q1

SLVS927D –MARCH 2009–REVISED SEPTEMBER 2011

www.ti.com

LDO1 LOAD TRANSIENT RESPONSE LDO2 LOAD TRANSIENT RESPONSE

Figure 23. Figure 24.

VRTC LOAD TRANSIENT RESPONSE

Figure 25.

Product Folder Link(s): TPS65023-Q1

TPS65023-Q1

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SLVS927D –MARCH 2009–REVISED SEPTEMBER 2011

DETAILED DESCRIPTION

VRTC Output and Operation With or Without Backup Battery

The VRTC pin is an always-on output, intended to supply up to 30 mA to a permanently required rail (i.e., for a

real-time clock). The TPS65023 asserts the RESPWRON signal if VRTC drops below 2.4 V. VRTC is selected

from a priority scheme based on the VSYSIN and VBACKUP inputs.

When the voltage at the VSYSIN pin exceeds 2.65 V, VRTC connects to the VSYSIN input via a PMOS switch

and all other paths to VRTC are disabled. The PMOS switch drops a maximum of 375 mV at 30 mA, which

should be considered when using VRTC. VSYSIN can be connected to any voltage source with the appropriate

input voltage, including VCC or, if set to 3.3-V output, DCDC2 or DCDC3. When VSYSIN falls below 2.65 V or

shorts to ground, the PMOS switch connecting VRTC and VSYSIN opens and VRTC then connects to either

VBACKUP or the output of a dedicated 3-V/30-mA LDO. Texas Instruments recommends connecting VSYSIN to

VCC or ground - VCC if a non-replaceable primary cell is connected to VBACKUP and ground if the VRTC

output will float.

If the PMOS switch between VSYSIN and VRTC is open and VBACKUP exceeds 2.65 V, VRTC connects to

VBACKUP via a PMOS switch. The PMOS switch drops a maximum of 375 mV at 30 mA, which should be

considered if using VRTC. A typical application may connect VBACKUP to a primary Li button cell, but any

battery that provides a voltage between 2.65 V and 6 V (i.e. a single Li-Ion cell or a single boosted NiMH battery)

is acceptable, to supply the VRTC output. In systems with no backup battery, the VBACKUP pin should be

connected to GND.

If the switches between VRTC and VSYSIN or VBACKUP are open, the dedicated 3-V/30-mA LDO, driven from

VCC, connects to VRTC. This LDO is disabled if the voltage at the VSYSIN input exceeds 2.65 V.

Inside TPS65023 there is a switch (Vmax switch) which selects the higher voltage between VCC and VBACKUP.

This is used as the supply voltage for some basic functions. The functions powered from the output of the Vmax

switch are:

•INT output

•RESPWRON output

•HOT_RESET input

•LOW_BAT output

•PWRFAIL output

•Enable pins for dc-dc converters, LDO1 and LDO2

•Undervoltage lockout comparator (UVLO)

•Reference system with low frequency timing oscillators

•LOW_BAT and PWRFAIL comparators

The main 2.25-MHz oscillator, and the I2C™interface are only powered from VCC.

Product Folder Link(s): TPS65023-Q1

RESPWRON

VRTC

LDO

VCC

VRTC

Vref

Vref Vref

priority

V_VSYSIN

V_VBACKUP

VBACKUP

V_VBACKUP

VSYSIN

V_VSYSIN

TPS65023-Q1

SLVS927D –MARCH 2009–REVISED SEPTEMBER 2011

www.ti.com

A. V_VSYSIN, V_VBACKUP thresholds: falling = 2.55 V, rising = 2.65 V ±3%

B. RESPWRON thresholds: falling = 2.4 V, rising = 2.52 V ±3%

Figure 26.

Step-Down Converters, VDCDC1, VDCDC2, and VDCDC3

The TPS65023 incorporates three synchronous step-down converters operating typically at 2.25 MHz fixed

frequency pulse width modulation (PWM) at moderate to heavy load currents. At light load currents, the

converters automatically enter the power save mode (PSM), and operate with pulse frequency modulation (PFM).

The VDCDC1 converter is capable of delivering 1.5 A output current, the VDCDC2 converter is capable of

delivering 1.2 A and the VDCDC3 converter is capable of delivering up to 1 A.

The converter output voltages can be programmed via the DEFDCDC1, DEFDCDC2 and DEFDCDC3 pins. The

pins can either be connected to GND, VCC, or to a resistor divider between the output voltage and GND. The

VDCDC1 converter defaults to 1.2 V or 1.6 V depending on the DEFDCDC1 configuration pin. If DEFDCDC1 is

tied to ground, the default is 1.2 V. If it is tied to VCC, the default is 1.6 V. When the DEFDCDC1 pin is

connected to a resistor divider, the output voltage can be set in the range of 0.6 V to VINDCDC1 V. See the

application information section for more details. The core voltage can be reprogrammed via the serial interface in

the range of 0.8 V to 1.6 V with a programmable slew rate. The converter is forced into PWM operation whilst

any programmed voltage change is underway, whether the voltage is being increased or decreased. The

DEFCORE and DEFSLEW registers are used to program the output voltage and slew rate during voltage

transitions.

The VDCDC2 converter defaults to 1.8 V or 3.3 V depending on the DEFDCDC2 configuration pin. If DEFDCDC2

is tied to ground, the default is 1.8 V. If it is tied to VCC, the default is 3.3 V. When the DEFDCDC2 pin is

connected to a resistor divider, the output voltage can be set in the range of 0.6 V to VINDCDC2 V.

The VDCDC3 converter defaults to 1.8 V or 3.3 V depending on the DEFDCDC3 configuration pin. If DEFDCDC3

is tied to ground the default is 1.8 V. If it is tied to VCC, the default is 3.3 V. When the DEFDCDC3 pin is

connected to a resistor divider, the output voltage can be set in the range of 0.6 V to VINDCDC3 V.

The step-down converter outputs (when enabled) are monitored by power good (PG) comparators, the outputs of

which are available via the serial interface. The outputs of the dc-dc converters can be optionally discharged via

on-chip 300-Ωresistors when the dc-dc converters are disabled.

Product Folder Link(s): TPS65023-Q1

I =

PFMDCDC1 enter

I =

PFMDCDC2 enter

I =

PFMDCDC3 enter

VINDCDC1

VINDCDC2

VINDCDC3

24 W

26 W

39 W

I =

PFMDCDC1 leave

I =

PFMDCDC2 leave

I =

PFMDCDC3 leave

VINDCDC1

VINDCDC2

VINDCDC3

18 W

20 W

29 W

TPS65023-Q1

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SLVS927D –MARCH 2009–REVISED SEPTEMBER 2011

During PWM operation, the converters use a unique fast response voltage mode controller scheme with input

voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output

capacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch is

turned on. The inductor current ramps up until the comparator trips and the control logic turns off the switch. The

current limit comparator also turns off the switch if the current limit of the P-channel switch is exceeded. After the

adaptive dead time used to prevent shoot through current, the N-channel MOSFET rectifier is turned on, and the

inductor current ramps down. The next cycle is initiated by the clock signal, again turning off the N-channel

rectifier and turning on the P-channel switch.

The three dc-dc converters operate synchronized to each other with the VDCDC1 converter as the master. A

180°phase shift between the VDCDC1 switch turn on and the VDCDC2 and a further 90°shift to the VDCDC3

switch turn on decreases the input RMS current and smaller input capacitors can be used. This is optimized for a

typical application where the VDCDC1 converter regulates a Li-Ion battery voltage of 3.7 V to 1.2 V, the

VDCDC2 converter from 3.7 V to 1.8 V, and the VDCDC3 converter from 3.7 V to 3.3 V. The phase of the three

converters can be changed using the CON_CTRL register.

Power-Save Mode Operation (PSM)

As the load current decreases, the converters enter the power-save mode operation. During PSM, the converters

operate in a burst mode (PFM mode) with a frequency between 750 kHz and 2.25 MHz, nominal for one burst

cycle. However, the frequency between different burst cycles depends on the actual load current and is typically

far less than the switching frequency with a minimum quiescent current to maintain high efficiency.

In order to optimize the converter efficiency at light load, the average current is monitored and if in PWM mode

the inductor current remains below a certain threshold, then PSM is entered. The typical threshold to enter PSM

is calculated as follows:

(1)

During the PSM the output voltage is monitored with a comparator, and by maximum skip burst width. As the

output voltage falls below the threshold, set to the nominal VO, the P-channel switch turns on and the converter

effectively delivers a constant current defined as follows.

(2)

If the load is below the delivered current then the output voltage rises until the same threshold is crossed in the

other direction. All switching activity ceases, reducing the quiescent current to a minimum until the output voltage

has again dropped below the threshold. The power save mode is exited, and the converter returns to PWM mode

if either of the following conditions are met:

1. the output voltage drops 2% below the nominal VOdue to increasing load current

2. the PFM burst time exceeds 16 ×1/fs (7.11 μs typical).

These control methods reduce the quiescent current to typically 14 μA per converter, and the switching activity to

Product Folder Link(s): TPS65023-Q1

Vinmin +Voutmin )Ioutmax ǒrDS(on)max)RLǓ

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SLVS927D –MARCH 2009–REVISED SEPTEMBER 2011

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a minimum, thus achieving the highest converter efficiency. Setting the comparator thresholds at the nominal

output voltage at light load current results in a low output voltage ripple. The ripple depends on the comparator

delay and the size of the output capacitor. Increasing capacitor values makes the output ripple tend to zero. The

PSM is disabled through the I2C interface to force the individual converters to stay in fixed frequency PWM

mode.

Low-Ripple Mode

Setting Bit 3 in register CON-CTRL to 1 enables the low ripple mode for all of the dc-dc converters if operated in

PFM mode. For an output current less than approximately 10 mA, the output voltage ripple in PFM mode is

reduced, depending on the actual load current. The lower the actual output current on the converter, the lower

the output ripple voltage. For an output current above 10 mA, there is only minor difference in output voltage

ripple between PFM mode and low ripple PFM mode. As this feature also increases switching frequency, it is

used to keep the switching frequency above the audible range in PFM mode down to a low output current.

Soft Start

Each of the three converters has an internal soft start circuit that limits the inrush current during start-up. The soft

start is realized by using a low current to initially charge the internal compensation capacitor. The soft start time

is typically 750 μs if the output voltage ramps from 5% to 95% of the final target value. If the output is already

precharged to some voltage when the converter is enabled, then this time is reduced proportionally. There is a

short delay of typically 170 μs between the converter being enabled and switching activity actually starting. This

allows the converter to bias itself properly, to recognize if the output is precharged, and if so to prevent

discharging of the output while the internal soft start ramp catches up with the output voltage.

100% Duty Cycle Low-Dropout Operation

The TPS65023 converters offer a low input to output voltage difference while still maintaining operation with the

use of the 100% duty cycle mode. In this mode the P-channel switch is constantly turned on. This is particularly

useful in battery-powered applications to achieve longest operation time by taking full advantage of the whole

battery voltage range. The minimum input voltage required to maintain dc regulation depends on the load current

and output voltage. It is calculated as:

(3)

with:

Ioutmax = maximum load current (Note: ripple current in the inductor is zero under these conditions)

rDS(on)max = maximum P-channel switch rDS(on)

RL= DC resistance of the inductor

Voutmin = nominal output voltage minus 2% tolerance limit

Active Discharge When Disabled

When the VDCDC1, VDCDC2, and VDCDC3 converters are disabled, due to an UVLO, DCDC_EN or

OVERTEMP condition, it is possible to actively pull down the outputs. This feature is disabled per default and is

individually enabled via the CON_CTRL2 register in the serial interface. When this feature is enabled, the

VDCDC1, VDCDC2, and VDCDC3 outputs are discharged by a 300 Ω(typical) load which is active as long as

the converters are disabled.

Power Good Monitoring

All three step-down converters and both the LDO1 and LDO2 linear regulators have power good comparators.

Each comparator indicates when the relevant output voltage has dropped 10% below its target value with 5%

hysteresis. The outputs of these comparators are available in the PGOODZ register via the serial interface. An

interrupt is generated when any voltage rail drops below the 10% threshold. The comparators are disabled when

the converters are disabled and the relevant PGOODZ register bits indicate that power is good.

Product Folder Link(s): TPS65023-Q1

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SLVS927D –MARCH 2009–REVISED SEPTEMBER 2011

Low-Dropout Voltage Regulators

The low dropout voltage regulators are designed to operate well with low value ceramic input and output

capacitors. They operate with input voltages down to 1.5 V. The LDOs offer a maximum dropout voltage of

300 mV at rated output current. Each LDO supports a current limit feature. Both LDOs are enabled by the

LDO_EN pin, both LDOs can be disabled or programmed via the serial interface using the REG_CTRL and

LDO_CTRL registers. The LDOs also have reverse conduction prevention. This allows the possibility to connect

external regulators in parallel in systems with a backup battery. The TPS65023 step-down and LDO voltage

regulators automatically power down when the VCC voltage drops below the UVLO threshold or when the junction

temperature rises above 160°C.

Power Good Monitoring

Both the LDO1 and LDO2 linear regulators have power good comparators. Each comparator indicates when the

relevant output voltage has dropped 10% below its target value, with 5% hysteresis. The outputs of these

comparators are available in the PGOODZ register via the serial interface. An interrupt is generated when any

voltage rail drops below the 10% threshold. The comparators are disabled when the LDOs are disabled and the

relevant PGOODZ register bits indicate that power is good.

Undervoltage Lockout

The undervoltage lockout circuit for the five regulators on the TPS65023 prevents the device from malfunctioning

at low-input voltages and from excessive discharge of the battery. It disables the converters and LDOs. The

UVLO circuit monitors the VCC pin, the threshold is set internally to 2.35 V with 5% (120 mV) hysteresis. Note

that when any of the dc-dc converters are running, there is an input current at the VCC pin, which is up to 3 mA

when all three converters are running in PWM mode. This current needs to be taken into consideration if an

external RC filter is used at the VCC pin to remove switching noise from the TPS65023 internal analog circuitry

supply.

Power-Up Sequencing

The TPS65023 power-up sequencing is designed to be entirely flexible and customer driven. This is achieved by

providing separate enable pins for each switch-mode converter, and a common enable signal for the LDOs. The

relevant control pins are described in Table 2.

Table 2. Control Pins and Status Outputs for DC-DC Converters

PIN NAME I/O FUNCTION

Defines the default voltage of the VDCDC3 switching converter. DEFDCDC3 = 0 defaults VDCDC3 to

DEFDCDC3 I 1.8 V, DEFDCDC3 = VCC defaults VDCDC3 to 3.3 V.

Defines the default voltage of the VDCDC2 switching converter. DEFDCDC2 = 0 defaults VDCDC2 to

DEFDCDC2 I 1.8 V, DEFDCDC2 = VCC defaults VDCDC2 to 3.3 V.

Defines the default voltage of the VDCDC1 switching converter. DEFDCDC1 = 0 defaults VDCDC1 to 1.2

DEFDCDC1 I V, DEFDCDC1 = VCC defaults VDCDC1 to 1.6 V.

DCDC3_EN I Set DCDC3_EN = 0 to disable and DCDC3_EN = 1 to enable the VDCDC3 converter

DCDC2_EN I Set DCDC2_EN = 0 to disable and DCDC2_EN = 1 to enable the VDCDC2 converter

DCDC1_EN I Set DCDC1_EN = 0 to disable and DCDC1_EN = 1 to enable the VDCDC1 converter

The HOT_RESET pin generates a reset (RESPWRON) for the processor.HOT_RESET does not alter any

TPS65023 settings except the output voltage of VDCDC1. Activating HOT_RESET sets the voltage of

HOT_RESET I VDCDC1 to its default value defined with the DEFDCDC1 pin. HOT_RESET is internally de-bounced by the

TPS65023.

RESPWRON is held low when power is initially applied to the TPS65023. The VRTC voltage is monitored:

RESPWRON O RESWPRON is low when VRTC <2.4 V and remains low for a time defined by the external capacitor at the

TRESPWRON pin. RESPWRON can also be forced low by activation of the HOT_RESET pin.

TRESPWRON I Connect a capacitor here to define the RESET time at the RESPWRON pin (1 nF typically gives 100 ms).

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System Reset and Control Signals

The RESPWRON signal can be used as a global reset for the application. It is an open drain output. The

RESPWRON signal is generated according to the power good comparator of VRTC, and remains low for tnrespwron

seconds after VRTC has risen above 2.52 V (falling threshold is 2.4 V, 5% hysteresis). tnrespwron is set by an

external capacitor at the TRESPWRON pin. 1 nF gives typically 100 ms. RESPWRON is also triggered by the

HOT_RESET input. This input is internally debounced, with a filter time of typically 30 ms.

The PWRFAIL and LOW_BAT signals are generated by two voltage detectors using the PWRFAIL_SNS and

LOWBAT_SNS input signals. Each input signal is compared to a 1 V threshold (falling edge) with 5% (50 mV)

hysteresis.

The DCDC1 converter is reset to its default output voltage defined by the DEFDCDC1 input, when HOT_RESET

is asserted. Other I2C registers are not affected. Generally, the DCDC1 converter is set to its default voltage with

one of these conditions: HOT_RESET active, VRTC lower than its threshold voltage, undervoltage lockout

(UVLO) condition, or RESPWRON active.

DEFLDO1 and DEFLDO2

These two pins are used to set the default output voltage of the two 200 mA LDOs. The digital value applied to

the pins is latched during power up and determines the initial output voltage according to Table 3. The voltage of

both LDOs can be changed during operation with the I2C interface as described in the interface description.

Table 3.

DEFLDO2 DEFLDO1 VLDO1 VLDO2

0 0 1.3 V 3.3 V

0 1 2.8 V 3.3 V

1 0 1.3 V 1.8 V

1 1 1.8 V 3.3 V

Interrupt Management and the INT Pin

The INT pin combines the outputs of the PGOOD comparators from each dc-dc converter and the LDOs. The

INT pin is used as a POWER_OK pin to indicate when all enabled supplies are in regulation. The INT pin

remains active (low state) during power up as long as all enabled power rails are below their regulation limit.

Once the last enabled power rail is within regulation, the INT pin transitions to a high state.

During operation, if one of the enabled supplies goes out of regulation, INT transitions to a low state, and the

corresponding bit in the PGOODZ register goes high. If the supply goes back to its regulation limits, INT

transitions back to a high state.

While INT is in an active low state, reading the PGOODZ register via the I2C bus forces INT into a high-Z state.

Since this pin requires an external pullup resistor, the INT pin transitions to a logic high state even though the

supply in question is still out of regulation. The corresponding bit in the PGOODZ register still indicates that the

power rail is out of regulation.

Interrupts can be masked using the MASK register. The default operation is to not mask any DCDC or LDO

interrupts, because these provide the POWER_OK function.

Product Folder Link(s): TPS65023-Q1

VCC

UVLO*

VRTC

VSYSIN=VBACKUP=GND;

VINLDO=VCC

tNRESPWRON

DCDCx_EN

VODCDCx

*...internalsignal

0.8V

1.9V

2.52V 3.0V

Rampwithin

800 μs

LDO_EN

slopedepending

onload

2.47V

VOLDOx

2.4V

2.35V

1.2V

1.9V

RESPWRON

TPS65023-Q1

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SLVS927D –MARCH 2009–REVISED SEPTEMBER 2011

Timing Diagrams

Figure 27. HOT_RESET Timing

Figure 28. Power-Up and Power-Down Timing

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Figure 29. DVS Timing

Serial Interface

The serial interface is compatible with the standard and fast mode I2C specifications, allowing transfers at up to

400 kHz. The interface adds flexibility to the power supply solution, enabling most functions to be programmed to

new values depending on the instantaneous application requirements and charger status to be monitored.

1001000, other addresses are available upon contact with the factory. Attempting to read data from the register

addresses not listed in this section results in FFh being read out.

Product Folder Link(s): TPS65023-Q1

DataLine

Stable;

DataValid

DATA

CLK

Change

ofData

Allowed

DATA

CLK

STARTCondition STOP Condition

SCLK

SDAT

Start Slave Address Register Address Data

A6 A5 A4 A0 R/W R7 R6 R5 R0 D7 D6 D5 D0

ACK ACK ACK

0 0 0

Stop

Note:SLAVE=TPS65020

TPS65023-Q1

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SLVS927D –MARCH 2009–REVISED SEPTEMBER 2011

For normal data transfer, DATA is allowed to change only when CLK is low. Changes when CLK is high are

reserved for indicating the start and stop conditions. During data transfer, the data line must remain stable

whenever the clock line is high. There is one clock pulse per bit of data. Each data transfer is initiated with a start

condition and terminated with a stop condition. When addressed, the TPS65023 device generates an

acknowledge bit after the reception of each byte. The master device (microprocessor) must generate an extra

clock pulse that is associated with the acknowledge bit. The TPS65023 device must pull down the DATA line

during the acknowledge clock pulse so that the DATA line is a stable low during the high period of the

acknowledge clock pulse. The DATA line is a stable low during the high period of the acknowledge–related clock

pulse. Setup and hold times must be taken into account. During read operations, a master must signal the end of

data to the slave by not generating an acknowledge bit on the last byte that was clocked out of the slave. In this

case, the slave TPS65023 device must leave the data line high to enable the master to generate the stop

condition

Figure 30. Bit Transfer on the Serial Interface

Figure 31. Start and Stop Conditions

Figure 32. Serial Interface Write to TPS65023 Device

Product Folder Link(s): TPS65023-Q1

SCLK

SDAT

Start

Repeated

Start

Slave

Drives

theData

Master

Drives

ACKandStop

Slave Address Slave Address

Address

A6A6 A0A0 R/W R/WR7 R0 D7 D0

ACK ACKACK ACK

0 0 0

Stop

Note:SLAVE=TPS65020

SCLK

SDA

Start

StopStart

Slave

Drives

theData

Master

Drives

ACKandStop

Slave Address Slave Address

Address

0 0 0 0

Stop

Note:SLAVE=TPS65020

A6A6 A0A0 R/W R/WR7 R0 D7 D0

ACK ACKACK ACK

CLK

DATA

STA STA STOSTO

th(STA)

t(BUF)

t(LOW)

trtf

th(DATA) tsu(DATA)

tsu(STA)

th(STA)

tsu(STO)

t(HIGH)

TPS65023-Q1

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Figure 33. Serial Interface Read from TPS65023: Protocol A

Figure 34. Serial Interface Read from TPS65023: Protocol B

Figure 35. Serial Interface Timing Diagram

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SLVS927D –MARCH 2009–REVISED SEPTEMBER 2011

Table 4. Serial Interface Timing

MIN MAX UNIT

fMAX Clock frequency 400 kHz

twH(HIGH) Clock high time 600 ns

twL(LOW) Clock low time 1300 ns

tRDATA and CLK rise time 300 ns

tFDATA and CLK fall time 300 ns

th(STA) Hold time (repeated) START condition (after this period the first clock pulse is generated) 600 ns

th(DATA) Setup time for repeated START condition 600 ns

th(DATA) Data input hold time 300 ns

tsu(DATA) Data input setup time 300 ns

tsu(STO) STOP condition setup time 600 ns

t(BUF) Bus free time 1300 ns

VERSION. Register Address: 00h (read only)

VERSION B7 B6 B5 B4 B3 B2 B1 B0

Bit name and 0 0 1 0 0 0 1 1

function

Read/Write R R R R R R R R

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PGOODZ. Register Address: 01h (read only)

PGOODZ B7 B6 B5 B4 B3 B2 B1 B0

Bit name and LOWBATTZ PGOODZ PGOODZ PGOODZ PGOODZ PGOODZ

PWRFAILZ

function VDCDC1 VDCDC2 VDCDC3 LDO2 LDO1

LOWBATT PGOODZ PGOODZ PGOODZ PGOODZ PGOODZ

Set by signal PWRFAIL VDCDC1 VDCDC2 VDCDC3 LDO2 LDO1

Default value LOWBATTZ PGOOD PGOOD PGOOD PGOOD PGOOD

PWRFAILZ

loaded by: VDCDC1 VDCDC2 VDCDC3 LDO2 LDO1

Read/Write R R R R R R R R

Bit 7 PWRFAILZ:

0 = indicates that the PWRFAIL_SNS input voltage is above the 1-V threshold.

1 = indicates that the PWRFAIL_SNS input voltage is below the 1-V threshold.

Bit 6 LOWBATTZ:

0 = indicates that the LOWBATT_SNS input voltage is above the 1-V threshold.

1 = indicates that the LOWBATT_SNS input voltage is below the 1-V threshold.

Bit 5 PGOODZ VDCDC1:

0 = indicates that the VDCDC1 converter output voltage is within its nominal range. This bit is zero if

the VDCDC1 converter is disabled.

1 = indicates that the VDCDC1 converter output voltage is below its target regulation voltage

Bit 4 PGOODZ VDCDC2:

0 = indicates that the VDCDC2 converter output voltage is within its nominal range. This bit is zero if

the VDCDC2 converter is disabled.

1 = indicates that the VDCDC2 converter output voltage is below its target regulation voltage

Bit 3 PGOODZ VDCDC3:

0 = indicates that the VDCDC3 converter output voltage is within its nominal range. This bit is zero if

the VDCDC3 converter is disabled and during a DVM controlled output voltage transition

1 = indicates that the VDCDC3 converter output voltage is below its target regulation voltage

Bit 2 PGOODZ LDO2:

0 = indicates that the LDO2 output voltage is within its nominal range. This bit is zero if LDO2 is

disabled.

1 = indicates that LDO2 output voltage is below its target regulation voltage

Bit 1 PGOODZ LDO1

0 = indicates that the LDO1 output voltage is within its nominal range. This bit is zero if LDO1 is

disabled.

1 = indicates that the LDO1 output voltage is below its target regulation voltage

Product Folder Link(s): TPS65023-Q1

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SLVS927D –MARCH 2009–REVISED SEPTEMBER 2011

MASK. Register Address: 02h (read/write) Default Value: C0h

MASK B7 B6 B5 B4 B3 B2 B1 B0

Bit name and MASK MASK MASK MASK MASK MASK MASK

function PWRFAILZ LOWBATTZ VDCDC1 VDCDC2 VDCDC3 LDO2 LDO1

Default 1 1 0 0 0 0 0 0

Default value UVLO UVLO UVLO UVLO UVLO UVLO UVLO

loaded by:

Read/Write R/W R/W R/W R/W R/W R/W R/W

The MASK register can be used to mask particular fault conditions from appearing at the INT pin. MASK<n>= 1

masks PGOODZ<n>.

REG_CTRL. Register Address: 03h (read/write) Default Value: FFh

The REG_CTRL register is used to disable or enable the power supplies via the serial interface. The contents of

the register are logically AND’ed with the enable pins to determine the state of the supplies. A UVLO condition

resets the REG_CTRL to 0xFF, so the state of the supplies defaults to the state of the enable pin. The

REG_CTRL bits are automatically reset to default when the corresponding enable pin is low.

REG_CTRL B7 B6 B5 B4 B3 B2 B1 B0

Bit name and VDCDC1 VDCDC2 VDCDC3 LDO2 LDO1

function ENABLE ENABLE ENABLE ENABLE ENABLE

Default 1 1 1 1 1 1 1 1

Set by signal DCDC1_ENZ DCDC2_ENZ DCDC3_ENZ LDO_ENZ LDO_ENZ

Default value UVLO UVLO UVLO UVLO UVLO

loaded by:

Read/Write R/W R/W R/W R/W R/W

Bit 5 VDCDC1 ENABLE

DCDC1 Enable. This bit is logically AND’ed with the state of the DCDC1_EN pin to turn on the DCDC1

converter. Reset to 1 by a UVLO condition, the bit can be written to 0 or 1 via the serial interface. The

bit is reset to 1 when the pin DCDC1_EN is pulled to GND, allowing DCDC1 to turn on when

DCDC1_EN returns high.

Bit 4 VDCDC2 ENABLE

DCDC2 Enable. This bit is logically AND’ed with the state of the DCDC2_EN pin to turn on the DCDC2

converter. Reset to 1 by a UVLO condition, the bit can be written to 0 or 1 via the serial interface. The

bit is reset to 1 when the pin DCDC2_EN is pulled to GND, allowing DCDC2 to turn on when

DCDC2_EN returns high.

Bit 3 VDCDC3 ENABLE

DCDC3 Enable. This bit is logically AND’ed with the state of the DCDC3_EN pin to turn on the DCDC3

converter. Reset to 1 by a UVLO condition, the bit can be written to 0 or 1 via the serial interface. The

bit is reset to 1 when the pin DCDC3_EN is pulled to GND, allowing DCDC3 to turn on when

DCDC3_EN returns high.

Bit 2 LDO2 ENABLE

LDO2 Enable. This bit is logically AND’ed with the state of the LDO2_EN pin to turn on LDO2. Reset to

1 by a UVLO condition, the bit can be written to 0 or 1 via the serial interface. The bit is reset to 1 when

the pin LDO_EN is pulled to GND, allowing LDO2 to turn on when LDO_EN returns high.

Bit 1 LDO1 ENABLE

LDO1 Enable. This bit is logically AND’ed with the state of the LDO1_EN pin to turn on LDO1. Reset to

1 by a UVLO condition, the bit can be written to 0 or 1 via the serial interface. The bit is reset to 1 when

the pin LDO_EN is pulled to GND, allowing LDO1 to turn on when LDO_EN returns high.

Product Folder Link(s): TPS65023-Q1

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CON_CTRL. Register Address: 04h (read/write) Default Value: B1h

CON_CTRL B7 B6 B5 B4 B3 B2 B1 B0

Bit name and DCDC2 DCDC2 DCDC3 DCDC3 LOW FPWM FPWM FPWM

function PHASE1 PHASE0 PHASE1 PHASE0 RIPPLE DCDC2 DCDC1 DCDC3

Default 1 0 1 1 0 0 0 0

Default value UVLO UVLO UVLO UVLO UVLO UVLO UVLO UVLO

loaded by:

Read/Write R/W R/W R/W R/W R/W R/W R/W R/W

The CON_CTRL register is used to force any or all of the converters into forced PWM operation, when low

output voltage ripple is vital. It is also used to control the phase shift between the three converters in order to

minimize the input RMS current, hence reduce the required input blocking capacitance. The DCDC1 converter is

taken as the reference and consequently has a fixed zero phase shift.

DCDC2 CONVERTER DCDC3 CONVERTER

CON_CTRL<7:6>CON_CTRL<5:4>

DELAYED BY DELAYED BY

00 zero 00 zero

01 1/4 cycle 01 1/4 cycle

10 1/2 cycle 10 1/2 cycle

11 3/4 cycle 11 3/4 cycle

Bit 3 LOW RIPPLE:

0 = PFM mode operation optimized for high efficiency for all converters

1 = PFM mode operation optimized for low output voltage ripple for all converters

Bit 2 FPWM DCDC2:

0 = DCDC2 converter operates in PWM / PFM mode

1 = DCDC2 converter is forced into fixed frequency PWM mode

Bit 1 FPWM DCDC1:

0 = DCDC1 converter operates in PWM / PFM mode

1 = DCDC1 converter is forced into fixed frequency PWM mode

Bit 0 FPWM DCDC3:

0 = DCDC3 converter operates in PWM / PFM mode

1 = DCDC3 converter is forced into fixed frequency PWM mode

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SLVS927D –MARCH 2009–REVISED SEPTEMBER 2011

CON_CTRL2. Register Address: 05h (read/write) Default Value: 40h

CON_CTRL2 B7 B6 B5 B4 B3 B2 B1 B0

Bit name and Core adj DCDC2 DCDC1 DCDC3

function allowed discharge discharge discharge

Default 0 1 0 0 0 0 0 0

Default value UVLO + RESET(1) UVLO UVLO UVLO

loaded by: DONE

Read/Write R/W R/W R/W R/W R/W

The CON_CTRL2 register can be used to take control the inductive converters.

RESET(1): CON_CTRL2[6] is reset to its default value by one of these events:

•undervoltage lockout (UVLO)

•HOT_RESET pulled low

•RESPWRON active

•VRTC below threshold

Bit 7 GO

0 = no change in the output voltage for the DCDC1 converter

1 = the output voltage of the DCDC1 converter is changed to the value defined in DEFCORE with

the slew rate defined in DEFSLEW. This bit is automatically cleared when the DVM transition is

complete. The transition is considered complete in this case when the desired output voltage

code has been reached, not when the VDCDC3 output voltage is actually in regulation at the

desired voltage.

Bit 6 CORE ADJ allowed

0 = the output voltage is set with the I2C register

1 = DEFDCDC1 is either connected to GND or VCC or an external voltage divider. When

connected to GND or VCC, VDCDC1 defaults to 1.2 V or 1.6 V respectively at start-up.

Bit 2–0 0 = the output capacitor of the associated converter is not actively discharged when the converter is

disabled

1 = the output capacitor of the associated converter is actively discharged when the converter is

disabled. This decreases the fall time of the output voltage at light load.

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DEFCORE. Register Address: 06h (read/write Default Value: 14h/1Eh

DEFCORE B7 B6 B5 B4 B3 B2 B1 B0

Bit name and CORE4 CORE3 CORE2 CORE1 CORE0

function

Default 0 0 0 1 DEFDCDC1 DEFDCDC1 DEFDCDC1 DEFDCDC1

Default value RESET(1) RESET(1) RESET(1) RESET(1) RESET(1)

loaded by:

Read/Write R/W R/W R/W R/W R/W

RESET(1): DEFCORE is reset to its default value by one of these events:

•undervoltage lockout (UVLO)

•HOT_RESET pulled low

•RESPWRON active

•VRTC below threshold

CORE4 CORE3 CORE2 CORE1 CORE0 VDCDC1 CORE4 CORE3 CORE2 CORE1 CORE0 VDCDC1

0 0 0 0 0 0.8 V 1 0 0 0 0 1.2 V

0 0 0 0 1 0.825 V 1 0 0 0 1 1.225 V

0 0 0 1 0 0.85 V 1 0 0 1 0 1.25 V

0 0 0 1 1 0.875 V 1 0 0 1 1 1.275 V

0 0 1 0 0 0.9 V 1 0 1 0 0 1.3 V

0 0 1 0 1 0.925 V 1 0 1 0 1 1.325 V

0 0 1 1 0 0.95 V 1 0 1 1 0 1.35 V

0 0 1 1 1 0.975 V 1 0 1 1 1 1.375 V

0 1 0 0 0 1 V 1 1 0 0 0 1.4 V

0 1 0 0 1 1.025 V 1 1 0 0 1 1.425 V

0 1 0 1 0 1.05 V 1 1 0 1 0 1.45 V

0 1 0 1 1 1.075 V 1 1 0 1 1 1.475 V

0 1 1 0 0 1.1 V 1 1 1 0 0 1.5 V

0 1 1 0 1 1.125 V 1 1 1 0 1 1.525 V

0 1 1 1 0 1.15 V 1 1 1 1 0 1.55 V

0 1 1 1 1 1.175 V 1 1 1 1 1 1.6 V

DEFSLEW. Register Address: 07h (read/write) Default Value: 06h

DEFSLEW B7 B6 B5 B4 B3 B2 B1 B0

Bit name and SLEW2 SLEW1 SLEW0

function

Default 1 1 0

Default value UVLO UVLO UVLO

loaded by:

Read/Write R/W R/W R/W

SLEW2 SLEW1 SLEW0 VDCDC1 SLEW RATE

0 0 0 0.225 mV/μs

0 0 1 0.45 mV/μs

0 1 0 0.9 mV/μs

0 1 1 1.8 mV/μs

1 0 0 3.6 mV/μs

1 0 1 7.2 mV/μs

1 1 0 14.4 mV/μs

1 1 1 Immediate

Product Folder Link(s): TPS65023-Q1

DIL+Vout 1*Vout

Vin

L ƒ

ILmax +Ioutmax )

DIL

TPS65023-Q1

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SLVS927D –MARCH 2009–REVISED SEPTEMBER 2011

LDO_CTRL. Register Address: 08h (read/write) Default Value: set with DEFLDO1 and DEFLDO2

LDO_CTRL B7 B6 B5 B4 B3 B2 B1 B0

Bit name and RSVD RSVD

LDO2_2 LDO2_1 LDO2_0 LDO1_2 LDO1_1 LDO1_0

function

Default DEFLDOx DEFLDOx DEFLDOx DEFLDOx DEFLDOx DEFLDOx

Default value UVLO UVLO UVLO UVLO UVLO UVLO

loaded by:

Read/Write R/W R/W R/W R/W R/W R/W

The LDO_CTRL registers can be used to set the output voltage of LDO1 and LDO2. LDO_CTRL[7] and

LDO_CTRL[3] are reserved and should always be written to 0.

The default voltage is set with DEFLDO1 and DEFLDO2 pins as described in Table 3.

LDO2 OUTPUT LDO1 OUTPUT

LDO2_2 LDO2_1 LDO2_0 LDO1_2 LDO1_1 LDO1_0

VOLTAGE VOLTAGE

0 0 0 1.05 V 0 0 0 1 V

0 0 1 1.2 V 0 0 1 1.1 V

0 1 0 1.3 V 0 1 0 1.3 V

0 1 1 1.8 V 0 1 1 1.8 V

1 0 0 2.5 V 1 0 0 2.2 V

1 0 1 2.8 V 1 0 1 2.6 V

1 1 0 3.0 V 1 1 0 2.8 V

1 1 1 3.3 V 1 1 1 3.15 V

Design Procedure

Inductor Selection for the DC-DC Converters

Each of the converters in the TPS65023 typically use a 2.2-μH output inductor. Larger or smaller inductor values

are used to optimize the performance of the device for specific operation conditions. The selected inductor has to

be rated for its dc resistance and saturation current. The dc resistance of the inductance influences directly the

efficiency of the converter. Therefore, an inductor with lowest dc resistance should be selected for highest

efficiency.

For a fast transient response, a 2.2-μH inductor in combination with a 22-μF output capacitor is recommended.

Equation 4 calculates the maximum inductor current under static load conditions. The saturation current of the

inductor should be rated higher than the maximum inductor current as calculated with Equation 4. This is needed

because during heavy load transient the inductor current rises above the value calculated under Equation 4.

(4)

(5)

with:

f = Switching Frequency (2.25 MHz typical)

L = Inductor Value

ΔIL= Peak-to-Peak inductor ripple current

ILMAX = Maximum Inductor current

The highest inductor current occurs at maximum Vin.

Open core inductors have a soft saturation characteristic, and they can usually handle higher inductor currents

versus a comparable shielded inductor.

Product Folder Link(s): TPS65023-Q1

IRMSCout =Vout x

1-

Vout

Vin

L x ¦x1

2x 3Ö

DVout =Vout x

1- Vout

Vin

L x ¦x+ESR

( )

8xC x

out ¦

TPS65023-Q1

SLVS927D –MARCH 2009–REVISED SEPTEMBER 2011

www.ti.com

A more conservative approach is to select the inductor current rating just for the maximum switch current of the

TPS65023 (2 A for the VDCDC1 and VDCDC2 converters, and 1.5 A for the VDCDC3 converter). The core

material from inductor to inductor differs and has an impact on the efficiency especially at high switching

frequencies.

See Table 5 and the typical applications for possible inductors.

Table 5. Tested Inductors

DEVICE INDUCTOR VALUE TYPE COMPONENT SUPPLIER

2.2 μH LPS4012-222LMB Coilcraft

All converters 2.2 μH VLCF4020T-2R2N1R7 TDK

Output Capacitor Selection

The advanced Fast Response voltage mode control scheme of the inductive converters implemented in the

TPS65023 allow the use of small ceramic capacitors with a typical value of 10 μF for each converter without

having large output voltage under and overshoots during heavy load transients. Ceramic capacitors having low

ESR values have the lowest output voltage ripple and are recommended. See Table 6 for recommended

components.

If ceramic output capacitors are used, the capacitor RMS ripple current rating always meets the application

requirements. Just for completeness, the RMS ripple current is calculated as:

(6)

At nominal load current, the inductive converters operate in PWM mode. The overall output voltage ripple is the

sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and

discharging the output capacitor:

(7)

Where the highest output voltage ripple occurs at the highest input voltage Vin.

At light load currents, the converters operate in PSM and the output voltage ripple is dependent on the output

capacitor value. The output voltage ripple is set by the internal comparator delay and the external capacitor. The

typical output voltage ripple is less than 1% of the nominal output voltage.

Input Capacitor Selection

Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is

required for best input voltage filtering and minimizing the interference with other circuits caused by high input

voltage spikes. Each dc-dc converter requires a 10-μF ceramic input capacitor on its input pin VINDCDCx. The

input capacitor is increased without any limit for better input voltage filtering. The VCC pin is separated from the

input for the dc-dc converters. A filter resistor of up to 10R and a 1-μF capacitor is used for decoupling the VCC

pin from switching noise. Note that the filter resistor may affect the UVLO threshold since up to 3 mA can flow via

this resistor into the VCC pin when all converters are running in PWM mode.

Table 6. Possible Capacitors

CAPACITOR VALUE CASE SIZE COMPONENT SUPPLIER COMMENTS

22 μF 1206 TDK C3216X5R0J226M Ceramic

22 μF 1206 Taiyo Yuden JMK316BJ226ML Ceramic

22 μF 0805 TDK C2012X5R0J226MT Ceramic

22μF 0805 Taiyo Yuden JMK212BJ226MG Ceramic

10 μF 0805 Taiyo Yuden JMK212BJ106M Ceramic

10 μF 0805 TDK C2012X5R0J106M Ceramic

Product Folder Link(s): TPS65023-Q1

VDCDC3

DCDC3_EN DEFDCDC3

AGND PGND

VCC

VINDCDC3

1 Fm

10R

V(bat)

VOUT DEFDCDCx

=V x R1+R2

R2 R1=R2x

VOUT

VDEFDCDCx

-R2

()

TPS65023-Q1

www.ti.com

SLVS927D –MARCH 2009–REVISED SEPTEMBER 2011

Output Voltage Selection

The DEFDCDC1, DEFDCDC2, and DEFDCDC3 pins are used to set the output voltage for each step-down

converter. See Table 7 for the default voltages if the pins are pulled to GND or to VCC. If a different voltage is

needed, an external resistor divider can be added to the DEFDCDCx pin as shown in Figure 36.

The output voltage of VDCDC1 is set with the I2C interface. If the voltage is changed from the default, using the

DEFCORE register, the output voltage only depends on the register value. Any resistor divider at DEFDCDC1

does not change the voltage set with the register.

Table 7.

PIN LEVEL DEFAULT OUTPUT VOLTAGE

VCC 1.6 V

DEFDCDC1 GND 1.2 V

VCC 3.3 V

DEFDCDC2 GND 1.8 V

VCC 3.3 V

DEFDCDC3 GND 1.8 V

Using an external resistor divider at DEFDCDCx:

Figure 36. External Resistor Divider

When a resistor divider is connected to DEFDCDCx, the output voltage can be set from 0.6 V up to the input

voltage V(bat). The total resistance (R1+R2) of the voltage divider should be kept in the 1-MR range in order to

maintain a high efficiency at light load.

V(DEFDCDCx) = 0.6 V

(8)

VRTC Output

It is recommended that a 4.7-μF (minimum) capacitor be added to the VRTC pin.

LDO1 and LDO2

The LDOs in the TPS65023 are general-purpose LDOs which are stable using ceramics capacitors. The

minimum output capacitor required is 2.2 μF. The LDOs output voltage can be changed to different voltages

between 1 V and 3.3 V using the I2C interface. Therefore, they can also be used as general-purpose LDOs in

applications powering processors different from DaVinci. The supply voltage for the LDOs needs to be connected

to the VINLDO pin, giving the flexibility to connect the lowest voltage available in the system and provides the

highest efficiency.

Product Folder Link(s): TPS65023-Q1

t =2

(reset) x128x

(1V-0.25V)xC(reset)

2 Am

()

TPS65023-Q1

SLVS927D –MARCH 2009–REVISED SEPTEMBER 2011

www.ti.com

TRESPWRON

This is the input to a capacitor that defines the reset delay time after the voltage at VRTC rises above 2.52 V.

The timing is generated by charging and discharging the capacitor with a current of 2 μA between a threshold of

0.25 V and 1 V for 128 cycles. A 1-nF capacitor gives a delay time of 100 ms.

(9)

Where:

t(reset) is the reset delay time

C(reset) is the capacitor connected to the TRESPWRON pin

VCC Filter

An RC filter connected at the VCC input is used to keep noise from the internal supply for the bandgap and other

analog circuitry. A typical value of 10 R and 1 μF is used to filter the switching spikes, generated by the dc-dc

converters. A larger resistor than 10 R should not be used because the current into VCC of up to 3 mA causes a

voltage drop at the resistor causing the undervoltage lockout circuitry connected at VCC internally to switch off

too early.

Product Folder Link(s): TPS65023-Q1

VCC/VINDCDC1

DCDC1_EN

VDCDC1

1.225V 1.225V 1.225V

TPS65023-Q1

www.ti.com

SLVS927D –MARCH 2009–REVISED SEPTEMBER 2011

APPLICATION INFORMATION

Typical Configuration for the Texas Instruments®TMS320DM644x DaVinci Processors

Reset Condition of DCDC1

If DEFDCDC1 is connected to ground and DCDC1_EN is pulled high after VINDCDC1 is applied, the output

voltage of DCDC1 defaults to 1.225 V instead of 1.2 V (high by 2%). Figure 37 illustrates the problem.

Figure 37. Default DCDC1

Product Folder Link(s): TPS65023-Q1

VCC/VINDCDC1

DCDC1_EN

VDCDC1

1.20V 1.20V 1.20V

VCC/VINDCDC1

DCDC1_EN

I2CBus

DEF_CORE

VDCDC1

?? 0x1F 0x11 0x10 ?? 0x1E0x1F 0x10

1.20V

1.225V 1.20V

PullDCDC1_ENHigh

WriteDEF_COREto0x10

WriteCON_CTRL [7]to1

WriteDEF_COREto0x10

PullDCDC1_ENHigh

VCC/VINDCDC1

DCDC1_EN

HOT_RESET

VDCDC1

1.225V

1.20V

1.225V 1.20V

TPS65023-Q1

SLVS927D –MARCH 2009–REVISED SEPTEMBER 2011

www.ti.com

Workaround 1: Tie DCDC1_EN to VINDCDC1 (Figure 38)

Figure 38. Workaround 1

Workaround 2: Write the correct voltage to the DEF_CORE register via I2C. This can be done before or after the

converter is enabled. If written before the enable, the only bit changed is DEF_CORE[0]. The voltage will be 1.2

V, however, when the enable is pulled high (Figure 39).

Figure 39. Workaround 2

Workaround 3: Generate a HOT_RESET after enabling DCDC1 (Figure 40)

Figure 40. Workaround 3

Product Folder Link(s): TPS65023-Q1

PACKAGE OPTION ADDENDUM

www.ti.com 16-Sep-2011

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

TPS65023QRHARQ1 ACTIVE VQFN RHA 40 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

TPS65023QRSBRQ1 ACTIVE WQFN RSB 40 3000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF TPS65023-Q1 :

•Catalog: TPS65023

NOTE: Qualified Version Definitions:

PACKAGE OPTION ADDENDUM

www.ti.com 16-Sep-2011

Addendum-Page 2

•Catalog - TI's standard catalog product

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

TPS65023QRHARQ1 VQFN RHA 40 3000 330.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TPS65023QRHARQ1 VQFN RHA 40 3000 367.0 367.0 38.0

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 2

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