ICS844001AGI - Integrated Circuit Systems, Inc.

844001AGI www.icst.com/products/hiperclocks.html REV. A JUNE 16, 2005

Integrated

Circuit

Systems, Inc.

ICS844001I

FEMTOCLOCKS™ C RYSTAL-TO- LVDS

CLOCK GENERATOR

PRELIMINARY

GENERAL DESCRIPTION

The ICS844001I is a Fibre Channel Clock

Generator and a member of the HiPerClocksTM

family of high performance devices from ICS.

The ICS844001I uses an 18pF parallel resonant

crystal over the range of 20.4MHz - 28.3MHz.

For Fibre Channel applications, a 26.5625MHz crystal is used.

The frequency select pin allows the device to generate

either 106.25MHz or 212.5MHz from a 26.5625MHz

crystal. To generate 187.5MHz for 12Gb Ethernet, a

23.4375MHz crystal is used. The ICS844001I uses ICS’ 3rd

generation low phase noise VCO technology and can

achieve <1ps typical rms phase jitter, easily meeting Fibre

Channel and Ethernet jitter requirements. The ICS844001I is

packaged in a small 8-pin TSSOP, making it ideal for use in

systems with limited board space.

FEATURES

•(1) Differential LVDS output

•Crystal oscillator interface, 18pF parallel resonant crystal

(20.4MHz - 28.3MHz)

•Output frequency range: 81.66MHz - 226.66MHz

•VCO range: 490MHz - 680MHz

•RMS phase jitter @ 106.25MHz, using a 26.5625MHz crystal

(637kHz - 10MHz): 0.74ps (typical)

•3.3V or 2.5V operating supply

•-40°C to 85°C ambient operating temperature

HiPerClockS™

ICS

ICS844001I

8-Lead TSSOP

4.40mm x 3.0mm x 0.925mm

package body

G Package

Top View

VDDA

GND

XTAL_OUT

XTAL_IN

VDD

FREQ_SEL

BLOCK DIAGRAM

OSC Phase

Detector

VCO

490MHz - 680MHz

M = ÷24 (fixed)

÷3

÷6

XTAL_IN

XTAL_OUT

COMMON CONFIGURATION TABLE - FIBRE CHANNEL, 12Gb ETHERNET

PIN ASSIGNMENT

FREQ_SEL

stupnI ycneuqerFtuptuO

)zHM(

)zHM(ycneuqerFlatsyrCLES_QERFMN noitacilpitluM

N/MeulaV

5265.620426 4 52.601

5265.621423 8 5.212

5734.321423 8 5.781

Pullup

The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial

product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.

844001AGI www.icst.com/products/hiperclocks.html REV. A JUNE 16, 2005

Integrated

Circuit

Systems, Inc.

ICS844001I

FEMTOCLOCKS™ C RYSTAL-TO- LVDS

CLOCK GENERATOR

PRELIMINARY

TABLE 2. PIN CHARACTERISTICS

TABLE 1. PIN DESCRIPTIONS

rebmuNemaNepyTnoitpircseD

ADD

rewoP.nipylppusgolanA

2DNGrewoP.dnuorgylppusrewoP

4,3 ,TUO_LATX

NI_LATX tupnI ,tupniehtsiNI_LATX.ecafretnirotal

licsolatsyrC

.tuptuoehtsiTUO_LATX

5LES_QERFtupnIpulluP.niptcelesycneuqerF

7,6Q,QntuptuO.slevelecafretniSDVL.stu

ptuokcolclaitnereffiD

rewoP.nipylppuseroC

:ETON

pulluP

.seulavlacipytrof,scitsiretcarahCniP,2elbaTeeS.srotsisertupnilanretniotsrefer

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

ecnaticapaCtupnI 4Fp

PULLUP

rotsiseRpulluPtupnI 15kΩ

844001AGI www.icst.com/products/hiperclocks.html REV. A JUNE 16, 2005

Integrated

Circuit

Systems, Inc.

ICS844001I

FEMTOCLOCKS™ C RYSTAL-TO- LVDS

CLOCK GENERATOR

PRELIMINARY

TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = -40°C TO 85°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

egatloVylppuSeroC 531.33.3564.3V

ADD

egatloVylppuSgolanA 531.33.3564.3V

tnerruCylppuSrewoP DBTAm

ADD

tnerruCylppuSgolanA DBTAm

ABSOLUTE MAXIMUM RATINGS

Supply Voltage, V

DD 4.6V

Inputs, VI-0.5V to VDD + 0.5 V

Outputs, IO (LVDS)

Continuous Current 10mA

Surge Current 15mA

Package Thermal Impedance, θJA 101.7°C/W (0 mps)

Storage Temperature, T

STG -65°C to 150°C

NOTE: Stresses beyond those listed under Absolute

Maximum Ratings may cause permanent damage to the

device. These ratings are stress specifications only. Functional

operation of product at these conditions or any conditions be-

yond those listed in the

DC Characteristics

AC Character-

istics

is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect product reliability.

TABLE 3C. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V±5% OR 2.5V±5%, TA = -40°C TO 85°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

egatloVhgiHtupnI V

V3.3=2V

3.0+V

V5.2=7.1V

3.0+V

egatloVwoLtupnI V

V3.3=3.0-8.0V

V5.2=3.0-7.0V

tnerruChgiHtupnILES_QERFV

V526.2roV564.3=5Aµ

tnerruCwoLtupnILES_QERFV

V,V526.2roV564.3=

V0=051-Aµ

TABLE 3D. LVDS DC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = -40°C TO 85°C

TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 2.5V±5%, TA = -40°C TO 85°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

egatloVylppuSeroC 573.25.2526.2V

ADD

egatloVylppuSgolanA 573.25.2526.2V

tnerruCylppuSrewoP DBTAm

ADD

tnerruCylppuSgolanA DBTAm

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

egatloVtuptuOlaitnereffiD 053Vm

ΔV

egnahCedutingaM 04Vm

egatloVtesffO 52.1V

ΔV

egnahCedutingaM 05Vm

.noitamrofnituptuorofnoitamrofnItnemerusaeMretemaraPotreferesaelP:ETON

844001AGI www.icst.com/products/hiperclocks.html REV. A JUNE 16, 2005

Integrated

Circuit

Systems, Inc.

ICS844001I

FEMTOCLOCKS™ C RYSTAL-TO- LVDS

CLOCK GENERATOR

PRELIMINARY

TABLE 4. CRYSTAL CHARACTERISTICS

retemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

noitallicsOfoedoM latnemadnuF

ycneuqerF 4.023.82zHM

)RSE(ecnats

iseRseireStnelaviuqE 05 Ω

ecnaticapaCtnuhS 7Fp

leveLevirD 1Wm

TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = 3.3V±5%, TA = -40°C TO 85°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

TUO

ycneuqerFtuptuO 66.1866.622zHM

)Ø(tij ;)modnaR(rettiJesahPSMR

1ETON

:egnaRnoitargetnI@zHM52.601

zHM01-zHk736 47.0sp

:egnaRnoitargetnI@zHM5.

781

zHM01-zHk736 84.0sp

:egnaRnoitargetnI@zHM5.212

zHM01-zHk736 07.0sp

emiTllaF/esiRtuptuO%08ot%02062sp

cdoelcyCytuDtuptuO 05%

.noitcessihtgniwollofstolPesioNesahPehtotreferesaelP:

1ETON

TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = 2.5V±5%, TA = -40°C TO 85°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

TUO

ycneuqerFtuptuO 66.1866.622zHM

)Ø(tij ;)modnaR(rettiJesahPSMR

1ETON

:egnaRnoitargetnI@zHM52.601

zHM01-zHk736 79.0sp

:egnaRnoitargetnI@zHM5.

781

zHM01-zHk736 85.0sp

:egnaRnoitargetnI@zHM5.212

zHM01-zHk736 59.0sp

emiTllaF/esiRtuptuO%08ot%02062sp

cdoelcyCytuDtuptuO 05%

.noitcessihtgniwollofstolPesioNesahPehtotreferesaelP:

1ETON

TABLE 3E. LVDS DC CHARACTERISTICS, VDD = VDDA = 2.5V±5%, TA = -40°C TO 85°C

lobmySretemaraPsnoitidnoCtseTmuminiMlacipyTmumixaMstinU

egatloVtuptuOlaitnereffiD 053Vm

ΔV

egnahCedutingaM 04Vm

egatloVtesffO 52.1V

ΔV

egnahCedutingaM 05Vm

.noitamrofnituptuorofnoitamrofnItnemerusaeMretemaraPotreferesaelP:ETON

844001AGI www.icst.com/products/hiperclocks.html REV. A JUNE 16, 2005

Integrated

Circuit

Systems, Inc.

ICS844001I

FEMTOCLOCKS™ C RYSTAL-TO- LVDS

CLOCK GENERATOR

PRELIMINARY

PARAMETER MEASUREMENT INFORMATION

OUTPUT RISE/FALL TIME OFFSET VOLTAGE SETUP

LVDS 3.3V OUTPUT LOAD AC TEST CIRCUIT LVDS 2.5V OUTPUT LOAD AC TEST CIRCUIT

RMS PHASE JITTER OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD

SCOPE

nQx

LVD S

3.3V±5%

POWER SUPPLY

Float GND

➤

100

out

LVDS

DC Input V

/Δ V

out

LVDS

DC Input

➤

/Δ V

VDD

Clock

Outputs 20%

80% 80%

20%

SWING

DIFFERENTIAL OUTPUT VOLTAGE SETUP

SCOPE

nQx

LVD S

2.5V±5%

POWER SUPPLY

Float GND

Phase Noise Mas

Offset Frequency

Phase Noise Plot

RMS Jitter = Area Under the Masked Phase Noise Plot

Noise Power

PERIOD

odc = x 100%

844001AGI www.icst.com/products/hiperclocks.html REV. A JUNE 16, 2005

Integrated

Circuit

Systems, Inc.

ICS844001I

FEMTOCLOCKS™ C RYSTAL-TO- LVDS

CLOCK GENERATOR

PRELIMINARY

APPLICATION INFORMATION

Figure 2. CRYSTAL INPUt INTERFACE

CRYSTAL INPUT INTERFACE

The ICS844001I has been characterized with 18pF parallel

resonant crystals. The capacitor values, C1 and C2, shown in

Figure 2

below were determined using a 26.5625MHz, 18pF par-

allel resonant crystal and were chosen to minimize the ppm er-

ror. The optimum C1 and C2 values can be slightly adjusted for

different board layouts.

33p

18pF Parallel Crystal

27p

XTAL_OUT

XTAL_IN

POWER SUPPLY FILTERING T ECHNIQUES

As in any high speed analog circuitry, the power supply pins

are vulnerable to random noise. The ICS844001I provides

separate power supplies to isolate any high switching

noise from the outputs to the internal PLL. VDD and VDDA should

be individually connected to the power supply

plane through vias, and bypass capacitors should be

used for each pin. To achieve optimum jitter performance,

power supply isolation is required.

Figure 1

illustrates how

a 10Ω resistor along with a 10μF and a .01μF bypass

capacitor should be connected to each VDDA pin. FIGURE 1. POWER SUPPLY FILTERING

10Ω

VDDA

10μF

.01μF

3.3V or 2.5V

.01μF

VDD

844001AGI www.icst.com/products/hiperclocks.html REV. A JUNE 16, 2005

Integrated

Circuit

Systems, Inc.

ICS844001I

FEMTOCLOCKS™ C RYSTAL-TO- LVDS

CLOCK GENERATOR

PRELIMINARY

3.3V, 2.5V LVDS DRIVER TERMINATION

A general LVDS interface is shown in

Figure 3.

In a 100Ω

differential transmission line environment, LVDS drivers

require a matched load termination of 100Ω across near

FIGURE 3. TYPICAL LVDS DRIVER TERMINATION

the receiver input. For a multiple LVDS outputs buffer, if only

partial outputs are used, it is recommended to terminate the

un-used outputs.

2.5V o r 3.3V

VDD

100 Ohm Different i al Trans miss i on Li ne

100

LVDS_Driver

844001AGI www.icst.com/products/hiperclocks.html REV. A JUNE 16, 2005

Integrated

Circuit

Systems, Inc.

ICS844001I

FEMTOCLOCKS™ C RYSTAL-TO- LVDS

CLOCK GENERATOR

PRELIMINARY

RELIABILITY INFORMATION

TRANSISTOR COUNT

The transistor count for ICS844001I is: 2533

TABLE 6. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP

θθ

θJA by Velocity (Meters per Second)

0 1 2.5

Multi-Layer PCB, JEDEC Standard Test Boards 101.7°C/W 90.5°C/W 89.8°C/W

844001AGI www.icst.com/products/hiperclocks.html REV. A JUNE 16, 2005

Integrated

Circuit

Systems, Inc.

ICS844001I

FEMTOCLOCKS™ C RYSTAL-TO- LVDS

CLOCK GENERATOR

PRELIMINARY

PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP

TABLE 7. PACKAGE DIMENSIONS

Reference Document: JEDEC Publication 95, MO-153

LOBMYS sretemilliM

muminiMmumixaM

A--02.1

1A50.051.0

2A08.050.1

b91.003.0

c90.002.0

D09.201.3

ECISAB04.6

1E03.405.4

eCISAB56.0

L54

.057.0

α°0°8

aaa--01.0

844001AGI www.icst.com/products/hiperclocks.html REV. A JUNE 16, 2005

Integrated

Circuit

Systems, Inc.

ICS844001I

FEMTOCLOCKS™ C RYSTAL-TO- LVDS

CLOCK GENERATOR

PRELIMINARY

TABLE 8. ORDERING INFORMATION

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use

or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use

in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not

recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product

for use in life support devices or critical medical instruments.

rebmuNredrO/traPgnikraMegakcaPgnigakcaPgnippihSerutarepmeT

IGA100448SCIA1004POSSTdael8ebutC°58otC°04-

TIGA10044

8SCIA1004POSSTdael8leer&epatC°58otC°04-

The aforementioned trademarks, HiPerClockS™ and FemtoClocks™ are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.