IRDC3822A
Rev 0.0
02/22/2008 1
IRDC3822A
Rev 0.0
02/22/2008 2
SupIRBuckTM
USER GUIDE FOR IR3822A EVALUATION BOARD
DESCRIPTION
The IR3822A is a synchronous buck
converter, providing a compact, high
performance and flexible solution in a small
5mmx6mm Power QFN package.
Key features offered by the IR3822A include
programmable soft-start ramp, precision
0.6V reference voltage, programmable
Power Good,thermal protection, fixed
300kHz switching frequency requiring no
external component, input under-voltage
lockout for proper start-up, and pre-bias
start-up.
An output over-current protection function is
implemented by sensing the voltage developed
across the on-resistance of the synchronous
rectifier MOSFET for optimum cost and
performance.
This user guide contains the schematic and bill
of materials for the IR3822A evaluation board.
The guide describes operation and use of the
evaluation board itself. Detailed application
information for IR3822A is available in the
IR3822A data sheet.
BOARD FEATURES
•Vin = +12V (13.2V Max)
•Vout = +1.8V @ 0- 6A
•L= 2.2uH
•Cin= 3x10uF (ceramic 1206) + 330uF (electrolytic)
•Cout= 6x22uF (ceramic 0805)
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CONNECTIONS and OPERATING INSTRUCTIONS
A well regulated +12V input supply should be connected to VIN+ and VIN-. A maximum 6A load should be
connected to VOUT+ and VOUT-. The connection diagram is shown in Fig. 1 and inputs and outputs of the
board are listed in Table I.
IR3822A has two input supplies, one for biasing (Vcc) and the other as input voltage (Vin). These inputs are
connected on the board with a zero ohm resistor (R15). Separate supplies can be applied to these inputs.
Vcc input cannot be connected unless R15 is removed. Vcc input should be a well regulated 5V-12V supply
and it would be connected to Vcc+ and Vcc-.
Table I. Connections
Connection Signal Name
VIN+ Vin (+12V)
VIN- Ground of Vin
Vcc+ Optional Vcc input
Vcc- Ground for Optional Vcc input
VOUT- Ground of Vout
VOUT+ Vout (+1.8V)
P_Good Power Good Signal
LAYOUT
The PCB is a 4-layer board. All of layers are 2 Oz. copper. The IR3822A SupIRBuck and all of the
passive components are mounted on the top side of the board.
Power supply decoupling capacitors, the charge-pump capacitor and feedback components are located
close to IR3822A. The feedback resistors are connected to the output voltage at the point of regulation
and are located close to the SupIRBuck.
To improve efficiency, the circuit board is designed to minimize the length of the on-board power ground
current path.
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Connection Diagram
V
P
V
in = +12v GROUND
VCC+
GROUND
Good
OUT = +1.8v
GROUND
Fig. 1: Connection diagram of IR3822A evaluation board
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Fig. 2: Board layout, top overlay
Fig. 3: Board layout, bottom overlay (rear view)
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Fig. 4: Board layout, mid-layer I.
AGND
Plain PGND
Plain
Fig. 5: Board layout, mid-layer II.
Single point
connection
between AGND
and PGND.
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Fig. 6: Schematic of the IR3822A evaluation board
Single point of connection between Pow er
Ground and Signal ( “analog” ) Ground
Vout-
1
+
C21
N/S
+
C22
N/S
Vin
C14
0.1uF
Vcc-
1
C10
0.22uF
PGND
1
C12
0.1uF
C24
1000pF
C23
N/S
D1
BAT54S
12
3
C26
1000pF
C13
1uF
Vout
Vcc+
1
C2
10uF
C5
N/S
R9
0
R1
34.8k
R10
N/S
C3
10uF
R3
40.2K
R4
2.61K
R2
80.6k
C4
10uF
C15
22uF
R6
20
C16
22uF
C25
0.1uF
C17
22uF
R12
12.4K
J1
SS
C9
N/S
C18
22uF C19
22uF C20
22uF
A
1
B
1
D2
N/S
12
R18
N/S
+
C1
330uF
L1
2.2uH
VCC
C8
180pF
C7
0.1uF
R15
0
Agnd
1
Vin+
1
Vin-
1
Vout+
1
Vout-
1
U1
IR3822A
Vc 14
Hg 13
AGnd3
15
AGnd2
5SW 11
PGood
9
COMP
3
OCset
7PGnd 10
SS
6
Vsns
1
FB
2
AGnd1
4
Vcc
8
Vin 12
R17
10K
PGood
1
C11
22pF
C6
N/S
VCC
VCC
Vin+
1
R16
3.09k
Vin-
1
R14
10k
Vout+
1
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Bill of Materials
It em Quantity Designat or Value Description Siz e Manufact urer Mfr . Part Number
1 1 C1 330uF SMD Elec trolytic, 25V, 20% SMD Panasonic EEV-FK1E331P
2 3 C2 C3 C4 10uF Ceramic, 16V, X7R, 10% 1206 Panasoni c EC J-3YX1C106K
34 C7 C12 C14
C25 0. 1uF C eramic, 50V, X7R, 10% 0603 Panasoni c EC J-1VB1H104K
4 1 C10 0. 22uF Ceramic, 10V, X5R, 10% 0603 Panasoni c EC J-1VB1A224K
5 1 C8 180pF Ceramic, 50V, NPO, 5% 0603 Murata GRM1885C1H181J A01
6 1 C11 22pF Ceramic, 50V, NPO, 5% 0603 Murata GRM1885C1H220J A 01
7 1 C13 1uF Ceramic, 16V, X5R, 10% 0603 Panasoni c EC J-1VB1C105K
86 C15 C16 C17
C18 C19 C20 22uF Ceramic, 6.3V, X5R, 20% 0805 Panasoni c EC J-2FB0J226M
9 2 C24, C26 1000pF Ceramic, 50V, NPO, 5% 0603 Murata GRM1885C1H102JA01
10 1 D1 BAT54S Diode Schottky , 40V , 200mA SOT- 23 Fai rchi ld BAT54S
11 1 L1 2.2uH SMT I nductor , 4. 2mOhm,
20% 11.8x
10.5mm ACT STS1205-2R2
12 1 R1 34. 8K Thick film, 1/10W, 1% 0603 Vishey/D ale CRCW060334K8FKE A
13 1 R3 40. 2K Thick film, 1/10W, 1% 0603 Vishey/D ale CRCW060340K2FKE A
14 1 R2 80. 6K Thick film, 1/10W, 1% 0603 Vishey/D ale CRCW060380K6FKE A
15 1 R4 2.61K Thi ck film, 1/10W, 1% 0603 Vi shey/Dale CRCW06032K61FKEA
16 1 R6 20 Thick film, 1/10W, 1% 0603 Vishey/D ale CRCW060320R0FKEA
17 2 R9 R15 0 Thick film, 1/10W, 1% 0603 Vishey/Dale CRCW06030000Z0E A
18 1 R12 12. 4K Thick film, 1/10W, 1% 0603 Vishey/D ale CRCW060312K4FKE A
19 2 R14, R17 10K Thick film, 1/10W, 1% 0603 Vishey/D ale CRCW060310K0FKE A
20 1 R16 3. 09K Thick film, 1/10W, 1% 0603 Vishey/Dale CRCW06033K09FKEA
21 1 U1 IR3822A 300kHz, 6A, SupIRB uck
Module 5x6mm International
Rectifier IR3822A
22 2 - - Banana Jack, Insulated
Solder Terminal, B lac k -Johnson
Components 105-0853-001
23 1 - - Banana Jack- Insulated
Solder Terminal, Red -Johnson
Components 105-0852-001
24 1 - - Banana Jack- Insulated
Solder Terminal, Green -Johnson
Components 105-0854-001
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TYPICAL OPERATING WAVEFORMS
Vin=Vcc=12.0V, Vo=1.8V, Io=0- 6A, Room Temperature, No Air Flow
Fig. 10: Output Voltage Ripple, 6A load
Ch1: Vout ,Ch4: Iout
Fig. 11: Inductor node at 6A load
Ch1:LX, Ch4:Iout
Fig. 12: Short (Hiccup) Recovery
Ch1:VSS , Ch2:Vout
Fig. 8: Start up at 6A Load,
Ch1:Vin, Ch2:VSS, Ch3:Vout, Ch4:VPGood
Fig. 7: Start up at 6A Load
Ch1:Vin, Ch2:VSS, Ch3:Vout, Ch4:Iout
Fig. 9: Start up with 0.5V Pre Bias, 0A
Load, Ch1:Vin, Ch2:VSS, Ch3:Vout
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TYPICAL OPERATING WAVEFORMS
Vin=Vcc=12V, Vo=1.8V, Io=3A- 6A, Room Temperature, No Air Flow
Fig. 13: Transient Response, 3A to 6A step
Ch1:Vout, Ch4:Iout
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TYPICAL OPERATING WAVEFORMS
Vin=Vcc=12V, Vo=1.8V, Io=6A, Room Temp erature, No Air Flow
Fig. 14: Bode Plot at 6A load shows a bandwidth of 52.7kHz and phase margin of 52 degrees
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55
60
65
70
75
80
85
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Load Current (A)
Efficiency (%)
Efficiency Vin =Vcc= 12V Effici ency Vin=12V Vcc=5V
TYPICAL OPERATING WAVEFORMS
Vin=12V, Vo=1 .8V, Io=0- 6A, Room Temper ature, No Air Flow
Fig.15: Efficiency versus load current
0.2
0.6
1.0
1.4
1.8
2.2
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0
Load Current (A)
Power Loss (W)
Power Loss Vin=V cc=12V Power Loss Vi n=12V Vcc=5V
Fig.16: Power loss versus load current
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THERMAL IMAGES
Vin=12V, Vo=1.8V, Io=6A, Room Temperature, No Air Flow
Fig. 17: Thermal Image at 6A load
Test point 3 is IR3822A
IRDC3822A
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PCB Metal and Components Placement
The lead lands (the 11 IC pins) width should be equal to the nominal part lead width. The minimum
lead to lead spacing should be ≥0.2mm to minimize shorting.
Lead land length should be equal to the maximum part lead length + 0.3 mm outboard extension. The
outboard extension ensures a large and inspectable toe fillet.
The pad lands (the 4 big pads other than the 11 IC pins) length and width should be equal to
maximum part pad length and width. Howe ver, the minimum metal to metal spacing should be no less
than 0.17mm for 2 oz. Copper; no less than 0.1mm for 1 oz. Copper and no less than 0.23mm for 3 oz.
Copper.
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Solder Resist
It is recommended that the lead lands are Non Solder Mask Defined (NSMD). The solder resist
should be pulled away from the metal lead lands by a minimum of 0.025mm to ensure NSMD
pads.
The land pad should be Solder Mask Defined (SMD), with a minimum overlap of the solder resist
onto the copper of 0.05mm to accommodate solder resist mis-alignment.
Ensure that the solder resist in between the lead lands and the pad land is ≥0.15mm due to the
high aspect ratio of the solder resist strip separating the lead lands from the pad land.
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Stencil Design
• The Stencil apertures for the lead lands should be approximately 80% of the area of the
lead lads. Reducing the amount of solder deposited will minimize the oc currences of lead
shorts. If too much solder is deposited on the center pad the part will float and the lead
lands will be open.
• The maximum length and width of the land pad stencil aperture should be equal to the
solder resist opening minus an annular 0.2mm pull back to decrease the incidence of
shorting the center land to the lead lands when the part is pushed into the solder paste.
IRDC3822A
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02/22/2008
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
This product has been designed and qualified for the Consumer market.
Visit us at www.irf.com for sales contact information
Data and specifications subject to change without notice. 11/07
