MM54HC32/MM74HC32 Quad 2-Input OR Gate General Description These OR gates utilize advanced silicon-gate CMOS tech- nology to achieve operating speeds similar to LS-TTL gates with the low power consumption of standard CMOS inte- grated circuits. All gates have buffered outputs, providing high noise immunity and the ability to drive 10 LS-TTL loads. The 54HG/74HC logic family is functionally as well as pin- out compatible with the standard 54LS/74LS logic family. All inputs are protected from damage due to static dis- charge by internal diode clamps to Vcc and ground. (AV vational Semiconductor January 1988 Features @ Typical propagation delay: 10 ns m@ Wide power supply range: 2-6V m Low quiescent current: 20 wA maximum (74HC Series) @ Low input current: 1 2A maximum @ Fanout of 10 LS-TTL loads Connection and Logic Diagrams Dual-In-Line Package Vec -B4 A4 4 B3 A3 Y3 [14 13 | 12 1 10 |9 |e + |2 |e | Js |e |r Al B1 Y1 A2 B2 Y2 GND TL/F/5132-1 Top View Order Number MM54HC32 or MM74HC32 (1 of 4) Y=A+B TL/F/5132-2 1995 National Semiconductor Corporation TL/F/5132 RRD-B30M105/Printed in U.S. A. 975 HO indul-z pend ZEOHPZW/ZEOHPSWNAbsolute Maximum Ratings (notes 1 2 2) Operating Conditions If Military/Aerospace specified devices are required, Min Max Units please contact the National Semiconductor Sales Supply Voltage (Vcc) 2 6 v Office/Distributors for availability and specifications. DG Input or Output Voltage 0 Voc Vv Supply Voltage (Vec) 0.5 to +7.0V (Vin. Vout) DC Input Voltage (Vin) 1.5 to Voot 1.5V Operating Temp. Range (Ta) DC Output Voltage (Vout) 0.5 to Veg + 0.5V MM74HC 40 +85 C Clamp Diode Current (lik, lox) +20 mA | een callT 55 +125 Cc : nput Rise or Fall Times + DC Output Current, per pin (lour) +25mA (ist) Voo=2.0V 4000 ns DC Vcc or GND Current, per pin (loc) +50 mA Voo=4.5V 500 ns Storage Temperature Range (Tstq) 65C to + 150C Voc =6.0V 400 ns Power Dissipation (Pp) (Note 3) 600 mw S.O. Package only 500 mw Lead Temperature (T,) (Soldering 10 seconds) 260C DC Electrical Characteristics (note 4) 1, =25C 74HC 54HC Symbol Parameter Conditions Vee A Ta=40 to 85C | Ta= 55to 125C | Units Typ Guaranteed Limits Vin Minimum High Level 2.0V 1.5 1.5 1.5 Vv Input Voltage 4.5V 3.15 3.15 3.15 Vv 6.0V 4.2 4.2 4.2 Vv VIL Maximum Low Level 2.0V 0.5 0.5 0.5 v Input Voltage** 4.5V 1.35 1.35 1.35 Vv 6.0V 1.8 1.8 1.8 Vv Vou Minimum High Level | Vin= Vin or Vit Output Voltage llour| <20 pA 20V| 20 |] 1.9 1.9 1.9 Vv 45V | 45 4.4 4.4 4.4 Vv 6.0V | 6.0 5.9 5.9 5.9 V Vin= Vin or Vit \lout| <4.0 mA 45V | 4.7 | 3.98 3.84 3.7 Vv llour| <5.2 mA 6.0V | 5.2 | 5.48 5.34 5.2 Vv VoL Maximum Low Level | Vin=ViL Output Voltage llout|<20 pA 20v | 0 04 04 04 v 4.5V 0 01 01 01 v 6.0V 0 0.1 0.1 04 Vv Vin= Vit \lout| <4.0 mA 45V | 0.2 | 0.26 0.33 0.4 Vv \lout|<5.2 mA 6.0V | 0.2 | 0.26 0.33 0.4 Vv lin Maximum Input Vin=VccorGND | 6.0V +04 +1.0 +1.0 pA Current loc Maximum Quiescent | Vin=VccorGND | 6.0V 2.0 20 40 pA Supply Current louT=0 pA Note 1; Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating plastic N package: 12 mW/C from 65C to 85C; ceramic J package: 12 mW/C from 100C to 125C, Note 4: For a power supply of 5V +10% the worst case output voltages (Voy, and Vo.) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case Vi} and Vi, occur at Voc = 5.5V and 4.5V respectively. (The V4 value at 5.5V is 3.85V.) The worst case leakage current (lin, loc, and loz) occur for CMOS at the higher voltage and so the 6.0V values should be used. **Viz limits are currently tested at 20% of Voc. The above Vi_ specification (30% of Voc) will be implemented no later than Q1, CY89.AC Electrical Characteristics v..=sv, T,= 25C, C, =15 pF, ,=1;=6 ns Symbol Parameter Conditions Typ oe Units TPHL: tPLH Maximum Propagation 10 18 ns Delay AC Electrical Characteristics Voc =2.0V to 6.0V, C_ =50 pF, t-=tp=6 ns (unless otherwise specified) 74HC 54HC Ta=25C Symbol Parameter Conditions | Vcc Ta=40 to 85C | Ta=55 to 125C | Units Typ Guaranteed Limits tpHL tpLH | Maximum Propagation 2.0V 30 100 125 150 ns Delay 4.5V 12 20 25 30 ns 6.0V 9 17 21 25 ns tty. ttrHL | Maximum Output Rise 2.0V 30 75 95 110 ns and Fall Time 4.5V 8 15 19 22 ns 6.0V 7 13 16 19 ns Cpp Power Dissipation (per gate) 50 pF Capacitance (Note 5) Cin Maximum Input 5 10 10 10 pF Capacitance Note 5: Cpp determines the no load dynamic power consumption, Pp = Cpp Voc? f+ loc Voc, and the no load dynamic current consumption, Is =Cpp Vcc f+lcec. Physical Dimensions inches (millimeters) 0.025 (0.635) RAD 0.290-0.320 0.005 (7.3668.128) (0.127) MIN 0.180 (4.572) { 9604 TYP W 10 MAX 0.008-0.012 0.310-0.410 (0.2030.305) (7874-1041) 0.098 | (2.488) 0.785 (19.939) MAX fal [3] fre] [7] [ro] [21 [a] 0.060 +0.005 (1.524 +0.127) 0.2200.310 (5.588-7.874) 0.200 (5.080) MAX 9.020-0.060 GLASS oi ] MAX BOTH ENDS 0.018 +0.003 ~|| oe OS | ae (0.457 +0.076) 0.100 +0.070 (0.508-1.524) (2.540 +0.254) Dual-In-Line Package (J) Order Number MM54HC32J or MM74HC32J NS Package Number J14A 0.125-0.200 (3.175-5.080) 0.150 (3.81) MIN J14A (REV Q)MM54HC32/MM74HC32 Quad 2-Input OR Gate Physical Dimensions: inches (mitimeters) (Continued) PIN NO. 1 WENT se DET TST TT syst 0 0,7400.770 (18.8019.56) 0.090 le 2ge) [3] 2) (9) [ro] Cs) fe] rc D 0,250 0.010 a (6.3500.264) 9.002 54, 0.030 max 7 (2.337) 10.762) DEPTH OPTION 1 0.135 = 0.005 {3.4290.127) 0.145 -0.200 {3.583 5.080) 0.060 O80 Typ i fg. 4? TYP (1.524) a \ OFTIONAL \ 0.020 (0.508) MIN .125D.150 (2.1789.810) 0.014 -0.023 10.356 0.584) LIFE SUPPORT POLICY TYP A ; i 90 44 TYP | ia 0.075+0.015 " =" 41-905-0.381) | 0.100.010 {2.540 0,254) we 0.050 0,010 (1-270 - 0.254) INDEX _ AREA a PINNO.1 + IDENT OPTION 02 0.300 -0.320 (7-620 -8.125} 0.065 >| (1.61) 95 5 0.008 0.016 "(0.203 0.408) 0.280 |e(7.112) >] MIN | +0.0a0 =0.015 (e288 +1 8) _-- 0.325 0.381 Dual-in-Line Package (N) Order Number MM74HC32N NS Package Number N14A Naa EV FL NATIONALS PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 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