Rev.2.00 May 28, 2004 page 1 of 100
38C2 Group (A Version)
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER REJ03B0096-0200Z
Rev.2.00
May 28, 2004
DESCRIPTION
The 38C2 group (A version) is the 8-bit microcomputer based on the
740 family core technology.
The 38C2 (A version) group has an LCD drive control circuit, a 10-
channel A-D converter, and a serial I/O as additional functions.
The various microcomputers in the 38C2 group (A version) include
variations of internal memory size and packaging. For details, refer
to the section on part numbering.
FEATURES
●Basic machine-language instructions ....................................... 71
●The minimum instruction execution time .......................... 0.40 µs
(at 10 MHz oscillation frequency)
●Memory size
ROM ................................................................16 K to 60 K bytes
RAM ................................................................. 640 to 2048 bytes
●Programmable input/output ports ......... 51 (common to SEG: 24)
●Interrupts................................................... 18 sources, 16 vectors
●Timers ............................................................8-bit ✕ 4, 16-bit ✕ 2
●A-D converter................................................. 10-bit ✕ 8 channels
●Serial I/O ........................8-bit ✕ 2 (UART or Clock-synchronized)
●PWM .................. 10-bit ✕ 2, 16-bit ✕ 1 (common to IGBT output)
●LCD drive control circuit
Bias ................................................................................... 1/2, 1/3
Duty ........................................................................... 1/2, 1/3, 1/4
Common output .......................................................................... 4
Segment output ........................................................................ 24
●Two clock generating circuits
(connect to external ceramic resonator or quartz-crystal oscillator)
●Watchdog timer............................................................... 8-bit ✕ 1
● LED direct drive port .................................................................. 8
(average current: 15 mA, peak current: 30 mA, total current: 90 mA)
●Power source voltage
• Mask ROM version
In frequency/2 mode ...................................................4.5 to 5.5 V
(at 10 MHz oscillation frequency)
In frequency/2 mode ...................................................4.0 to 5.5 V
(at 8 MHz oscillation frequency)
In frequency/4 mode ...................................................1.8 to 5.5 V
(at 4 MHz oscillation frequency, A-D operation excluded)
In low-speed mode .....................................................1.8 to 5.5 V
(at 32 kHz oscillation frequency)
• Flash memory version
In frequency/2 mode ...................................................4.5 to 5.5 V
(at 10 MHz oscillation frequency)
In frequency/2 mode ...................................................4.0 to 5.5 V
(at 8 MHz oscillation frequency)
In frequency/4 mode ...................................................2.5 to 5.5 V
(at 8 MHz oscillation frequency)
In low-speed mode .....................................................2.5 to 5.5 V
(at 32 kHz oscillation frequency)
●Power dissipation
• In frequency/2 mode (at 8 MHz oscillation frequency, VCC = 5 V)
Mask ROM version ............................................................14 mW
Flash memory version .......................................................25 mW
• In low-speed mode (at 32 kHz oscillation frequency, VCC = 3 V)
Mask ROM version .............................................................24 µW
Flash memory version ......................................................375 µW
●Operating temperature range ................................... – 20 to 85°C
Rev.2.00 May 28, 2004 page 2 of 100
38C2 Group (A Version)
PIN CONFIGURATION
(TOP VIEW)
Package type : 64P6U-A/64P6Q-A
Fig. 1 M38C2XMXA-XXXFP/HP pin configuration
P
0
6
/
S
E
G
6
P
0
7
/
S
E
G
7
P
1
0
/
S
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8
P
1
1
/
S
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G
9
P
1
2
/
S
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G
1
0
P
1
3
/
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1
1
P
1
4
/
S
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G
1
2
P
1
5
/
S
E
G
1
3
P
1
6
/
S
E
G
1
4
P
1
7
/
S
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G
1
5
P
6
0
/
C
N
T
R
1
P
3
7
/
C
N
T
R
0
/
(
L
E
D
7
)
6
1
3
2
3
1
3
0
2
9
28
27
26
25
24
23
22
21
6 7 8 9 10111213141516
4
544434
24140393
8373
63
53
43
3
P
2
4
/
S
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2
0
P
2
5
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2
1
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2
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1
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M
0
P
2
7
/
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2
3
/
V
L
2
P
2
6
/
S
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2
2
/
V
L
1
CO
M
3
(
K
W
7
)
/
P
0
3
/
S
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G
3
P
0
4
/
S
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4
P
0
5
/
S
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G
5
P
5
1
/
I
N
T
1
(
K
W
2
)
/
P
5
6
/
S
C
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K
1
(
K
W
1
)
/
P
5
5
/
T
X
D
1
(KW
0
)/
P
5
4
/R
X
D
1
5
3
/T
4OUT
/
WM
1
P
2
0
/
S
E
G
1
6
P
2
1
/
S
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G
1
7
P
2
2
/
S
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1
8
P
2
3
/
S
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G
1
9
4
9
5
0
5
1
5
2
5
3
4
84
74
6
6
2
6
3
6
4
12345
20
19
18
17
5
5
5
6
5
7
5
8
5
9
6
0
M
3
8
C
2
X
M
X
A
-
X
X
X
F
P
/
H
P
M
3
8
C
2
9
F
F
A
F
P
/
H
P
5
4
P
3
6
/T
2OUT
/φ/(LED
6)
X
O
U
T
5
2
/
T
3
O
U
T
/
W
M
0
VRE
F
V
L
3
P
4
3
/
A
N
3
P
4
2
/
A
N
2
P
4
4
/
A
N
4
P
4
7
/
R
T
P
1
/
A
N
7
P
4
6
/RT
P
0
/AN
6
P
4
5
/
A
N
5
V
S
S
P
3
2
/
T
X
D
2
/
(
L
E
D
2
)
P
3
1
/
S
C
L
K
2
/
(
L
E
D
1
)
P
3
3
/
R
X
D
2
/
(
L
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D
3
)
P
5
0
/INT
0
A
V
S
S
(
K
W
6
)
/
P
0
2
/
S
E
G
2
(
K
W
5
)
/
P
0
1
/
S
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G
1
(
K
W
4
)
/
P
0
0
/
S
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G
0
P
4
1
/
O
O
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T
1
/
A
N
1
P
4
0
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A
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C
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S
S
P
6
2
/
X
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6
1
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C
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C
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S
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(
K
W
3
)
/
P
5
7
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S
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1
P
3
0
/
S
R
D
Y
2
/
(
L
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D
0
)
P
3
5
/T
XOUT
/(LED
5)
P
3
4
/
I
N
T
2
/
(
L
E
D
4
)
Rev.2.00 May 28, 2004 page 3 of 100
38C2 Group (A Version)
FUNCTIONAL BLOCK DIAGRAM
Fig. 2 Functional block diagram
T
i
m
e
r
T
i
m
e
r
X
(
1
6
b
i
t
s
)
P
W
M
(
1
6
b
i
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s
)
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G
B
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p
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T
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Y
(
1
6
b
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T
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1
(
8
b
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T
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2
(
8
b
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T
i
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3
(
8
b
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P
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0
(
1
0
b
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T
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4
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8
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1
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0
b
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P
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P
0
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8
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8
P
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P
1
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8
)
8
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2
(
8
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8
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8
8
P
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4
(
8
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P
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5
(
8
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6
(
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P
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3
(
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8
3
Rev.2.00 May 28, 2004 page 4 of 100
38C2 Group (A Version)
• Apply voltage of 1.8 V to 5.5 V to VCC, and 0 V to VSS.
•Reference voltage input pin for A-D converter.
•GND input pin for A-D converter. Connect to VSS.
•Reset input pin for active “L.”
•Input and output pins for the main clock generating circuit.
•Feedback resistor is built in between XIN pin and XOUT pin.
•Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins to
set the oscillation frequency. When an external clock is used, connect the clock source to XIN,
and leave XOUT pin open.
• Input 0 ≤ VL1 ≤ VL2 ≤ VL3 ≤ VCC voltage.
•Input 0 – VL3 voltage to LCD.
•LCD common output pins.
•COM2 and COM3 are not used at 1/2 duty ratio.
•COM3 is not used at 1/3 duty ratio.
• 8-bit I/O port.
• CMOS compatible input level.
•CMOS 3-state output structure.
•I/O direction register allows each pin to be individually
programmed as either input or output.
• Pull-up control is enabled in a bit unit.
VCC, VSS
VREF
AVSS
RESET
XIN
VL3
COM0 –
COM3
P00/SEG0 –
P03/SEG3
P04/SEG4 –
P07/SEG7
P10/SEG8 –
P17/SEG15
P20/SEG16 –
P25/SEG21
P26/SEG22/VL1
P27/SEG23/VL2
P30/SRDY2
P31/SCLK2
P32/TxD2
P33/RxD2
P34/INT2
P35/TXOUT
P36/T2OUT/φ
P37/CNTR0
P40/OOUT0/AN0
P41/OOUT1/AN1
P42/AN2–
P45/AN5
P46/RTP0/AN6
P47/RTP1/AN7
P50/INT0
P51/INT1
P52/T3OUT/PWM0
P53/T4OUT/PWM1
P54/RxD1
P55/TxD1
P56/SCLK1
P57/SRDY1
Power source
Analog reference
voltage
Analog power source
Reset input
Clock input
LCD power
source
Common output
I/O port P0
I/O port P1
I/O port P2
I/O port P3
I/O port P4
I/O port P5
Function except a port function
PIN DESCRIPTION
Table 1 Pin description (1)
Function
Pin Name
•LCD segment
output pins
• Serial I/O2 function pins
•External interrupt pin
• Timer X, Timer 2 output pins
• Timer X function pin
• AD converter input
pins
•External interrupt pins
•Timer 3, Timer 4 output pins
•PWM output pins
•Serial I/O1 function pins
•Key input interrupt input pins
•Key input interrupt
pins
•LCD power source
input pins
•Oscillation external
output pins
•Real time port
function pins
XOUT Clock output
Rev.2.00 May 28, 2004 page 5 of 100
38C2 Group (A Version)
Function except a port function
PIN DESCRIPTION
Table 2 Pin description (2)
FunctionPin Name
P60/CNTR1
P61/XCIN
P62/XCOUT
CNVSS
I/O port P6
CNVSS
•3-bit I/O port.
•CMOS compatible input level.
•CMOS 3-state output structure.
•I/O direction register allows each pin to be individually
programmed as either input or output.
•Pull-up control is enabled.
•VPP power input pin in the flash mode. When MCU is operating, connect to VSS.
•Timer Y function pin
•Sub clock generating I/O pin (resonator
connected)
Rev.2.00 May 28, 2004 page 6 of 100
38C2 Group (A Version)
PART NUMBERING
Fig. 3 Part numbering
M
3
8
C
2
9
M
C
A
–
X
X
X
H
P
P
r
o
d
u
c
t
ROM
/
Fl
as
h
me mory s
i
ze
1
2
3
4
5
6
7
8
: 4096
b
ytes
: 8192 by tes
: 12288 bytes
: 16384 bytes
: 20480 bytes
: 24576 bytes
: 28672 bytes
: 32768 bytes
Th
e
fi
rst 128
b
ytes an
d
t
h
e
l
ast 2
b
ytes o
f
ROM
a r e reserved areas ; they c annot be used .
M
emory type
M
F :
M
a
s
k
R
O
M
v
e
r
s
i
o
n
:
F
l
a
s
h
m
e
m
o
r
y
v
e
r
s
i
o
n
RAM
s
i
ze
0
1
2
3
4
5
6
7
8
9
: 192
b
ytes
: 256 by tes
: 384 by tes
: 512 by tes
: 640 by tes
: 768 by tes
: 896 by tes
: 1024 by tes
: 1536 by tes
: 2048 by tes
P
a
c
k
a
g
e
t
y
p
e
F
P
H
P
ROM
num
b
er
Omitted in Flash memory version.
Ch
aracter
i
st
i
cs
A : A ver sion
: 64P6U - A pac kage
: 64P6Q-A package
9
A
B
C
D
E
F
: 36864
b
ytes
: 40960 bytes
: 45056 bytes
: 49152 bytes
: 53248 bytes
: 57344 bytes
: 61440 bytes
Rev.2.00 May 28, 2004 page 7 of 100
38C2 Group (A Version)
GROUP EXPANSION
Renesas plans to expand the 38C2 group (A version) as follows.
Memory Type
Support for mask ROM, Flash memory versions
Memory Size
ROM/flash memory size......................................16 K to 60 K bytes
RAM size............................................................. 640 to 2048 bytes
Memory Expansion Plan
Fig. 4 Memory expansion plan
Currently supported products are listed below.
As of May.2004
Package
64P6U-A
64P6Q-A
64P6U-A
64P6Q-A
64P6U-A
64P6Q-A
64P6U-A
64P6Q-A
Product name ROM size (bytes)
ROM size for User in ( )
49152 (49022)
24576 (24446)
16384 (16254)
61440 (61310)
RAM size
(bytes)
2048
640
640
2048
Table 3 Support products
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
Mask ROM version
Flash memory version
Flash memory version
Remarks
Packages
64P6Q-A ..................................... 0.5 mm-pitch plastic molded QFP
64P6U-A ..................................... 0.8 mm-pitch plastic molded QFP
ROM size (bytes)
32
K
28
K
24
K
20
K
16
K
12
K
8
K
4
K
256 384 512 640 768 896 1024
192
RAM size
(
b
y
tes
)
40
K
48
K
56K
60K
Mass production
Mass production
Mass production
1536 2048
M38C24M6A
M38C24M4A
AAAAAAAA
AAAAAAAA
M38C29FFA
Mass production
AAAAAAAA
AAAAAAAA
AAAAAAAA
M38C29MCA
M38C29MCA-XXXFP
M38C29MCA-XXXHP
M38C24M6A-XXXFP
M38C24M6A-XXXHP
M38C24M4A-XXXFP
M38C24M4A-XXXHP
M38C29FFAFP
M38C29FFAHP
Rev.2.00 May 28, 2004 page 8 of 100
38C2 Group (A Version)
FUNCTIONAL DESCRIPTION
Central Processing Unit (CPU)
The 38C2 group uses the standard 740 Family instruction set. Refer
to the table of 740 Family addressing modes and machine instruc-
tions or the 740 Family Software Manual for details on the instruction
set.
Machine-resident 740 Family instructions are as follows:
The FST and SLW instructions cannot be used.
The STP, WIT, MUL, and DIV instructions can be used.
The central processing unit (CPU) has six registers. Figure 5 shows
the 740 Family CPU register structure.
[Accumulator (A)]
The accumulator is an 8-bit register. Data operations such as arith-
metic data transfer , etc., are executed mainly through the accumula-
tor.
[Index Register X (X)]
The index register X is an 8-bit register . In the index addressing modes,
the value of the OPERAND is added to the contents of register X and
specifies the real address.
[Index Register Y (Y)]
The index register Y is an 8-bit register. In partial instruction, the
value of the OPERAND is added to the contents of register Y and
specifies the real address.
[Stack Pointer (S)]
The stack pointer is an 8-bit register used during subroutine calls
and interrupts. This register indicates start address of stored area
(stack) for storing registers during subroutine calls and interrupts.
The low-order 8 bits of the stack address are determined by the con-
tents of the stack pointer. The high-order 8 bits of the stack address
are determined by the stack page selection bit. If the stack page
selection bit is “0” , the high-order 8 bits becomes “0016”. If the stack
page selection bit is “1”, the high-order 8 bits becomes “0116”.
The operations of pushing register contents onto the stack and pop-
ping them from the stack are shown in Figure 6.
Store registers other than those described in Figure 6 with program
when the user needs them during interrupts or subroutine calls.
[Program Counter (PC)]
The program counter is a 16-bit counter consisting of two 8-bit regis-
ters PCH and PCL. It is used to indicate the address of the next in-
struction to be executed.
Fig. 5 740 Family CPU register structure
A Accumulator
b7
b7
b7
b7 b0
b7b15 b0
b7 b0
b0
b0
b0
X Index register X
Y Index register Y
S Stack pointer
PCLProgram counterPCH
N V T B D I Z C Processor status register (PS)
Carry flag
Zero flag
Interrupt disable flag
Decimal mode flag
Break flag
Index X mode flag
Overflow flag
Negative flag
Rev.2.00 May 28, 2004 page 9 of 100
38C2 Group (A Version)
Table 4 Push and pop instructions of accumulator or processor status register
Accumulator
Processor status register
Push instruction to stack
PHA
PHP
Pop instruction from stack
PLA
PLP
Fig. 6 Register push and pop at interrupt generation and subroutine call
Note: Condition for acceptance of an interrupt request here Interrupt enable bit corresponding to each interrupt source is “1”
E
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J
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On-going Routin
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M
(
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)(
P
C
H
)
(
S
)
(
S
)
–
1
M
(
S
)(
P
C
L
)
Execute RTS
(
P
C
L
)M
(
S
)
(
S
)
(
S
)
–
1
(S)
(S) + 1
(S)
(S) + 1
(PC
H
)M (S)
S
u
b
r
o
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t
i
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POP return
address from stack
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T
I
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(
S
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(
S
)
–
1
(S)
(S) + 1
Interrupt
Service Routine
P
O
P
c
o
n
t
e
n
t
s
o
f
p
r
o
c
e
s
s
o
r
s
t
a
t
u
s
r
e
g
i
s
t
e
r
f
r
o
m
s
t
a
c
k
M (S) (PC
H
)
(S)
(S) – 1
M (S) (PC
L
)
(
S
)
(
S
)
–
1
(PC
L
)M (S)
(
S
)
(
S
)
+
1
(S)
(S) + 1
(PC
H
)M (S)
POP return
address
from stack
I Flag is set from “0” to “1”
Fetch the jump vector
P
u
s
h
r
e
t
u
r
n
a
d
d
r
e
s
s
o
n
s
t
a
c
k
P
u
s
h
c
o
n
t
e
n
t
s
o
f
p
r
o
c
e
s
s
o
r
s
t
a
t
u
s
r
e
g
i
s
t
e
r
o
n
s
t
a
c
k
I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
(
N
o
t
e
)
I
n
t
e
r
r
u
p
t
e
n
a
b
l
e
b
i
t
c
o
r
r
e
s
p
o
n
d
i
n
g
t
o
e
a
c
h
i
n
t
e
r
r
u
p
t
s
o
u
r
c
e
i
s
“
0
”
Rev.2.00 May 28, 2004 page 10 of 100
38C2 Group (A Version)
[Processor Status Register (PS)]
The processor status register is an 8-bit register consisting of 5 flags
which indicate the status of the processor after an arithmetic opera-
tion and 3 flags which decide MCU operation. Branch operations
can be performed by testing the Carry (C) flag , Zero (Z) flag, Over-
flow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N
flags are not valid.
•Bit 0: Carry flag (C)
The C flag contains a carry or borrow generated by the arithmetic
logic unit (ALU) immediately after an arithmetic operation. It can
also be changed by a shift or rotate instruction.
•Bit 1: Zero flag (Z)
The Z flag is set to “1” if the result of an immediate arithmetic
operation or a data transfer is “0”, and set to “0” if the result is
anything other than “0”.
•Bit 2: Interrupt disable flag (I)
The I flag disables all interrupts except for the interrupt generated
by the BRK instruction.
Interrupts are disabled when the I flag is “1”.
•Bit 3: Decimal mode flag (D)
The D flag determines whether additions and subtractions are ex-
ecuted in binary or decimal. Binary arithmetic is executed when
this flag is “0”; decimal arithmetic is executed when it is “1”.
Decimal correction is automatic in decimal mode. Only the ADC
and SBC instructions can be used for decimal arithmetic.
•Bit 4: Break flag (B)
The B flag is used to indicate that the current interrupt was gener-
ated by the BRK instruction. When the BRK instruction is gener-
ated, the B flag is set to “1” automatically. When the other inter-
rupts are generated, the B flag is set to “0”, and the processor
status register is pushed onto the stack.
•Bit 5: Index X mode flag (T)
When the T flag is “0”, arithmetic operations are performed be-
tween accumulator and memory. When the T flag is “1”, direct arith-
metic operations and direct data transfers are enabled between
memory locations.
•Bit 6: Overflow flag (V)
The V flag is used during the addition or subtraction of one byte of
signed data. It is set if the result exceeds +127 to -128. When the
BIT instruction is executed, bit 6 of the memory location operated
on by the BIT instruction is stored in the overflow flag.
•Bit 7: Negative flag (N)
The N flag is set to “1” if the result of an arithmetic operation or
data transfer is negative. When the BIT instruction is executed, bit
7 of the memory location operated on by the BIT instruction is stored
in the negative flag.
Table 5 Set and clear instructions of each bit of processor status register
Set instruction
Clear instruction
C flag
SEC
CLC
Z flag
–
–
I flag
SEI
CLI
D flag
SED
CLD
B flag
–
–
T flag
SET
CLT
V flag
–
CLV
N flag
–
–
Rev.2.00 May 28, 2004 page 11 of 100
38C2 Group (A Version)
[CPU Mode Register (CPUM)] 003B16
The CPU mode register contains the stack page selection bit and
the control bit for the internal system clock.
The CPU mode register is allocated at address 003B16.
Fig. 7 Structure of CPU mode register
Not available
Processor mode bits
b1 b0
0 0 : Single-chip mode
0 1 :
1 0 :
1 1 :
Stack page selection bit
0 : RAM in the zero page is used as stack area
1 : RAM in page 1 is used as stack area
Not used (returns “1” when read)
(Do not write “0” to this bit.)
Main clock (XIN
–X
OUT
) d
ivision ratio selection bits
b5 b4
0 0 : XIN
/8 (frequency/8 mode)
0 1 : XIN
/4 (frequency/4 mode)
1 0 : XIN
/2 (frequency/2 mode)
1 1 : Not available
System clock control bits
b7 b6
0 0 : XIN
stop, X
CIN
oscillating, system clock = X
CIN
0 1 : XIN
oscillating, X
CIN
stop, system clock = X
IN
1 0 : XIN
oscillating, X
CIN
oscillating, system clock = X
CIN
1 1 : XIN
oscillating, X
CIN
oscillating, system clock = X
IN
CPU mode register
(CPUM (CM) : address 003B16)
b7 b0
Rev.2.00 May 28, 2004 page 12 of 100
38C2 Group (A Version)
MEMORY
Special Function Register (SFR) Area
The Special Function Register area in the zero page contains control
registers such as I/O ports and timers.
RAM
RAM is used for data storage and for stack area of subroutine calls
and interrupts.
ROM
The first 128 bytes and the last 2 bytes of ROM are reserved for
device testing and the rest is user area for storing programs.
Interrupt Vector Area
The interrupt vector area contains reset and interrupt vectors.
Zero Page
Access to this area with only 2 bytes is possible in the zero page
addressing mode.
Special Page
Access to this area with only 2 bytes is possible in the special page
addressing mode.
Fig. 8 Memory map diagram
0
1
0
0
1
6
0
0
0
0
1
6
0
0
4
0
1
6
0
8
4
0
1
6
FF00
16
FFDC
16
FFFE
16
FFFF
16
1
9
2
2
5
6
3
8
4
5
1
2
6
4
0
7
6
8
8
9
6
1
0
2
4
1
5
3
6
2
0
4
8
XXXX
16
00FF
16
013F
16
01BF
16
023F
16
02BF
16
033F
16
03BF
16
043F
16
063F
16
083F
16
4096
8192
12288
16384
20480
24576
28672
32768
36864
40960
45056
49152
53248
57344
61440
F000
16
E000
16
D000
16
C000
16
B000
16
A000
16
9000
16
8000
16
7000
16
6000
16
5000
16
4000
16
3000
16
2000
16
1000
16
F080
16
E080
16
D080
16
C080
16
B080
16
A080
16
9080
16
8080
16
7080
16
6080
16
5080
16
4080
16
3080
16
2080
16
1080
16
YYYY
16
ZZZZ
16
RAM
R
O
M
R
A
M
a
r
e
a
R
A
M
s
i
z
e
(
b
y
t
e
s
)A
d
d
r
e
s
s
X
X
X
X
1
6
ROM area
R
O
M
s
i
z
e
(
b
y
t
e
s
)Address
YYYY
16
A
d
d
r
e
s
s
Z
Z
Z
Z
1
6
Reserved are a
SFR area
Not used
Interrupt vector area
R
e
s
e
r
v
e
d
R
O
M
a
r
e
a
(
1
2
8
b
y
t
e
s
)
Z
e
r
o
p
a
g
e
Special
page
LCD d is play RAM a rea
Reserved ROM area
SFR area
0
0
4
C
1
6
0FE0
16
1000
16
Rev.2.00 May 28, 2004 page 13 of 100
38C2 Group (A Version)
Fig. 9 Memory map of special function register (SFR)
0
FF
916
0
0
2
01
6
0
0
2
11
6
0
0
2
21
6
0
0
2
31
6
0
0
2
41
6
0
0
2
51
6
0
0
2
61
6
0
0
2
71
6
0
0
2
81
6
0
0
2
91
6
002
A
16
0
0
2
B
1
6
0
0
2
C
1
6
0
0
2
D
1
6
002
E
16
002
F
16
0
0
3
01
6
0
0
3
11
6
0
0
3
21
6
0
0
3
31
6
0
0
3
41
6
003516
0
0
3
61
6
0
0
3
71
6
003816
0
0
3
91
6
003
A
16
003
B
16
0
0
3
C
1
6
003
D
16
003
E
16
003
F
16
0
0
0
01
6
0
0
0
11
6
0
0
0
21
6
0
0
0
31
6
0
0
0
41
6
0
0
0
51
6
0
0
0
61
6
0
0
0
71
6
0
0
0
81
6
0
0
0
91
6
000
A
16
0
0
0
B
1
6
0
0
0
C
1
6
0
0
0
D
1
6
000
E
16
0
0
0
F
1
6
0
0
1
01
6
0
0
1
11
6
0
0
1
21
6
0
0
1
31
6
0
0
1
41
6
001516
0
0
1
61
6
0
0
1
71
6
001816
0
0
1
91
6
001
A
16
001
B
16
0
0
1
C
1
6
001
D
16
001
E
16
0
0
1
F
1
6
P
o
r
t
P
0
(
P
0
)
P
o
r
t
P
0
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
0
D
)
P
o
r
t
P
1
(
P
1
)
P
o
r
t
P
1
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
1
D
)
P
o
r
t
P
2
(
P
2
)
P
o
r
t
P
2
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
2
D
)
P
o
r
t
P
3
(
P
3
)
P
o
r
t
P
4
(
P
4
)
P
o
r
t
P
4
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
4
D
)
P
ort
P
5
(P
5
)
P
ort
P
5
di
rect
i
on r eg
i
ster
(P
5
D)
P
o
r
t
P
6
(
P
6
)
P
o
r
t
P
6
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
6
D
)
A
-
D
contro
l
reg
i
ster
(ADCON)
A
-
D
c
o
n
v
e
r
s
i
o
n
r
e
g
i
s
t
e
r
(
l
o
w
-
o
r
d
e
r
)
(
A
D
L
)
A
-
D
convers
i
on reg
i
ster
(hi
g
h
-or
d
er
)
(ADH)
I
nterru pt contro
l
reg
i
ster 2
(ICON
2
)
I
nterru pt e
d
ge se
l
ect
i
on reg
i
ster
(INTEDGE)
CPU
mo
d
e reg
i
ster
(CPUM)
I
nterrupt request reg
i
ster 1
(IREQ
1
)
I
nterrupt request reg
i
ster 2
(IREQ
2
)
I
nterru pt contro
l
reg
i
ster 1
(ICON
1
)
Ti
me r 1
(T
1
)
Ti
me r 3
(T
3
)
PWM
01 reg
i
ster
(PWM
01
)
Ti
me r 12 mo
d
e reg
i
ster
(T
12
M)
Ti
me r 2
(T
2
)
Ti
me r 4
(T
4
)
C
ompare reg
i
ster
(l
ow-or
d
er
)
(COMPL)
C
o
m
p
a
r
e
r
e
g
i
s
t
e
r
(
h
i
g
h
-
o
r
d
e
r
)
(
C
O
M
P
H
)
Ti
mer
X
(l
ow-or
d
er
)
(TXL)
LCD
power contro
l
reg
i
ster
(VLCON)
LCD
mo
d
e reg
i
ster
(LM)
Ti
mer
X
(hi
g
h
-or
d
er
)
(TXH)
Ti
mer
X
(
extens
i
on
)
(TXEX)
0
FF
016
0
FF
116
0
FF
216
0
FF
316
0
FF
416
0
FF
516
0
FF
616
0
FF
716
0
F
E
01
6
0
F
E
11
6
0
FE
216
0
F
E
61
6
0
FE
716
0
F
E
91
6
0
F
E
31
6
0
F
E
41
6
0
FE
516
P
o
r
t
P
3
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
3
D
)
T
ransm
i
t/rece
i
ve
b
u
ff
er reg
i
ster 1
(TB
1/
RB
1
)
S
e
r
i
a
l
I
/
O
1
s
t
a
t
u
s
r
e
g
i
s
t
e
r
(
S
I
O
1
S
T
S
)
T
ransm
i
t/rece
i
ve
b
u
ff
er reg
i
ster 2
(TB
2/
RB
2
)
S
e
r
i
a
l
I
/
O
2
s
t
a
t
u
s
r
e
g
i
s
t
e
r
(
S
I
O
2
S
T
S
)
U
A
R
T
1
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
U
A
R
T
1
C
O
N
)
S
er
i
a
l
I
/
O
1 contro
l
reg
i
ster
(SIO
1
CON)
S
er
i
a
l
I
/
O
2 contro
l
reg
i
ster
(SIO
2
CON)
B
a
u
d
r
a
t
e
g
e
n
e
r
a
t
o
r
1
(
B
R
G
1
)
B
au
d
rat e gen er at or 2
(BRG
2
)
U
A
R
T
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
U
A
R
T
2
C
O
N
)
0
FEA
16
0
F
E
B
1
6
0
FEC
16
0
F
E
D
1
6
0
F
E
E
1
6
0
FEF
16
Cl
oc
k
output contro
l
reg
i
ster
(CKOUT)
PULL
reg
i
ster
(PULL)
Ti
me r 34 mo
d
e reg
i
ster
(T
34
M)
Ti
mer
Y
(l
ow-or
d
er
)
(TYL)
Ti
mer
Y
(hi
g
h
-or
d
er
)
(TYH)
Ti
mer
X
mo
d
e reg
i
ster
(TXM)
Ti
mer
Y
mo
d
e reg
i
ster
(TYM)
W
atc
hd
og t
i
mer cont ro
l
reg
i
ster
(WDTCON)
0
FF
816
0
FFA
16
0
FFB
16
0
FFC
16
0
FFD
16
0
FFE
16
0
FFF
16
O
sc
ill
at
i
on output contro
l
re g
i
ster
(OSCOUT)
K
ey
i
nput contro
l
re g
i
ster
(KIC)
T
i
m
e
r
1
2
3
4
m
o
d
e
r
e
g
i
s
t
e
r
(
T
1
2
3
4
M
)
T
i
m
e
r
X
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
T
X
C
O
N
)
Tim er 12 frequency div isi on s election register (PR E 12)
T
i
m
e
r
3
4
f
r
e
q
u
e
n
c
y
d
i
v
i
s
i
o
n
s
e
l
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
R
E
3
4
)
T
i
m
e
r
X
Y
f
r
e
q
u
e
n
c
y
d
i
v
i
s
i
o
n
s
e
l
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
P
R
E
X
Y
)
S
e
g
m
e
n
t
o
u
t
p
u
t
d
i
s
a
b
l
e
r
e
g
i
s
t
e
r
0
(
S
E
G
0
)
S
eg m ent output
di
sa
bl
e reg
i
ster 1
(SEG
1
)
S
eg m ent output
di
sa
bl
e reg
i
ster 2
(SEG
2
)
T
i
m
e
r
Y
m
o
d
e
r
e
g
i
s
t
e
r
2
(
T
Y
M
2
)
Fl
as
h
m emory contro
l
reg
i
ster
(FMCR)
R
eserve
d
area
(
access
di
sa
bl
e
d)
0
F
E
81
6
Rev.2.00 May 28, 2004 page 14 of 100
38C2 Group (A Version)
I/O PORTS
Direction Registers
The I/O ports P0–P6 have direction registers which determine the
input/output direction of each individual pin. Each bit in a direction
register corresponds to one pin, each pin can be set to be input port
or output port.
When “0” is written to the bit of the direction register , the correspond-
ing pin becomes an input pin. As for ports P0–P2, when “1” is written
to the bit of the direction register and the segment output disable
register, the corresponding pin becomes an output pin. As for ports
P3–P6, when “1” is written to the bit of the direction register, the
corresponding pin becomes an output pin.
If data is read from a pin set to output, the value of the port latch is
read, not the value of the pin itself. Pins set to input are floating. If a
pin set to input is written to, only the port output latch is written to and
the pin remains floating.
Pull-up Control
Each individual bit of ports P0–P2 can be pulled up with a program
by setting direction registers and segment output disable registers 0
to 2 (addresses 0FF816 to 0FFA16).
The pin is pulled up by setting “0” to the direction register and “1” to
the segment output disable register.
By setting the PULL register (address 0FF116), ports P3–P6 can con-
trol pull-up with a program.
However, the contents of PULL register do not affect ports pro-
grammed as the output ports.
Fig. 11 Structure of PULL register and segment output disable register
Fig. 10 Structure of ports P0 to P2
S
e
g
m
e
n
t
o
u
t
p
u
t
d
i
s
a
b
l
e
r
e
g
i
s
t
e
r
Direction register
“0”
“
1
”
“0”“1”
I
n
p
u
t
p
o
r
t
N
o
p
u
l
l
-
u
p
Segment
output P
o
r
t
o
u
t
p
u
t
Input port
Pull-up
I
n
i
t
i
a
l
s
t
a
t
e
P3
0
–P3
3
pull-up
P3
4
–P3
7
pull-up
P4
0
–P4
3
pull-up
P4
4
–P4
7
pull-up
P5
0
–P5
3
pull-up
P5
4
–P5
7
pull-up
P6
0
–P6
2
pull-up
Not used (return “0” when read)
PULL register
(PULL : address 0FF1
16
)
b7 b0
P0
0
pull-up
P0
1
pull-up
P0
2
pull-up
P0
3
pull-up
P0
4
pull-up
P0
5
pull-up
P0
6
pull-up
P0
7
pull-up
Segment output disable register 0
(SEG0 : address 0FF8
16
)
b7 b0
Notes 1: The PULL register and segment output disable register affect only ports
programmed as the input ports.
2: When the VL pin input selection bit (VLSEL) of the LCD power control
register (address 0038
16
) is “1”, settings of P2
6
and P2
7
are invalid.
0: No pull-up
1: Pull-up
P1
0
pull-up
P1
1
pull-up
P1
2
pull-up
P1
3
pull-up
P1
4
pull-up
P1
5
pull-up
P1
6
pull-up
P1
7
pull-up
b7 b0 Segment output disable register 1
(SEG1 : address 0FF9
16
)
P2
0
pull-up
P2
1
pull-up
P2
2
pull-up
P2
3
pull-up
P2
4
pull-up
P2
5
pull-up
P2
6
pull-up
P2
7
pull-up
b7 b0 Segment output disable register 2
(SEG2 : address 0FFA
16
)
0: No pull-up
1: Pull-up
Rev.2.00 May 28, 2004 page 15 of 100
38C2 Group (A Version)
Name
Port P0
Port P1
Port P2
Port P3
Port P4
Port P5
Port P6
Common
Input/Output
Input/Output,
individual bits
Input/Output,
individual bits
Input/Output,
individual bits
Input/Output,
individual bits
Input/Output,
individual bits
Input/Output,
individual bits
Input/Output,
individual bits
Output
I/O format
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
CMOS compatible
input level
CMOS 3-state output
LCD common output
Non-port function
LCD segment
output
Serial I/O2 function I/O
External interrupt input
Timer X output
Timer 2 output
Timer X function input
A-D conversion
input
External interrupt input
Timer 3 output
Timer 4 output
PWM output
Serial I/O1
function I/O
T imer Y function input
Sub-clock oscillation circuit
Related SFRs
Segment output disable
register 1
Segment output disable
register 2
Segment output disable
register 3
PULL register
Serial I/O2 control register
Serial I/O2 status register
UART2 control register
PULL register
Interrupt edge selection
register
PULL register
Timer X mode register
Timer 12 mode register
PULL register
Timer X mode register
PULL register
A-D control register
PULL register
A-D control register
Timer Y mode register
PULL register
Interrupt edge selection
register
PULL register
Timer 12 mode register
PULL register
Serial I/O1 control register
Serial I/O1 status register
UART1 control register
PULL register
Timer Y mode register
PULL register
CPU mode register
LCD mode register
Ref. No.
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(7)
(11)
(10)
(11)
(7)
(9)
(12)
(13)
(14)
(15)
(7)
(16)
(17)
(18)
Table 6 List of I/O port function
Notes 1: For details of how to use double/triple function ports as function I/O ports, refer to the applicable sections.
2: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction.
When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate.
P00/SEG0 –
P03/SEG3
P04/SEG4 –
P07/SEG7
P10/SEG8 –
P17/SEG15
P20/SEG16 –
P25/SEG21
P26/SEG22/VL1
P27/SEG23/VL2
P30/SRDY2
P31/SCLK2
P32/TxD2
P33/RxD2
P34/INT2
P35/TXOUT
P36/T2OUT/φ
P37/CNTR0
P40/OOUT0/AN0
P41/OOUT1/AN1
P42/AN2–
P45/AN5
P46/RTP0/AN6
P47/RTP1/AN7
P50/INT0
P51/INT1
P52/T3OUT/PWM0
P53/T4OUT/PWM1
P54/RxD1
P55/TxD1
P56/SCLK1
P57/SRDY1
P60/CNTR1
P61/XCIN
P62/XCOUT
COM0–COM3
Pin Key input
(key-on wakeup)
interrupt input
LCD power
input
Oscillation
external
output
Real time
port function
output
Key input
(key-on wakeup)
interrupt input
Rev.2.00 May 28, 2004 page 16 of 100
38C2 Group (A Version)
Fig. 12 Port block diagram (1)
(1) Ports P00–P03
(
3
)
P
o
r
t
P
30
D
a
t
a
b
u
s
S
e
r
i
a
l
I
/
O
o
u
t
p
u
t
P
o
r
t
l
a
t
c
h
P
u
l
l
-
u
p
c
o
n
t
r
o
l
Serial I/O ready output
D
a
t
a
b
u
sPort latch
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
Pull-up control
P
u
l
l
-
u
p
c
o
n
t
r
o
l
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
D
a
t
a
b
u
s
S
e
r
i
a
l
I
/
O
i
n
p
u
t
Port latch
Data bus
Serial I/O clock output
S
e
r
i
a
l
I
/
O
c
l
o
c
k
i
n
p
u
t
Serial I/O mode selection bi
t
Serial I/O enable bi
t
Port latch
Direction register
Pull-up control
S
e
g
m
e
n
t
o
u
t
p
u
t
d
i
s
a
b
l
e
b
i
t
D
a
t
a
b
u
sP
o
r
t
l
a
t
c
h
V
L
2
/
V
L
3
V
L1
/V
SS
K
e
y
i
n
p
u
t
c
o
n
t
r
o
l
K
e
y
-
o
n
w
a
k
e
u
p
i
n
t
e
r
r
u
p
t
i
n
p
u
t
S
e
g
m
e
n
t
d
a
t
a
S
e
g
m
e
n
t
o
u
t
p
u
t
d
i
s
a
b
l
e
b
i
t
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
Data bus P
o
r
t
l
a
t
c
h
L
C
D
p
o
w
e
r
i
n
p
u
t
(
V
L
1
,
V
L
2
)
only for P2
6
,P2
7
V
L
2
/
V
L
3
V
L
1
/
V
S
S
Segment data
S
e
g
m
e
n
t
o
u
t
p
u
t
d
i
s
a
b
l
e
b
i
t
Segment output disable bi t
(2) Ports P04–P07, P1, P2
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
S
e
r
i
a
l
I
/
O
m
o
d
e
s
e
l
e
c
t
i
o
n
b
i
t
S
e
r
i
a
l
I
/
O
e
n
a
b
l
e
b
i
t
S
R
D
Y
o
u
t
p
u
t
e
n
a
b
l
e
b
i
t
(
5
)
P
o
r
t
P
32
P
3
2
/
T
x
D
2
P
-
c
h
a
n
n
e
l
o
u
t
p
u
t
d
i
s
a
b
l
e
b
i
t
S
e
r
i
a
l
I
/
O
e
n
a
b
l
e
b
i
t
T
r
a
n
s
m
i
t
e
n
a
b
l
e
b
i
t
(
6
)
P
o
r
t
P
33
S
e
r
i
a
l
I
/
O
e
n
a
b
l
e
b
i
t
R
e
c
e
i
v
e
e
n
a
b
l
e
b
i
t
(4) Port P31
Serial I/O synchronous
clock selection bit
Serial I/O enable bit
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
Rev.2.00 May 28, 2004 page 17 of 100
38C2 Group (A Version)
Fig. 13 Port block diagram (2)
Analog input pin selection bit
A
-
D
c
o
n
v
e
r
s
i
o
n
i
n
p
u
t
D
a
t
a
b
u
sP
o
r
t
l
a
t
c
h
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
Pull-up control
Data bus
Serial I/O clock output
Port latch
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
Pull-up control
S
e
r
i
a
l
I
/
O
c
l
o
c
k
i
n
p
u
t
Key-on wakeup interrupt input Key input control
D
a
t
a
b
u
s
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
Port latch
Pull-up control
Port latch
D
a
t
a
b
u
s
Pulse output mode
Timer X output
Direction register
P
u
l
l
-
u
p
c
o
n
t
r
o
l
Direction register
Data bus
S
e
r
i
a
l
I
/
O
e
n
a
b
l
e
b
i
t
R
e
c
e
i
v
e
e
n
a
b
l
e
b
i
t
Port latch
Pull-up control
S
e
r
i
a
l
I
/
O
i
n
p
u
t
Key-on wakeup interrupt input K
e
y
i
n
p
u
t
c
o
n
t
r
o
l
P
o
r
t
l
a
t
c
h
D
a
t
a
b
u
s
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
Pull-up control
Data bus P
o
r
t
l
a
t
c
h
Direction register
Pull-up control
A
n
a
l
o
g
i
n
p
u
t
p
i
n
s
e
l
e
c
t
i
o
n
b
i
t
A-D conversion input
D
a
t
a
b
u
s
Serial I/O output
Port latch
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
u
l
l
-
u
p
c
o
n
t
r
o
l
K
e
y
-
o
n
w
a
k
e
u
p
i
n
t
e
r
r
u
p
t
i
n
p
u
tKey input control
(
7
)
P
o
r
t
s
P
34,
P
37,
P
50,
P
51,
P
60
(
9
)
P
o
r
t
s
P
36,
P
52,
P
53
(11) Ports P40, P41, P46, P47
(
1
3
)
P
o
r
t
P
55
(14) Port P56
(
1
2
)
P
o
r
t
P
54
(8) Port P35
(10) Ports P42–P45
C
N
T
R
0
,
C
N
T
R
1
i
n
t
e
r
r
u
p
t
i
n
p
u
t
I
N
T
0
–
I
N
T
2
i
n
t
e
r
r
u
p
t
i
n
p
u
t
Port/Timer output selection
Timer output/PWM output
Timer output/System clock φ output
Oscillation output control bit/
Real time control bit
O
s
c
i
l
l
a
t
i
o
n
o
u
t
p
u
t
/
D
a
t
a
f
o
r
r
e
a
l
t
i
m
e
p
o
r
t
Serial I/O enable bit
Transmit enable bit
Serial I/O synchronous clock
selection bit
Serial I/O enable bit
Serial I/O mode selection bit
Serial I/O enable bit
P
5
5
/
T
x
D
1
P
-
c
h
a
n
n
e
l
o
u
t
p
u
t
d
i
s
a
b
l
e
b
i
t
Rev.2.00 May 28, 2004 page 18 of 100
38C2 Group (A Version)
Fig. 14 Port block diagram (3)
VL3
VL2
VL
1
VSS
(
1
5
)
P
o
r
t
P
5
7
S
e
r
i
a
l
I
/
O
r
e
a
d
y
o
u
t
p
u
t
D
a
t
a
b
u
sP
o
r
t
l
a
t
c
h
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
u
l
l
-
u
p
c
o
n
t
r
o
l
K
e
y
-
o
n
w
a
k
e
u
p
i
n
t
e
r
r
u
p
t
i
n
p
u
tK
e
y
i
n
p
u
t
c
o
n
t
r
o
l
X
c
o
s
c
i
l
l
a
t
i
o
n
e
n
a
b
l
e
d
Port P6
1
O
s
c
i
l
l
a
t
o
r
Xc oscillation enabled
(
1
7
)
P
o
r
t
P
6
2
Data bus P
o
r
t
l
a
t
c
h
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
X
c
o
s
c
i
l
l
a
t
i
o
n
e
n
a
b
l
e
d
+
P
u
l
l
-
u
p
c
o
n
t
r
o
l
(17) COM
0
–COM
3
(
1
6
)
P
o
r
t
P
6
1
D
a
t
a
b
u
sP
o
r
t
l
a
t
c
h
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
X
c
o
s
c
i
l
l
a
t
i
o
n
e
n
a
b
l
e
d
Xc oscillation enabled + Pull-up control
S
u
b
-
c
l
o
c
k
g
e
n
e
r
a
t
i
o
n
c
i
r
c
u
i
t
i
n
p
u
t
S
e
r
i
a
l
I
/
O
m
o
d
e
s
e
l
e
c
t
i
o
n
b
i
t
S
e
r
i
a
l
I
/
O
e
n
a
b
l
e
b
i
t
S
R
D
Y
o
u
t
p
u
t
e
n
a
b
l
e
b
i
t
Gate input signal of
each gate depends
on the duty ratio
and bias values.
Rev.2.00 May 28, 2004 page 19 of 100
38C2 Group (A Version)
INTERRUPTS
Interrupts occur by nineteen sources: six external, twelve internal,
and one software.
Interrupt Control
Each interrupt except the BRK instruction interrupt have both an in-
terrupt request bit and an interrupt enable bit, and is controlled by the
interrupt disable flag. An interrupt occurs if the corresponding inter-
rupt request and enable bits are “1” and the interrupt disable flag is
“0”.
Interrupt enable bits can be set or cleared by program. Interrupt re-
quest bits can be cleared by program, but cannot be set by software.
The BRK instruction interrupt and reset cannot be disabled with any
flag or bit. The I flag disables all interrupts except the BRK instruction
interrupt and reset. If several interrupt requests occur at the same
time, the interrupt with highest priority is accepted first.
Interrupt Operation
By acceptance of an interrupt, the following operations are automati-
cally performed:
1.The contents of the program counter and processor status reg-
ister are automatically pushed onto the stack.
2.The interrupt disable flag is set to “1” and the corresponding
interrupt request bit is set to “0”.
3.The interrupt jump destination address is read from the vector
table into the program counter.
■ Notes on Interrupts
When setting the followings, the interrupt request bit may be set to
“1”.
•When switching external interrupt active edge
Related register: Interrupt edge selection register (address 3A16)
Timer X control register (address FF416)
Timer Y mode register (address 3016)
•When switching interrupt sources of an interrupt vector address
where two or more interrupt sources are allocated
Related register: Interrupt edge selection register (address 3A16)
When not requiring the interrupt occurrence synchronous with these
setting, take the following sequence.
➀Set the corresponding interrupt enable bit to “0” (disabled).
➁Set the interrupt edge select bit (polarity switch bit) or the interrupt
source selection bit.
➂Set the corresponding interrupt request bit to “0” after 1 or more
instructions have been executed.
➃Set the corresponding interrupt enable bit to “1” (enabled).
Interrupt Source
Reset (Note 2)
INT0
INT1
INT2
Key input
(key-on wakeup)
Serial I/O1 receive
Serial I/O1 transmit
Serial I/O2 receive
Serial I/O2 transmit
Timer X
Timer 1
Timer 2
Timer 3
Timer 4
CNTR0
T imer Y
CNTR1
A-D conversion
BRK instruction
Priority
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
V ector Addresses (Note 1)
High
FFFD16
FFFB16
FFF916
FFF716
FFF516
FFF316
FFF116
FFEF16
FFED16
FFEB16
FFE916
FFE716
FFE516
FFE316
FFE116
FFDF16
FFDD16
Interrupt Request
Generating Conditions
At reset
At detection of either rising or falling
edge of INT0 input
At detection of either rising or falling
edge of INT1 input
At detection of either rising or falling
edge of INT2 input
At falling of ports P00–P03, P54–P57
input logical level AND
At completion of serial I/O1 data receive
At completion of serial I/O1 transmit
shift or transmit buffer is empty
At completion of serial I/O2 data receive
At completion of serial I/O2 transmit
shift or transmit buffer is empty
At timer X underflow
At timer 1 underflow
At timer 2 underflow
At timer 3 underflow
At timer 4 underflow
At detection of either rising or falling
edge of CNTR0 input
At timer Y underflow
At detection of either rising or falling
edge of CNTR1 input
At completion of A-D conversion
At BRK instruction execution
Non-maskable
External interrupt (active edge selectable)
External interrupt (active edge selectable)
Valid when INT2 interrupt is selected
External interrupt (active edge selectable)
Valid when key input interrupt is selected
External interrupt (falling valid)
Valid only when serial I/O1 is selected
Valid only when serial I/O1 is selected
Valid only when serial I/O2 is selected
Valid only when serial I/O2 is selected
V alid only when timer 1 interrupt is selected
V alid only when timer 2 interrupt is selected
External interrupt (active edge selectable)
External interrupt (active edge selectable)
V alid when A-D conversion interrupt is se-
lected
Non-maskable software interrupt
Low
FFFC16
FFFA16
FFF816
FFF616
FFF416
FFF216
FFF016
FFEE16
FFEC16
FFEA16
FFE816
FFE616
FFE416
FFE216
FFE016
FFDE16
FFDC16
Notes 1: Vector addresses contain interrupt jump destination addresses.
2: Reset function in the same way as an interrupt with the highest priority.
Table 7 Interrupt vector addresses and priority
Remarks
Rev.2.00 May 28, 2004 page 20 of 100
38C2 Group (A Version)
Fig. 15 Interrupt control
Fig. 16 Structure of interrupt-related registers
Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
BRK instruction
Reset Interrupt request
b7 b0 Interrupt edge selection register
INT0 interrupt edge selection bit
INT1 interrupt edge selection bit
INT2 interrupt edge selection bit
INT2/Key input interrupt switch bit
Timer Y/CNTR1 interrupt switch bit
Not used (return “0” when read)
(Do not write to “1”)
(INTEDGE : address 003A16)
Interrupt request register 1
INT0 interrupt request bit
INT1 interrupt request bit
INT2 interrupt request bit
Key input interrupt request bit
Serial I/O1 receive interrupt request bit
Serial I/O1 transmit interrupt request bit
Serial I/O2 receive interrupt request bit
Serial I/O2 transmit interrupt request bit
Timer X interrupt request bit
Interrupt control register 1
INT0 interrupt enable bit
INT1 interrupt enable bit
INT2 interrupt enable bit
Key input interrupt enable bit
Serial I/O1 receive interrupt enable bit
Serial I/O1 transmit interrupt enable bit
Serial I/O2 receive interrupt enable bit
Serial I/O2 transmit interrupt enable bit
Timer X interrupt enable bit
0 : No interrupt request issued
1 : Interrupt request issued
(IREQ1 : address 003C16)
(ICON1 : address 003E16)
Interrupt request register 2
Timer 1 interrupt request bit
Timer 2 interrupt request bit
Timer 3 interrupt request bit
Timer 4 interrupt request bit
CNTR0 interrupt request bit
Timer Y interrupt request bit
CNTR1 interrupt request bit
AD conversion interrupt request bit
Not used (returns “0” when read)
(IREQ2 : address 003D16)
Interrupt control register 2
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
Timer 3 interrupt enable bit
Timer 4 interrupt enable bit
CNTR0 interrupt enable bit
Timer Y interrupt enable bit
CNTR1 interrupt enable bit
AD conversion interrupt enable bit
Not used (returns “0” when read)
(Do not write to “1”.)
0 : Interrupts disabled
1 : Interrupts enabled
(ICON2 : address 003F16)
0 : Falling edge active
1 : Rising edge active
b7 b0
b7 b0
b7 b0
b7 b0
0 : INT2 interrupt
1 : Key input interrupt
0 : Timer Y interrupt
1 : CNTR1 interrupt
Rev.2.00 May 28, 2004 page 21 of 100
38C2 Group (A Version)
Key Input Interrupt (Key-on Wake-Up)
A key input interrupt request is generated by detecting the falling
edge from any pin of ports P00–P03, P54–P57 that have been set to
input mode. In other words, it is generated when AND of input level
goes from “1” to “0”. An example of using a key input interrupt is
shown in Figure 17, where an interrupt request is generated by press-
ing one of the keys consisted as an active-low key matrix which in-
puts to ports P54–P57.
Fig. 17 Connection example when using key input interrupt and ports P0 and P5 block diagram
Key input control
register = “1”
Key input control
register = “1”
Key input control
register = “1”
Key input control
register = “1”
K
e
y
i
n
p
u
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
=
“
1
”
K
e
y
i
n
p
u
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
=
“
1
”
K
e
y
i
n
p
u
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
=
“
1
”
Port P5
4
latch
P
o
r
t
P
5
4
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
=
“
0
”
Port P5
5
latch
Port P5
5
direction register = “0”
Port P5
6
latch
Port P5
6
direction register = “0”
Port P5
7
latch
P
o
r
t
P
5
7
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
=
“
0
”
Port P0
0
latch
P
o
r
t
P
0
0
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
=
“
1
”
Port P0
1
latch
P
o
r
t
P
0
1
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
=
“
1
”
P
o
r
t
P
0
2
l
a
t
c
h
Port P0
2
direction register = “1”
P
o
r
t
P
0
3
l
a
t
c
h
Port P0
3
direction register = “1”
P
5
4
i
n
p
u
t
P
5
5
i
n
p
u
t
P5
6
input
P5
7
input
P0
0
output
P
0
1
o
u
t
p
u
t
P
0
2
o
u
t
p
u
t
P
0
3
o
u
t
p
u
t
PULL register
Bit 5 = “1”
P
o
r
t
P
0
I
n
p
u
t
r
e
a
d
i
n
g
c
i
r
c
u
i
t
Port PXx
“L” level out put
K
e
y
i
n
p
u
t
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
P
o
r
t
P
5
I
n
p
u
t
r
e
a
d
i
n
g
c
i
r
c
u
i
t
K
e
y
i
n
p
u
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
=
“
1
”
Segment output
disable register 0
Bit 3 = “1”
S
e
g
m
e
n
t
o
u
t
p
u
t
d
i
s
a
b
l
e
r
e
g
i
s
t
e
r
0
B
i
t
2
=
“
1
”
Segment output
disable register 0
Bit 1 = “1”
S
e
g
m
e
n
t
o
u
t
p
u
t
d
i
s
a
b
l
e
r
e
g
i
s
t
e
r
0
B
i
t
0
=
“
1
”
✽ P-channel transistor for pull-up
✽ ✽ CMOS output buff e r
✽
✽
✽
✽
✽
✽
✽
✽✽✽
✽✽
✽✽
✽✽
✽✽
✽✽
✽✽
✽✽
Rev.2.00 May 28, 2004 page 22 of 100
38C2 Group (A Version)
A key input interrupt is controlled by the key input control register and
port direction registers. When the key input interrupt is enabled, set
“1” to the key input control register. A key input of any pin of ports
P00–P03, P54–P57 that have been set to input mode is accepted.
Fig. 18 Structure of key input control register
Key input control register
P5
4
key input control bit
P5
5
key input control bit
P5
6
key input control bit
P5
7
key input control bit
P0
0
key input control bit
P0
1
key input control bit
P0
2
key input control bit
P0
3
key input control bit
(KIC : address 0FF2
16
)
b7 b0
0 : Key input interrupt disabled
1 : Key input interrupt enabled
Rev.2.00 May 28, 2004 page 23 of 100
38C2 Group (A Version)
TIMERS
8-Bit Timer
The 38C2 group has four built-in timers : Timer 1, Timer 2, Timer 3,
and T imer 4.
Each timer has the 8-bit timer latch. All timers are down-counters.
When the timer reaches “0016”, the contents of the timer latch is
reloaded into the timer with the next count pulse. In this mode, the
interrupt request bit corresponding to that timer is set to “1”.
The count can be stopped by setting the stop bit of each timer to “1”.
● Frequency Divider For Timer
Timer 1, timer 2, timer 3 and timer 4 have the frequency divider for
the count source. The count source of the frequency divider is switched
to XIN or XCIN by the CPU mode register. The frequency divider is
controlled by each timer division ratio selection bit. The division ratio
can be selected from as follows;
1/1, 1/2, 1/16, 1/32, 1/64, 1/128, 1/256, 1/1024 of f(XIN); or f(XCIN).
● Timer 1, Timer 2
The count sources of timer 1 and timer 2 can be selected by setting
the timer 12 mode register.
When f(XCIN) is selected as the count source, counting can be per-
formed regardless of XCIN oscillation. However , when XCIN is stopped,
the external pulse input from XCIN pin is counted. Also, by the timer
12 mode register, each time timer 2 underflows, the signal of which
polarity is inverted can be output from P36/T2OUT pin.
At reset, all bits of the timer 12 mode register are set to “0,” timer 1 is
set to “FF16”, and timer 2 is set to “0116”.
When executing the STP instruction, previously set the wait time at
return.
● Timer 3, Timer 4
The count sources of timer 3 and timer 4 can be selected by setting
the timer 34 mode register . Also, by the timer 34 mode register, each
time timer 3 or timer 4 underflows, the signal of which polarity is
inverted can be output from P52/T3OUT pin or P53/T4OUT pin.
● Timer 3 PWM0 Mode, Timer 4 PWM1 Mode
A PWM rectangular waveform corresponding to the 10-bit accuracy
can be output from the P52/PWM0 pin and P53/PWM1 pin by set-
ting the timer 34 mode register and PWM01 register (refer to Figure
21).
One output pulse is the short interval. Four output pulses are the
long interval. The “n” is the value set in the timer 3 (address 002216)
or the timer 4 (address 002316). The “ts” is one period of timer 3 or
timer 4 count source. “H” width of the short interval is obtained by n
✕ ts.
However, in the long interval, “H” width of output pulse is extended
for ts which is set by the PWM01 register (address 002416).
■ Notes on T imer 3 PWM0 Mode, Timer 4 PWM1
Mode
●When PWM output is suspended after starting PWM output, de-
pending on the level of the output pulse at that time to resume an
output, the delay of the one section of the short interval may be
needed.
Stop at “H”: No output delay
Stop at “L”: Output is delayed time of 256 ✕ ts
●In the PWM mode, the follows are performed every cycle of the
long interval (4 ✕ 256 ✕ ts).
•Generation of timer 3, timer 4 interrupt requests
•Update of timer 3, timer 4
■ Writing to Timer 2, Timer 3, Timer 4
When writing to the latch only, if the write timing to the reload latch
and the underflow timing are almost the same, the value is set into
the timer and the timer latch at the same time. In this time, counting
is stopped during writing to the reload latch.
Rev.2.00 May 28, 2004 page 24 of 100
38C2 Group (A Version)
Timer 12 mode register
(T12M: address 0025
16
)
Timer 1 count stop bit
0 : Count operation
1 : Count stop
Timer 2 count stop bit
0 : Count operation
1 : Count stop
Timer 1 count source selection bits
b3 b2
0 0 : Frequency divider for Timer 1
0 1 : f(X
CIN
)
1 0 : Underflow of Timer Y
1 1 : Not available
Timer 2 count source selection bits
b5 b4
0 0 : Underflow of Timer 1
0 1 : f(X
CIN
)
1 0 : Frequency divider for Timer 2
1 1 : Not available
Timer 2 output selection bit (P3
6
)
0 : I/O port
1 : Timer 2 output
T
2OUT
output edge switch bit
0 : Start at “L” output
1 : Start at “H” output
Timer 34 mode register
(T34M: address 0026
16
)
Timer 3 count stop bit
0 : Count operation
1 : Count stop
Timer 4 count stop bit
0 : Count operation
1 : Count stop
Timer 3 count source selection bit
0 : Frequency divider for Timer 3
1 : Underflow of Timer 2
Timer 4 count source selection bits
b4 b3
0 0 : Frequency divider for Timer 4
0 1 : Underflow of Timer 3
1 0 : Underflow of Timer 2
1 1 : Not available
Timer 3 operating mode selection bit
0 : Timer mode
1 : PWM mode
Timer 4 operating mode selection bit
0 : Timer mode
1 : PWM mode
Not used (returns “0” when read)
Timer 1234 mode register
(T1234M: address 0FF3
16
)
T
3OUT
output edge switch bit
0 : Start at “L” output
1 : Start at “H” output
T
4OUT
output edge switch bit
0 : Start at “L” output
1 : Start at “H” output
Timer 3 output selection bit (P5
2
)
0 : I/O port
1 : Timer 3 output
Timer 4 output selection bit (P5
3
)
0 : I/O port
1 : Timer 4 output
Timer 2 write control bit
0 : Write data to both timer latch and timer
1 : Write data to timer latch only
Timer 3 write control bit
0 : Write data to both timer latch and timer
1 : Write data to timer latch only
Timer 4 write control bit
0 : Write data to both timer latch and timer
1 : Write data to timer latch only
Not used (returns “0” when read)
b7 b0
b7 b0
b7 b0
PWM01 register
(PWM01: address 0024
16
)
PWM0 set bits
b1 b0
0 0 : No extended
0 1 : Extended once in four periods
1 0 : Extended twice in four periods
1 1 : Extended three times in four periods
PWM1 set bits
b3 b2
0 0 : No extended
0 1 : Extended once in four periods
1 0 : Extended twice in four periods
1 1 : Extended three times in four periods
Not used (returns “0” when read)
Timer 12 frequency division selection register
(PRE12: address 0FF5
16
)
Timer 1 frequency division selection bits
b2 b1 b0
0 0 0 : 1/16 ✕ f(X
IN
) or 1/16 ✕ f(X
CIN
)
0 0 1 : 1/1 ✕ f(X
IN
) or 1/1 ✕ f(X
CIN
)
0 1 0 : 1/2 ✕ f(X
IN
) or 1/2 ✕ f(X
CIN
)
0 1 1 : 1/32 ✕ f(X
IN
) or 1/32 ✕ f(X
CIN
)
1 0 0 : 1/64 ✕ f(X
IN
) or 1/64 ✕ f(X
CIN
)
1 0 1 : 1/128 ✕ f(X
IN
) or 1/128 ✕ f(X
CIN
)
1 1 0 : 1/256 ✕ f(X
IN
) or 1/256 ✕ f(X
CIN
)
1 1 1 : 1/1024 ✕ f(X
IN
) or 1/1024 ✕ f(X
CIN
)
Timer 2 frequency division selection bits
b5 b4 b3
0 0 0 : 1/16 ✕ f(X
IN
) or 1/16 ✕ f(X
CIN
)
0 0 1 : 1/1 ✕ f(X
IN
) or 1/1 ✕ f(X
CIN
)
0 1 0 : 1/2 ✕ f(X
IN
) or 1/2 ✕ f(X
CIN
)
0 1 1 : 1/32 ✕ f(X
IN
) or 1/32 ✕ f(X
CIN
)
1 0 0 : 1/64 ✕ f(X
IN
) or 1/64 ✕ f(X
CIN
)
1 0 1 : 1/128 ✕ f(X
IN
) or 1/128 ✕ f(X
CIN
)
1 1 0 : 1/256 ✕ f(X
IN
) or 1/256 ✕ f(X
CIN
)
1 1 1 : 1/1024 ✕ f(X
IN
) or 1/1024 ✕ f(X
CIN
)
Not used (returns “0” when read)
b7 b0
b7 b0
Timer 34 frequency division selection register
(PRE34: address 0FF6
16
)
Timer 3 frequency division selection bits
b2 b1 b0
0 0 0 : 1/16 ✕ f(X
IN
) or 1/16 ✕ f(X
CIN
)
0 0 1 : 1/1 ✕ f(X
IN
) or 1/1 ✕ f(X
CIN
)
0 1 0 : 1/2 ✕ f(X
IN
) or 1/2 ✕ f(X
CIN
)
0 1 1 : 1/32 ✕ f(X
IN
) or 1/32 ✕ f(X
CIN
)
1 0 0 : 1/64 ✕ f(X
IN
) or 1/64 ✕ f(X
CIN
)
1 0 1 : 1/128 ✕ f(X
IN
) or 1/128 ✕ f(X
CIN
)
1 1 0 : 1/256 ✕ f(X
IN
) or 1/256 ✕ f(X
CIN
)
1 1 1 : 1/1024 ✕ f(X
IN
) or 1/1024 ✕ f(X
CIN
)
Timer 4 frequency division selection bits
b5 b4 b3
0 0 0 : 1/16 ✕ f(X
IN
) or 1/16 ✕ f(X
CIN
)
0 0 1 : 1/1 ✕ f(X
IN
) or 1/1 ✕ f(X
CIN
)
0 1 0 : 1/2 ✕ f(X
IN
) or 1/2 ✕ f(X
CIN
)
0 1 1 : 1/32 ✕ f(X
IN
) or 1/32 ✕ f(X
CIN
)
1 0 0 : 1/64 ✕ f(X
IN
) or 1/64 ✕ f(X
CIN
)
1 0 1 : 1/128 ✕ f(X
IN
) or 1/128 ✕ f(X
CIN
)
1 1 0 : 1/256 ✕ f(X
IN
) or 1/256 ✕ f(X
CIN
)
1 1 1 : 1/1024 ✕ f(X
IN
) or 1/1024 ✕ f(X
CIN
)
Not used (returns
“
0
”
when read)
b7 b0
Fig. 19 Structure of timer related register
Rev.2.00 May 28, 2004 page 25 of 100
38C2 Group (A Version)
Fig. 20 Block diagram of timers 1, 2, 3 and 4
T
i
m
e
r
1
l
a
t
c
h
(
8
)
T
i
m
e
r
1
(
8
)
T
i
m
e
r
1
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
Timer 2 interrupt request
Timer 3 interrupt request
X
CIN
Data bus
T
i
m
e
r
1
c
o
u
n
t
s
t
o
p
b
i
t
10 bi t
PWM1
circuit
1
/
2
Q
Q
ST
P
5
3
l
a
t
c
h
P5
3
/PWM
1
/T
4OUT
1
0
b
i
t
P
W
M
0
c
i
r
c
u
i
t
1
/
2
Q
Q
ST
T
i
m
e
r
3
o
p
e
r
a
t
i
n
g
m
o
d
e
s
e
l
e
c
t
i
o
n
b
i
t
P
5
2
l
a
t
c
h
Ti mer 3 o ut p u t c ontrol bit
P5
2
dir ect ion
register
P
5
2
/
P
W
M
0
/
T
3
O
U
T
“
0
0
”
“01”
Clock for
Timer 1
C
l
o
c
k
f
o
r
T
i
m
e
r
2
Clock for
Timer 3
Clock for
Timer 4
S
y
s
t
e
m
c
l
o
c
k
c
o
n
t
r
o
l
b
i
t
sFrequency division
selection bits
(3 bits for each Timer)
C
l
o
c
k
f
o
r
T
i
m
e
r
4
C
l
o
c
k
f
o
r
T
i
m
e
r
3
C
l
o
c
k
f
o
r
T
i
m
e
r
2
C
l
o
c
k
f
o
r
T
i
m
e
r
1
1
2
T
h
e
f
o
l
l
o
w
i
n
g
v
a
l
u
e
s
c
a
n
b
e
s
e
l
e
c
t
e
d
t
h
e
c
l
o
c
k
f
o
r
T
i
m
e
r
;
1
/
1
,
1
/
2
,
1
/
1
6
,
1
/
3
2
,
1
/
6
4
,
1
/
1
2
8
,
1
/
2
5
6
,
1
/
1
0
2
4
F
r
e
q
u
e
n
c
y
d
i
v
i
d
e
r
1
/
2
Q
Q
ST
T
2
O
U
T
o
u
t
p
u
t
e
d
g
e
s
w
i
t
c
h
b
i
t
Ti mer 2 o ut p u t c ontrol bit
P
3
6
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
3
6
/
T
2
O
U
T
/φ/(LED
6
)
P3
6
latch
Ti mer 2 output selection bit
P3
6
clock output
co ntr o l bi t
X
C
I
N
X
I
N
System clock φ
“10”
Timer Y
output
Ti mer 3 write
control bit
PWM01 register (2)
PWM01 register (2)
Ti mer 2 write
control bit
Ti mer 1 count
source selection
bits
Ti mer 2 count
source selection
bits
T
i
m
e
r
2
c
o
u
n
t
s
t
o
p
b
i
t
Timer 3 count source
selection bit
T
i
m
e
r
3
c
o
u
n
t
s
t
o
p
b
i
t
Timer 1
Timer 2
Timer 3
Timer 4
Timer 2 latch (8)
T
i
m
e
r
2
(
8
)
T
i
m
e
r
3
l
a
t
c
h
(
8
)
T
i
m
e
r
3
(
8
)
Timer 4 interrupt request
Ti mer 4 write
control bit
Timer 4 latch (8)
T
i
m
e
r
4
(
8
)
Timer 4 count source
selection bit s
T
i
m
e
r
4
c
o
u
n
t
s
t
o
p
b
i
t
T
3OUT
output
edge switch bit
T
i
m
e
r
3
o
u
t
p
u
t
s
e
l
e
c
t
i
o
n
b
i
t
Timer 4 operating
mode selection bit
Ti mer 4 o ut p u t c ontrol bit
P
5
3
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
rT
4OUT
output
edge switch bit
T
i
m
e
r
4
o
u
t
p
u
t
s
e
l
e
c
t
i
o
n
b
i
t
“00”
“01”
“10”
“
0
”
“
1
”
“0”
“1”
“1”
“0”
“
1
”
“
0
”“0”
“
1
”
“
0
1
”
“10”
“00”
“
1
”
“
0
”“0”
“
1
”
Rev.2.00 May 28, 2004 page 26 of 100
38C2 Group (A Version)
16-bit Timer
● Frequency Divider For Timer
Each timer X and timer Y have the frequency dividers for the count
source. The count source of the frequency divider is switched to XIN
or XCIN by the CPU mode register. The division ratio of each timer
can be controlled by each timer division ratio selection bit. The divi-
sion ratio can be selected from as follows;
1/1, 1/2, 1/16, 1/32, 1/64, 1/128, 1/256, 1/1024 of f(XIN); or f(XCIN).
● Timer X
The timer X count source can be selected by setting the timer X mode
register. When f(XCIN) is selected as the count source, counting can
be performed regardless of XCIN oscillation. However, when XCIN is
stopped, the external pulse input from XCIN pin is counted.
The timer X operates as down-count. When the timer contents reach
“000016”, an underflow occurs at the next count pulse and the timer
latch contents are reloaded. After that, the timer continues count-
down. When the timer underflows, the interrupt request bit correspond-
ing to the timer X is set to “1”.
Six operating modes can be selected for timer X by the timer X mode
register and timer X control register.
(1) Timer Mode
The count source can be selected by setting the timer X mode regis-
ter. In this mode, timer X operates as the 18-bit counter by setting the
timer X register (extension).
(2) Pulse Output Mode
Pulses of which polarity is inverted each time the timer underflows
are output from the TXOUT pin. Except for that, this mode operates
just as in the timer mode.
When using this mode, set the port sharing the TXOUT pin to output
mode.
(3) IGBT Output Mode
After dummy output from the TXOUT pin, count starts with the INT0
pin input as a trigger. In the case that the timer X output edge switch
bit is “0”, when the trigger is detected or the timer X underflows, “H” is
output from the TXOUT pin. And then, when the count value corre-
sponds with the compare register value, the TXOUT output becomes
“L”.
After noise is cleared by noise filters, judging continuous 4-time same
levels with sampling clocks to be signals, the INT0 signal can use 4
types of delay time by a delay circuit.
When using this mode, set the port sharing the INT0 pin to input
mode and set the port sharing the TXOUT pin to output mode.
When the timer X output control bit 1 or 2 of the timer X control reg-
ister is set to “1”, the timer X count stop bit is fixed to “1” forcibly by
the interrupt signal of INT1 or INT2. And then, the TXOUT output can
be set to “L” forcibly at the same time that the timer X stops counting.
Do not write “1” to the timer X register (extension) when using the
IGBT output mode.
(4) PWM Mode
IGBT dummy output, an external trigger with the INT0 pin and output
control with pins INT1 and INT2 are not used. Except for those, this
mode operates just as in the IGBT output mode.
The period of PWM waveform is specified by the timer X set value. In
the case that the timer X output edge switch bit is “0”, the “H” interval
is specified by the compare register set value.
When using this mode, set the port sharing the TXOUT pin to output
mode.
Do not write “1” to the timer X register (extension) when using the
PWM mode.
Output waveform of Timer 3 PWM0 or Timer 4 PWM1
2
5
6
✕
t
s256 ✕
t
s256 ✕
t
s 2
5
6
✕
t
s
n
✕
t
sn
✕
t
sn ✕
t
sn ✕
t
s
n ✕ tsn ✕
t
sn ✕
t
s
n
✕
t
s
n ✕ ts
n
✕
t
s
P
W
M
0
1
r
e
g
i
s
t
e
r
=
“
0
0
2
”
n: Setting value of Timer 3 or Timer 4
ts: One period of Ti m er 3 c ount sour c e or Timer 4 count s our ce
PWM01 register (address 0024
16
) : 2-bit value correspond ing to PWM0 ( bits 0, 1) or PWM 1 (bits 2, 3)
(n+1) ✕
t
s
(n+1) ✕
t
s
(n+1) ✕
t
s(n+1) ✕
t
s (
n
+
1
)
✕
t
s
(
n
+
1
)
✕
t
s
P
W
M
0
1
r
e
g
i
s
t
e
r
=
“
0
1
2
”
P
W
M
0
1
r
e
g
i
s
t
e
r
=
“
1
0
2
”
P
W
M
0
1
r
e
g
i
s
t
e
r
=
“
1
1
2
”
Short interval S
h
o
r
t
i
n
t
e
r
v
a
l Short interval S
h
o
r
t
i
n
t
e
r
v
a
l
4 ✕
2
5
6
✕
t
s
Long interval
I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
tI
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
Fig. 21 Waveform of PWM0 and PWM1
Rev.2.00 May 28, 2004 page 27 of 100
38C2 Group (A Version)
Fig. 22 Waveform of PWM/IGBT
(5) Event Counter Mode
The timer counts signals input through the CNTR0 pin. In this mode,
timer X operates as the 18-bit counter by setting the timer X register
(extension). When using this mode, set the port sharing the CNTR0
pin to input mode.
In this mode, the window control can be performed by the timer 1
underflow. When the bit 5 (data for control of event counter window)
of the timer X mode register is set to “1”, counting is stopped at the
next timer 1 underflow. When the bit is set to “0”, counting is re-
started at the next timer 1 underflow.
(6) Pulse Width Measurement Mode
In this mode, the count source is the output of frequency divider for
timer. In this mode, timer X operates as the 18-bit counter by setting
the timer X register (extension). When the bit 6 of the CNTR0 active
edge switch bits is “0”, counting is executed during the “H” interval of
CNTR0 pin input. When the bit is “1”, counting is executed during the
“L” interval of CNTR0 pin input. When using this mode, set the port
sharing the CNTR0 pin to input mode.
■ Notes on Timer X
(1) Write Order to Timer X
•In the timer mode, pulse output mode, event counter mode and
pulse width measurement mode, write to the following registers in
the order as shown below;
the timer X register (extension),
the timer X register (low-order),
the timer X register (high-order).
Do not write to only one of them.
When the above mode is set and timer X operates as the 16-bit
counter, if the timer X register (extension) is never set after reset is
released, setting the timer X register (extension) is not required. In
this case, write the timer X register (low-order) first and the timer X
register (high-order). However, once writing to the timer X register
(extension) is executed, note that the value is retained to the reload
latch.
• In the IGBT output and PWM modes, do not write “1” to the timer X
register (extension). Also, when “1” is already written to the timer X
register, be sure to write “0” to the register before using.
Write to the following registers in the order as shown below;
the compare register (high- and low-order),
the timer X register (extension),
the timer X register (low-order),
the timer X register (high-order).
It is possible to use whichever order to write to the compare regis-
ter (high- and low-order). However , write both the compare register
and the timer X register at the same time.
(2) Read Order to Timer X
•In all modes, read the following registers in the order as shown below;
the timer X register (extension),
the timer X register (high-order),
the timer X register (low-order).
When reading the timer X register (extension) is not required, read
the timer X register (high-order) first and the timer X register (low-
order).
Read order to the compare register is not specified.
•If reading to the timer X register during write operation or writing to
it during read operation is performed, normal operation will not be
performed.
(3) Write to Timer X
•Which write control can be selected by the timer X write control bit
(b3) of the timer X mode register (address 2F16), writing data to
both the latch and the timer at the same time or writing data only to
the latch. When writing a value to the timer X address to write to the
latch only, the value is set into the reload latch and the timer is
updated at the next underflow. After reset release, when writing a
value to the timer X address, the value is set into the timer and the
timer latch at the same time, because they are written at the same
time.
When writing to the latch only, if the write timing to the high-order
reload latch and the underflow timing are almost the same, the value
is set into the timer and the timer latch at the same time. In this time,
counting is stopped during writing to the high-order reload latch.
•Do not switch the timer count source during timer count operation.
Stop the timer count before switching it.
t
s
T
i
m
e
r
X
c
o
u
n
t
s
o
u
r
c
e
T
i
m
e
r
X
P
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M
m
o
d
e
I
G
B
T
o
u
t
p
u
t
m
o
d
e(
n
-
m
+
1
)
✕
t
sm
✕
t
s
(n+1) ✕ ts
W
h
e
n
t
h
e
T
i
m
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r
X
s
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t
t
i
n
g
v
a
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u
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=
n
a
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d
t
h
e
c
o
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p
a
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g
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t
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m
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t
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c
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t
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e
f
o
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l
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g
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w
a
v
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f
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m
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s
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t
p
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t
;
D
u
t
y
:
(
n
-
m
+
1
)
/
(
n
+
1
)
P
e
r
i
o
d
:
(
n
+
1
)
✕
t
s
Rev.2.00 May 28, 2004 page 28 of 100
38C2 Group (A Version)
(4) Set of Timer X Mode Register
Set the write control bit of the timer X mode register to “1” (write to
the latch only) when setting the IGBT output and PWM modes.
Output waveform simultaneously reflects the contents of both regis-
ters at the next underflow after writing to the timer X register (high-
order).
(5) Output Control Function of Timer X
When using the output control function (INT1 and INT2) in the IGBT
output mode, set the levels of INT1 and INT2 to “H” in the falling edge
active or to “L” in the rising edge active before switching to the IGBT
output mode.
(6) Note on Switch of CNTR0 Active Edge
• When the CNTR0 active edge switch bits are set, at the same time,
the interrupt active edge is also affected.
• When the pulse width is measured, set the bit 7 of the CNTR0 ac-
tive edge switch bits to “0”.
Timer Y
Timer Y is a 16-bit timer. The timer Y count source can be selected
by setting the timer Y mode register. When f(XCIN) is selected as the
count source, counting can be performed regardless of XCIN oscilla-
tion. However, when XCIN is stopped, the external pulse input from
XCIN pin is counted.
Four operating modes can be selected for timer Y by the timer Y
mode register. Also, the real time port can be controlled.
(1) Timer Mode
The timer Y count source can be selected by setting the timer Y mode
register.
(2) Period Measurement Mode
The interrupt request is generated at rising or falling edge of CNTR1
pin input signal. Simultaneously, the value in timer Y latch is reloaded
in timer Y and timer Y continues counting. Except for that, this mode
operates just as in the timer mode.
The timer value just before the reloading at rising or falling of CNTR1
pin input is retained until the timer Y is read once after the reload.
The rising or falling timing of CNTR1 pin input is found by CNTR1
interrupt. When using this mode, set the port sharing the CNTR1 pin
to input mode.
(3) Event Counter Mode
The timer counts signals input through the CNTR1 pin.
Except for that, this mode operates just as in the timer mode.
When using this mode, set the port sharing the CNTR1 pin to input
mode.
(4) Pulse Width HL Continuously Measurement
Mode
The interrupt request is generated at both rising and falling edges of
CNTR1 pin input signal. Except for that, this mode operates just as in
the period measurement mode. When using this mode, set the port
sharing the CNTR1 pin to input mode.
■ Notes on Timer Y
● CNTR1 Interrupt Active Edge Selection
CNTR1 interrupt active edge depends on the CNTR1 active edge
switch bit. However, in pulse width HL continuously measurement
mode, CNTR1 interrupt request is generated at both rising and falling
edges of CNTR1 pin input signal regardless of the setting of CNTR1
active edge switch bit.
● Timer Y Read/Write Control
• When reading from/writing to timer Y, read from/write to both the
high-order and low-order bytes of timer Y. When the value is read,
read the high-order bytes first and the low-order bytes next. When
the value is written, write the low-order bytes first and the high-
order bytes next.
If reading from the timer Y register during write operation or writing
to it during read operation is performed, normal operation will not
be performed.
• When writing a value to the timer Y address to write to the latch
only, the value is set into the reload latch and the timer is updated
at the next underflow. Normally, when writing a value to the timer Y
address, the value is set into the timer and the timer latch at the
same time, because they are set to write at the same time.
When writing to the latch only, if the write timing to the high-order
reload latch and the underflow timing are almost the same, the value
is set into the timer and the timer latch at the same time. In this
time, counting is stopped during writing to the high-order reload
latch.
• Do not switch the timer count source during timer count operation.
Stop the timer count before switching it.
● Real Time Port Control
When the real time port function is valid, data for the real time port is
output from ports P47 and P46 each time the timer Y underflows.
(However, if the real time port control bit is changed from “0” to “1”
after the data for real time port is set, data is output independent of
the timer Y operation.) When the data for the real time port is changed
while the real time port function is valid, the changed data is output at
the next underflow of timer Y. Before using this function, set the cor-
responding port direction registers to output mode.
Rev.2.00 May 28, 2004 page 29 of 100
38C2 Group (A Version)
Fig. 23 Structure of Timer X, Y related registers
Timer X mode register
(TXM: address 002F16)
T
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m
e
r
X
o
p
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r
a
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g
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b
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b
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00 0
:
T
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00 1
:
P
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11 0
:
N
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(
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T
X
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:
a
d
d
r
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s
s
0
F
F
41
6)
Noise filter sampling clock selection bit
0 : f(XIN)/2
1 : f(XIN)/4
External trigger delay time selection bits
b2 b1
0 0 : Not delayed
0 1 : (4/f (XIN)) µs
1 0 : (8/f (XIN)) µs
1 1 : (16/f(XIN)) µs
Timer X output control bit 1 (P51)
0 : Not used
1 : INT1 interrupt used
Timer X output control bit 2 (P34)
0 : Not used
1 : INT2 interrupt used
Timer X output edge switch bit
0 : Start at “L” output
1 : Start at “H” output
CNTR0 active edge switch bits
b7 b6
0 0 : Count at rising edge in event counter mode
Falling edge active for CNTR0 interrupt
Measure “H” pulse width in pulse width measurement mode
0 1 : Count at falling edge in event counter mode
Rising edge active for CNTR0 interrupt
Measure “L” pulse width in pulse width measurement mode
1 0 : Count at both edges in event counter mode
Both edges active for CNTR0 interrupt
1 1 : Count at both edges in event counter mode
Both edges active for CNTR0 interrupt
b7 b
0
Timer XY frequency division selection regi ster
(PREXY: address 0FF716)
T
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r
X
f
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q
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:
1
/
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✕
f
(
XI
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✕
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(
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✕
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(
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:
1
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✕
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(
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N)
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r
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✕
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(
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:
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2
✕
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(
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r
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3
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✕
f
(
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10 0
:
1
/
6
4
✕
f
(
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r
1
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6
4
✕
f
(
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:
1
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1
2
8
✕
f
(
XI
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/
1
2
8
✕
f
(
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11 0
:
1
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2
5
6
✕
f
(
XI
N)
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r
1
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5
6
✕
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(
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:
1
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0
2
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✕
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(
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r
1
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2
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✕
f
(
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T
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:
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(
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(
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:
1
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✕
f
(
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r
1
/
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✕
f
(
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N)
01 0
:
1
/
2
✕
f
(
XI
N)
o
r
1
/
2
✕
f
(
XC
I
N)
01 1
:
1
/
3
2
✕
f
(
XI
N)
o
r
1
/
3
2
✕
f
(
XC
I
N)
10 0
:
1
/
6
4
✕
f
(
XI
N)
o
r
1
/
6
4
✕
f
(
XC
I
N)
10 1
:
1
/
1
2
8
✕
f
(
XI
N)
o
r
1
/
1
2
8
✕
f
(
XC
I
N)
11 0
:
1
/
2
5
6
✕
f
(
XI
N)
o
r
1
/
2
5
6
✕
f
(
XC
I
N)
11 1
:
1
/
1
0
2
4
✕
f
(
XI
N)
o
r
1
/
1
0
2
4
✕
f
(
XC
I
N)
N
o
t
u
s
e
d
(
r
e
t
u
r
n
s
“
0
”
w
h
e
n
r
e
a
d
)
b7 b0
Timer Y mode register
(TYM: address 003016)
R
e
a
l
t
i
m
e
p
o
r
t
c
o
n
t
r
o
l
b
i
t
0
:
R
e
a
l
t
i
m
e
p
o
r
t
f
u
n
c
t
i
o
n
i
n
v
a
l
i
d
1
:
R
e
a
l
t
i
m
e
p
o
r
t
f
u
n
c
t
i
n
v
a
l
i
d
P
46
d
a
t
a
f
o
r
r
e
a
l
t
i
m
e
p
o
r
t
P
47
d
a
t
a
f
o
r
r
e
a
l
t
i
m
e
p
o
r
t
T
i
m
e
r
Y
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
0
:
F
r
e
q
u
e
n
c
y
d
i
v
i
d
e
r
o
u
t
p
u
t
1
:
f
(
XC
I
N)
T
i
m
e
r
Y
o
p
e
r
a
t
i
n
g
m
o
d
e
b
i
t
s
b
5
b
4
00
:
T
i
m
e
r
m
o
d
e
01
:
P
e
r
i
o
d
m
e
a
s
u
r
e
m
e
n
t
m
o
d
e
10
:
E
v
e
n
t
c
o
u
n
t
e
r
m
o
d
e
11
:
P
u
l
s
e
w
i
d
t
h
H
L
c
o
n
t
i
n
u
o
u
s
m
e
a
s
u
r
e
m
e
n
t
m
o
d
e
C
N
T
R1
a
c
t
i
v
e
e
d
g
e
s
w
i
t
c
h
b
i
t
0
:
C
o
u
n
t
a
t
r
i
s
i
n
g
e
d
g
e
i
n
e
v
e
n
t
c
o
u
n
t
e
r
m
o
d
e
M
e
a
s
u
r
e
f
a
l
l
i
n
g
p
e
r
i
o
d
i
n
p
e
r
i
o
d
m
e
a
s
u
r
e
m
e
n
t
m
o
d
e
F
a
l
l
i
n
g
e
d
g
e
a
c
t
i
v
e
f
o
r
C
N
T
R1
i
n
t
e
r
r
u
p
t
1
:
C
o
u
n
t
a
t
f
a
l
l
i
n
g
e
d
g
e
i
n
e
v
e
n
t
c
o
u
n
t
e
r
m
o
d
e
M
e
a
s
u
r
e
r
i
s
i
n
g
p
e
r
i
o
d
i
n
p
e
r
i
o
d
m
e
a
s
u
r
e
m
e
n
t
m
o
d
e
R
i
s
i
n
g
e
d
g
e
a
c
t
i
v
e
f
o
r
C
N
T
R1
i
n
t
e
r
r
u
p
t
T
i
m
e
r
Y
c
o
u
n
t
s
t
o
p
b
i
t
0
:
C
o
u
n
t
o
p
e
r
a
t
i
o
n
1
:
C
o
u
n
t
s
t
o
p
b
7b
0
Timer Y mode register 2
(TYM2: address 0FFB16)
Timer Y wr ite control bit
0 : Write data to both timer latch and timer
1 : Write data to timer latch only
Not used (returns “0” when read)
b
7b
0
Rev.2.00 May 28, 2004 page 30 of 100
38C2 Group (A Version)
Fig. 24 Block diagram of Timer X, Y
Real time port
control bit
R
e
a
l
t
i
m
e
p
o
r
t
c
o
n
t
r
o
l
b
i
tQ
D
L
a
t
c
h
Q D
L
a
t
c
h
P
4
7
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
rP
4
7
l
a
t
c
h
P4
7
data for real time port
P
4
6
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
rP
4
6
l
a
t
c
h
P4
6
data for real time port
“
1
”
T
i
m
e
r
Y
(
l
o
w
-
o
r
d
e
r
)
l
a
t
c
h
(
8
)
“0”
C
N
T
R
1
a
c
t
i
v
e
e
d
g
e
s
w
i
t
c
h
b
i
t
“
1
0
”
P
47/
R
T
P1/
A
N7
P
46/
R
T
P0/
A
N6
P60/CNTR1
Falling edge detection Period measurement mode
T
i
m
e
r
Y
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
P
u
l
s
e
w
i
d
t
h
H
L
c
o
n
t
i
n
u
o
u
s
m
e
a
s
u
r
e
m
e
n
t
m
o
d
e
Timer Y operating
mode bits
CNTR1
interr upt request
Rising edge detection
Count source selection bit
X
cI
N“
1
”
Clock for Timer Y
Data bus
1
/
21
/
4
F
r
e
q
u
e
n
c
y
d
i
v
i
d
e
r
Noise filter sampling
clock selection bit
“
1
”
“0”
T
i
m
e
r
X
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
E
q
u
a
l
“
0
0
0
”
“
0
0
1
”
“
0
1
0
”
“
0
1
1
”
“
1
0
1
”
P
u
l
s
e
w
i
d
t
h
m
e
a
s
u
r
e
m
e
n
t
m
o
d
e
T
i
m
e
r
X
c
o
u
n
t
s
t
o
p
b
i
t
Compare register (low-order)(8) Compare register (high-order)(8)
Output selection bit
P
3
5
l
a
t
c
h
P
3
5
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P35/TXOUT/(LED5)
P51/INT1
P
34/
I
N
T2/
(
L
E
D4)S
Q
Q
T
R
T
XOUT
edge
switch bit
S
“0”
“
1
”Q
Q
T
S
Pulse output mode
C
N
T
R
0
a
c
t
i
v
e
e
d
g
e
s
w
i
t
c
h
b
i
t
s
T
i
m
e
r
X
o
p
e
r
a
t
i
n
g
m
o
d
e
b
i
t
s
C
N
T
R0
i
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
“
1
0
0
”
E
x
t
e
n
d
l
a
t
c
h
(
2
)
Extend counter (2)
T
i
m
e
r
X
w
r
i
t
e
c
o
n
t
r
o
l
b
i
t
Timer 1 interrupt
D Q
L
a
t
c
h
D
a
t
a
f
o
r
c
o
n
t
r
o
l
o
f
e
v
e
n
t
c
o
u
n
t
e
r
w
i
n
d
o
w
P
37/
C
N
T
R0/
(
L
E
D7)
P
50/
I
N
T0
0 µs
D
e
l
a
y
t
i
m
e
s
e
l
e
c
t
i
o
n
b
i
t
s
4/f(X
IN
)
“00”
“01”
“10”
“11”
8/f(X
IN
)
16/f(X
IN
)
N
o
i
s
e
f
i
l
t
e
r
(
4
t
i
m
e
s
s
a
m
e
l
e
v
e
l
s
j
u
d
g
m
e
n
t
)
INT0
interr upt request
Count source selection bit
X
cI
N
C
l
o
c
k
f
o
r
T
i
m
e
r
X
System clock control bits
3
C
l
o
c
k
f
o
r
T
i
m
e
r
Y
XI
N
Real time port control bit
Timer Y mode register
write signal
T
i
m
e
r
Y
(
l
o
w
-
o
r
d
e
r
)
(
8
)
X
cI
N
XI
N
F
r
e
q
u
e
n
c
y
d
i
v
i
d
e
r
IGBT output mode
PWM mode Timer Y operating mode bits
T
i
m
e
r
X
f
r
e
q
u
e
n
c
y
d
i
v
i
s
i
o
n
s
e
l
e
c
t
i
o
n
b
i
ts
T
i
m
e
r
Y
f
r
e
q
u
e
n
c
y
d
i
v
i
s
i
o
n
s
e
l
e
c
t
i
o
n
b
i
t
s
3
B
o
t
h
e
d
g
e
s
d
e
t
e
c
t
i
o
n
“00”
“
0
1
”
“10”
“11”
T
X
O
U
T
o
u
t
p
u
t
c
o
n
t
r
o
l
b
i
t
1
T
X
O
U
T
o
u
t
p
u
t
c
o
n
t
r
o
l
b
i
t
2
T
i
m
e
r
X
o
p
e
r
a
t
i
n
g
m
o
d
e
b
i
t
s
“010”
“00”, “01”, “11”
“1”
“
0
”
“
1
”
“
0
”
“1”
“0”
“00”, “01”, “10”
“11”
“
0
”
T
i
m
e
r
Y
w
r
i
t
e
c
o
n
t
r
o
l
b
i
t
T
i
m
e
r
Y
c
o
u
n
t
s
t
o
p
b
i
t
“
0
0
0
”
“
0
0
1
”
“
0
1
1
”
“
1
0
0
”
“
1
0
1
”
Timer X operating
mode bits
“
0
1
0
”
Delay
circuit
Timer Y (high-order) latch (8)
Timer Y (high-order)(8)
Timer X (low-order) latch (8)
T
i
m
e
r
X
(
l
o
w
-
o
r
d
e
r
)
(
8
)
T
i
m
e
r
X
(
h
i
g
h
-
o
r
d
e
r
)
l
a
t
c
h
(
8
)
Timer X (high-order)(8)
T
h
e
f
o
l
l
o
w
i
n
g
v
a
l
u
e
s
c
a
n
b
e
s
e
l
e
c
t
e
d
t
h
e
c
l
o
c
k
f
o
r
T
i
m
e
r
;
1
/
1
,
1
/
2
,
1
/
1
6
,
1
/
3
2
,
1
/
6
4
,
1
/
1
2
8
,
1
/
2
5
6
,
1
/
1
0
2
4
“
1
”
“
0
”
E
d
g
e
s
e
l
e
c
t
i
o
n
*
Edge
selection *
Edge
detection
Edge
selection *
*
I
n
t
e
r
r
u
p
t
e
d
g
e
s
o
f
I
N
T
0
,
I
N
T
1
,
I
N
T
2
c
a
n
b
e
s
e
l
e
c
t
e
d
b
y
t
h
e
i
n
t
e
r
r
u
p
t
e
d
g
e
s
e
l
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
a
d
d
r
e
s
s
0
0
3
A1
6)
.
0
:
F
a
l
l
i
n
g
e
d
g
e
a
c
t
i
v
e
1
:
R
i
s
i
n
g
e
d
g
e
a
c
t
i
v
e
Rev.2.00 May 28, 2004 page 31 of 100
38C2 Group (A Version)
SERIAL I/O
The 38C2 group has built-in two 8-bit serial I/O.
Serial I/O can be used as either clock synchronous or asynchronous
(UART) serial I/O. A dedicated timer is also provided for baud rate
generation.
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O mode can be selected by setting the
serial I/O mode selection bit of the serial I/O control register to “1”.
For clock synchronous serial I/O, the transmitter and the receiver
must use the same clock. If an internal clock is used, transfer is
started by a write signal to the TB/RB.
Fig. 25 Block diagram of clock synchronous serial I/O
Fig. 26 Operation of clock synchronous serial I/O function
1/4
1/4
F/F
P5
6
/S
CLK1
[P3
1
/S
CLK2
]
Serial I/O status register
Serial I/O control register
P5
7
/S
RDY1
[P3
0
/S
RDY2
]
P5
4
/R
X
D
1
[P3
3
/R
X
D
2
]
P5
5
/T
X
D
1
[P3
2
/T
X
D
2
]
f(X
IN
)
Receive buffer register
Address 001C
16
[Address 001E
16
]
Receive shift register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Clock control circuit
Shift clock
Serial I/O synchronous
clock selection bit
Frequency division ratio 1/(n+1)
Baud rate generator
Address 0FE2
16
[Address 0FE5
16
]
BRG count source selection bit
Clock control circuit
Falling-edge detector
Transmit buffer register
Data bus
Address 001C
16
[Address 001E
16
]
Shift clock Transmit shift completion flag (TSC)
Transmit buffer empty flag (TBE)
Transmit interrupt request (TI)
Transmit interrupt source selection bit
Address 001D
16
[Address 001F
16
]
Data bus
Address 0FE0
16
[Address 0FE3
16
]
Transmit shift register
(f(X
CIN
) in low-speed mode)
[ ] : For Serial I/O2
D
7
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
0
D
1
D
2
D
3
D
4
D
5
D
6
RBF = 1
TSC = 1
TBE = 0 TBE = 1
TSC = 0
Transfer shift clock
(1/2 to 1/2048 of the internal
clock, or an external clock)
Serial output TxD
Serial input RxD
Write pulse to receive/transmit
buffer register
Overrun error (OE)
detection
Notes 1: As the transmit interrupt (TI) source, which can be selected, either when the transmit buffer has emptied (TBE = 1) or
after the transmit shift operation has ended (TSC = 1), by setting the transmit interrupt source selection bit (TIC) of the
serial I/O control register.
2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data
is output continuously from the TxD pin.
3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
Receive enable signal
S
RDY
Rev.2.00 May 28, 2004 page 32 of 100
38C2 Group (A Version)
(2) Asynchronous Serial I/O (UART) Mode
Clock asynchronous serial I/O mode (UART) can be selected by set-
ting the serial I/O mode selection bit of the serial I/O control register
to “0”.
Eight serial data transfer formats can be selected, and the transfer
formats used by a transmitter and receiver must be identical.
The transmit and receive shift registers each have a buffer, but the
two buffers have the same address in memory. Since the shift regis-
ter cannot be written to or read from directly, transmit data is written
to the transmit buffer register, and receive data is read from the re-
ceive buffer register.
The transmit buffer register can also hold the next data to be trans-
mitted, and the receive buffer register can hold a character while the
next character is being received.
Fig. 27 Block diagram of UART serial I/O
f(X
IN
)
1/4
OE
PE FE
1/16
1/16
Data bus
Receive buffer register
Receive shift register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Baud rate generator
Frequency division ratio 1/(n+1)
ST/SP/PA generator
Transmit buffer register
Data bus
Transmit shift register
Transmit shift completion flag (TSC)
Transmit buffer empty flag (TBE)
Transmit interrupt request (TI)
ST detector
SP detector UART control register
Address 0FE1
16
[Address 0FE4
16
]
Character length selection bit
BRG count source selection bit
Transmit interrupt source selection bit
Serial I/O synchronous clock selection bit
Clock control circuit
Character length selection bit
7 bits
8 bits
Serial I/O control register
Serial I/O status register
(f(X
CIN
) in low-speed mode)
P5
6
/S
CLK1
[P3
1
/S
CLK2
]
P5
4
/R
X
D
1
[P3
3
/R
X
D
2
]
P5
5
/T
X
D
1
[P3
2
/T
X
D
2
]
Address 001C
16
[Address 001E
16
]
Address 0FE2
16
[Address 0FE5
16
]
Address 001C
16
[Address 001E
16
]Address 001D
16
[Address 001F
16
]
Address 0FE0
16
[Address 0FE3
16
]
[ ] : For Serial I/O2
Fig. 28 Operation of UART serial I/O function
T
S
C
=
0
T
B
E
=
1
RBF=0
T
B
E
=
0T
B
E
=
0
RBF=1 R
B
F
=
1
S
T
D0D1S
P
D0D1
S
T
S
P
T
B
E
=
1T
S
C
=
1
S
T
D0D1S
P
D0D1
S
T
S
P
T
r
a
n
s
m
i
t
o
r
r
e
c
e
i
v
e
c
l
o
c
k
T
r
a
n
s
m
i
t
b
u
f
f
e
r
r
e
g
i
s
t
e
r
w
r
i
t
e
s
i
g
n
a
l
Generated at 2nd bit in 2-stop-bit m ode
1 start bit
7 or 8 data bit
1 or 0 parity bit
1 or 2 stop bit ( s)
1
:
E
r
r
o
r
f
l
a
g
d
e
t
e
c
t
i
o
n
o
c
c
u
r
s
a
t
t
h
e
s
a
m
e
t
i
m
e
t
h
a
t
t
h
e
R
B
F
f
l
a
g
b
e
c
o
m
e
s
“
1
”
(
a
t
1
s
t
s
t
o
p
b
i
t
,
d
u
r
i
n
g
r
e
c
e
p
t
i
o
n
)
.
2
:
A
s
t
h
e
t
r
a
n
s
m
i
t
i
n
t
e
r
r
u
p
t
(
T
I
)
,
w
h
e
n
e
i
t
h
e
r
t
h
e
T
B
E
o
r
T
S
C
f
l
a
g
b
e
c
o
m
e
s
“
1
,
”
c
a
n
b
e
s
e
l
e
c
t
e
d
t
o
o
c
c
u
r
d
e
p
e
n
d
i
n
g
o
n
t
h
e
s
e
t
t
i
n
g
o
f
t
h
e
t
r
a
n
s
m
i
t
i
n
t
e
r
r
u
p
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
(
T
I
C
)
o
f
t
h
e
s
e
r
i
a
l
I
/
O
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
.
3
:
T
h
e
r
e
c
e
i
v
e
i
n
t
e
r
r
u
p
t
(
R
I
)
i
s
s
e
t
w
h
e
n
t
h
e
R
B
F
f
l
a
g
b
e
c
o
m
e
s
“
1
”
.
4
:
A
f
t
e
r
d
a
t
a
i
s
w
r
i
t
t
e
n
t
o
t
h
e
t
r
a
n
s
m
i
t
b
u
f
f
e
r
w
h
e
n
T
S
C
f
l
a
g
=
“
1
”
,
0
.
5
t
o
1
.
5
c
y
c
l
e
s
o
f
t
h
e
d
a
t
a
s
h
i
f
t
c
y
c
l
e
i
s
n
e
c
e
s
s
a
r
y
u
n
t
i
l
c
h
a
n
g
i
n
g
t
o
T
S
C
f
l
a
g
=
“
0
”
.
N
o
t
e
s
✽
✽
S
e
r
i
a
l
o
u
t
p
u
t
TXD
S
e
r
i
a
l
i
n
p
u
t
RXD
R
e
c
e
i
v
e
b
u
f
f
e
r
r
e
g
i
s
t
e
r
r
e
a
d
s
i
g
n
a
l
Rev.2.00 May 28, 2004 page 33 of 100
38C2 Group (A Version)
[Transmit Buffer Register/Receive Buffer Reg-
ister (TB/RB)]
The transmit buffer register and the receive buffer register are lo-
cated at the same address. The transmit buffer is write-only and the
receive buffer is read-only. If a character bit length is 7 bits, the MSB
of data stored in the receive buffer is “0”.
[Serial I/O Status Register (SIO1STS, SIO2STS)]
The read-only serial I/O status register consists of seven flags (bits 0
to 6) which indicate the operating status of the serial I/O function and
various errors.
Three of the flags (bits 4 to 6) are valid only in UART mode.
The receive buffer full flag (bit 1) is set to “0” when the receive buffer
register is read.
If there is an error, it is detected at the same time that data is trans-
ferred from the receive shift register to the receive buffer register,
and the receive buffer full flag is set. A write to the serial I/O status
register sets all the error flags OE, PE, FE, and SE (bit 3 to bit 6,
respectively) to “0”. Writing “0” to the serial I/O enable bit SIOE (bit 7
of the serial I/O control register) also sets all the status flags to “0”,
including the error flags.
All bits of the serial I/O status register are set to “0” at reset, but if the
transmit enable bit (bit 4) of the serial I/O control register has been
set to “1”, the transmit shift completion flag (bit 2) and the transmit
buffer empty flag (bit 0) become “1”.
[Serial I/O Control Register (SIO1CON, SIO2CON)]
The serial I/O control register consists of eight control bits for the
serial I/O function.
[UART Control Register (UART1CON, UART2CON)]
The UART control register consists of four control bits (bits 0 to 3)
which are valid when asynchronous serial I/O is selected and set the
data format of an data transfer and one bit (bit 4) which is always
valid and sets the output structure of the P55/TXD1 [P32/TxD2] pin.
[Baud Rate Generator (BRG1, BRG2)]
The baud rate generator determines the baud rate for serial transfer.
The baud rate generator divides the frequency of the count source
by 1/(n + 1), where n is the value written to the baud rate generator.
Rev.2.00 May 28, 2004 page 34 of 100
38C2 Group (A Version)
b7
b7
Transmit buffer empty flag (TBE)
0: Buffer full
1: Buffer empty
Receive buffer full flag (RBF)
0: Buffer empty
1: Buffer full
Transmit shift completion flag (TSC)
0: Transmit shift in progress
1: Transmit shift completed
Overrun error flag (OE)
0: No error
1: Overrun error
Parity error flag (PE)
0: No error
1: Parity error
Framing error flag (FE)
0: No error
1: Framing error
Summing error flag (SE)
0: (OE) U (PE) U (FE)=0
1: (OE) U (PE) U (FE)=1
Not used (returns “1” when read)
Serial I/O status register
Serial I/O control register
b0 b0
BRG count source selection bit (CSS)
0: f(X
IN
) (f(X
CIN
) in low-speed mode)
1: f(X
IN
)/4 (f(X
CIN
)/4 in low-speed mode)
Serial I/O synchronous clock selection bit (SCS)
0: BRG output divided by 4 when clock synchronous
serial I/O is selected.
BRG output divided by 16 when UART is selected.
1: External clock input when clock synchronous serial
I/O is selected.
External clock input divided by 16 when UART is selected.
S
RDY
output enable bit (SRDY)
0: P5
7
[P3
0
] pin operates as ordinary I/O pin
1: P5
7
[P3
0
] pin operates as S
RDY
output pin
Transmit interrupt source selection bit (TIC)
0: Interrupt when transmit buffer has emptied
1: Interrupt when transmit shift operation is completed
Transmit enable bit (TE)
0: Transmit disabled
1: Transmit enabled
Receive enable bit (RE)
0: Receive disabled
1: Receive enabled
Serial I/O mode selection bit (SIOM)
0: Clock asynchronous (UART) serial I/O
1: Clock synchronous serial I/O
Serial I/O enable bit (SIOE)
0: Serial I/O disabled
(pins P5
4
[P3
0
] to P5
7
[P3
3
] operate as ordinary I/O pins)
1: Serial I/O enabled
(pins P5
4
[P3
0
] to P5
7
[P3
3
] operate as serial I/O pins)
b7
UART control register
Character length selection bit (CHAS)
0: 8 bits
1: 7 bits
Parity enable bit (PARE)
0: Parity checking disabled
1: Parity checking enabled
Parity selection bit (PARS)
0: Even parity
1: Odd parity
Stop bit length selection bit (STPS)
0: 1 stop bit
1: 2 stop bits
P5
5
/TXD
1
[P3
2
/TxD
2
] P-channel output disable bit (POFF)
0: CMOS output (in output mode)
1: N-channel open drain output (in output mode)
Not used (return “1” when read)
b0
(SIO1STS : address 001D
16
)
[SIO2STS : address 001F
16
](SIO1CON : address 0FE0
16
)
[SIO2CON : address 0FE3
16
]
(UART1CON : address 0FE1
16
)
[UART2CON : address 0FE4
16
]
( ) : For Serial I/O1
[ ] : For Serial I/O2
Fig. 29 Structure of serial I/O related registers
■Notes on serial I/O
When setting transmit enable bit to “1”, the serial I/O transmit inter-
rupt request bit is automatically set to “1”. When not requiring the
interrupt occurrence synchronous with the transmision enabled, take
the following sequence.
➀Set the serial I/O transmit interrupt enable bit to “0” (disabled).
➁Set the transmit enable bit to “1”.
➂Set the serial I/O transmit interrupt request bit to “0” after 1 or more
instructions have been executed.
➃Set the serial I/O transmit interrupt enable bit to “1” (enabled).
Rev.2.00 May 28, 2004 page 35 of 100
38C2 Group (A Version)
A-D CONVERTER
The 38C2 group has a 10-bit A-D converter. The A-D converter per-
forms successive approximation conversion.
[A-D Conversion Register (ADL, ADH)]
One of these registers is a high-order register, and the other is a low-
order register . The high-order 8 bits of a conversion result is stored in
the A-D conversion register (high-order) (address 001B16), and the
low-order 2 bits of the same result are stored in bit 7 and bit 6 of the
A-D conversion register (low-order) (address 001A16).
During A-D conversion, do not read these registers.
Also, the connection between the resistor ladder and reference volt-
age input pin (VREF) can be controlled by the VREF input switch bit (bit
0 of address 001A16). When “1” is written to this bit, the resistor ladder
is always connected to VREF. When “0” is written to this bit, the resistor
ladder is disconnected from VREF except during the A-D conversion.
[A-D Control Register (ADCON)]
This register controls A-D converter. Bits 2 to 0 are analog input pin
selection bits. Bit 3 is an AD conversion completion bit and “0” during A-
D conversion. This bit is set to “1” upon completion of A-D conversion.
A-D conversion is started by setting “0” in this bit.
[Comparison Voltage Generator]
The comparison voltage generator divides the voltage between AVSS
and VREF, and outputs the divided voltages.
[Channel Selector]
The channel selector selects one of the input ports P47/AN7–P40/
AN0 and inputs it to the comparator.
[Comparator and Control Circuit]
The comparator and control circuit compares an analog input volt-
age with the comparison voltage and store the result in the A-D con-
version register. When an A-D conversion is completed, the control
circuit sets the AD conversion completion bit and the AD conversion
interrupt request bit to “1.”
Note that because the comparator consists of a capacitor coupling,
set the A-D clock frequency to 250 kHz or more during an A-D con-
version.
Also, when the STP instruction is executed during the A-D conver-
sion, the A-D conversion is stopped immediately, the A-D conversion
completion bit is set to “1”, and the interrupt request is generated.
Fig. 31 Block diagram of A-D converter
Fig. 30 Structure of A-D control register
Data bus
AV
SS
A-D interrupt request
b7 b0
3
P4
0
/O
OUT0
/AN
0
P4
1
/O
OUT1
/AN
1
P4
2
/AN
2
P4
3
/AN
3
P4
4
/AN
4
P4
5
/AN
5
P4
6
/AN
6
P4
7
/AN
7
A-D control register
Channel selector
Comparator
A-D control circuit
A-D conversion register (H) A-D conversion register (L)
(Address 001B
16
)(Address 001A
16
)
Resistor ladder
V
REF
A
n
a
l
o
g
i
n
p
u
t
p
i
n
s
e
l
e
c
t
i
o
n
b
i
t
s
b
2
b
1
b
0
00 0
:
P
40/
A
N0
00 1
:
P
41/
A
N1
01 0
:
P
42/
A
N2
01 1
:
P
43/
A
N3
10 0
:
P
44/
A
N4
10 1
:
P
45/
A
N5
11 0
:
P
46/
A
N6
11 1
:
P
47/
A
N7
A
D
c
o
n
v
e
r
s
i
o
n
c
o
m
p
l
e
t
i
o
n
b
i
t
0
:
C
o
n
v
e
r
s
i
o
n
i
n
p
r
o
g
r
e
s
s
1
:
C
o
n
v
e
r
s
i
o
n
c
o
m
p
l
e
t
e
d
A
D
c
o
n
v
e
r
s
i
o
n
c
l
o
c
k
s
e
l
e
c
t
i
o
n
b
i
t
s
b
5
b
4
00
:
XI
N/
2
01
:
XI
N/
4
10
:
XI
N/
8
11
:
XI
N/
1
6
1
0
-
b
i
t
o
r
8
-
b
i
t
c
o
n
v
e
r
s
i
o
n
s
w
i
t
c
h
b
i
t
0
:
1
0
-
b
i
t
A
D
1
:
8
-
b
i
t
A
D
B
o
o
s
t
e
r
s
e
l
e
c
t
i
o
n
b
i
t
(
W
h
e
n
A
-
D
c
o
n
v
e
t
e
r
i
s
u
s
e
d
a
t
VC
C
=
2
.
5
V
o
r
l
e
s
s
,
w
r
i
t
e
“
1
”
t
o
t
h
i
s
b
i
t
.
)
0
:
B
o
o
s
t
e
r
n
o
t
u
s
e
d
1
:
B
o
o
s
t
e
r
u
s
e
d
A
-
D
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
A
D
C
O
N
:
a
d
d
r
e
s
s
0
0
1
9
1
6
)
b
7b
0
1
0
-
b
i
t
r
e
a
d
i
n
g
(
R
e
a
d
a
d
d
r
e
s
s
0
0
1
B
1
6
b
e
f
o
r
e
0
0
1
A
1
6
)
A
-
D
c
o
n
v
e
r
s
i
o
n
r
e
g
i
s
t
e
r
1
(
A
d
d
r
e
s
s
0
0
1
B
1
6
)
A
-
D
c
o
n
v
e
r
s
i
o
n
r
e
g
i
s
t
e
r
2
(
A
d
d
r
e
s
s
0
0
1
A
1
6
)
8
-
b
i
t
r
e
a
d
i
n
g
(
R
e
a
d
o
n
l
y
a
d
d
r
e
s
s
0
0
1
B
1
6
)
(
A
d
d
r
e
s
s
0
0
1
B
1
6
)
b
0
b7 b
0
b
1
* V
REF
input switch bit
b
9
b8 b7 b
6
b
5
b4 b3 b
2
b7 b
0
b
9
b
8b
7b
6
b
5
b
4b
3b
2
b
7b
0
*
(
h
i
g
h
-
o
r
d
e
r
)
(
l
o
w
-
o
r
d
e
r
)
N
o
t
e
:
T
h
e
b
i
t
5
t
o
b
i
t
1
o
f
a
d
d
r
e
s
s
0
0
1
A
1
6
b
e
c
o
m
e
“
0
”
a
t
r
e
a
d
i
n
g
.
A
l
s
o
,
b
i
t
0
i
s
u
n
d
e
f
i
n
e
d
a
t
r
e
a
d
i
n
g
.
1: ON
0
:
O
N
o
n
l
y
d
u
r
i
n
g
A
-
D
c
o
n
v
e
r
s
i
o
n
Rev.2.00 May 28, 2004 page 36 of 100
38C2 Group (A Version)
LCD DRIVE CONTROL CIRCUIT
The 38C2 group has the built-in Liquid Crystal Display (LCD) drive
control circuit consisting of the following.
•LCD display RAM
•Segment output disable register
•LCD mode register
•Selector
•Timing controller
•Common driver
•Segment driver
•Bias control circuit
A maximum of 24 segment output pins and 4 common output pins
can be used.
Up to 96 pixels can be controlled for an LCD display. When the LCD
enable bit is set to “1” after data is set in the LCD mode register, the
Fig. 32 Structure of LCD related registers
segment output disable register, and the LCD display RAM, the LCD
drive control circuit starts reading the display data automatically, per-
forms the bias control and the duty ratio control, and displays the
data on the LCD panel.
Table 8 Maximum number of display pixels at each duty ratio
Duty ratio
2
3
4
Maximum number of display pixels
48 dots
or 8 segment LCD 6 digits
72 dots
or 8 segment LCD 9 digits
96 dots
or 8 segment LCD 12 digits
Segment output disable bit 0
0 : Segment output SEG
0
1 : Output port P0
0
Segment output disable bit 1
0 : Segment output SEG
1
1 : Output port P0
1
Segment output disable bit 2
0 : Segment output SEG
2
1 : Output port P0
2
Segment output disable bit 3
0 : Segment output SEG
3
1 : Output port P0
3
Segment output disable bit 4
0 : Segment output SEG
4
1 : Output port P0
4
Segment output disable bit 5
0 : Segment output SEG
5
1 : Output port P0
5
Segment output disable bit 6
0 : Segment output SEG
6
1 : Output port P0
6
Segment output disable bit 7
0 : Segment output SEG
7
1 : Output port P0
7
Segment output disable register 0
(SEG0 : address 0FF8
16
)
b7 b0 LCD mode register
(LM : address 0039
16
)
Duty ratio selection bits
b1 b0
0 0 : Not used
0 1 : 2 (use COM
0
,COM
1
)
1 0 : 3 (use COM
0
–COM
2
)
1 1 : 4 (use COM
0
–COM
3
)
Bias control bit
0 : 1/3 bias
1 : 1/2 bias
LCD enable bit
0 : LCD OFF
1 : LCD ON
LCD drive timing selection bit
0 : Type A
1 : Type B
LCD circuit divider division ratio selection bits
b6 b5
0 0 : Clock input
0 1 : 2 division of clock input
1 0 : 4 division of clock input
1 1 : 8 division of clock input
LCDCK count source selection bit (Note)
0 : f(X
CIN
)/32
1 : f(X
IN
)/8192 (f(X
CIN
)/8192 in low-speed mode)
Note : LCDCK is a clock for an LCD timing controller.
b7 b0
Segment output disable bit 8
0 : Segment output SEG
8
1 : Output port P1
0
Segment output disable bit 9
0 : Segment output SEG
9
1 : Output port P1
1
Segment output disable bit 10
0 : Segment output SEG
10
1 : Output port P1
2
Segment output disable bit 11
0 : Segment output SEG
11
1 : Output port P1
3
Segment output disable bit 12
0 : Segment output SEG
12
1 : Output port P1
4
Segment output disable bit 13
0 : Segment output SEG
13
1 : Output port P1
5
Segment output disable bit 14
0 : Segment output SEG
14
1 : Output port P1
6
Segment output disable bit 15
0 : Segment output SEG
15
1 : Output port P1
7
Segment output disable register 1
(SEG1 : address 0FF9
16
)
b7 b0
Segment output disable bit 16
0 : Output port P2
0
1 : Segment output SEG
16
Segment output disable bit 17
0 : Output port P2
1
1 : Segment output SEG
17
Segment output disable bit 18
0 : Output port P2
2
1 : Segment output SEG
18
Segment output disable bit 19
0 : Output port P2
3
1 : Segment output SEG
19
Segment output disable bit 20
0 : Output port P2
4
1 : Segment output SEG
20
Segment output disable bit 21
0 : Output port P2
5
1 : Segment output SEG
21
Segment output disable bit 22
0 : Output port P2
6
1 : Segment output SEG
22
Segment output disable bit 23
0 : Output port P2
7
1 : Segment output SEG
23
Segment output disable register 2
(SEG2 : address 0FFA
16
)
b7 b0
Notes 1: Only pins set to output ports by the direction register can be controlled to switch
to output ports or segment outputs by the segment output disable register.
2: When the VL pin input selection bit (VLSEL) of the LCD power control register
(address 0038
16
) is “1”, settings of the segment output disable bit 22 and segment
output disable bit 23 are invalid.
Rev.2.00 May 28, 2004 page 37 of 100
38C2 Group (A Version)
Fig. 33 Block diagram of LCD controller/driver
f
(
X
C
I
N
)
/
3
2
f
(
X
I
N
)
/
8
1
9
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Rev.2.00 May 28, 2004 page 38 of 100
38C2 Group (A Version)
Duty
ratio
2
3
4
Voltage value
VL3=VLCD
VL2=2/3 VLCD
VL1=1/3 VLCD
VL3=VLCD
VL2=VL1=1/2 VLCD
Bias Control and Applied V oltage to LCD Power
Input Pins
When the voltage is applied from the LCD power input pins (VL1–
VL3), set the VL pin input selection bit (bit 5 of the LCD power control
register) and VL3 connection bit (bit 6 of LCD power control register)
to “1”, apply the voltage value shown in Table 9 according to the bias
value. In this case, SEG22 pin and SEG23 pin cannot be used.
Select a bias value by the bias control bit (bit 2 of the LCD mode
register).
Fig. 34 Example of circuit at each bias (at external power input)
Table 9 Bias control and applied voltage to VL1–VL3
Bias value
1/3 bias
1/2 bias
Note : VLCD is the maximum value of supplied voltage for the LCD panel.
Table 10 Duty ratio control and common pins used
Note: Unused common pin outputs the unselected waveform.
Common pins used
COM0, COM1
COM0–COM2
COM0–COM3
Bit 1
0
1
1
Bit 0
1
0
1
Duty ratio selection bits
Common Pin and Duty Ratio Control
The common pins (COM0–COM3) to be used are determined by duty
ratio. Select duty ratio by the duty ratio selection bits (bits 0 and 1 of
the LCD mode register). When reset is released, VCC voltage is out-
put from the common pin.
Segment Signal Output Pin
The segment signal output pins (SEG0–SEG23) are shared with ports
P0–P2. When these pins are used as the segment signal output pins,
set the direction registers of the corresponding pins to “1”, and set
the segment output disable register to “0”.
Also, these pins are set to the input port after reset, the VCC voltage
is output by the pull-up resistor.
V
L
3
V
L
2
V
L
1
R4
R5
R
4
=
R
5
Contrast adjust
1
/
2
b
i
a
s
V
L
3
V
L
2
V
L
1
Contrast adjust
R1
R2
R3
R
1
=
R
2
=
R
3
1
/
3
b
i
a
s
Rev.2.00 May 28, 2004 page 39 of 100
38C2 Group (A Version)
LCD Power Circuit
The LCD power circuit has the dividing resistor for LCD power which
can be connected/disconnected with the LCD power control register .
Fig. 35 Structure of LCD power control register
Fig. 36 VL block diagram
V
L3
P2
7
/SEG
23
/
V
L2
P
2
6
/
S
E
G
2
2
/
V
L
1
Vcc
L
C
D
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r
(
b
i
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2
)
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(
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r
(
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)
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(
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i
t
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)
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C
D
i
n
t
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r
n
a
l
V
L
3
L
C
D
i
n
t
e
r
n
a
l
V
L
2
L
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D
i
n
t
e
r
n
a
l
V
L
1
Di
v
idi
ng res
i
stor
f
or
LCD
power contro
l
bi
t
(LCDRON)
0 : Internal dividing resistor disconnected from LCD power circuit
1 : Internal dividing resistor connected to LCD power circuit
Dividing resistor for LCD power selection bits (RSEL)
b3 b2
1 0 : Larger resistor
0 1 :
0 0 :
1 1 : Smaller resistor
Not used (retu rn “0” when read)
(Do not write to “1”)
VL pin input selection bit (VLSEL)
0 : Input invalid
1 : VL input function valid
V
L3
connection bit
0 : Connect LCD internal V
L3
to V
CC
1 : Connect LCD internal V
L3
to V
L3
pin
Not used (retu rn “0” when read)
(Do not write to “1”)
LCD
power c ontro
l
reg
i
ster
(VLCON : address 0038
16
)
b
7
b
0
N
o
t
e
s
1
:
W
h
e
n
v
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t
a
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p
p
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d
t
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1
t
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3
b
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t
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x
t
e
r
n
a
l
r
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s
i
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t
o
r
,
w
r
i
t
e
“
1
0
2
”
t
o
d
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v
i
d
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r
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s
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p
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b
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s
.
2
: S
e
t
t
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g
t
o
t
h
e
V
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p
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p
u
t
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l
e
c
t
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o
n
b
i
t
(
V
L
S
E
L
)
=
“
1
”
h
a
s
t
h
e
m
o
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t
p
r
i
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r
i
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t
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g
t
o
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h
e
p
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d
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g
i
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t
e
r
(
a
d
d
r
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s
s
0
0
0
5
)
a
n
d
s
e
g
m
e
n
t
o
u
t
p
u
t
d
i
s
a
b
l
e
r
e
g
i
s
t
e
r
2
(
a
d
d
r
e
s
s
0
F
F
A
)
.
3
:
W
h
e
n
t
h
e
L
C
D
d
r
i
v
e
c
o
n
t
r
o
l
c
i
r
c
u
i
t
i
s
u
s
e
d
a
t
V
L
3
=
V
C
C
,
a
p
p
l
y
V
C
C
t
o
V
L
3
p
i
n
a
n
d
w
r
i
t
e
“
1
”
t
o
V
L
3
c
o
n
n
e
c
t
i
o
n
b
i
t
.
1
616
Rev.2.00 May 28, 2004 page 40 of 100
38C2 Group (A Version)
(frequency of count source for LCDCK)
(divider division ratio for LCD)
f(LCDCK)=
f(LCDCK)
duty ratio
Frame frequency=
Fig. 37 LCD display RAM map
LCD Display RAM
The 12-byte area of address 004016 to 004B16 is the designated
RAM for the LCD display. When “1” is written to these addresses, the
corresponding segments of the LCD display panel are turned on.
LCD Drive Timing
For the LCD drive timing, type A or type B can be selected.
The LCD drive timing is selected by the timing selection bit (bit 4 of
LCD mode register).
T ype A is selected by setting the LCD drive timing selection bit to “0”,
type B is selected by setting the bit to “1”. Type A is selected after
reset.
The LCDCK timing frequency (LCD drive timing) is generated inter-
nally and the frame frequency can be determined with the following
equation;
■ Note
(1) When the STP instruction is executed, the following bits are set
to “0”;
• LCD enable bit (bit 3 of LCD mode register)
• Bits other than bit 6 of the LCD power control register.
(2) When the voltage is applied to VL1 to VL3 by using the external
resistor, write “102” to dividing resistor for LCD power selection
bits (RSEL) of the LCD power control register (address 003816).
(3) When the LCD drive control circuit is used at VL3 = VCC, apply
VCC to VL3 pin and write “1” to VL3 connection bit of the LCD
power control register (address 003816).
COM3 COM2 COM1 COM0
B
i
t
Address 7 6543210
0
0
4
01
6
0
0
4
11
6
0
0
4
21
6
0
0
4
31
6
0
0
4
41
6
0
0
4
51
6
0
0
4
61
6
0
0
4
71
6
0
0
4
81
6
0
0
4
91
6
0
0
4
A1
6
0
0
4
B1
6
SEG1
SEG3
SEG5
SEG7
SEG9
SEG11
SEG13
SEG15
SEG17
SEG19
SEG21
SEG23
S
E
G0
S
E
G2
S
E
G4
S
E
G6
S
E
G8
S
E
G1
0
S
E
G1
2
S
E
G1
4
S
E
G1
6
S
E
G1
8
S
E
G2
0
S
E
G2
2
C
O
M3
C
O
M2
C
O
M1
C
O
M0
Rev.2.00 May 28, 2004 page 41 of 100
38C2 Group (A Version)
Fig. 38 LCD drive waveform (1/2 bias, type A)
1
/
4
d
u
t
yV
o
l
t
a
g
e
l
e
v
e
l
V
L
3
V
L
2
=
V
L
1
V
SS
V
L3
V
SS
C
O
M
0
C
O
M
1
C
O
M
2
C
O
M
3
SEG
0
O
F
FO
N O
F
FO
N
C
O
M
3
COM
2
COM
1
COM
0
C
O
M
3
COM
2
COM
1
COM
0
1
/
3
d
u
t
y
V
L3
V
L
2
=
V
L
1
V
S
S
V
L
3
V
S
S
O
F
FO
N O
NOFF ON O
F
F
1/2 du ty
COM
0
C
O
M
1
C
O
M
2
SEG
0
C
O
M
0
C
O
M
1
SEG
0
V
L3
V
L
2
=
V
L
1
V
S
S
V
L
3
V
S
S
O
F
FO
N O
F
FO
NOFFON OFFO
N
COM
0
COM
2
COM
1
COM
0
COM
2
COM
1
COM
0
COM
2
C
O
M
1
C
O
M
0
COM
1
C
O
M
0
C
O
M
1
COM
0
C
O
M
1
C
O
M
0
I
n
t
e
r
n
a
l
s
i
g
n
a
l
L
C
D
C
K
t
i
m
i
n
g
L
C
D
L
C
D
LCD
Rev.2.00 May 28, 2004 page 42 of 100
38C2 Group (A Version)
Fig. 39 LCD drive waveform (1/3 bias, type A)
V
L
3
V
S
S
COM
0
C
O
M
1
C
O
M
2
C
O
M
3
S
E
G
0
C
O
M
3
COM
2
COM
1
COM
0
C
O
M
3
COM
2
COM
1
COM
0
C
O
M
0
COM
1
C
O
M
2
SEG
0
COM
0
C
O
M
1
S
E
G
0
V
L3
V
L2
V
SS
V
L1
V
L3
V
L2
V
SS
V
L1
V
L3
V
SS
V
L3
V
L2
V
SS
V
L1
V
L3
V
S
S
C
O
M
0
C
O
M
2
C
O
M
1
COM
0
C
O
M
2
C
O
M
1
COM
0
COM
2
C
O
M
1
C
O
M
0
C
O
M
1
COM
0
C
O
M
1
C
O
M
0
COM
1
COM
0
1/4 du ty V
o
l
t
a
g
e
l
e
v
e
l
O
F
FO
NOFFO
N
1
/
3
d
u
t
y
O
F
FO
NO
NOFF O
NOFF
1/2 du ty
OFFON OFFON OFFON OFFON
I
n
t
e
r
n
a
l
s
i
g
n
a
l
L
C
D
C
K
t
i
m
i
n
g
L
C
D
L
C
D
LCD
Rev.2.00 May 28, 2004 page 43 of 100
38C2 Group (A Version)
Fig. 40 LCD drive waveform (1/2 bias, type B)
C
O
M
0
C
O
M
1
C
O
M
2
C
O
M
3
SEG
0
COM
3
COM
2
COM
1
COM
0
COM
3
COM
2
COM
1
COM
0
COM
0
C
O
M
1
COM
2
SEG
0
C
O
M
0
C
O
M
1
SEG
0
V
L
3
V
L
2
=
V
L
1
V
S
S
COM
0
COM
2
COM
1
COM
0
COM
2
COM
1
COM
0
COM
2
COM
1
C
O
M
0
C
O
M
1
C
O
M
0
C
O
M
1
COM
0
C
O
M
1
COM
0
1 frame 1
f
r
a
m
e
1 frame 1 frame 1 frame 1 frame
1 frame 1
f
r
a
m
e
V
L
3
V
S
S
V
L
3
V
S
S
V
L3
V
S
S
V
L
3
V
L
2
=
V
L
1
V
S
S
V
L
3
V
L2=
V
L1
V
SS
1
/
4
d
u
t
yV
o
l
t
a
g
e
l
e
v
e
l
OFF ON OFF ON
1/3 du ty
O
F
FO
NO
NO
F
FO
NO
F
F
1
/
2
d
u
t
y
OFFON OFFON OFFON OFFON
I
n
t
e
r
n
a
l
s
i
g
n
a
l
L
C
D
C
K
t
i
m
i
n
g
LCD
LCD
L
C
D
Rev.2.00 May 28, 2004 page 44 of 100
38C2 Group (A Version)
Fig. 41 LCD drive waveform (1/3 bias, type B)
C
O
M
0
C
O
M
1
C
O
M
2
C
O
M
3
SEG
0
C
O
M
3
COM
2
COM
1
COM
0
C
O
M
3
COM
2
COM
1
COM
0
COM
0
C
O
M
1
COM
2
SEG
0
C
O
M
0
C
O
M
1
SEG
0
V
L
3
V
L
2
V
S
S
V
L
1
V
L
3
V
L
2
V
S
S
V
L1
V
L
3
V
L2
V
S
S
V
L
1
COM
0
COM
2
COM
1
COM
0
COM
2
COM
1
COM
0
COM
2
C
O
M
1
C
O
M
0
C
O
M
1
C
O
M
0
C
O
M
1
C
O
M
0
C
O
M
1
C
O
M
0
V
L
3
V
L
2
V
S
S
V
L1
V
L
3
V
L2
V
S
S
V
L
1
V
L3
V
L
2
V
S
S
V
L
1
1
f
r
a
m
e 1
f
r
a
m
e
1 frame 1 frame 1 frame 1 frame
1
f
r
a
m
e 1
f
r
a
m
e
1/4 du ty Voltage lev el
O
F
FO
NO
F
FO
N
1
/
3
d
u
t
y
OFFON ON OFF ON OFF
1/2 du ty
O
F
FO
NOFFO
NOFFON O
F
FON
I
n
t
e
r
n
a
l
s
i
g
n
a
l
L
C
D
C
K
t
i
m
i
n
g
L
C
D
L
C
D
L
C
D
Rev.2.00 May 28, 2004 page 45 of 100
38C2 Group (A Version)
WATCHDOG TIMER
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example, because
of a software run-away). The watchdog timer consists of an 8-bit
counter.
Initial Value of Watchdog Timer
At reset or writing to the watchdog timer control register , each watch-
dog timer is set to “FF16.” Instructions such as STA, LDM and CLB to
generate the write signals can be used.
The written data in bits 0 to 5 are not valid, and the above values are
set.
Standard Operation of Watchdog Timer
The watchdog timer is in the stop state at reset and the watchdog
timer starts to count down by writing an optional value in the watch-
dog timer control register . An internal reset occurs at an underflow of
the watchdog timer. Then, reset is released after the reset release
time is elapsed, the program starts from the reset vector address.
Normally, writing to the watchdog timer control register before an
underflow of the watchdog timer is programmed. If writing to the watch-
dog control register is not executed, the watchdog timer does not
operate.
Fig. 44 Timing diagram of reset output
When reading the watchdog timer control register is executed, the
contents of the high-order 6-bit counter and the STP instruction dis-
able bit (bit 6), and the count source selection bit (bit 7) are read out.
When the STP instruction disable bit is “0”, the STP instruction is
valid. The STP instruction is disabled by writing to “1” to this bit. In
this time, when the STP instruction is executed, it is handled as the
undefined instruction, the internal reset occurs. This bit cannot be
set to “0” by program. This bit is “0” after reset.
The time until the underflow of the watchdog timer control register
after writing to the watchdog timer control register is executed is as
follows (when the bit 7 of the watchdog timer control register is “0”) ;
• at frequency/2/4/8 mode (f(XIN)) = 8 MHz): 32.768 ms
• at low-speed mode (f(XCIN) = 32 KHz): 8.19s
■ Note
The watchdog timer continues to count even during the wait time set
by timer 1 and timer 2 to release the stop state and in the wait mode.
Accordingly, do not underflow the watchdog timer in this time.
Fig. 42 Block diagram of Watchdog timer
Fig. 43 Structure of Watchdog timer control register
b0
STP instruction disable bit
0: STP instruction enabled
1: STP instruction disabled
Watchdog timer count source selection bit
0: 1/1024 of system clock
1: 1/4 of system clock
Watchdog timer H (for read-out of high-order 6 bit)
“FF
16
” is set to watchdog timer by writing to these bits.
Watchdog timer control register
(WDTCON : address 0037
16
)
b7
I
n
t
e
r
n
a
l
r
e
s
e
t
s
i
g
n
a
l
W
a
t
c
h
d
o
g
t
i
m
e
r
d
e
t
e
c
t
e
d
Approx.
32
msec
(at f(X
IN
)=8MH
Z
)
f
(
X
I
N
)
X
IN
X
CIN
Sy
s
t
e
m
c
l
o
c
k
c
o
n
t
r
o
l
b
i
t
(
b
i
t
6
)
1
/
1
0
2
4
Undefined instruction
Reset
R
E
S
E
TW
a
i
t
u
n
t
i
l
r
e
s
e
t
r
e
l
e
a
s
e
1
/
4
D
a
t
a
b
u
s
W
a
t
c
h
d
o
g
t
i
m
e
r
H
c
o
u
n
t
s
o
u
r
c
e
s
e
l
e
c
t
i
o
n
b
i
t
R
e
s
e
t
c
i
r
c
u
i
t
S
T
P
i
n
s
t
r
u
c
t
i
o
n
d
i
s
a
b
l
e
b
i
t
W
a
t
c
h
d
o
g
t
i
m
e
r
H
(
6
)
I
n
t
e
r
n
a
l
r
e
s
e
t
STP instruction
Watchdog timer
L (2)
“FF
16
” is set when
watchdog timer
control register is
writte n to .
“
0
”
“
1
”
“
0
”
“
1
”
Rev.2.00 May 28, 2004 page 46 of 100
38C2 Group (A Version)
CLOCK OUTPUT FUNCTION
A system clock φ can be output from I/O port P36.The triple function
of I/O port, timer 2 output function and system clock φ output function
is performed by the clock output control register (address 001816)
and the timer 2 output selection bit of the timer 12 mode register
(address 002516).
In order to output a system clock φ from I/O port P36, set the timer 2
output selection bit and bit 0 of the clock output control register to “1”.
When the clock output function is selected, a clock is output while
the direction register of port P36 is set to the output mode.
P36 is switched to the port output or the output (timer 2 output and
the clock output) except port at the cycle after the timer 2 output
control bit is switched.
Fig. 46 Block diagram of Clock output function
Fig. 45 Structure of clock output control register
T
i
m
e
r
2
l
a
t
c
h
(
8
)
T
i
m
e
r
2
(
8
)1/2 Q
Q
S
T
T2OUT output
ed ge s witch bit
T
i
m
e
r
2
o
u
t
p
u
t
c
o
n
t
r
o
l
b
i
t
P36 latch
Timer 2 out
p
ut selection bit
P36 direction register
P3
6
/T
2OUT
/φ
S
y
s
t
e
m
c
l
o
c
k
φ
P
36
c
l
o
c
k
o
u
t
p
u
t
c
o
n
t
r
o
l
b
i
t
b7 b0 T
i
m
e
r
1
2
m
o
d
e
r
e
g
i
s
t
e
r
(
a
d
d
r
e
s
s
0
0
2
51
6)
T
1
2
M
Tim er 2 output se lec tio n bit
0: I/O po rt
1: Timer 2 output
“0”
“1”“0”
“1”
b
0
N
o
t
u
s
e
d
(
r
e
t
u
r
n
s
“
0
”
w
h
e
n
r
e
a
d
)
(
D
o
n
o
t
w
r
i
t
e
“
1
”
t
o
t
h
e
s
e
b
i
t
s
.
)
P
3
6
c
l
o
c
k
o
u
t
p
u
t
c
o
n
t
r
o
l
b
i
t
0
:
T
i
m
e
r
2
o
u
t
p
u
t
1
:
S
y
s
t
e
m
c
l
o
c
k
φ
o
u
t
p
u
t
C
l
o
c
k
o
u
t
p
u
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
(
C
K
O
U
T
:
a
d
d
r
e
s
s
0
0
1
8
1
6
)
b
7
Rev.2.00 May 28, 2004 page 47 of 100
38C2 Group (A Version)
RESET CIRCUIT
To reset the microcomputer, RESET pin should be held at an “L”
level for 2 µs or more. Then the RESET pin is returned to an “H” level
(the power source voltage should be between VCC (min.) and 5.5 V,
and the quartz-crystal oscillator should be stable), reset is released.
After the reset is completed, the program starts from the address
contained in address FFFD16 (high-order byte) and address FFFC16
(low-order byte). Make sure that the reset input voltage meets VIL
spec. when a power source voltage passes VCC (min.).
Fig. 48 Reset sequence
Fig. 47 Reset circuit example
VIL spec.
0V
0V
Poweron
V
CC
RESET
V
CC
RESET
Power source
voltage detection
circuit
Power source
voltage
Reset input
voltage
RESET
Internal
reset
Address
Data
SYNC
φ
X
IN
FFFC FFFD AD
H,
AD
L
AD
L
????
X
IN
: about 8000 cycles
Note
Reset address from
vector table
1: The frequency relation of f(X
IN
) and f(φ) is f(X
IN
) = 8 • f(φ).
2: The question marks (?) indicate an undefined state that depends on the previous state.
AD
H
Rev.2.00 May 28, 2004 page 48 of 100
38C2 Group (A Version)
Fig. 49 Internal status at reset
F
F1
6
F
F1
6
0
01
6
002A16
0
0
2
B1
6
0
0
2
C1
6
003716
003816
003A16
X: Not fi x e d
Since the initial values for other than above mentio ned regi ste rs and
RAM contents are indefinite at reset, they must be set.
A
d
d
r
e
s
s
R
e
g
i
s
t
e
r
c
o
n
t
e
n
t
sAddress Register contents
0
01
6
0016
0
01
6
0
01
6
0
01
6
0
01
6
0
01
6
0
01
6
0
01
6
0
01
6
0
01
6
0
01
6
0016
0
01
6
0016
F
F1
6
F
F1
6
0
01
6
0
0
0
01
6
0
0
0
11
6
0
0
0
21
6
0
0
0
41
6
0
0
0
51
6
0
0
0
61
6
0
0
0
81
6
0
0
0
91
6
0
0
0
A1
6
0
0
0
B1
6
000C16
0
0
0
D1
6
0
0
1
81
6
001916
0
0
1
D1
6
001F16
0
0
2
01
6
002116
0
0
2
21
6
002316
0
0
2
41
6
002516
002816
Compare register (low-orde r)
P
o
r
t
P
0
P
o
r
t
P
0
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
Port P1
Port P2
P
o
r
t
P
2
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
o
r
t
P
3
P
o
r
t
P
4
P
o
r
t
P
4
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
o
r
t
P
5
P
o
r
t
P
5
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
o
r
t
P
6
Port P6 direction register
Clock output control register
A
-
D
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
Serial I/O1 status register
T
i
m
e
r
2
Timer 3
T
i
m
e
r
4
P
W
M
0
1
r
e
g
i
s
t
e
r
T
i
m
e
r
1
2
m
o
d
e
r
e
g
i
s
t
e
r
T
i
m
e
r
3
4
m
o
d
e
r
e
g
i
s
t
e
r
C
o
m
p
a
r
e
r
e
g
i
s
t
e
r
(
h
i
g
h
-
o
r
d
e
r
)
T
i
m
e
r
X
(
l
o
w
-
o
r
d
e
r
)
Timer X (high-order)
(
1
)
(
2
)
(
3
)
(5)
(
6
)
(
7
)
(
8
)
(
9
)
(
1
0
)
(
1
1
)
(
1
2
)
(13)
(
1
4
)
(
1
5
)
(
1
6
)
(
1
7
)
(18)
(
1
9
)
(20)
(
2
1
)
(22)
(
2
3
)
(24)
(
2
5
)
(
2
6
)
(27)
(
2
8
)
(
2
9
)
0016
002916
T
i
m
e
r
X
(
e
x
t
e
n
s
i
o
n
)
(30)
(
3
2
)
(
3
3
)
(35)
(36)
(37)
(38)
Timer Y (low-order)
T
i
m
e
r
Y
(
h
i
g
h
-
o
r
d
e
r
)
Timer X mode register
W
a
t
c
h
d
o
g
t
i
m
e
r
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
L
C
D
p
o
w
e
r
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
L
C
D
m
o
d
e
r
e
g
i
s
t
e
r
I
n
t
e
r
r
u
p
t
e
d
g
e
s
e
l
e
c
t
i
o
n
r
e
g
i
s
t
e
r
0
01
6
0
01
6
0
01
6
003B16
003C16
003F16
0FE016
0FE116
0FE316
0FE416
(39)
(40)
(43)
(44)
(45)
(46)
(47)
C
P
U
m
o
d
e
r
e
g
i
s
t
e
r
I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
r
e
g
i
s
t
e
r
1
I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
r
e
g
i
s
t
e
r
2
I
n
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
1
I
n
t
e
r
r
u
p
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
2
0
01
6
0
01
6
0
01
6
S
e
r
i
a
l
I
/
O
2
s
t
a
t
u
s
r
e
g
i
s
t
e
r
Timer 1
(
3
1
)
F
F
F
C
1
6
c
o
n
t
e
n
t
s
(PS)
(
P
CH)
(PCL)
P
r
o
g
r
a
m
c
o
u
n
t
e
r
P
r
o
c
e
s
s
o
r
s
t
a
t
u
s
r
e
g
i
s
t
e
r
F
F
F
D
1
6
c
o
n
t
e
n
t
s
1
✕
003916
0
81
6
FF16
0
11
6
F
F1
6
FF16
0
01
6
0
01
6
0
01
6
✕✕✕✕✕✕
0
01
6
0
0
0
31
6
P
o
r
t
P
1
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
(
4
)
003E16
(41)
(42)
0
01
6
0
01
6
003D16
0016
0
01
6
0016
0FF016
0FF116
0FF216
0FF316
(48)
(49)
(50)
(51) 0016
0016
0FF416
0FF516
0FF616
(52)
(53)
(54)
0
01
6
0
01
6
0
01
6
FF16
0FF716
0FF816
0FF916
(55)
(56)
(57) F
F1
6
F
F1
6
0FFA16
0FFB16
0FFE16
(58)
(59)
(60)
0
01
6
(61)
(62)
P
o
r
t
P
3
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r0
0
0
71
6
0
0
2
61
6
0
0
2
D1
6
0
0
2
E1
6
0
0
2
F1
6
100000 00
100000 00
0
01
6
(
3
4
)Timer Y mode register 0
0
3
01
6
S
e
r
i
a
l
I
/
O
1
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
U
A
R
T1
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
S
e
r
i
a
l
I
/
O
2
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
UART2 control register
Oscillation output control regist er
P
U
L
L
r
e
g
i
s
t
e
r
K
e
y
i
n
p
u
t
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
T
i
m
e
r
1
2
3
4
m
o
d
e
r
e
g
i
s
t
e
r
T
i
m
e
r
X
c
o
n
t
r
o
l
r
e
g
i
s
t
e
r
T
i
m
e
r
1
2
f
r
e
q
u
e
n
c
y
d
i
v
i
s
i
o
n
s
e
l
e
c
t
i
o
n
r
e
g
i
s
t
e
r
Timer 34 frequency di v is ion selec tion register
T
i
m
e
r
X
Y
f
r
e
q
u
e
n
c
y
d
i
v
i
s
i
o
n
s
e
l
e
c
t
i
o
n
r
e
g
i
s
t
e
r
Segment output disable regist er 0
Segment output disable regist er 1
Segment output disable regist er 2
Timer Y mode register 2
Flash me mo ry c o ntro l register
0011 11 11
010010 00
0
01
6
111000 00
111000 00
1
✕✕✕
0
000
Rev.2.00 May 28, 2004 page 49 of 100
38C2 Group (A Version)
CLOCK GENERATING CIRCUIT
The 38C2 group has two built-in oscillation circuits; main clock XIN–
XOUT and sub-clock XCIN–XCOUT. An oscillation circuit can be formed
by connecting a resonator between XIN and XOUT (XCIN and XCOUT).
Use the circuit constants in accordance with the resonator
manufacturer’s recommended values. No external resistor is needed
between XIN and XOUT since a feedback resistor exists on-chip. How-
ever, an external feedback resistor is needed between XCIN and
XCOUT.
To supply a clock signal externally, input it to the XIN pin and make
the XOUT pin open. The sub clock XCIN-XCOUT oscillation circuit can-
not directly input clocks that are externally generated. Accordingly,
be sure to cause an external resonator to oscillate.
Immediately after poweron, only the XIN oscillation circuit starts os-
cillating, and XCIN and XCOUT pins function as I/O ports.
Frequency Control
(1) Frequency/8 Mode
The system clock φ is the frequency of XIN divided by 8. After reset is
released, this mode is selected.
(2) Frequency/4 Mode
The system clock φ is the frequency of XIN divided by 4.
(3) Frequency/2 Mode
The system clock φ is the frequency of XIN divided by 2.
(4) Low-speed Mode
The system clock φ is the frequency of XCIN divided by 2. In the low-
speed mode, the low-power dissipation operation can be performed
when the main clock XIN is stopped by setting the bit 7 of the CPU
mode register to “0”. In this case, when main clock XIN oscillation is
restarted, generate the wait time until the oscillation is stable by pro-
gram after the bit 7 of the CPU mode register is set to “1”.
Fig. 50 Ceramic resonator circuit Fig. 51 External clock input circuit
XOUT
CIN COUT
CCIN CCOUT
Rf
XCIN XCOUT XIN
Rd
(Note)
Note: An external feed-back resistor may be
needed depending on conditions.
■ Notes on Clock Generating Circuit
If you switch the mode between frequency/2/4, or 8 and low-speed,
stabilize both XIN and XCIN oscillations. The suf ficient time is required
for the sub clock to stabilize, especially immediately after power on
and at returning from stop mode. When switching the mode, set the
frequency in the condition that f(XIN) > 3•f(XCIN).
Oscillation Control
(1) Stop Mode
If the STP instruction is executed, the system clock φ stops at an “H”
level, and main clock and sub-clock oscillators stop.
In this time, values set previously to timer 1 latch and timer 2 latch
are loaded automatically to timer 1 and timer 2. Set the values to
generate the wait time required for oscillation stabilization to timer 1
latch and timer 2 latch (low-order 8 bits of timer 1 and high-order 8
bits of timer 2) before the STP instruction.
The frequency divider for timer 1 is used for the timer 1 count source,
and the output of timer 1 is forcibly connected to timer 2. In this time,
bits 0 to 5 of the timer 12 mode register are cleared to “0”.
The values of the timer 12 frequency divider selection register are
not changed.
Set the interrupt enable bits of the timer 1 and timer 2 to disabled
(“0”) before executing the STP instruction.
Oscillator restarts when reset occurs or an interrupt request is re-
ceived, but the system clock φ is not supplied to the CPU until timer 2
underflows. This allows time for the clock circuit oscillation to stabi-
lize.
(2) Wait Mode
If the WIT instruction is executed, only the system clock φ stops at an
“H” state. The states of main clock and sub clock are the same as the
state before executing the WIT instruction, and oscillation does not
stop. Since supply of system clock φ is started immediately after the
interrupt is received, the instruction can be executed immediately.
X
CIN
X
COUT
X
IN
X
OUT
V
CC
V
S
S
Open
E
x
t
e
r
n
a
l
o
s
c
i
l
l
a
t
i
o
n
c
i
r
c
u
i
t
R
d
Rf
C
C
O
U
T
C
CIN
Rev.2.00 May 28, 2004 page 50 of 100
38C2 Group (A Version)
Fig. 52 Clock generating circuit block diagram
S
R
Q
S
R
QS
R
Q
X
I
N
X
O
U
T
1
/
2
1
/
21/2
1
/
2
P
6
1
/
X
C
I
N
P
6
2
/
X
C
O
U
T
Timer 1 count source
selection bits
“
0
1
”
“
0
0
”
“
0
1
”
“
0
0
”
“
0
0
”
“
1
0
”
Timer 2 count source
selection bits
“
0
0
,
1
0
,
1
1
”
“01”
“
0
1
,
1
0
,
1
1
”
“
0
0
”
“
1
0
”
“
0
0
,
1
0
”
“00,10”
“01,11”
“
0
1
,
1
1
”
W
I
T
i
n
s
t
r
u
c
t
i
o
n
System clock φ
S
T
P
i
n
s
t
r
u
c
t
i
o
n
T
i
m
e
r
2
T
i
m
e
r
1
I
n
t
e
r
r
u
p
t
r
e
q
u
e
s
t
Reset
S
y
s
t
e
m
c
l
o
c
k
c
o
n
t
r
o
l
b
i
t
s
M
a
i
n
c
l
o
c
k
d
i
v
i
s
i
o
n
r
a
t
i
o
s
e
l
e
c
t
i
o
n
b
i
t
s
I
n
t
e
r
r
u
p
t
d
i
s
a
b
l
e
f
l
a
g
I
S
T
P
i
n
s
t
r
u
c
t
i
o
n
S
y
s
t
e
m
c
l
o
c
k
c
o
n
t
r
o
l
b
i
t
s
S
y
s
t
e
m
c
l
o
c
k
c
o
n
t
r
o
l
b
i
t
s
S
y
s
t
e
m
c
l
o
c
k
c
o
n
t
r
o
l
b
i
t
s
F
r
e
q
u
e
n
c
y
d
i
v
i
d
e
r
f
o
r
T
i
m
e
r
Frequency/8 mode
Frequency/4 mode
Frequency/2 mode
“
0
0
”
“
0
0
,
1
0
,
1
1
”“
0
1
”
S
y
s
t
e
m
c
l
o
c
k
c
o
n
t
r
o
l
b
i
t
s
Rev.2.00 May 28, 2004 page 51 of 100
38C2 Group (A Version)
Fig. 53 State transitions of system clock
XIN oscillation, XCIN stop
CM7=0, CM6=1
F
r
e
q
u
e
n
c
y
/
2
m
o
d
e
S
y
s
t
e
m
c
l
o
c
k
φ
:
f
(
X
I
N
)
/
2
C
M
5
=
1C
M
4
=
0
C
M
7
=
“
0
”
C
M
6
=
“
1
”
L
o
w
-
s
p
e
e
d
m
o
d
e
S
y
s
t
e
m
c
l
o
c
k
φ
:
f
(
XC
I
N)
/
2
XI
N
s
t
o
p
,
XC
I
N
o
s
c
i
l
l
a
t
i
o
n
C
M7=
0
,
C
M6=
0
Low-power dissipation mode
System clock φ : f(X
CIN
)/2
CM
7
=“1”
C
M
7
=
“
0
”
C
M
6
=
“
0
”
S
y
s
t
e
m
c
l
o
c
k
=
M
a
i
n
c
l
o
c
k
f
(
XI
N)
R
e
s
e
t
C
M5
C
M4
:
M
a
i
n
c
l
o
c
k
d
i
v
i
s
i
o
n
r
a
t
i
o
s
e
l
e
c
t
i
o
n
b
i
t
s
0
0
:
XI
N/
8
(
f
r
e
q
u
e
n
c
y
/
8
)
0
1
:
XI
N/
4
(
f
r
e
q
u
e
n
c
y
/
4
)
1
0
:
XI
N/
2
(
f
r
e
q
u
e
n
c
y
/
2
)
1
1
:
N
o
t
a
v
a
i
l
a
b
l
e
C
M7
C
M6
:
S
y
s
t
e
m
c
l
o
c
k
c
o
n
t
r
o
l
b
i
t
s
0
0
:
XI
N
s
t
o
p
,
XC
I
N
o
s
c
i
l
l
a
t
i
o
n
,
s
y
s
t
e
m
c
l
o
c
k
=
XC
I
N
0
1
:
XI
N
o
s
c
i
l
l
a
t
i
o
n
,
XC
I
N
s
t
o
p
,
s
y
s
t
e
m
c
l
o
c
k
=
XI
N
1
0
:
XI
N
o
s
c
i
l
l
a
t
i
o
n
,
XC
I
N
o
s
c
i
l
l
a
t
i
o
n
,
s
y
s
t
e
m
c
l
o
c
k
=
XC
I
N
1
1
:
XI
N
o
s
c
i
l
l
a
t
i
o
n
,
XC
I
N
o
s
c
i
l
l
a
t
i
o
n
,
s
y
s
t
e
m
c
l
o
c
k
=
XI
N
CPU mode regist er
(CPUM : address 003B16)
b7 b4
1: When the mode is switched from frequency/2/4/8 to the low-speed mode, or the opposite is
perform ed, chang e CM7 at first, and then, change CM6 after the oscillation of the changed mode
is stabilized.
2: The all modes can be switched to the stop mode or the wait mode and return to the source mode
when the stop mode or the wait mode is ended.
3: Timer and LCD operate in the wait mode.
4: When the stop mode is ended, a delay time can be set by connecting timer 1 and timer 2.
N
o
t
e
s
F
r
e
q
u
e
n
c
y
/
4
m
o
d
e
S
y
s
t
e
m
c
l
o
c
k
φ
:
f
(
X
I
N
)
/
4
C
M
5
=
0C
M
4
=
1
F
r
e
q
u
e
n
c
y
/
8
m
o
d
e
S
y
s
t
e
m
c
l
o
c
k
φ
:
f
(
X
I
N
)
/
8
C
M
5
=
0C
M
4
=
0
C
M
7
=
“
1
”
XIN oscillation, XCIN oscillation
CM7=1, CM6=1
F
r
e
q
u
e
n
c
y
/
2
m
o
d
e
S
y
s
t
e
m
c
l
o
c
k
φ
:
f
(
X
I
N
)
/
2
C
M
5
=
1C
M
4
=
0
F
r
e
q
u
e
n
c
y
/
8
m
o
d
e
F
r
e
q
u
e
n
c
y
/
4
m
o
d
e
S
y
s
t
e
m
c
l
o
c
k
φ
:
f
(
X
I
N
)
/
4
C
M
5
=
0C
M
4
=
1
S
y
s
t
e
m
c
l
o
c
k
φ
:
f
(
X
I
N
)
/
8
C
M
5
=
0C
M
4
=
0
System clock
= Sub clock f(XCIN)
XI
N
o
s
c
i
l
l
a
t
i
o
n
,
XC
I
N
o
s
c
i
l
l
a
t
i
o
n
C
M7=
1
,
C
M6=
0
Rev.2.00 May 28, 2004 page 52 of 100
38C2 Group (A Version)
Oscillation External Output Function
The 38C2 group has the oscillation external output function to output
the rectangular waveform of the clock obtained by the oscillation cir-
cuits from P41 and P40.
In order to validate the oscillation external output function, set P40 or
P41, or both to the output mode (set the corresponding direction reg-
ister to “1”).
The level of the XCOUT external output signal becomes “H” by the
P40/P41 oscillation output control bits (bits 0 and 1) of the oscillation
output control register (address 0FF016) in the following states;
• the function to output the signal from the XCOUT pin externally is
selected
• the sub clock (XCIN–XCOUT) is in the stop oscillating or stop mode.
Likewise, the level of the XOUT external output signal becomes “H”
by the P40/P41 oscillation output control bits (bits 0 and 1) of the
oscillation output control register (address 0FF016) in the following
states;
• the function to output the signal from the XOUT pin externally is
selected
• the main clock (XIN–XOUT) is in the stop oscillating or stop mode.
Fig. 55 Block diagram of Oscillation output function
Fig. 54 Structure of oscillation output control register
Oscillation output control register
P4
0
/P4
1
oscillation output control bits
b1b0
00: P4
1
, P4
0
= Normal port
01: P4
1
= Normal port, P4
0
= X
OUT
10: P4
1
= Normal port, P4
0
= X
COUT
11: P4
1
= X
COUT
, P4
0
= X
OUT
Not used (return “0” when read)
(Do not write to “1”)
(OSCOUT : address 0FF0
16
)
b7 b0
S
T
P
i
n
s
t
r
u
c
t
i
o
n
S
R
Q
X
I
N
X
O
U
T
Interrupt request
I
n
t
e
r
r
u
p
t
d
i
s
a
b
l
e
f
l
a
g
I
Reset
System clock control bits
P
6
1
/
X
C
I
N
P
6
2
/
X
C
O
U
T
Sy
s
t
e
m
c
l
o
c
k
c
o
n
t
r
o
l
b
i
t
s
“01”
Sy
s
t
e
m
c
l
o
c
k
c
o
n
t
r
o
l
b
i
t
s
P4
1
/O
OUT1
P4
0
/O
OUT0
P
4
1
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
4
0
d
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
O
S
C
O
U
T
c
o
n
t
r
o
l
P
4
1
o
u
t
p
u
t
l
a
t
c
h
P4
0
output latch
Oscillation
output
selection
circuit
“00”, “10”, “11”
“01”
“00”, “10”, “11”
“
0
0
”
“
0
1
”
,
“
1
0
”
,
“
1
1
”
■ Note
When the signal from the XOUT pin or XCOUT pin of the oscillation
circuit is input directly to the circuit except this MCU and used, the
system operation may be unstabilized.
In order to share the oscillation circuit safely, use the clock output
from P40 and P41 by this function for the circuits except this MCU.
Rev.2.00 May 28, 2004 page 53 of 100
38C2 Group (A Version)
NOTES ON PROGRAMMING
Processor Status Register
The contents of the processor status register (PS) after a reset are
undefined, except for the interrupt disable flag (I) which is “1.” After a
reset, initialize flags which affect program execution. In particular, it
is essential to initialize the index X mode (T) and the decimal mode
(D) flags because of their effect on calculations.
Interrupts
The contents of the interrupt request bits do not change immediately
after they have been written. After writing to an interrupt request reg-
ister, execute at least one instruction before performing a BBC or
BBS instruction.
Decimal Calculations
•To calculate in decimal notation, set the decimal mode flag (D) to
“1,” then execute an ADC or SBC instruction. After executing an
ADC or SBC instruction, execute at least one instruction before
executing an SEC, CLC, or CLD instruction.
•In decimal mode, the values of the negative (N), overflow (V), and
zero (Z) flags are invalid.
Timers
• If a value n (between 0 and 255) is written to a timer latch, the
frequency division ratio is 1/(n+1).
• The timers share the one frequency divider to generate the count
source. Accordingly, when each timer starts operating, initializing
the frequency divider is not executed. Therefore, when the frequency
divider is selected for the count source, the delay of the maximum
one cycle of the count source is generated until the timer starts
counting or the waveform is output from timer starts operating. Also,
the count source cannot be checked externally.
Multiplication and Division Instructions
•The index X mode (T) and the decimal mode (D) flags do not affect
the MUL and DIV instruction.
•The execution of these instructions does not change the contents
of the processor status register.
Ports
The contents of the port direction registers cannot be read. The fol-
lowing cannot be used:
•The data transfer instruction (LDA, etc.)
•The operation instruction when the index X mode flag (T) is “1”
•The addressing mode which uses the value of a direction register
as an index
•The bit-test instruction (BBC or BBS, etc.) to a direction register
•The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a
direction register.
Use instructions such as LDM and STA, etc., to set the port direction
registers.
Serial I/O
In clock synchronous serial I/O, if the receive side is using an exter-
nal clock and it is to output the SRDY signal, set the transmit enable
bit, the receive enable bit, and the SRDY output enable bit to “1.”
Serial I/O continues to output the final bit from the TXD pin after trans-
mission is completed.
A-D Converter
The comparator uses internal capacitors whose charge will be lost if
the clock frequency is too low.
Therefore, set the A-D clock frequency to 250 kHz or more.
Also, when the STP instruction is executed during the A-D conver-
sion, the A-D conversion is stopped immediately, the A-D conversion
completion bit is set to “1”, and the interrupt request is generated.
Instruction Execution Time
The instruction execution time is obtained by multiplying the number
of cycles shown in the list of machine instructions by the period of the
internal clock φ.
Rev.2.00 May 28, 2004 page 54 of 100
38C2 Group (A Version)
NOTES ON USE
VL3 pin
When LCD drive control circuit is not used, connect VL3 to VCC.
Countermeasures against noise
(1) Shortest wiring length
➀ Wiring for RESET pin
Make the length of wiring which is connected to the RESET pin as
short as possible. Especially, connect a capacitor across the
RESET pin and the VSS pin with the shortest possible wiring (within
20mm).
● Reason
The width of a pulse input into the RESET pin is determined by
the timing necessary conditions. If noise having a shorter pulse
width than the standard is input to the RESET pin, the reset is
released before the internal state of the microcomputer is com-
pletely initialized. This may cause a program runaway.
Fig. 57 Wiring for clock I/O pins
(2) Connection of bypass capacitor across VSS line and VCC line
Connect an approximately 0.1
µ
F bypass capacitor across the VSS
line and the VCC line as follows:
• Connect a bypass capacitor across the VSS pin and the VCC pin at
equal length.
• Connect a bypass capacitor across the VSS pin and the VCC pin
with the shortest possible wiring.
• Use lines with a larger diameter than other signal lines for VSS line
and VCC line.
• Connect the power source wiring via a bypass capacitor to the VSS
pin and the VCC pin.
Fig. 56 Wiring for the RESET pin
➁ Wiring for clock input/output pins
• Make the length of wiring which is connected to clock I/O pins as
short as possible.
• Make the length of wiring (within 20 mm) across the grounding
lead of a capacitor which is connected to an oscillator and the
VSS pin of a microcomputer as short as possible.
• Separate the VSS pattern only for oscillation from other VSS pat-
terns.
● Reason
If noise enters clock I/O pins, clock waveforms may be deformed.
This may cause a program failure or program runaway. Also, if a
potential difference is caused by the noise between the VSS level
of a microcomputer and the VSS level of an oscillator, the correct
clock will not be input in the microcomputer.
RESET
Reset
circuit
Noise
V
SS
V
SS
Reset
circuit
V
SS
RESET
V
SS
N.G.
O.K.
Fig. 58 Bypass capacitor across the VSS line and the VCC line
Noise
X
IN
X
OUT
V
SS
X
IN
X
OUT
V
SS
N.G. O.K.
VSS
VCC
AA
AA
AA
AA
AA
AA
VSS
VCC
AA
AA
AA
AA
AA
AA
AA
AA
AA
AA
N.G. O.K.
Rev.2.00 May 28, 2004 page 55 of 100
38C2 Group (A Version)
(3) Oscillator concerns
Take care to prevent an oscillator that generates clocks for a micro-
computer operation from being affected by other signals.
➀ Keeping oscillator away from large current signal lines
Install a microcomputer (and especially an oscillator) as far as pos-
sible from signal lines where a current larger than the tolerance of
current value flows.
● Reason
In the system using a microcomputer, there are signal lines for
controlling motors, LEDs, and thermal heads or others. When a
large current flows through those signal lines, strong noise occurs
because of mutual inductance.
➁ Installing oscillator away from signal lines where potential levels
change frequently
Install an oscillator and a connecting pattern of an oscillator away
from signal lines where potential levels change frequently. Also,
do not cross such signal lines over the clock lines or the signal
lines which are sensitive to noise.
● Reason
Signal lines where potential levels change frequently (such as the
CNTR pin signal line) may affect other lines at signal rising edge
or falling edge. If such lines cross over a clock line, clock wave-
forms may be deformed, which causes a microcomputer failure or
a program runaway.
➀ Keeping oscillator away from large current signal lines
➁ Installing oscillator away from signal lines where potential levels
change frequently
C
N
VS
S/
VP
P
VS
S
About 10kΩ
(4) Wiring to VPP pin of flash memory version
Connect an approximately 10 kΩ resistor to the VPP pin the shortest
possible in series and also to the VSS pin.
Note: Even when a circuit which included an approximately 10 kΩ
resistor is used in the Mask ROM version, the microcomputer
operates correctly.
● Reason
The VPP pin of the flash memory version is the power source input
pin for the built-in flash memory. When programming/erasing in the
built-in flash memory, the impedance of the VPP pin is low to allow the
electric current for writing/erasing flow into the flash memory. Be-
cause of this, noise can enter easily. If noise enters the VPP pin, ab-
normal instruction codes or data are read from the built-in flash
memory, which may cause a program runaway.
Fig. 60 Wiring for the VPP pin of flash memory
Electric Characteristic Differences Between
Mask ROM and Flash memory Version MCUs
There are differences in electric characteristics, operation margin,
noise immunity, and noise radiation between the mask ROM and
flash memory version MCUs due to the difference in the manufactur-
ing processes.
When manufacturing an application system with the flash memory
version and then switching to use of the mask ROM version, please
perform sufficient evaluations for the commercial samples of the Mask
ROM version.
Oscillation Circuit Constant
(1) Determine an oscillation circuit constant after consulting the os-
cillator manufacturer about the matching characteristic evalua-
tion.
(2) Since oscillation circuit constants may be differences between
the flash memory version and the mask ROM version, evaluate
them, respectively.
X
I
N
X
O
U
T
V
SS
M
Microcomputer
M
u
t
u
a
l
i
n
d
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current
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o
t
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o
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s
N
.
G
.
Fig. 59 Wiring for a large current signal line/Writing of signal
lines where potential levels change frequently
Rev.2.00 May 28, 2004 page 56 of 100
38C2 Group (A Version)
Table 11 Summary of 38C2 group (A version)’s flash memory version
FLASH MEMORY MODE
The 38C2 group (A version)’s flash memory version has an internal
new DINOR (DIvided bit line NOR) flash memory that can be rewrit-
ten with a single power source when VCC is 4.5 to 5.5 V, and 2 power
sources when VCC is 3.0 to 4.5 V.
For this flash memory, three flash memory modes are available in
which to read, program, and erase: the parallel I/O and standard
serial I/O modes in which the flash memory can be manipulated us-
ing a programmer and the CPU rewrite mode in which the flash
memory can be manipulated by the Central Processing Unit (CPU).
Summary
Table 11 lists the summary of the 38C2 group (A version)’s flash
memory version.
This flash memory version has some blocks on the flash memory as
shown in Figure 61 and each block can be erased.
In addition to the ordinary User ROM area to store the MCU opera-
tion control program, the flash memory has a Boot ROM area that is
used to store a program to control rewriting in CPU rewrite and stan-
dard serial I/O modes. This Boot ROM area has had a standard se-
rial I/O mode control program stored in it when shipped from the
factory. However, the user can write a rewrite control program in this
area that suits the user ’s application system. This Boot ROM area
can be rewritten in only parallel I/O mode.
Item
Power source voltage (Vcc)
Program/Erase VPP voltage (VPP)
Flash memory mode
Erase block division User ROM area
Boot ROM area
Program method
Erase method
Program/Erase control method
Number of commands
Number of program/Erase times
ROM code protection
Specifications
VCC = 2.5 to 5.5 V (Note 1)
VCC = 2.5 to (VCC at program/erase) + 0.5 V (Note 2)
VPP = 4.5 to 5.5 V, VCC = 3.0 to 5.5 V
3 modes; Parallel I/O mode, Standard serial I/O mode, CPU rewrite mode
Refer to Fig. 61.
Not divided (4K bytes) (Note 3)
In units of bytes
Block erase
Program/Erase control by software command
5 commands
100 times
Available in parallel I/O mode and standard serial I/O mode
Notes 1: It is the rating value when Vcc = 5.0 to 5.5 V at program/erase.
2: It is the rating value when Vcc = 3.0 to 5.0 V at program/erase.
3: The Boot ROM area has had a standard serial I/O mode control program stored in it when shipped from the factory. This Boot ROM area can be erased and
written in only parallel I/O mode.
Rev.2.00 May 28, 2004 page 57 of 100
38C2 Group (A Version)
Fig. 61 Block diagram of built-in flash memory
(1) CPU Rewrite Mode
In CPU rewrite mode, the internal flash memory can be operated on
(read, program, or erase) under control of the Central Processing
Unit (CPU).
In CPU rewrite mode, only the User ROM area shown in Figure 61
can be rewritten; the Boot ROM area cannot be rewritten. Make sure
the program and block erase commands are issued for only the User
ROM area and each block area.
The control program for CPU rewrite mode can be stored in either
User ROM or Boot ROM area. In the CPU rewrite mode, because
the flash memory cannot be read from the CPU, the rewrite control
program must be transferred to internal RAM area before it can be
executed.
Boot Mode
The control program for CPU rewrite mode must be written into the
User ROM or Boot ROM area in parallel I/O mode beforehand. (If the
control program is written into the Boot ROM area, the standard se-
rial I/O mode becomes unusable.)
See Figure 61 for details about the Boot ROM area.
Normal microcomputer mode is entered when the microcomputer is
reset with pulling CNVSS pin low . In this case, the CPU starts operat-
ing using the control program in the User ROM area.
When the microcomputer is reset by pulling the P41(CE) pin high,
the CNVSS pin high, the CPU starts operating (start address of pro-
gram is stored into addresses FFFC16 and FFFD16) using the control
program in the Boot ROM area. This mode is called the “Boot mode”.
Also, User ROM area can be rewritten using the control program in
the Boot ROM area.
Block Address
Block addresses refer to the maximum address of each block. These
addresses are used in the block erase command.
1
0
0
0
1
6
8
0
0
0
1
6
F
F
F
F
1
6
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0
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6
BSEL=0 BSEL=1
U
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r
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r
e
a
4 Kbytes
Boot RO M ar ea
Notes 1: The Boo t RO M ar ea can be rewritten in on ly par alle l I/ O mode.
(Acces s to any other ar eas is inhibited.)
2: To sp ec ify a blo c k , use the ma x im um address in the bloc k .
P
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User area / Boot area select bit = “1”
Product name Flash memory
top ad dr es s
Rev.2.00 May 28, 2004 page 58 of 100
38C2 Group (A Version)
Outline Performance (CPU Rewrite Mode)
CPU rewrite mode is usable in the single-chip or Boot mode. The
only User ROM area can be rewritten.
In CPU rewrite mode, the CPU erases, programs and reads the in-
ternal flash memory as instructed by software commands. This re-
write control program must be transferred to internal RAM area be-
fore it can be executed.
The MCU enters CPU rewrite mode by applying 4.5 V to 5.5 V to the
CNVSS pin and setting “1” to the CPU rewrite mode select bit (bit 1 of
address 0FFE16). Then, software commands can be accepted.
Use software commands to control program and erase operations.
Whether a program or erase operation has terminated normally or in
error can be verified by reading the status register.
Figure 62 shows the flash memory control register.
Bit 0 of the flash memory control register is the RY/BY status flag
used exclusively to read the operating status of the flash memory.
During programming and erase operations, it is “0” (busy). Other-
wise, it is “1” (ready).
Bit 1 of the flash memory control register is the CPU rewrite mode
select bit. When this bit is set to “1”, the MCU enters CPU rewrite
mode. And then, software commands can be accepted. In CPU re-
write mode, the CPU becomes unable to access the internal flash
memory directly. Therefore, use the control program in the internal
RAM for write to bit 1. To set this bit 1 to “1”, it is necessary to write
“0” and then write “1” in succession to bit 1. The bit can be set to “0”
by only writing “0”.
Bit 2 of the flash memory control register is the CPU rewrite mode
entry flag. This flag indicates “1” in CPU rewrite mode, so that read-
ing this flag can check whether CPU rewrite mode has been entered
or not.
Bit 3 of the flash memory control register is the flash memory reset
bit used to reset the control circuit of internal flash memory. This bit is
used when exiting CPU rewrite mode and when flash memory ac-
cess has failed. When the CPU rewrite mode select bit is “1”, setting
“1” for this bit resets the control circuit. To release the reset, it is
necessary to set this bit to “0”.
Bit 4 of the flash memory control register is the User area/Boot area
select bit. When this bit is set to “1”, Boot ROM area is accessed, and
CPU rewrite mode in Boot ROM area is available. In Boot mode, this
bit is set to “1” automatically. Programming of this bit must be ex-
ecuted on program of the internal RAM.
Figure 63 shows a flowchart for setting/releasing CPU rewrite mode.
Fig. 62 Structure of flash memory control register
Flash memory control register (address 0FFE16)
FMCR
RY/BY status flag
0: Busy (being written or erased)
1: Ready
CPU rewrite mode select bit (Note 2)
0: Normal mode (Software commands invalid)
1: CPU rewrite mode (Software commands acceptable)
CPU rewrite mode entry flag
0: Normal mode (Software commands invalid)
1: CPU rewrite mode (Software commands acceptable)
Flash memory reset bit (Note 3)
0: Normal operation
1: Reset
User area / Boot area select bit
0: User ROM area accessed
1: Boot ROM area accessed
Reserved bits (“0” at write, undefined at read)
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Rev.2.00 May 28, 2004 page 59 of 100
38C2 Group (A Version)
Fig. 63 CPU rewrite mode set/release flowchart
End
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Notes 1: When starting the MC U in the single- chip m ode, supp ly 4.5 to 5.5 V to the CNVss
pin until checking the CPU rewrite mode entry flag.
2: Set the main clock as follows depending on the X
IN
divider select bits of cloc
k
control register (bits 4, 5 of address 003F
16
):
3: Before exiting the CPU rewrite mode after completing erase or program operat ion,
always be sure to execute the read array command or reset the flash memory.
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Rev.2.00 May 28, 2004 page 60 of 100
38C2 Group (A Version)
Notes on CPU Rewrite Mode
Take the notes described below when rewriting the flash memory in
CPU rewrite mode.
●Operation speed
During CPU rewrite mode, set the system clock φ to 4.0 MHz or less
using the main clock division ratio selection bits (bits 4 and 5 of ad-
dress 003B16).
●Instructions inhibited against use
The instructions which refer to the internal data of the flash memory
cannot be used during CPU rewrite mode.
●Interrupts inhibited against use
The interrupts cannot be used during CPU rewrite mode because
they refer to the internal data of the flash memory.
●Watchdog timer
If the watchdog timer has been already activated, internal reset due
to an underflow will not occur because the watchdog timer is surely
cleared during program or erase.
●Reset
Reset is always valid. The MCU is activated using the boot mode at
release of reset in the condition of CNVss = “H”, so that the program
will begin at the address which is stored in addresses FFFC16 and
FFFD16 of the boot ROM area.
Rev.2.00 May 28, 2004 page 61 of 100
38C2 Group (A Version)
Software Commands
Table 12 lists the software commands.
After setting the CPU rewrite mode select bit to “1”, execute a soft-
ware command to specify an erase or program operation.
Each software command is explained below.
●Read Array Command (FF16)
The read array mode is entered by writing the command code “FF16”
in the first bus cycle. When an address to be read is input in one of
the bus cycles that follow, the contents of the specified address are
read out at the data bus (D0 to D7).
The read array mode is retained until another command is written.
●Read Status Register Command (7016)
When the command code “7016” is written in the first bus cycle, the
contents of the status register are read out at the data bus (D0 to D7)
by a read in the second bus cycle.
The status register is explained in the next section.
●Clear Status Register Command (5016)
This command is used to clear the bits SR4 and SR5 of the status
register after they have been set. These bits indicate that operation
has ended in an error. To use this command, write the command
code “5016” in the first bus cycle.
●Program Command (4016)
Program operation starts when the command code “4016” is written
in the first bus cycle. Then, if the address and data to program are
written in the 2nd bus cycle, program operation (data programming
and verification) will start.
Whether the write operation is completed can be confirmed by read
_____
status register or the RY/BY status flag. When the program starts,
the read status register mode is entered automatically and the con-
tents of the status register is read at the data bus (D0 to D7). The
status register bit 7 (SR7) is set to “0” at the same time the write
operation starts and is returned to “1” upon completion of the write
operation. In this case, the read status register mode remains active
until the read array command (FF16) is written.
Table 12 List of software commands (CPU rewrite mode)
The RY/BY status flag of the flash memory control register is “0”
during write operation and “1” when the write operation is completed
as is the status register bit 7.
At program end, program results can be checked by reading the sta-
tus register.
Fig. 64 Program flowchart
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Rev.2.00 May 28, 2004 page 62 of 100
38C2 Group (A Version)
●Block Erase Command (2016/D016)
By writing the command code “2016” in the first bus cycle and the
confirmation command code “D016” and the block address in the sec-
ond bus cycle that follows, the block erase (erase and erase verify)
operation starts for the block address of the flash memory to be speci-
fied.
Whether the block erase operation is completed can be confirmed
by read status register or the RY/BY status flag of flash memory con-
trol register. At the same time the block erase operation starts, the
read status register mode is automatically entered, so that the con-
tents of the status register can be read out. The status register bit 7
(SR7) is set to “0” at the same time the block erase operation starts
and is returned to “1” upon completion of the block erase operation.
In this case, the read status register mode remains active until the
read array command (FF16) is written.
The RY/BY status flag is “0” during block erase operation and “1”
when the block erase operation is completed as is the status register
bit 7.
After the block erase ends, erase results can be checked by reading
the status register. For details, refer to the section where the status
register is detailed.
Fig. 65 Erase flowchart
W
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2
0
1
6
D
0
1
6
B
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a
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d
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Erase compl et ed
(write read command
FF
16
)
NO
YES
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t
a
r
t
Write
SR5 = 0
?
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E
S
N
O
SR
7 = 1
?
or
RY/BY = 1 ?
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a
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u
s
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g
i
s
t
e
r
Rev.2.00 May 28, 2004 page 63 of 100
38C2 Group (A Version)
Table 13 Definition of each bit in status register
Status Register
The status register shows the operating status of the flash memory
and whether erase operations and programs ended successfully or
in error. It can be read in the following ways:
(1) By reading an arbitrary address from the User ROM area after
writing the read status register command (7016)
(2) By reading an arbitrary address from the User ROM area in the
period from when the program starts or erase operation starts to
when the read array command (FF16) is input.
Also, the status register can be cleared by writing the clear status
register command (5016).
After reset, the status register is set to “8016”.
Table 13 shows the status register. Each bit in this register is ex-
plained below.
•Sequencer status (SR7)
The sequencer status indicates the operating status of the flash
memory. This bit is set to “0” (busy) during write or erase operation
and is set to “1” when these operations ends.
After power-on, the sequencer status is set to “1” (ready).
•Erase status (SR5)
The erase status indicates the operating status of erase operation. If
an erase error occurs, it is set to “1”. When the erase status is cleared,
it is reset to “0”.
•Program status (SR4)
The program status indicates the operating status of write operation.
When a write error occurs, it is set to “1”.
The program status is reset to “0” when it is cleared.
If “1” is written for any of the SR5 and SR4 bits, the read array, pro-
gram, and block erase commands are not accepted. Before execut-
ing these commands, execute the clear status register command
(5016) and clear the status register.
Also, if any commands are not correct, both SR5 and SR4 are set to
“1”.
Each bit of
SRD bits
SR7 (bit7)
SR6 (bit6)
SR5 (bit5)
SR4 (bit4)
SR3 (bit3)
SR2 (bit2)
SR1 (bit1)
SR0 (bit0)
Sequencer status
Reserved
Erase status
Program status
Reserved
Reserved
Reserved
Reserved
Status name “1”
Ready
-
Terminated normally
Terminated normally
-
-
-
-
“0”
Busy
-
Terminated normally
Terminated normally
-
-
-
-
Definition
Rev.2.00 May 28, 2004 page 64 of 100
38C2 Group (A Version)
Full Status Check
By performing full status check, it is possible to know the execution
results of erase and program operations. Figure 66 shows a full sta-
tus check flowchart and the action to be taken when each error oc-
curs.
Fig. 66 Full status check flowchart and remedial procedure for errors
R
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Program error
End (block erase, program)
Execute the clear status register command (5016)
to clear the status register. Try performing the
operation one more time after confirming that the
command is entered correctly.
Should an erase error occur, the block in error
cannot be used.
N
o
t
e:
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Should a program error occur, the block in error
cannot be used.
Rev.2.00 May 28, 2004 page 65 of 100
38C2 Group (A Version)
Functions To Inhibit Rewriting Flash Memory
Version
To prevent the contents of internal flash memory from being read out
or rewritten easily, this MCU incorporates a ROM code protect func-
tion for use in parallel I/O mode and an ID code check function for
use in standard serial I/O mode.
●ROM Code Protect Function
The ROM code protect function is the function to inhibit reading out
or modifying the contents of internal flash memory by using the ROM
code protect control address (address FFDB16) in parallel I/O mode.
Figure 67 shows the ROM code protect control address (address
FFDB16). (This address exists in the User ROM area.)
If one or both of the pair of ROM code protect bits is set to “0”, the
ROM code protect is turned on, so that the contents of internal flash
memory are protected against readout and modification. The ROM
code protect is implemented in two levels. If level 2 is selected, the
flash memory is protected even against readout by a shipment in-
spection LSI tester, etc. When an attempt is made to select both
level 1 and level 2, level 2 is selected by default.
If both of the two ROM code protect reset bits are set to “00”, the
ROM code protect is turned off, so that the contents of internal flash
memory can be readout or modified. Once the ROM code protect is
turned on, the contents of the ROM code protect reset bits cannot be
modified in parallel I/O mode. Use the serial I/O or CPU rewrite mode
to rewrite the contents of the ROM code protect reset bits.
Fig. 67 Structure of ROM code protect control address
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Notes 1: When ROM code protect is turned on, the internal flash memory is protected
against readout or modification in parallel I/O mode.
2: When ROM code protect level 2 is turned on, ROM code readout by a shipment
inspection LSI tester, etc. also is inhibited.
3: The ROM code protect re set bits can be used to turn off ROM code protect level 1
and ROM code protect level 2. However, since these bits cannot be modified in
parallel I/O mode, they need to be rewritten in serial I/O mode or CPU rewrite
mode.
Rev.2.00 May 28, 2004 page 66 of 100
38C2 Group (A Version)
ID Code Check Function
Use this function in standard serial I/O mode. When the contents of
the flash memory are not blank, the ID code sent from the program-
mer is compared with the ID code written in the flash memory to see
if they match. If the ID codes do not match, the commands sent from
the programmer are not accepted. The ID code consists of 8-bit data,
and its areas are FFD416 to FFDA16. Write a program which has had
the ID code preset at these addresses to the flash memory.
Fig. 68 ID code store addresses
ROM code protect control
ID7
ID6
ID5
ID4
ID3
ID2
ID1
FFDB
16
FFDA
16
FFD9
16
F
F
D
8
1
6
F
F
D
7
1
6
F
F
D
6
1
6
F
F
D
5
1
6
F
F
D
4
1
6
A
d
d
r
e
s
s
Interrupt vector area
Rev.2.00 May 28, 2004 page 67 of 100
38C2 Group (A Version)
(2) Parallel I/O Mode
The parallel I/O mode is used to input/output software commands,
address and data in parallel for operation (read, program and erase)
to internal flash memory.
Use the external device (writer) only for 38C2 Group group (A
version)’s flash memory version. For details, refer to the user’s manual
of each writer manufacturer.
User ROM and Boot ROM Areas
In parallel I/O mode, the User ROM and Boot ROM areas shown in
Figure 61 can be rewritten. Both areas of flash memory can be oper-
ated on in the same way.
Program and block erase operations can be performed only in the
User ROM area.
The Boot ROM area is 4 Kbytes in size and located at addresses
F00016 through FFFF16. Make sure program and block erase opera-
tions are always performed within this address range. (Access to any
location outside this address range is prohibited.)
In the Boot ROM area, an erase block operation is applied to only
one 4 Kbyte block. The boot ROM area has had a standard serial I/O
mode control program stored in it when shipped from our factory.
Therefore, using the MCU in standard serial I/O mode, do not rewrite
to the Boot ROM area.
Rev.2.00 May 28, 2004 page 68 of 100
38C2 Group (A Version)
(3) Standard serial I/O Mode
The standard serial I/O mode inputs and outputs the software com-
mands, addresses and data needed to operate (read, program, erase,
etc.) the internal flash memory. This I/O is clock synchronized serial.
This mode requires a purpose-specific peripheral unit.
The standard serial I/O mode is different from the parallel I/O mode
in that the CPU controls flash memory rewrite (uses the CPU rewrite
mode), rewrite data input and so forth. The standard serial I/O mode
is started by connecting “H” to the P41 (CE) pin and “H” to the CNVSS
pin (when VCC = 4.5 to 5.5 V, connect to VCC, and when VCC = 3.0 to
4.5 V, apply 4.5 V to 5.5 V to Vpp from an external source), and
releasing the reset operation. (In the ordinary microcomputer mode,
set CNVss pin to “L” level.)
This control program is written in the Boot ROM area when the prod-
uct is shipped from Renesas. Accordingly, make note of the fact that
the standard serial I/O mode cannot be used if the Boot ROM area is
rewritten in parallel I/O mode. Figure 69 shows the pin connections
for the standard serial I/O mode.
In standard serial I/O mode, serial data I/O uses the four UART2 pins
SCLK2, RxD2, TxD2 and SRDY2 (BUSY). The SCLK2 pin is the transfer
clock input pin through which an external transfer clock is input. The
TxD2 pin is for CMOS output. The SRDY2 (BUSY) pin outputs “L”
level when ready for reception and “H” level when reception starts.
Serial data I/O is transferred serially in 8-bit units.
In standard serial I/O mode, only the User ROM area shown in Fig-
ure 61 can be rewritten. The Boot ROM area cannot.
In standard serial I/O mode, a 7-byte ID code is used. When there is
data in the flash memory, commands sent from the peripheral unit
(programmer) are not accepted unless the ID code matches.
Outline Performance (Standard Serial I/O Mode)
In standard serial I/O mode, software commands, addresses and
data are input and output between the MCU and peripheral units
(serial programer, etc.) using 4-wire clock-synchronized serial I/O
(UART2).
In reception, software commands, addresses and program data are
synchronized with the rise of the transfer clock that is input to the
SCLK2 pin, and are then input to the MCU via the RxD2 pin. In trans-
mission, the read data and status are synchronized with the fall of
the transfer clock, and output from the TxD2 pin.
The TxD2 pin is for CMOS output. Transfer is in 8-bit units with LSB
first.
When busy, such as during transmission, reception, erasing or pro-
gram execution, the SRDY2 (BUSY) pin is “H” level. Accordingly, al-
ways start the next transfer after the SRDY2 (BUSY) pin is “L” level.
Also, data and status registers in a memory can be read after input-
ting software commands. Status, such as the operating state of the
flash memory or whether a program or erase operation ended suc-
cessfully or not, can be checked by reading the status register. Here
following explains software commands, status registers, etc.
Rev.2.00 May 28, 2004 page 69 of 100
38C2 Group (A Version)
Pin name Signal name I/O
VCC,VSS Power supply
CNVSS CNVSS I
RESET Reset input I
AVSS Analog power supply
VREF Analog reference voltage I
P00–P07I/O port P0 I/O
P10–P17I/O port P1 I/O
P20–P27I/O port P2 I/O
P30BUSY output O
P31SCLK input I
P32TXD output O
P33RXD input I
P34–P37I/O port P3 I/O
P40I/O port P4 I/O
P41CE input I
P42–P47I/O port P4 I/O
P50–P57I/O port P5 I/O
P60I/O port P6 I/O
P61/XCIN I/O port P6/Sub clock input I/O
P62/XCOUT I/O port P6/Sub clock output I/O
COM0–COM3Common output O
VL3Power supply for LCD
Table 14 Description of pin function (Flash Memory Serial I/O Mode)
Function
Apply guaranteed voltage of program/erase to the Vcc pin and 0 V to the Vss pin.
Connect this pin to Vcc at Vcc = 4.5 to 5.5 V.
Connect this pin to VPP at Vcc = 3.0 to 4.5 V.
Reset input pin. When XIN oscillation is stable, input “L” level for 2 µs or more.
Connect a ceramic resonator or crystal oscillator between the XIN and XOUT pins.
When entering an externally driven clock, enter it from XIN and input the inverted
signal of XIN pin to XOUT pin.
Connect to Vss.
Apply reference voltage of A-D to this pin.
Input “L” or “H” level, or keep open.
Input “L” or “H” level, or keep open.
Input “L” or “H” level, or keep open.
BUSY signal output pin.
Serial clock input pin.
Serial data output pin.
Serial data input pin.
Input “L” or “H” level, or keep open.
Input “L” or “H” level, or keep open.
Input “H” level.
Input “L” or “H” level, or keep open.
Input “L” or “H” level, or keep open.
Input “L” or “H” level, or keep open.
When these pins are used for sub-clock, connect a quartz-crystal oscillator be-
tween the XCIN and XCOUT pins.
When entering an externally driven clock, enter it from XCIN and leave XOUT open.
When these pins are used as port, input “L” or “H” level, or keep open.
When the LCD control circuit is not used, keep open.
Apply LCD power source to this pin. When the LCD drive control circuit is not
used, connect this pin to Vcc.
XIN Clock input I
XOUT Clock output O
Rev.2.00 May 28, 2004 page 70 of 100
38C2 Group (A Version)
Fig. 69 Pin connection diagram in serial I/O mode
*1
*2
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VSS
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5
4
P3
6
/T
2OUT
/φ/(LED
6)
X
O
U
T
P5
2
/T
3OUT
/PWM
0
V
R
E
F
V
L
3
P
4
3
/
A
N
3
P
4
2
/
A
N
2
P
4
4
/
A
N
4
P4
7
/RTP
1
/AN
7
P4
6
/RTP
0
/AN
6
P
4
5
/
A
N
5
V
S
S
P
3
2
/
T
X
D
2
/
(
L
E
D
2
)
P3
1
/S
CLK2
/(LED
1
)
P
3
3
/
R
X
D
2
/
(
L
E
D
3
)
P5
0
/INT
0
A
V
S
S
(
K
W
6
)
/
P
0
2
/
S
E
G
2
(
K
W
5
)
/
P
0
1
/
S
E
G
1
(
K
W
4
)
/
P
0
0
/
S
E
G
0
P
4
1
/
A
N
1
P
4
0
/
A
N
0
C
N
V
S
S
P
6
2
/
X
C
O
U
T
P
6
1
/
X
C
I
N
V
C
C
X
I
N
R
E
S
E
T
(
K
W
3
)
/
P
5
7
/
S
R
D
Y
1
P
3
0
/
S
R
D
Y
2
/
(
L
E
D
0
)
P3
5
/T
XOUT
/(LED
5)
P3
4
/INT
2
/(LED
4)
V
P
P
TXD
RXD
SC
L
K
64P6U-A/64P6Q-A
C
E
*1.C onnect to oscillation circu it.
*2.Connect to Vcc when Vcc=4.5 to 5.5V.
Connect to VPP (=4.5 to 5. 5V) when Vcc=3. 0 to 4.5V.
M
o
d
e
s
e
t
u
p
m
e
t
h
o
d
S
i
g
n
a
lV
a
l
u
e
C
N
V
s
s
C
E
R
E
S
E
T
4.5 to 5.5 V
Vcc
Vss→Vcc
Rev.2.00 May 28, 2004 page 71 of 100
38C2 Group (A Version)
Example Circuit Application for Standard Se-
rial I/O Mode
Figure 70 shows a circuit application for the standard serial I/O mode.
Control pins will vary according to a programmer, therefore see a
programmer manual for more information.
Fig. 70 Example circuit application for standard serial I/O mode
SRDY2(BUSY)
SCLK2
R
X
D2
T
X
D2
CNVss
M38C29FFA
P41(CE)
Clock input
BUSY output
Data input
Data output
Notes 1: Control pins and external circuitry will vary according to a programmer. For more
information, see the programmer manual.
2: In this example, the Vpp power supply is supplied from an external source (programmer).
To use the user’s power source, connect to 4.5 V to 5.5 V.
V
PP
power source input
Rev.2.00 May 28, 2004 page 72 of 100
38C2 Group (A Version)
ELECTRICAL CHARACTERISTICS (Flash memory version)
Absolute Maximum Ratings
Table 15 Absolute maximum ratings (Flash memory version)
Parameter
Power source voltage
Input voltage P00–P07, P10–P17, P20–P27, P30–P37,
P40–P47, P50–P57, P60–P62
Input voltage VL1
Input voltage VL2
Input voltage VL3
Input voltage RESET, XIN
Input voltage CNVSS
Output voltage P00–P07, P10–P17, P20–P27
Output voltage COM0–COM3
Output voltage P30–P37, P40–P47, P50–P57, P60–P62
Output voltage XOUT
Power dissipation
Operating temperature
Storage temperature
Symbol
VCC
VI
VI
VI
VI
VI
VI
VO
VO
VO
VO
Pd
Topr
Tstg
Conditions
All voltages are based on Vss.
Output transistors are cut off.
At output port
At segment output
Ta = 25°C
At MCU operation
At flash memory mode
Ratings
–0.3 to 6.5
–0.3 to VCC+0.3
–0.3 to VL2
VL1 to VL3
VL2 to 6.5
–0.3 to VCC+0.3
–0.3 to 6.5
–0.3 to VCC+0.3
–0.3 to VL3+0.3
–0.3 to VL3+0.3
–0.3 to VCC+0.3
–0.3 to VCC+0.3
300
–20 to 85
25 ± 5
–40 to 125
Unit
V
V
V
V
V
V
V
V
V
V
V
V
mW
°C
°C
°C
Recommended Operating Conditions
Table 16 Recommended operating conditions (Flash memory version)
(Vcc = 2.5 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Power source voltage f(φ) = 5 MHz
(Note 1) f(φ) = 4 MHz
f(φ) = 2 MHz
Low-speed mode
Oscillation start voltage (Note 2)
Power source voltage
Power source voltage for LCD
A-D converter reference voltage
Analog power source voltage
Analog input voltage AN0–AN7
“H” input voltage P04–P07, P10–P17, P20–P27, P30, P32, P35,
P36, P40–P47, P52, P53, P62
“H” input voltage P00–P03, P31, P33, P34, P37, P50, P51,
P54–P57, P60, P61
“H” input voltage RESET
“H” input voltage XIN
“H” input voltage XCIN (Note 4)
“L” input voltage P04–P07, P10–P17, P20–P27, P30, P32,P35,
P36, P40–P47, P52, P53, P62
“L” input voltage P00–P03, P31, P33, P34, P37, P50, P51,
P54–P57, P60, P61, CNVSS
“L” input voltage RESET
“L” input voltage XIN
“L” input voltage XCIN (Note 5)
VCC
VSS
VL3
VREF
AVSS
VIA
VIH
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIL
VIL
Limits
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Parameter Min.
4.5
4.0
2.5
2.5
0.15 ✕ f + 1.3
2.5
2.0
AVSS
0.7VCC
0.8VCC
0.8VCC
0.8VCC
1.5
0
0
0
0
0
Typ.
5.0
5.0
5.0
5.0
0
0
Max.
5.5 (Note 3)
5.5 (Note 3)
5.5 (Note 3)
5.5 (Note 3)
5.5
VCC
VCC
VCC
VCC
VCC
VCC
VCC
0.3VCC
0.2VCC
0.2VCC
0.2VCC
0.4
Symbol Unit
Notes 1: When using the A-D converter, refer to “A-D Converter Characteristics”.
2: The oscillation start voltage and the oscillation start time differ in accordance with an oscillator, a circuit constant, or temperature, etc. When power supply
voltage is low and the high frequency oscillator is used, an oscillation start will require sufficient conditions.
f: This is the XIN oscillator’s oscillation frequency (≥ 1 MHz). For example, when oscillation frequency is 8 MHz, substitute “8”.
3: It is the rating value when VCC = 5.0 to 5.5 V at program/erase. The value is (VCC at program/erase) + 0.5 V when VCC = 3.0 to 5.0 V at program/erase.
4: When the XCIN/P61 pin is not connected to an oscillator, refer to VIH for P61.
5: When the XCIN/P61 pin is not connected to an oscillator, refer to VIL for P61.
Rev.2.00 May 28, 2004 page 73 of 100
38C2 Group (A Version)
“H” total peak output current (Note 1)
P00–P07, P10–P17, P20–P27, P30–P37
“H” total peak output current (Note 1)
P40–P47, P50–P57, P60–P62
“L” total peak output current (Note 1)
P00–P07, P10–P17, P20–P27
“L” total peak output current (Note 1)
P40–P47, P50, P51, P54–P57, P60–P62
“L” total peak output current (Note 1)
P30–P37, P52, P53
“H” total average output current (Note 1)
P00–P07, P10–P17, P20–P27, P30–P37
“H” total average output current (Note 1)
P40–P47, P50–P57, P60–P62
“L” total average output current (Note 1)
P00–P07, P10–P17, P20–P27
“L” total average output current (Note 1)
P40–P47, P50, P51, P54–P57, P60–P62
“L” total average output current (Note 1)
P30–P37, P52, P53
“H” peak output current (Note 2)
P00–P07, P10–P17, P20–P27
“H” peak output current (Note 2)
P30–P37, P40–P47, P50–P57, P60–P62
“L” peak output current (Note 2)
P00–P07, P10–P17, P20–P27
“L” peak output current (Note 2)
P40–P47, P50, P51, P54–P57, P60–P62
“L” peak output current (Note 2)
P30–P37, P52, P53
“H” average output current (Note 3)
P00–P07, P10–P17, P20–P27
“H” average output current (Note 3)
P30–P37, P40–P47, P50–P57, P60–P62
“L” average output current (Note 3)
P00–P07, P10–P17, P20–P27
“L” average output current (Note 3)
P40–P47, P50, P51, P54–P57, P60–P62
“L” average output current (Note 3)
P30–P37, P52, P53
ΣIOH(peak)
ΣIOH(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
ΣIOH(avg)
ΣIOL(avg)
ΣIOL(avg)
ΣIOL(avg)
IOH(peak)
IOH(peak)
IOL(peak)
IOL(peak)
IOL(peak)
IOH(avg)
IOH(avg)
IOL(avg)
IOL(avg)
IOL(avg)
Limits
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Parameter Min. Typ. Max.
Symbol Unit
–20
–20
20
20
110
–10
–10
10
10
90
–1.0
–5.0
10
10
30
–0.5
–2.5
5.0
5.0
15
Table 17 Recommended operating conditions (Flash memory version)
(Vcc = 2.5 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over
100 ms. The total peak current is the peak value of all the currents.
2: The peak output current is the peak current flowing in each port.
3: The average output current is average value measured over 100 ms.
Rev.2.00 May 28, 2004 page 74 of 100
38C2 Group (A Version)
Table 18 Recommended operating conditions (Flash memory version)
(Vcc = 2.5 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Timer X and Timer Y
Input frequency (duty cycle 50%)
Timer X, Timer Y, Timer 1, Timer 2, Timer 3 and
Timer 4 Clock input frequency
(Count source frequency of each timer)
System clock φ frequency
Main clock input oscillation frequency
(Notes 1, 3)
Sub-clock input oscillation frequency
(Notes 1, 2, 3)
f(CNTR0)
f(CNTR1)
f(Tclk)
f(φ)
f(XIN)
f(XCIN)
Limits
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
kHz
Parameter Min.
1.0
1.0
Typ.
32.768
Max.
5.0
2 ✕ VCC–4
VCC
10.0
4 ✕ VCC–8
2 ✕ VCC
5.0
2 ✕ VCC–4
VCC
10.0
8.0
50
Symbol Unit
(4.5 V ≤ VCC ≤ 5.5 V)
(4.0 V ≤ VCC < 4.5 V)
(VCC < 4.0 V)
(4.5 V ≤ VCC ≤ 5.5 V)
(4.0 V ≤ VCC < 4.5 V)
(VCC < 4.0 V)
(4.5 V ≤ VCC ≤ 5.5 V)
(4.0 V ≤ VCC < 4.5 V)
(VCC < 4.0 V)
(4.5 V ≤ VCC ≤ 5.5 V)
(2.5 V ≤ VCC < 4.5 V)
Notes 1: When the oscillation frequency has a duty cycle of 50%.
2: When using the microcomputer in low-speed mode, set the clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3.
3: The oscillation start voltage and the oscillation start time differ in accordance with an oscillator, a circuit constant, or temperature, etc. When power supply
voltage is low and the high frequency oscillator is used, an oscillation start will require sufficient conditions.
Test conditions
Rev.2.00 May 28, 2004 page 75 of 100
38C2 Group (A Version)
IOH = –1 mA
IOH = –0.25 mA
VCC = 2.5 V
IOH = –5 mA
IOH = –1.5 mA
IOH = –1.25 mA
VCC = 2.5 V
IOL = 10 mA
IOL = 3 mA
IOL = 2.5 mA
VCC = 2.5 V
IOL = 15 mA
IOL = 4 mA
VCC = 2.5 V
VI = VCC
VI = VCC
VI = VCC
VI = VSS
Pull-up “OFF”
VCC = 5.0 V, VI = VSS
Pull-up “ON”
VCC = 3.0 V, VI = VSS
Pull-up “ON”
VI = VSS
VI = VSS
“H” output voltage
P00–P07, P10–P17, P20–P27
“H” output voltage
P30–P37, P40–P47, P50–P57, P60–P62
“L” output voltage
P00–P07, P10–P17, P20–P27, P40–P47,
P50, P51, P54–P57, P60–P62
“L” output voltage
P30–P37, P52, P53
Hysteresis
INT0–INT2, CNTR0, CNTR1, P00–P03, P54–P57
Hysteresis SCLK1, SCLK2, RxD1, RxD2
Hysteresis RESET
“H” input current
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,
P50–P57, P60–P62
“H” input current RESET
“H” input current XIN
“L” input current
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,
P50–P57, P60–P62
“L” input current RESET
“L” input current XIN
Limits
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
µA
µA
Parameter Min.
VCC–2.0
VCC–0.8
VCC–2.0
VCC–0.5
VCC–0.8
–60
–25
Typ.
0.5
0.5
0.5
4.0
–120
–40
–4.0
Max.
2.0
0.5
0.8
2.0
0.8
5.0
5.0
–5.0
–240
–100
–5.0
Symbol UnitTest conditions
VOH
VOH
VOL
VOL
VT+–VT-
VT+–VT-
VT+–VT-
IIH
IIH
IIH
IIL
IIL
IIL
Electrical Characteristics
Table 19 Electrical characteristics (Flash memory version)
(Vcc = 4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Rev.2.00 May 28, 2004 page 76 of 100
38C2 Group (A Version)
RAM hold voltage
Power source current
Limits
Parameter Min.
1.8 Typ.
6.0
5.0
1.0
150
6
125
4
0.1
Max.
5.5
8.6
7.2
2.0
200
10
165
8
1.0
10
Symbol Unit
When clock is stopped
Frequency/2 mode, Vcc = 5 V
f(XIN) = 10 MHz
f(XCIN) = 32.768 kHz
Output transistors “OFF”,
A-D converter in operating
Frequency/2 mode, Vcc = 5 V
f(XIN) = 8 MHz
f(XCIN) = 32.768 kHz
Output transistors “OFF”,
A-D converter in operating
Frequency/2 mode, Vcc = 5 V
f(XIN) = 8 MHz (in WIT state)
f(XCIN) = 32.768 kHz
Output transistors “OFF”,
A-D converter stopped
Low-speed mode, VCC = 5 V,
Ta ≤ 55 °C
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “OFF”
Low-speed mode, VCC = 5 V,
Ta = 25 °C
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “OFF”
Low-speed mode, VCC = 3 V,
Ta ≤ 55 °C
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “OFF”
Low-speed mode, VCC = 3 V,
Ta = 25 °C
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “OFF”
All oscillation stopped
(in STP state)
Output transistors “OFF”
Test conditions
VRAM
ICC
V
mA
mA
mA
µA
µA
µA
µA
µA
µA
Ta = 25 °C
Ta = 85 °C
Table 20 Electrical characteristics (Flash memory version)
(Vcc = 2.5 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
VPP Power source current (at read)
VPP Power source current
(at programming)
VPP Power source current (at erase)
VPP Power source voltage
Limits
Parameter Min.
4.5
Typ. Max.
100
60
30
5.5
Symbol Unit
VPP = VCC, at flash memory mode
At flash memory mode
Test conditions
IPP1
IPP2
IPP3
VPP
µA
mA
mA
V
Table 21 Direct-electrical characteristics (Flash memory version)
(Vcc = 4.5 to 5.5 V, Ta = 25 °C, unless otherwise noted)
Rev.2.00 May 28, 2004 page 77 of 100
38C2 Group (A Version)
A-D Converter Characteristics
Table 22 A-D converter characteristics (Flash memory version)
(Vcc = 2.5 to 5.5 V, Vss = AVSS = 0 V, Ta = –20 to 85 °C, Port state = stopped, unless otherwise noted)
Resolution
Absolute accuracy
(quantification error excluded)
Conversion time
Ladder resistor
Reference input current
Analog input current
Unit
Bits
LSB
µs
kΩ
µA
µA
Limits
Parameter Min.
12
50
Typ.
35
150
Max.
10
±6
±5
±2
tc(XIN)✕121
(Note)
100
200
5.0
Symbol
VCC = VREF = 5 V
AD clock frequency = 5 MHz
10bitAD mode
VCC = VREF = 4 V
AD clock frequency = 4 MHz
10bitAD mode
VCC = VREF = 2.5 V
AD clock frequency = 500 kHz
10bitAD mode, booster effective
VCC = VREF = 5 V
AD clock frequency = 4 MHz
8bitAD mode
VCC = VREF = 2.5 V
AD clock frequency = 1 MHz
8bitAD mode, booster effective
AD conversion clock selection bit :XIN/2,
10bitAD mode
VREF = 5 V
Test conditions
—
—
Tconv
RLADDER
IVREF
IIA
Note: When “Frequency/4, 8 or 16” is selected by the AD conversion clock selection bit, the above conversion time is multiplied by 2, 4 or 8.
LCD Power Supply Characteristics
Table 23 LCD power supply characteristics (when connecting division resistors for LCD power supply) (Flash memory version)
(Vcc = 2.5 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted)
Division resistor
for LCD power supply
(Note)
Unit
kΩ
Limits
Parameter Min. Typ.
200
5
120
90
150
120
170
150
190
170
150
120
170
150
190
170
190
190
Max.
Symbol
RSEL = “10”
RSEL = “11”
LCD drive timing A LCD circuit division ratio = divided by 1 RSEL = “01”
RSEL = “00”
LCD circuit division ratio = divided by 2 RSEL = “01”
RSEL = “00”
LCD circuit division ratio = divided by 4 RSEL = “01”
RSEL = “00”
LCD circuit division ratio = divided by 8 RSEL = “01”
RSEL = “00”
LCD drive timing B LCD circuit division ratio = divided by 1 RSEL = “01”
RSEL = “00”
LCD circuit division ratio = divided by 2 RSEL = “01”
RSEL = “00”
LCD circuit division ratio = divided by 4 RSEL = “01”
RSEL = “00”
LCD circuit division ratio = divided by 8 RSEL = “01”
RSEL = “00”
Test conditions
RLCD
Note: The value is the average of each one division resistor.
Rev.2.00 May 28, 2004 page 78 of 100
38C2 Group (A Version)
tw(RESET)
tc(XIN)
twH(XIN)
twL(XIN)
tc(XCIN)
twH(XCIN)
twL(XCIN)
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
tc(SCLK)
twH(SCLK)
twL(SCLK)
tsu(RxD-SCLK)
th(SCLK-RxD)
Reset input “L” pulse width
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
Sub clock input cycle time
Sub clock input “H” pulse width
Sub clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0–INT2 input “H” pulse width
INT0–INT2 input “L” pulse width
Serial I/O1, 2 clock input cycle time (Note)
Serial I/O1, 2 clock input “H” pulse width (Note)
Serial I/O1, 2 clock input “L” pulse width (Note)
Serial I/O1, 2 input setup time
Serial I/O1, 2 input hold time
tw(RESET)
tc(XIN)
twH(XIN)
twL(XIN)
tc(XCIN)
twH(XCIN)
twL(XCIN)
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
tc(SCLK)
twH(SCLK)
twL(SCLK)
tsu(RxD-SCLK)
th(SCLK-RxD)
Limits
µs
ns
ns
ns
ns
ns
ns
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter Min.
2
100
1000(4 ✕ Vcc - 8)
40
45
40
45
20
9
9
200
1000(2 ✕ Vcc - 4)
85
105
85
105
80
80
800
370
370
220
100
Typ. Max.
1000
1000
500
500
500
500
Symbol Unit
Limits
µs
ns
ns
ns
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter Min.
2
125
50
50
20
9
9
750/(VCC–1)
tc(CNTR)/2–20
tc(CNTR)/2–20
230
230
2000
950
950
400
200
Typ. Max.
1000
500
500
Symbol Unit
Reset input “L” pulse width
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
Sub clock input cycle time
Sub clock input “H” pulse width
Sub clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0–INT2 input “H” pulse width
INT0–INT2 input “L” pulse width
Serial I/O1, 2 clock input cycle time (Note)
Serial I/O1, 2 clock input “H” pulse width (Note)
Serial I/O1, 2 clock input “L” pulse width (Note)
Serial I/O1, 2 input setup time
Serial I/O1, 2 input hold time
Table 25 Timing requirements 2 (Flash memory version)
(Vcc = 2.5 to 4.0 V, Vss = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Timing Requirements And Switching Characteristics
Table 24 Timing requirements 1 (Flash memory version)
(Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Note : When bit 6 of address 0FE016 or 0FE316 is “1” (clock synchronous).
Divide this value by four when bit 6 of address 0FE016 or 0FE316 is “0” (UART).
Note : When bit 6 of address 0FE016 or 0FE316 is “1” (clock synchronous).
Divide this value by four when bit 6 of address 0FE016 or 0FE316 is “0” (UART).
(4.5 V ≤ VCC ≤ 5.5 V)
(4.0 V ≤ VCC < 4.5 V)
(4.5 V ≤ VCC ≤ 5.5 V)
(4.0 V ≤ VCC < 4.5 V)
(4.5 V ≤ VCC ≤ 5.5 V)
(4.0 V ≤ VCC < 4.5 V)
(4.5 V ≤ VCC ≤ 5.5 V)
(4.0 V ≤ VCC < 4.5 V)
(4.5 V ≤ VCC ≤ 5.5 V)
(4.0 V ≤ VCC < 4.5 V)
(4.5 V ≤ VCC ≤ 5.5 V)
(4.0 V ≤ VCC < 4.5 V)
Rev.2.00 May 28, 2004 page 79 of 100
38C2 Group (A Version)
twH(SCLK)
twL(SCLK)
td(SCLK-TxD)
tV(SCLK-TxD)
tr(SCLK)
tf(SCLK)
tr(CMOS)
tf(CMOS)
twH(SCLK)
twL(SCLK)
td(SCLK-TxD)
tV(SCLK-TxD)
tr(SCLK)
tf(SCLK)
tr(CMOS)
tf(CMOS)
Limits
Parameter Min.
tc(SCLK)/2–30
tc(SCLK)/2–30
–30
Typ.
25
15
15
Max.
140
30
30
40
30
30
Symbol Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes 1: When the P-channel output disable bit (bit 4 of address 0FE116 or 0FE416) is “0.”
2: The XOUT, XCOUT pins are excluded.
Serial I/O1, 2 clock output “H” pulse width
Serial I/O1, 2 clock output “L” pulse width
Serial I/O1, 2 output delay time (Note 1)
Serial I/O1, 2 output valid time (Note 1)
Serial I/O1, 2 clock output rising time
Serial I/O1, 2 clock output falling time
CMOS output rising time
CMOS output falling time
Table 26 Switching characteristics 1 (Flash memory version)
(Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Limits
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter Min.
tC(SCLK)/2–80
tC(SCLK)/2–80
–30
Typ.
60
40
40
Max.
400
80
80
120
80
80
Symbol Unit
Serial I/O1, 2 clock output “H” pulse width
Serial I/O1, 2 clock output “L” pulse width
Serial I/O1, 2 output delay time (Note 1)
Serial I/O1, 2 output valid time (Note 1)
Serial I/O1, 2 clock output rising time
Serial I/O1, 2 clock output falling time
CMOS output rising time
CMOS output falling time
Table 27 Switching characteristics 2 (Flash memory version)
(Vcc = 2.5 to 4.0 V, Vss = 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Notes 1: When the P-channel output disable bit (bit 4 of address 0FE116 or 0FE416) is “0.”
2: The XOUT, XCOUT pins are excluded.
Fig. 71 Circuit for measuring output switching characteristics
P00–P07, P10–P17, P20–P27 (Note 2)
P30–P37, P40–P47, P50–P57, P60–P62
(Note 2)
P00–P07, P10–P17, P20–P27 (Note 2)
P30–P37, P40–P47, P50–P57, P60–P62
(Note 2)
P00–P07, P10–P17, P20–P27 (Note 2)
P30–P37, P40–P47, P50–P57, P60–P62
(Note 2)
P00–P07, P10–P17, P20–P27 (Note 2)
P30–P37, P40–P47, P50–P57, P60–P62
(Note 2)
M
e
a
s
u
r
e
m
e
n
t
o
u
t
p
u
t
p
i
n
1
0
0
p
F
CMOS output
Measurement output pin
1
0
0
p
F
N-channel open-drain output (Note)
1kΩ
Note: When bit 4 of the UART control register
(address 0EF1
16
or 0FE4
16
) is “ 1.”
(N-channel open-drain output mode)
Rev.2.00 May 28, 2004 page 80 of 100
38C2 Group (A Version)
Fig. 72 Timing chart
0.2V
CC
t
d
(
S
C
L
K
-
T
X
D
)
t
f
0
.
2
V
C
C
0.8V
CC
0.8V
CC
t
r
t
su
(R
X
D-S
CLK
)t
h
(S
CLK
-R
X
D)
t
v
(
S
C
L
K
-
T
X
D
)
t
C
(
S
C
L
K
)
t
WL
(S
CLK
) t
WH
(S
CLK
)
TXD1
TXD2
RXD1
RXD2
SCLK1
SCLK2
0.2V
CC
t
W
L
(
X
I
N
)
0.8V
CC
t
WH
(X
IN
)t
C
(
X
I
N
)
XIN
0
.
2
V
C
C
0
.
8
V
C
C
t
W
(RESET)
R
E
S
E
T
C
N
T
R0,
C
N
T
R10
.
2
V
C
C
t
WL
(CNTR)
0.8V
CC
t
W
H
(
C
N
T
R
)
t
C
(
C
N
T
R
)
I
N
T0
t
o
I
N
T20
.
2
V
C
C
t
W
L
(
I
N
T
)
0.8V
CC
t
W
H
(
I
N
T
)
0.2V
CC
t
WL
(X
CIN
)
0.8V
CC
t
WH
(X
CIN
)t
C
(
X
C
IN
)
XC
IN
Rev.2.00 May 28, 2004 page 81 of 100
38C2 Group (A Version)
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Table 28 Absolute maximum ratings (Mask ROM version)
Parameter
Power source voltage
Input voltage P00–P07, P10–P17, P20–P27, P30–P37,
P40–P47, P50–P57, P60–P62
Input voltage VL1
Input voltage VL2
Input voltage VL3
Input voltage RESET, XIN, CNVSS
Output voltage P00–P07, P10–P17, P20–P27
Output voltage COM0–COM3
Output voltage P30–P37, P40–P47, P50–P57, P60–P62
Output voltage XOUT
Power dissipation
Operating temperature
Storage temperature
Symbol
VCC
VI
VI
VI
VI
VI
VO
VO
VO
VO
Pd
Topr
Tstg
Conditions
All voltages are based on Vss.
Output transistors are cut off.
At output port
At segment output
Ta = 25°C
Ratings
–0.3 to 6.5
–0.3 to VCC+0.3
–0.3 to VL2
VL1 to VL3
VL2 to 6.5
–0.3 to VCC+0.3
–0.3 to VCC+0.3
–0.3 to VL3+0.3
–0.3 to VL3+0.3
–0.3 to VCC+0.3
–0.3 to VCC+0.3
300
–20 to 85
–40 to 125
Unit
V
V
V
V
V
V
V
V
V
V
V
mW
°C
°C
Rev.2.00 May 28, 2004 page 82 of 100
38C2 Group (A Version)
Recommended Operating Conditions
Table 29 Recommended operating conditions (Mask ROM version)
(Vcc = 1.8 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Power source voltage f(φ) = 5 MHz
(Note 1) f(φ) = 4 MHz
f(φ) = 2 MHz
f(φ) = 1 MHz
Low-speed mode
Oscillation start voltage (Note 2)
Power source voltage
Power source voltage for LCD
A-D converter reference voltage
Analog power source voltage
Analog input voltage AN0–AN7
“H” input voltage P04–P07, P10–P17, P20–P27, P30, P32, P35,
P36, P40–P47, P52, P53, P62
“H” input voltage P00–P03, P31, P33, P34, P37, P50, P51,
P54–P57, P60, P61
“H” input voltage RESET
“H” input voltage XIN
“H” input voltage XCIN (Note 3)
“L” input voltage P04–P07, P10–P17, P20–P27, P30, P32,P35,
P36, P40–P47, P52, P53, P62
“L” input voltage P00–P03, P31, P33, P34, P37, P50, P51,
P54–P57, P60, P61, CNVSS
“L” input voltage RESET
“L” input voltage XIN
“L” input voltage XCIN (Note 4)
VCC
VSS
VL3
VREF
AVSS
VIA
VIH
VIH
VIH
VIH
VIH
VIL
VIL
VIL
VIL
VIL
Limits
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Parameter Min.
4.5
4.0
2.0
1.8
1.8
0.15 ✕ f + 1.3
2.5
2.0
AVSS
0.7VCC
0.8VCC
0.8VCC
65 ✕ VCC–99
100
0.8Vcc
1.5
0
0
0
0
0
0
Typ.
5.0
5.0
5.0
5.0
5.0
0
0
Max.
5.5
5.5
5.5
5.5
5.5
5.5
VCC
VCC
VCC
VCC
VCC
VCC
VCC
VCC
0.3VCC
0.2VCC
0.2VCC
65 ✕ VCC–99
100
0.2Vcc
0.4
Symbol Unit
2.2 V ≤ VCC ≤ 5.5 V
VCC ≤ 2.2 V
2.2 V ≤ VCC ≤ 5.5 V
VCC ≤ 2.2 V
VCC –
Notes 1: When using the A-D converter, refer to “A-D Converter Characteristics”.
2: The oscillation start voltage and the oscillation start time differ in accordance with an oscillation start time differ accordance with an oscillator, a circuit
constant, or temperature, etc. When power supply voltage is low and the high frequency oscillator is used, an oscillation start will require sufficient
conditions.
f: This is an oscillator’s oscillation frequency (≥ 1 MHz). For example, when oscillation frequency is 8 MHz, substitute “8”.
3: When the XCIN/P61 pin is not connected to an oscillator, refer to VIH for P61.
4: When the XCIN/P61 pin is not connected to an oscillator, refer to VIL for P61.
Rev.2.00 May 28, 2004 page 83 of 100
38C2 Group (A Version)
“H” total peak output current (Note 1)
P00–P07, P10–P17, P20–P27, P30–P37
“H” total peak output current (Note 1)
P40–P47, P50–P57, P60–P62
“L” total peak output current (Note 1)
P00–P07, P10–P17, P20–P27
“L” total peak output current (Note 1)
P40–P47, P50, P51, P54–P57, P60–P62
“L” total peak output current (Note 1)
P30–P37, P52, P53
“H” total average output current (Note 1)
P00–P07, P10–P17, P20–P27, P30–P37
“H” total average output current (Note 1)
P40–P47, P50–P57, P60–P62
“L” total average output current (Note 1)
P00–P07, P10–P17, P20–P27
“L” total average output current (Note 1)
P40–P47, P50, P51, P54–P57, P60–P62
“L” total average output current (Note 1)
P30–P37, P52, P53
“H” peak output current (Note 2)
P00–P07, P10–P17, P20–P27
“H” peak output current (Note 2)
P30–P37, P40–P47, P50–P57, P60–P62
“L” peak output current (Note 2)
P00–P07, P10–P17, P20–P27
“L” peak output current (Note 2)
P40–P47, P50, P51, P54–P57, P60–P62
“L” peak output current (Note 2)
P30–P37, P52, P53
“H” average output current (Note 3)
P00–P07, P10–P17, P20–P27
“H” average output current (Note 3)
P30–P37, P40–P47, P50–P57, P60–P62
“L” average output current (Note 3)
P00–P07, P10–P17, P20–P27
“L” average output current (Note 3)
P40–P47, P50, P51, P54–P57, P60–P62
“L” average output current (Note 3)
P30–P37, P52, P53
ΣIOH(peak)
ΣIOH(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOL(peak)
ΣIOH(avg)
ΣIOH(avg)
ΣIOL(avg)
ΣIOL(avg)
ΣIOL(avg)
IOH(peak)
IOH(peak)
IOL(peak)
IOL(peak)
IOL(peak)
IOH(avg)
IOH(avg)
IOL(avg)
IOL(avg)
IOL(avg)
Limits
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
Parameter Min. Typ. Max.
Symbol Unit
–20
–20
20
20
110
–10
–10
10
10
90
–1.0
–5.0
10
10
30
–0.5
–2.5
5.0
5.0
15
Table 30 Recommended operating conditions (Mask ROM version)
(Vcc = 1.8 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over
100 ms. The total peak current is the peak value of all the currents.
2: The peak output current is the peak current flowing in each port.
3: The average output current is average value measured over 100 ms.
Rev.2.00 May 28, 2004 page 84 of 100
38C2 Group (A Version)
Table 31 Recommended operating conditions (Mask ROM version)
(Vcc = 1.8 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Timer X and Timer Y
Input frequency (duty cycle 50%)
Timer X, Timer Y, Timer 1, Timer 2, Timer 3 and
Timer 4 Clock input frequency
(Count source frequency of each timer)
System clock φ frequency
Main clock input oscillation frequency (Notes 1, 3)
Sub-clock input oscillation frequency (Notes 1, 2, 3)
f(CNTR0)
f(CNTR1)
f(Tclk)
f(φ)
f(XIN)
f(XCIN)
Limits
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
kHz
Parameter Min.
1.0
1.0
1.0
Typ.
32.768
Max.
5.0
2✕VCC–4
VCC
5✕VCC–8
10.0
4✕VCC–8
2✕VCC
10✕VCC–16
5.0
2✕VCC–4
VCC
5✕VCC–8
10.0
8.0
20✕VCC–32
50
Symbol Unit
(4.5 V ≤ VCC ≤ 5.5 V)
(4.0 V ≤ VCC < 4.5 V)
(2.0 V ≤ VCC < 4.0 V)
(VCC < 2.0 V)
(4.5 V ≤ VCC ≤ 5.5 V)
(4.0 V ≤ VCC < 4.5 V)
(2.0 V ≤ VCC < 4.0 V)
(VCC < 2.0 V)
(4.5 V ≤ VCC ≤ 5.5 V)
(4.0 V ≤ VCC < 4.5 V)
(2.0 V ≤ VCC < 4.0 V)
(VCC < 2.0 V)
(4.5 V ≤ VCC ≤ 5.5 V)
(2.0 V ≤ VCC < 4.5 V)
(VCC < 2.0 V)
Notes 1: When the oscillation frequency has a duty cycle of 50%.
2: When using the microcomputer in low-speed mode, set the clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3.
3: The oscillation start voltage and the oscillation start time differ in accordance with an oscillator, a circuit constant, or temperature, etc. When power supply
voltage is low and the high frequency oscillator is used, an oscillation start will require sufficient conditions.
Rev.2.00 May 28, 2004 page 85 of 100
38C2 Group (A Version)
IOH = –1 mA
IOH = –0.25 mA
VCC = 1.8 V
IOH = –5 mA
IOH = –1.5 mA
IOH = –1.25 mA
VCC = 1.8 V
IOL = 10 mA
IOL = 3 mA
IOL = 2.5 mA
VCC = 1.8 V
IOL = 15 mA
IOL = 4 mA
VCC = 1.8 V
VI = VCC
VI = VCC
VI = VCC
VI = VSS
Pull-up “OFF”
VCC = 5.0 V, VI = VSS
Pull-up “ON”
VCC = 1.8 V, VI = VSS
Pull-up “ON”
VI = VSS
VI = VSS
“H” output voltage
P00–P07, P10–P17, P20–P27
“H” output voltage
P30–P37, P40–P47, P50–P57, P60–P62
“L” output voltage
P00–P07, P10–P17, P20–P27, P40–P47,
P50, P51, P54–P57, P60–P62
“L” output voltage
P30–P37, P52, P53
Hysteresis
INT0–INT2, CNTR0, CNTR1, P00–P03, P54–P57
Hysteresis SCLK1, SCLK2, RxD1, RxD2
Hysteresis RESET
“H” input current
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,
P50–P57, P60–P62
“H” input current RESET
“H” input current XIN
“L” input current
P00–P07, P10–P17, P20–P27, P30–P37, P40–P47,
P50–P57, P60–P62
“L” input current RESET
“L” input current XIN
Limits
V
V
V
V
V
V
V
V
V
V
V
V
V
µA
µA
µA
µA
µA
µA
µA
µA
Parameter Min.
VCC–2.0
VCC–0.8
VCC–2.0
VCC–0.5
VCC–0.8
–60
–5.0
Typ.
0.5
0.5
0.5
4.0
–120
–20
–4.0
Max.
2.0
0.5
0.8
2.0
0.8
5.0
5.0
–5.0
–240
–40
–5.0
Symbol UnitTest conditions
VOH
VOH
VOL
VOL
VT+–VT-
VT+–VT-
VT+–VT-
IIH
IIH
IIH
IIL
IIL
IIL
Electrical Characteristics
Table 32 Electrical characteristics (Mask ROM version)
(Vcc = 4.0 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Rev.2.00 May 28, 2004 page 86 of 100
38C2 Group (A Version)
RAM hold voltage
Power source current
Limits
Parameter Min.
1.8 Typ.
3.4
2.7
1.0
14
6
8
4
0.1
Max.
5.5
5.1
4.2
2.0
21
10
13
8
1.0
10
Symbol Unit
When clock is stopped
Frequency/2 mode, Vcc = 5 V
f(XIN) = 10 MHz
f(XCIN) = 32.768 kHz
Output transistors “OFF”,
A-D converter in operating
Frequency/2 mode, Vcc = 5 V
f(XIN) = 8 MHz
f(XCIN) = 32.768 kHz
Output transistors “OFF”,
A-D converter in operating
Frequency/2 mode, Vcc = 5 V
f(XIN) = 8 MHz (in WIT state)
f(XCIN) = 32.768 kHz
Output transistors “OFF”,
A-D converter stopped
Low-speed mode, VCC = 5 V,
Ta ≤ 55 °C
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “OFF”
Low-speed mode, VCC = 5 V,
Ta = 25 °C
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “OFF”
Low-speed mode, VCC = 3 V,
Ta ≤ 55 °C
f(XIN) = stopped
f(XCIN) = 32.768 kHz
Output transistors “OFF”
Low-speed mode, VCC = 3 V,
Ta = 25 °C
f(XIN) = stopped
f(XCIN) = 32.768 kHz (in WIT state)
Output transistors “OFF”
All oscillation stopped
(in STP state)
Output transistors “OFF”
Test conditions
VRAM
ICC
V
mA
mA
mA
µA
µA
µA
µA
µA
µA
Ta = 25 °C
Ta = 85 °C
Table 33 Electrical characteristics (Mask ROM version)
(Vcc = 1.8 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Rev.2.00 May 28, 2004 page 87 of 100
38C2 Group (A Version)
A-D Converter Characteristics
Table 34 A-D converter characteristics (Mask ROM version)
(Vcc = 2.2 to 5.5 V, Vss = AVSS = 0 V, Ta = –20 to 85°C, Port state = stopped, unless otherwise noted)
Resolution
Absolute accuracy
(quantification error excluded)
Conversion time
Ladder resistor
Reference input current
Analog input current
Unit
Bits
LSB
µs
kΩ
µA
µA
Limits
Parameter Min.
12
50
Typ.
35
150
Max.
10
±5
±4
±2
tc(XIN)✕121
(Note)
100
200
5.0
Symbol
VCC = VREF = 5 V
AD clock frequency = 5 MHz
10bitAD mode
VCC = VREF = 4 V
AD clock frequency = 4 MHz
10bitAD mode
VCC = VREF = 2.2 V
AD clock frequency = 500 kHz
10bitAD mode, booster effective
VCC = VREF = 5 V
AD clock frequency = 4 MHz
8bitAD mode
VCC = VREF = 2.2 V
AD clock frequency = 1 MHz
8bitAD mode, booster effective
AD conversion clock selection bit :XIN/2,
10bitAD mode
VREF = 5 V
Test conditions
—
—
Tconv
RLADDER
IVREF
IIA
Note: When “Frequency/4, 8 or 16” is selected by the AD conversion clock selection bit, the above conversion time is multiplied by 2, 4 or 8.
LCD Power Supply Characteristics
Table 35 LCD power supply characteristics (when connecting division resistors for LCD power supply) (Mask ROM version)
(Vcc = 1.8 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)
Division resistor
for LCD power supply
(Note)
Unit
kΩ
Limits
Parameter Min. Typ.
200
5
120
90
150
120
170
150
190
170
150
120
170
150
190
170
190
190
Max.
Symbol
RSEL = “10”
RSEL = “11”
LCD drive timing A LCD circuit division ratio = divided by 1 RSEL = “01”
RSEL = “00”
LCD circuit division ratio = divided by 2 RSEL = “01”
RSEL = “00”
LCD circuit division ratio = divided by 4 RSEL = “01”
RSEL = “00”
LCD circuit division ratio = divided by 8 RSEL = “01”
RSEL = “00”
LCD drive timing B LCD circuit division ratio = divided by 1 RSEL = “01”
RSEL = “00”
LCD circuit division ratio = divided by 2 RSEL = “01”
RSEL = “00”
LCD circuit division ratio = divided by 4 RSEL = “01”
RSEL = “00”
LCD circuit division ratio = divided by 8 RSEL = “01”
RSEL = “00”
Test conditions
RLCD
Note: The value is the average of each one division resistor.
Rev.2.00 May 28, 2004 page 88 of 100
38C2 Group (A Version)
Reset input “L” pulse width
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
Sub clock input cycle time
Sub clock input “H” pulse width
Sub clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0–INT2 input “H” pulse width
INT0–INT2 input “L” pulse width
Serial I/O1, 2 clock input cycle time (Note)
Serial I/O1, 2 clock input “H” pulse width (Note)
Serial I/O1, 2 clock input “L” pulse width (Note)
Serial I/O1, 2 input setup time
Serial I/O1, 2 input hold time
tw(RESET)
tc(XIN)
twH(XIN)
twL(XIN)
tc(XCIN)
twH(XCIN)
twL(XCIN)
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
tc(SCLK)
twH(SCLK)
twL(SCLK)
tsu(RxD-SCLK)
th(SCLK-RxD)
Limits
µs
ns
ns
ns
ns
ns
ns
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter Min.
2
100
1000/(4 ✕ Vcc – 8)
40
45
40
45
20
9
9
200
1000/(2 ✕ Vcc – 4)
85
105
85
105
80
80
800
370
370
220
100
Typ. Max.
1000
1000
500
500
500
500
Symbol Unit
Timing Requirements And Switching Characteristics
Table 36 Timing requirements 1 (Mask ROM version)
(Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Note : When bit 6 of address 0FE016 or 0FE316 is “1” (clock synchronous).
Divide this value by four when bit 6 of address 0FE016 or 0FE316 is “0” (UART).
(4.5 V ≤ VCC ≤ 5.5 V)
(4.0 V ≤ VCC < 4.5 V)
(4.5 V ≤ VCC ≤ 5.5 V)
(4.0 V ≤ VCC < 4.5 V)
(4.5 V ≤ VCC ≤ 5.5 V)
(4.0 V ≤ VCC < 4.5 V)
(4.5 V ≤ VCC ≤ 5.5 V)
(4.0 V ≤ VCC < 4.5 V)
(4.5 V ≤ VCC ≤ 5.5 V)
(4.0 V ≤ VCC < 4.5 V)
(4.5 V ≤ VCC ≤ 5.5 V)
(4.0 V ≤ VCC < 4.5 V)
Rev.2.00 May 28, 2004 page 89 of 100
38C2 Group (A Version)
tw(RESET)
tc(XIN)
twH(XIN)
twL(XIN)
tc(XCIN)
twH(XCIN)
twL(XCIN)
tc(CNTR)
twH(CNTR)
twL(CNTR)
twH(INT)
twL(INT)
tc(SCLK)
twH(SCLK)
twL(SCLK)
tsu(RxD-SCLK)
th(SCLK-RxD)
Limits
µs
ns
ns
ns
ns
ns
ns
µs
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter Min.
2
125
250/(5✕VCC–8)
50
tc(XIN)/2–12.5
50
tc(XIN)/2–12.5
20
9
9
1000/VCC
1000/(5✕VCC–8)
tc(CNTR)/2–20
tc(CNTR)/2–20
230
230
2000
950
950
400
200
Typ. Max.
1000
1000
500
500
500
500
Symbol Unit
Reset input “L” pulse width
Main clock input cycle time (XIN input)
Main clock input “H” pulse width
Main clock input “L” pulse width
Sub clock input cycle time
Sub clock input “H” pulse width
Sub clock input “L” pulse width
CNTR0, CNTR1 input cycle time
CNTR0, CNTR1 input “H” pulse width
CNTR0, CNTR1 input “L” pulse width
INT0–INT2 input “H” pulse width
INT0–INT2 input “L” pulse width
Serial I/O1, 2 clock input cycle time (Note)
Serial I/O1, 2 clock input “H” pulse width (Note)
Serial I/O1, 2 clock input “L” pulse width (Note)
Serial I/O1, 2 input setup time
Serial I/O1, 2 input hold time
Table 37 Timing requirements 2 (Mask ROM version)
(Vcc = 1.8 to 4.0 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Note : When bit 6 of address 0FE016 or 0FE316 is “1” (clock synchronous).
Divide this value by four when bit 6 of address 0FE016 or 0FE316 is “0” (UART).
2.0 V ≤ VCC ≤ 4.0 V
VCC < 2.0 V
2.0 V ≤ VCC ≤ 4.0 V
VCC < 2.0 V
2.0 V ≤ VCC ≤ 4.0 V
VCC < 2.0 V
2.0 V ≤ VCC ≤ 4.0 V
VCC < 2.0 V
Rev.2.00 May 28, 2004 page 90 of 100
38C2 Group (A Version)
twH(SCLK)
twL(SCLK)
td(SCLK-TxD)
tV(SCLK-TxD)
tr(SCLK)
tf(SCLK)
tr(CMOS)
tf(CMOS)
twH(SCLK)
twL(SCLK)
td(SCLK-TxD)
tV(SCLK-TxD)
tr(SCLK)
tf(SCLK)
tr(CMOS)
tf(CMOS)
Limits
Parameter Min.
tc(SCLK)/2–30
tc(SCLK)/2–30
–30
Typ.
25
15
15
Max.
140
30
30
40
30
30
Symbol Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes 1: When the P-channel output disable bit (bit 4 of address 0FE116 or 0FE416) is “0.”
2: The XOUT, XCOUT pins are excluded.
Serial I/O1, 2 clock output “H” pulse width
Serial I/O1, 2 clock output “L” pulse width
Serial I/O1, 2 output delay time (Note 1)
Serial I/O1, 2 output valid time (Note 1)
Serial I/O1, 2 clock output rising time
Serial I/O1, 2 clock output falling time
CMOS output rising time
CMOS output falling time
Table 38 Switching characteristics 1 (Mask ROM version)
(Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Limits
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter Min.
tC(SCLK)/2–80
tC(SCLK)/2–80
–30
Typ.
60
40
40
Max.
400
80
80
120
80
80
Symbol Unit
Serial I/O1, 2 clock output “H” pulse width
Serial I/O1, 2 clock output “L” pulse width
Serial I/O1, 2 output delay time (Note 1)
Serial I/O1, 2 output valid time (Note 1)
Serial I/O1, 2 clock output rising time
Serial I/O1, 2 clock output falling time
CMOS output rising time
CMOS output falling time
Table 39 Switching characteristics 2 (Mask ROM version)
(Vcc = 1.8 to 4.0 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted)
Notes 1: When the P-channel output disable bit (bit 4 of address 0FE116 or 0FE416) is “0.”
2: The XOUT, XCOUT pins are excluded.
Fig. 73 Circuit for measuring output switching characteristics
P00–P07, P10–P17, P20–P27 (Note 2)
P30–P37, P40–P47, P50–P57, P60–P62
(Note 2)
P00–P07, P10–P17, P20–P27 (Note 2)
P30–P37, P40–P47, P50–P57, P60–P62
(Note 2)
P00–P07, P10–P17, P20–P27 (Note 2)
P30–P37, P40–P47, P50–P57, P60–P62
(Note 2)
P00–P07, P10–P17, P20–P27 (Note 2)
P30–P37, P40–P47, P50–P57, P60–P62
(Note 2)
Measurement output pin
1
0
0
p
F
CMOS output
Measurement output pin
1
0
0
p
F
N-channel open-drain output (Note)
1
kΩ
Note: When bit 4 of the UART control register
(address 0EF1
16
or 0FE4
16
) is “ 1.”
(N-channel open-drain output mode)
Rev.2.00 May 28, 2004 page 91 of 100
38C2 Group (A Version)
Fig. 74 Timing chart
0.2V
CC
t
d
(
S
C
L
K
-
T
X
D
)
t
f
0
.
2
V
C
C
0.8V
CC
0.8V
CC
t
r
t
su
(R
X
D-S
CLK
)t
h
(S
CLK
-R
X
D)
t
v
(
S
C
L
K
-
T
X
D
)
t
C
(
S
C
L
K
)
t
WL
(S
CLK
) t
WH
(S
CLK
)
TXD1
TXD2
RXD1
RXD2
SCLK1
SCLK2
0.2V
CC
t
W
L
(
X
I
N
)
0.8V
CC
t
WH
(X
IN
)t
C
(
X
I
N
)
XIN
0
.
2
V
C
C
0
.
8
V
C
C
t
W
(RESET)
R
E
S
E
T
C
N
T
R0,
C
N
T
R10
.
2
V
C
C
t
WL
(CNTR)
0.8V
CC
t
W
H
(
C
N
T
R
)
t
C
(
C
N
T
R
)
I
N
T0
t
o
I
N
T20
.
2
V
C
C
t
W
L
(
I
N
T
)
0.8V
CC
t
W
H
(
I
N
T
)
0.2V
CC
t
WL
(X
CIN
)
0.8V
CC
t
WH
(X
CIN
)t
C
(
X
C
IN
)
XC
IN
Rev.2.00 May 28, 2004 page 92 of 100
38C2 Group (A Version)
PACKAGE OUTLINE
LQFP64-P-1010-0.5 Weight(g)
—
JEDEC Code
EIAJ Package Code Lead Material
Cu Alloy
64P6Q-A Plastic 64pin 10✕10mm body LQFP
—
0.1
—
——
0.2
—
—
——
—
———
—
Symbol Min Nom Max
A
A
2
b
c
D
E
H
E
L
L
1
y
b
2
Dimension in Millimeters
H
D
A
1
0.225 ——
I
2
1.0 ——
M
D
10.4 ——
M
E
10.4
10¡0¡0.1
1.0 0.70.50.3 12.212.011.8 12.212.011.8 0.5 10.110.09.9 10.110.09.9 0.1750.1250.105 0.280.180.13 1.4
01.7
e
e
E
H
E
49
48 33
32
17
161
64
H
D
D
M
D
M
E
A
F
y
b
2
I
2
Recommended Mount Pad
Lp 0.45
—
—
0.6
0.25
—
0.75
—
0.08
x
A3
bx
M
A
1
A
2
L
1
L
Detail F Lp
A3
c
e
LQFP64-P-1414-0.8 Weight(g)
—
JEDEC Code
EIAJ Package Code Lead Material
Cu Alloy
64P6U-A Plastic 64pin 14✕14mm body LQFP
—
0.1
0.8
—
——
0.2
—
—
——
—
———
—
Symbol Min Nom Max
A
A
2
b
c
D
E
H
E
L
L
1
y
b
2
Dimension in Millimeters
H
D
A
1
——
I
2
——
M
D
14.4 ——
M
E
14.4
0¡8¡
0.1
0.2
1.0 0.70.50.3
16.215.8
14.113.9
16.215.8
14.0 14.113.9 14.0
16.0
16.0
0.1750.1250.105 0.450.370.32 1.4
01.7
e
Lp 0.45
0.95
—
—
0.6
0.5
0.25
—
0.75
—
x
A3
Recommended Mount Pad
Detail F
E
H
E
49
1 16
48 33
64
32
17
H
D
D
A
ybx
M
eF
M
D
l
2
b
2
M
E
e
A
1
A
2
L
1
L
Lp
A3
c
Rev.2.00 May 28, 2004 page 93 of 100
38C2 Group (A Version)
APPENDIX
NOTES ON PROGRAMMING
1. Processor status register
(1) Initializing of processor status register
Flags which affect program execution must be initialized after a re-
set.
In particular , it is essential to initialize the T and D flags because they
have an important effect on calculations.
<Reason>
After a reset, the contents of the processor status register (PS) are
undefined except for the I flag which is “1”.
Reset
↓
Initializing of flags
↓
Main program
Fig.1 Initialization of processor status register
(2) How to reference the processor status register
To reference the contents of the processor status register (PS), ex-
ecute the PHP instruction once then read the contents of (S+1). If
necessary, execute the PLP instruction to return the PS to its original
status.
A NOP instruction should be executed after every PLP instruction.
Fig. 2 Sequence of PLP instruction execution
PLP instruction execution
↓
NOP
Fig. 3 Stack memory contents after PHP instruction execution
2. Decimal calculations
(1) Execution of decimal calculations
The ADC and SBC are the only instructions which will yield proper
decimal notation, set the decimal mode flag (D) to “1” with the SED
instruction. After executing the ADC or SBC instruction, execute an-
other instruction before executing the SEC, CLC, or CLD instruction.
(
S
)
(
S
)
+
1 S
t
o
r
e
d
P
S
(2) Notes on status flag in decimal mode
When decimal mode is selected, the values of three of the flags in
the status register (the N, V, and Z flags) are invalid after a ADC or
SBC instruction is executed.
The carry flag (C) is set to “1” if a carry is generated as a result of the
calculation, or is cleared to “0” if a borrow is generated. To determine
whether a calculation has generated a carry, the C flag must be ini-
tialized to “0” before each calculation. To check for a borrow, the C
flag must be initialized to “1” before each calculation.
Set D flag to “1”
↓
ADC or SBC instruction
↓
NOP instruction
↓
SEC, CLC, or CLD instruction
Fig. 4 Status flag at decimal calculations
3. JMP instruction
When using the JMP instruction in indirect addressing mode, do not
specify the last address on a page as an indirect address.
4. BRK instruction
When the BRK instruction is executed with the following conditions
satisfied, the interrupt execution is started from the address of
interrupt vector which has the highest priority.
• Interrupt request bit and interrupt enable bit are set to “1”.
• Interrupt disable flag (I) is set to “1” to disable interrupt.
5. Multiplication and Division Instructions
• The index X mode (T) and the decimal mode (D) flags do not af fect
the MUL and DIV instruction.
• The execution of these instructions does not change the contents
of the processor status register.
6. Read-modify-write instruction
Do not execute a read-modify-write instruction to the read invalid
address (memory and SFR).
The read-modify-write instruction operates in the following sequence:
read one-byte of data from memory, modify the data, write the data
back to original memory. The following instructions are classified as
the read-modify-write instructions in the 740 Family.
• Bit management instructions: CLB, SEB
• Shift and rotate instructions: ASL, LSR, ROL, ROR, RRF
• Add and subtract instructions: DEC, INC
• Logical operation instructions (1’s complement): COM
Add and subtract/logical operation instructions (ADC, SBC, AND,
EOR, and ORA) when T flag = “1” operate in the way as the read-
modify-write instruction. Do not execute the read invalid memory and
SFR.
<Reason>
When the read-modify-write instruction is executed to read invalid
memory and SFR, the instruction may cause the following conse-
quence: the instruction reads unspecified data from the memory due
to the read invalid condition. Then the instruction modifies this un-
specified data and writes the data to the memory. The result will be
random data written to the memory or some unexpected event.
Rev.2.00 May 28, 2004 page 94 of 100
38C2 Group (A Version)
NOTES ON PERIPHERAL FUNCTIONS
Notes on I/O Ports
1. Pull-up control register
When using each port which built in pull-up resistor as an output
port, the pull-up control bit of corresponding port becomes invalid,
and pull-up resistor is not connected.
<Reason>
Pull-up control is effective only when each direction register is set to
the input mode.
2. Modifying output data with bit managing instruction
When the port latch of an I/O port is modified with the bit managing
instruction (Note), the value of the unspecified bit may be changed.
<Reason>
I/O ports can be set to input or output mode in a bit unit. When read-
ing or writing are performed to the port Pi (i = 0–7) register , the micro-
computer operates as follows.
• Port in input mode
-Read-access: reads pin’s level (The contents of port latch and
pin’s level are unrelated.)
-Write-access: writes data to port latch (The contents of port latch
and pin’s level are unrelated.)
• Port in output mode
-Read-access: reads port latch (The contents of port latch and pin’s
level are unrelated.)
-Write-access: writes data to port latch (The contents of port latch
are output from the pin.)
The bit managing instructions are read-modify-write form instructions
for reading and writing data by a byte unit.
Therefore, when the bit managing instructions are executed to the
port set to input mode, the instruction read the pin’s states, modify
the specification bit, and then write data to the port latch. At this time,
if the contents of the original port latch are different from the pins’s
level, the contents of the port latch of bit which is not specified by
instruction will change.
In addition to this, if the bit managing instructions are executed to the
port Pi register in order to setting output data when port Pi is config-
ured as a mixed input and output port, the contents of the port latch
of bit in the input mode which is not specified by instruction may
change.
Note: Bit managing instructions: SEB instruction, CLB instruction
3. Port direction register
The port direction registers are write-only registers. Therefore, the
following instructions cannot be used to this register:
• LDA instruction
• Memory operation instruction when T flag is “1”
• Instructions operating in addressing mode that modifies direction
register
• Bit test instructions such as BBC and BBS
• Bit modification instructions such as CLB and SEB
• Arithmetic instructions using read-modify-write form instructions such
as ROR
The LDM, STA instructions etc. are used for setting of the direction
register.
Notes on Termination of Unused Pins
1. Terminate unused pins
Perform the following wiring at the shortest possible distance (20
mm or less) from microcomputer pins.
(1) I/O ports
Set the I/O ports for the input mode and connect each pin to VCC or
VSS through each resistor of 1 kΩ to 10 kΩ. The port which can se-
lect a built-in pull-up resistor can also use the built-in pull-up resistor .
When using the I/O ports as the output mode, open them at “L” or
“H”.
• When opening them in the output mode, the input mode of the initial
status remains until the mode of the ports is switched over to the
output mode by the program after reset. Thus, the potential at these
pins is undefined and the power source current may increase in the
input mode. With regard to an effects on the system, thoroughly
perform system evaluation on the user side.
• Since the direction register setup may be changed because of a
program runaway or noise, set direction registers by program peri-
odically to increase the reliability of program.
2. Termination remarks
(1) Input ports
Do not open them.
<Reason>
• If the input level is undefined, the power source current may in-
crease.
• An ef fect due to noise may be easily produced as compared with “1.
(1) I/O ports“ shown on the above.
(2) I/O ports setting as input mode
[1] Do not open in the input mode.
<Reason>
• The power source current may increase depending on the first-
stage circuit.
• An ef fect due to noise may be easily produced as compared with “1.
(1) I/O ports“ shown on the above.
[2] I/O ports :
Do not connect to VCC or VSS directly.
<Reason>
If the direction register setup changes for the output mode because
of a program runaway or noise, a short circuit may occur.
[3] I/O ports :
Do not connect multiple ports in a lump to VCC or VSS through a
resistor.
<Reason>
If the direction register setup changes for the output mode because
of a program runaway or noise, a short circuit may occur between
ports.
Rev.2.00 May 28, 2004 page 95 of 100
38C2 Group (A Version)
Fig. 5 Sequence of changing relevant register
<Reason>
When setting the followings, the interrupt request bit may be set to “1”.
•When selecting external interrupt active edge
INT0 interrupt edge selection bit
(bit 0 of interrupt edge selection register (address 003A16))
INT1 interrupt edge selection bit
(bit 1 of interrupt edge selection register (address 003A16))
INT2 interrupt edge selection bit
(bit 2 of interrupt edge selection register (address 003A16))
CNTR0 active edge switch bit
(bit 6 of timer X control register (address 0FF416))
CNTR1 active edge switch bit
(bit 6 of timer Y mode register (address 003016))
•When switching interrupt sources of an interrupt vector address
where two or more interrupt sources are allocated
Interrupt edge selection register (address 003A16)
3. Check of interrupt request bit
When executing the BBC or BBS instruction to an interrupt request
bit of an interrupt request register immediately after this bit is set to
“0”, take the following sequence.
<Reason>
If the BBC or BBS instruction is executed immediately after an inter-
rupt request bit of an interrupt request register is cleared to “0”, the
value of the interrupt request bit before being cleared to “0” is read.
Set the corresponding interrupt enable bit to “0” (disabled) .
↓
Set the interrupt edge select bit, active edge switch bit, or the
interrupt source select bit.
↓
NOP (One or more instructions)
↓
Set the corresponding interrupt request bit to “0”
(no interrupt request issued).
↓
Set the corresponding interrupt enable bit to “1” (enabled).
Set the interrupt request bit to “0” (no interrupt issued)
↓
NOP (one or more instructions)
↓
Execute the BBC or BBS instruction
Fig. 6 Sequence of check of interrupt request bit
Notes on Interrupts
1. Unused interrupts
Set the interrupt enable bit for unused interrupts to “0” (disabled).
2. Change of relevant register settings
When not requiring for the interrupt occurrence synchronous with
the following case, take the sequence shown in Figure 5.
•When selecting external interrupt active edge
•When switching interrupt sources of an interrupt vector address
where two or more interrupt sources are allocated
Notes on Timer
1. When n (0 to 255) is written to a timer latch, the frequency divisin
ratio is 1/(n+1).
2. The timers share the one frequency divider to generate the count
source. Accordingly, when each timer starts operating, initializing
the frequency divider is not executed. Therefore, when the frequency
divider is selected for the count source, the delay of the maximum
one cycle of the count source is generated until the timer starts
counting or the waveform is output from timer starts operating. Also,
the count source cannot be checked externally.
3. Set the timer which is not used as follows:
• Stop the count (when using a timer with stop control)
• Set “0” to the corresponding interrupt enable bit
Notes on Timer X
1. CNTR0 active edge selection
• The CNTR0 active edge selection bit (bit 6 of timer X mode register)
also effects the active edge of the generation of the CNTR0 inter-
rupt request.
• When the pulse width is measured, set the bit 7 of the CNTR0 ac-
tive edge switch bits to “0”.
2. Write order to timer X
• In the timer mode, pulse output mode, event counter mode and
pulse width measurement mode, write to the following registers in
the order as shown below;
the timer X register (extension),
the timer X register (low-order),
the timer X register (high-order).
Do not write to only one of them.
When the above mode is set and timer X operates as the 16-bit
counter, if the timer X register (extension) is never set after reset is
released, setting the timer X register (extension) is not required. In
this case, write the timer X register (low-order) first and the timer X
register (high-order). However, once writing to the timer X register
(extension) is executed, note that the value is retained to the reload
latch.
• In the IGBT output and PWM modes, do not write “1” to the timer X
register (extension). Also, when “1” is already written to the timer X
register, be sure to write “0” to the register before using.
Write to the following registers in the order as shown below;
the compare register (high- and low-order),
the timer X register (extension),
the timer X register (low-order),
the timer X register (high-order).
It is possible to use whichever order to write to the compare regis-
ter (high- and low-order). However, write both the compare register
and the timer X register at the same time.
Rev.2.00 May 28, 2004 page 96 of 100
38C2 Group (A Version)
3. Read order to timer X
• In all modes, read the following registers in the order as shown
below;the timer X register (extension),
the timer X register (high-order),
the timer X register (low-order).
When reading the timer X register (extension) is not required, read
the timer X register (high-order) first and the timer X register (low-
order). Read order to the compare register is not specified.
• If reading to the timer X register during write operation or writing to
it during read operation is performed, normal operation will not be
performed.
4. Write to timer X
• Which write control can be selected by the timer X write control bit
(b3) of the timer X mode register (address 002F16), writing data to
both the latch and the timer at the same time or writing data only to
the latch. When writing a value to the timer X address to write to the
latch only, the value is set into the reload latch and the timer is
updated at the next underflow. After reset release, when writing a
value to the timer X address, the value is set into the timer and the
timer latch at the same time, because they are written at the same
time.
When writing to the latch only, if the write timing to the high-order
reload latch and the underflow timing are almost the same, the value
is set into the timer and the timer latch at the same time. In this
time, counting is stopped during writing to the high-order reload
latch.
• Do not switch the timer count source during timer count operation.
Stop the timer count before switching it.
5. Set of timer X mode register
Set the write control bit of the timer X mode register to “1” (write to
the latch only) when setting the IGBT output and PWM modes.
Output waveform simultaneously reflects the contents of both regis-
ters at the next underflow after writing to the timer X register (high-
order).
6. When selecting timer X pulse width measurement mode
When selecting the timer X pulse width measurement mode, enable
(set “0”) data for the event couter window control (bit 5 of timer X
mode register (address 002F16)).
<Reason>
When data for the event counter window control is set to “1” (dis-
abled), the CNTR0 input is not accepted after timer 1 underflow be-
cause this bit controls the CNTR0 input.
7. IGBT output mode
•Do not write “1” to the timer X register (extension) when using the
IGBT output mode.
•When using the IGBT output mode, set the port sharing the INT0 pin
to input mode and set the port sharing the TXOUT pin to output mode.
When using the output control function (INT1, INT2), set the port
sharing the INT1, INT2 pin to input mode.
• When using the output control function (INT1 and INT2) in the IGBT
output mode, set the levels of INT1 and INT2 to “H” in the falling
edge active or to “L” in the rising edge active before switching to the
IGBT output mode. Set the level of INT0 to “H” in the falling edge
active or to “L” in the rising edge active before switching to the IGBT
output mode.
•When setting the timer X output control bit 1 or 2 (bit 3 or 4 of timer
X control register (address 0FF416)) to “1” and initializing the output
of the TXOUT pin by interrupt signal of INT1 or INT 2, while the output
level from the TXOUT pin changes after setting the timer X output
control bit 1 or 2 to “1”, the following delay will occur.
Minimum: Analog delay
Maximum: Timer X count source 1 cycle + Analog delay
•In the following case, the timer X interrupti request bit (bit 7 of inter-
rupt request register 1 (address 003C16)) is set to “1”.
•When Timer X underflow
•When input from INT0 pin is detected at the time of IGBT output
mode
Notes on Timer Y
1. Timer Y read/write control
• When reading from/writing to timer Y, read from/write to both the
high-order and low-order bytes of timer Y. When the value is read,
read the high-order bytes first and the low-order bytes next. When
the value is written, write the low-order bytes first and the high-
order bytes next.
If reading from the timer Y register during write operation or writing
to it during read operation is performed, normal operation will not
be performed.
• When writing a value to the timer Y address to write to the latch
only, the value is set into the reload latch and the timer is updated at
the next underflow. Normally, when writing a value to the timer Y
address, the value is set into the timer and the timer latch at the
same time, because they are set to write at the same time.
When writing to the latch only, if the write timing to the high-order
reload latch and the underflow timing are almost the same, the value
is set into the timer and the timer latch at the same time. In this time,
counting is stopped during writing to the high-order reload latch.
• Do not switch the timer count source during timer count operation.
Stop the timer count before switching it.
2. CNTR1 interrupt active edge selection
CNTR1 interrupt active edge depends on the CNTR1 active edge
switch bit. However, in pulse width HL continuously measurement
mode, CNTR1 interrupt request is generated at both rising and falling
edges of CNTR1 pin input signal regardless of the setting of CNTR1
active edge switch bit.
Rev.2.00 May 28, 2004 page 97 of 100
38C2 Group (A Version)
Notes on Timers 1 to 4
1. Cascading connection
• When using cascading connection, set the value of timer in the
order of the timer 1 register, the timer 2 register , the timer 3 register,
and the timer 4 register after the count source selection of timer 1 to
4.
<Reason>
• When the count source of timers 1 to 4 is selected, the timer count-
ing value may become arbitrary value because a thin pulse is gen-
erated in count input of timer.
2. Timer 3PWM0 mode, timer 4PWM1 mode
• When PWM output is suspended after starting PWM output, de-
pending on the level of the output pulse at that time to resume an
output, the delay of the one section of the short interval may be
needed.
Stop at “H”: No output delay
Stop at “L”: Output is delayed time of 256 ✕ ts
• In the PWM mode, the follows are performed every cycle of the
long interval (4 ✕ 256 ✕ ts).
• Generation of timer 3, timer 4 interrupt requests
• Update of timer 3, timer 4
• When “L” is output from the P52/T3OUT/PWM0 pin continuously in
the timer 3PMW0 mode, set the P52/T3OUT/PWM0 pin as I/O port
by set the timer 3 output selection bit to “0” before “L” is output.
Do not set “0016” to timer 3 in this mode. The value which can be set
are 1-255.
• When “L” is output from the P53/T4OUT/PWM1 pin continuously in
the timer 4PMW1 mode, set the P53/T4OUT/PWM1 pin as I/O port
by set the timer 4 output selection bit to “0” before “L” is output.
Do not set “0016” to timer 4 in this mode. The value which can be set
are 1-255.
3. Writing to Timer 2, Timer 3, Timer 4
When writing to the latch only, if the write timing to the reload latch
and the underflow timing are almost the same, the value is set into
the timer and the timer latch at the same time. In this time, counting
is stopped during writing to the reload latch.
Notes on Serial I/O1
1. Writing to baud rate generator (BRG)
Write data to BRG while the transmission and reception operations
are stopped.
2. Setting procedure when using serial I/O1 transmit interrupt
When the serial I/O1 transmit interrupt is used, take the following
sequence.
➀Set the serial I/O1 transmit interrupt enable bit (bit 4 of interrupt
control register 1 (address 003E16)) to “0” (disabled).
➁Set the transmit enable bit (bit 4 of serial I/O1 control register (ad-
dress 0FE016)) to “1”.
➂Set the serial I/O1 transmit interrupt request bit (bit 3 of interrupt
request register 1 (address 003C16)) to “0” (no interrupt request
issued) after 1 or more instruction has executed.
➃Set the serial I/O1 transmit interrupt enable bit to “1” (enabled).
<Reason>
When the transmission enable bit is set to “1”, the transmit buffer
empty flag (bit 0 of serial I/O1 status register (address 001D16)) and
the transmit shift register completion flag are set to “1”.
Therefore, the serial I/O1 transmit interrupt request bit is set to “1”
regardless of the state of the transmit interrupt source selection bit
(bit 3 of serial I/O1 control register).
3. Data transmission control with referring to transmit shift register
completion flag
After the transmit data is written to the transmit buffer register (ad-
dress 001816), the transmit shift register completion flag (bit 2 of se-
rial I/O1 status reguster (address 001D16)) changes from “1” to “0”
with a delay of 0.5 to 1.5 shift clocks. When data transmission is
controlled with referring to the flag after writing the data to the trans-
mit buffer register, note the delay.
4. Setting serial I/O1 control register again
Set the serial I/O1 control register again after the transmission and
the reception circuits are reset by setting both the transmit enable bit
and the receive enable bit to “0”.
Fig. 7 Sequence of setting serial I/O1 control register again
Set both the transmit enable bit (TE)
and the receive enable bit (RE) to “0”
↓
Set the bits 0 to 3 and bit 6 of the serial
I/O1 control register
↓
Set both the transmit enable bit (TE)
and the receive enable bit (RE), or one
of them to “1”
Can be set with
the LDM instruc-
tion at the same
time
5. Pin state after transmit completion
The TxD pin holds the state of the last bit of the transmission after
transmission completion. When the internal clock is selected for the
transmit clock in the clock synchronous serial I/O mode, the SCLK1
pin holds “H”.
6. Serial I/O1 enable bit during transmit operation
When the serial I/O1 enable bit (bit 7 of serial I/O1 control register
(address 0FE016)) is set to “0” (serial I/O1 disabled) when data trans-
mission is in progress, the transmission progress internally. How-
ever, the external data transfer is terminated because the pins be-
come regular I/O ports. In addition to this, when data is written to the
transmission buffer register, data transmission is started internally.
When the serial I/O1 enable bit is set to “1”, the transmission is out-
put to the TxD pin in the middle of the transfer.
7. Transmission control when external clock is selected
When an external clock is used as the synchronous clock for data
transmission, set the transmit enable bit to “1” at “H” of the SCLK1
input level. Also, write the transmit data to the transmit buf fer register
at “H” of the SCLK1 input level.
8. Receive operation in clock synchronous serial I/O mode
When receiving data in the clock synchronous serial I/O mode, set
not only the receive enable bit but also the transmit enable bit to “1”.
Then write dummy data to the transmission buffer register. When the
internal clock is selected as the synchronous clock, the synchronous
clock is output at this point and the receive operation is started. When
the external clock is selected as the transfer clock, the serial
I/O becomes ready for data receive at this point and, when the exter-
nal clock is input to the clock input pin, the receive operation is started.
The P45/TxD pin outputs the dummy data written in the transmission
buffer register.
Rev.2.00 May 28, 2004 page 98 of 100
38C2 Group (A Version)
9. Transmit and receive operation in clock synchronous serial I/O
mode
When stopping transmitting and receiving operations in the clock
synchronous serial I/O mode, set the receive enable bit and the trans-
mit enable bit to “0” simultaneously. If only one of them is stopped the
receive or transmit operation may loose synchronization, causing a
bit slippage.
Notes on Serial I/O2
1. Switching synchronous clock
When switching the synchronous clock by the serial I/O2 mode se-
lection bit (bit 6 of serial I/O2 control register (address 0FE316)), ini-
tialize the serial I/O2 counter (write data to transmit/receive buffer
register 2 (address 001E16)).
2. Notes when selecting external clock
When an external clock is selected as the synchronous clock, the
TxD2 pin holds the output level of D7 after transmission is completed.
However , if the clock is input to the serial I/O continuously, the trans-
mit/receive buffer register continue the shift operation and output data
from the TxD2 pin continuously.
A write operation to the transmit/receive buffer register 2 must be
performed when the SCLK2 pin is “H”.
When the internal clock is selected as the synchronous clock, the
TxD2 pin holds the high-impedance state after transmission.
Notes on Programming for Serial I/O
In clock synchronous serial I/O, if the receive side is using an exter-
nal clock and it is to output the SRDY signal, set the transmit enable
bit, the receive enable bit, and the SRDY output enable bit to “1.”
Serial I/O continues to output the final bit from the TXD pin after trans-
mission is completed.
Notes on A-D Converter
1. Analog input pin
Make the signal source impedance for analog input low, or equip an
analog input pin with an external capacitor of 0.01 µF to 1 µF. Fur-
ther, be sure to verify the operation of application products on the
user side.
<Reason>
An analog input pin includes the capacitor for analog voltage com-
parison. Accordingly, when signals from signal source with high im-
pedance are input to an analog input pin, charge and discharge noise
generates. This may cause the A-D conversion precision to be worse.
2. Read A-D conversion register
How to read the A-D conversion register at 10-bit A-D conversion
and 8-bit A-D conversion is shown in Fig. 8.
1
0
-
b
i
t
r
e
a
d
i
n
g
(
R
e
a
d
a
d
d
r
e
s
s
0
0
1
B
1
6
b
e
f
o
r
e
0
0
1
A
1
6
)
A
-
D
c
o
n
v
e
r
s
i
o
n
r
e
g
i
s
t
e
r
1
(
A
d
d
r
e
s
s
0
0
1
B
1
6
)
A
-
D
c
o
n
v
e
r
s
i
o
n
r
e
g
i
s
t
e
r
2
(
A
d
d
r
e
s
s
0
0
1
A
1
6
)
8
-
b
i
t
r
e
a
d
i
n
g
(
R
e
a
d
o
n
l
y
a
d
d
r
e
s
s
0
0
1
B
1
6
)
(
A
d
d
r
e
s
s
0
0
1
B
1
6
)
b0
b
7b
0
b
1
* V
REF
input switch bit
b
9
b8 b
7b
6
b
5
b
4b
3b
2
b
7b
0
b
9
b8 b
7b
6
b
5
b
4b
3b
2
b
7b
0
*
(
h
i
g
h
-
o
r
d
e
r
)
(
l
o
w
-
o
r
d
e
r
)
N
o
t
e
:
T
h
e
b
i
t
5
t
o
b
i
t
1
o
f
a
d
d
r
e
s
s
0
0
1
A
1
6
b
e
c
o
m
e
“
0
”
a
t
r
e
a
d
i
n
g
.
A
l
s
o
,
b
i
t
0
i
s
u
n
d
e
f
i
n
e
d
a
t
r
e
a
d
i
n
g
.
1
:
O
N
0
:
O
N
o
n
l
y
d
u
r
i
n
g
A
-
D
c
o
n
v
e
r
s
i
o
n
Fig. 8 A-D conversion register reading
3. Analog power source input pin AVss
The AVss pin is an analog power source input pin. Regardless of
using the A-D conversion function or not, connect it as following :
• AVSS : Connect to the VSS line
<Reason>
If the AVss pin is opened, the microcomputer may have a failure be-
cause of noise or others.
4. Reference voltage input pin VREF
Connect an approximately 1000 pF capacitor across the AVss pin
and the VREF pin. Besides, connect the capacitor across the VREF
pin and the AVss pin at equal length as close as possible.
5. Clock frequency during A-D conversion
Use the A-D converter in the following conditions:
• Select XIN-XOUT as system clock
φ
by the system clock selection bit
(bit 7 of CPU mode register (address 003B16)). When selecting XCIN-
XCOUT as system clock
φ
, the A-D conversion function cannot be
used.
• f(XIN) is 500 kHz or more.
• Do not execute the STP or WIT instruction during A-D conversion.
<Reason>
The comparator consists of a capacity coupling, and a charge of the
capacity will be lost if the clock frequency is too low. This may cause
the A-D conversion precision to be worse.
6. Write to A-D conversion completion bit durng A-D conversion
When “0” is set to the A-D conversion completion bit by the program
during A-D conversion, re-conversion is performed.
7. Write during A-D conversion
The A-D converter will not operate normally if one of the following
operation is applied during the A-D conversion:
• Writing to CPU mode register
• Writing to A-D control register
8. Notes on programming for A-D conversion
The comparator uses internal capacitors whose charge will be lost if
the clock frequency is too low . Therefore, set the A-D clock frequency
to 250 kHz or more. Also, when the STP instruction is executed dur-
ing the A-D conversion, the A-D conversion is stopped immediately,
the A-D conversion completion bit is set to “1”, and the interrupt re-
quest is generated.
Rev.2.00 May 28, 2004 page 99 of 100
38C2 Group (A Version)
Notes on LCD Drive Control Circuit
1. Count source for LCDCK
The LCDCK count source selection bit (bit 7 of LCD mode register
(address 003916)) is set to “0” after reset, selecting f(XCIN)/32. The
sub clock has stopped after reset. Therefore, turn on LCD after start-
ing the oscillation and stabilizing the oscillation. Select the LCDCK
count source after the corresponding clock source becomes stable.
2. STP instruction
When executing the STP instruction, bits 0 to 5 and bit 7 of the LCD
power supply control register and the LCD enable bit (bit 3 of LCD
mode register) are set to “0”. Set these bits again after returning from
stop mode.
3. When not using LCD
When not using an LCD, leave the LCD segment and common pins
open. Connect the VL1 pin to Vss, and the VL2 and VL3 pins to Vcc.
4. LCD drive power supply
(1) Power supply capacitor may be insufficient with the division resis-
tance for LCD power supply, and the characteristic of the LCD
panel. In this case, there is the method of connecting the bypass
capacitor about 0.1–0.33 µF to VL1–VL3 pins. The example of a
strengthening measure of the LCD drive power supply is shown
in Figure 9.
V
L3
V
L2
V
L1
•Connect by the shortest possible wiring.
•Connect the bypass capacitor to the V
L1
–V
L3
pins
as short as possible.
(Referential value: 0.1–0.33 µF)
38C2 group
(A version)
Fig. 9 Strengthening measure example of LCD drive power
supply
(2) When the LCD drive control circuit is used at VL3 = VCC, apply
VCC to VL3 pin and write “1” to VL3 connection bit (bit 6 of the LCD
power control register (address 003816)).
(3) When the voltage is applied to VL1 to VL3 by using the external
resistor, write “102” to dividing resistor for LCD power selection
bits (RSEL) of the LCD power control register (address 003816).
5. Segment output disable register
(1) Only pins set to output ports by the direction register can be con-
trolled to switch to output ports or segment outputs by the seg-
ment output disable register.
(2) When the VL pin input selection bit (VLSEL) of the LCD power
control register (address 0038
16
) is “1”, settings of the segment
output disable bit 22 and segment output disable bit 23 are in
valid.
6. Data setting to LCD display RAM
When writing a data into the LCD display RAM during LCD being
turned ON (LCD enable bit = “1”), write the confirmed data. Do not
write temporarily on the LCD display RAM because this might cause
the LCD display flickering. Figure 10 shows the write procedure for
LCD display RAM when LCD is on.
Fig. 10 Write procedure for LCD display RAM when LCD is on
Notes on Watchdog Timer
1. The watchdog timer is operating during the wait mode. Write data
to the watchdog timer control register to prevent timer underflow.
2. The watchdog timer stops during the stop mode. However, the
watchdog timer is running during the wait time (time set by timer 1
and timer 2) and the watchdog timer control register must be writ-
ten just before executing the STP instruction.
3. The count source of the watchdog timer is affected by the system
clock
φ
selected by the system clock selection bits (bits 6, 7 of
CPU mode register (address 003B16)).
(1)Right process example
LCD
ON
LCD
ON
or
OFF
•Sets determinate data to
LCD display RAM
Sets LCD display RAM data
LRAM0 (Address : 40
16
) ← “FF
16
”
LCD display
ON or OFF ?
•Sets turn off data to LCD display RAM
•Sets determinate
data to LCD diplay
RAM
(2) Error process example
LCD
ON
LCD
ON
or
OFF
LCD
OFF
OFF
OFF
ON
ON
Contents of addres 0040
16
are “FF
16
”
LCD display
ON or OFF ?
Sets LCD display RAM data
LRAM0 (Address : 40
16
) ← “FF
16
”
Sets LCD display RAM data
LRAM0 (Address : 40
16
) ← “00
16
”
Sets LCD display RAM data
LRAM0 (Address : 40
16
) ← “00
16
”
Contents of addres 0040
16
are “FF
16
”
Rev.2.00 May 28, 2004 page 100 of 100
38C2 Group (A Version)
Notes on Reset Circuit
1. Reset input voltage control
Make sure that the reset input voltage is less than 0.2 Vcc for Vcc(min).
2. Countermeasures for reset signal slow rising
In case where the RESET signal rise time is long, connect a ceramic
capacitor or others across the RESET pin and the Vss pin. Use a
1000 pF or more capacitor for high frequency use. When connecting
the capacitor, note the following:
•Make the length of the wiring which is connected to a capacitor as
short as possible.
•Be sure to verify the operation of application products on the user
side.
<Reason>
If the several nanosecond or several ten nanosecond impulse noise
enters the RESET pin, it may cause a microcomputer failure.
3. Port state immediately after reset
Table 1 shows the each pin state during RESET pin is “L”.
Table 1 Each pin state during RESET pin is “L”
Pin name
P0–P2 (SEG0–SEG23)
P3, P4, P5, P60–P62
COM0–COM3
Pin state
Input mode (with pull-up)
Input mode (high-impedance)
Vcc level input
4. Frequency relation of f(XIN) and f(
φ
)
The frequency relation of f(XIN) and f(
φ
) is f(XIN) = 8 • f(
φ
).
Notes on Reset Circuit
1. Mode transition
(1) Both the main clock (XIN-XOUT) and sub-clock (XCIN-XCOUT) need
time for the oscillations to stabilize. The mode transition between
middle-/high-speed and low-speed mode must be performed af-
ter the corresponding clock becomes stable. The sub-clock, needs
extra time to stabilize particularly when executing operations af-
ter power-on and stop mode. The main and sub clocks require
the following condition for mode transition.
f(XIN) > 3✕ f(XCIN)
(2) The all modes can be switched to the stop mode or the wait mode
and return to the source mode when the stop mode or the wait
mode is ended.
2. State transitions of system clock
When the mode is switched from frequency/2/4/8 to the low-speed
mode, or the opposite is performed, change CM7 (bit 7 of system
clock control bits of CPU mode register (address 003B16)) at first,
and then, change CM6 (bit 6 of system clock control bits of CPU
mode register (address 003B16)) after the oscillation of the changed
mode is stabilized.
3. Wait mode
Timer and LCD operate in the wait mode.
Notes on Oscillation External Output Function
When the signal from the XOUT pin or XCOUT pin of the oscillation
circuit is input directly to the circuit except this MCU and used, the
system operation may be unstabilized.
In order to share the oscillation circuit safely, use the clock output
from P40 and P41 by the oscillation external output function for the
circuits except this MCU.
NOTES ON HARDWARE
Handling of Source Pins
In order to avoid a latch-up occurrence, connect a capacitor suitable
for high frequencies as bypass capacitor between power source pin
(VCC pin) and GND pin (VSS pin). Besides, connect the capacitor to
as close as possible. For bypass capacitor which should not be lo-
cated too far from the pins to be connected, a ceramic capacitor of
0.01
µ
F–0.1
µ
F is recommended.
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Colophon .1.0
REVISION HISTORY
Rev. Date Description
Page Summary
38C2 Group (A VERSION) Data Sheet
First edition issued –1.00 Feb. 13, 2003
Explanations of “(5) Output Control Function of Timer X” are partly eliminated.
Figure 50 is partly revised.
Explanations of “Software Commands” of Rev.1.00 are eliminated.
Note 2 of Table 16 is partly revised.
“APPENDIX” is added.
28
49
70
72
93 to 100
2.00 May. 28, 2004