APA3010/1 3W Mono Low-Voltage Audio Power Amplifier Features * * * * * * * * * * General Description Operating Voltage : 2.5V-5.5V The APA3010/1 is a bridged-tied load (BTL) audio power Bridge-Tied Load (BTL) Mode Operation Supply Current - IDD=7mA at VDD=5V amplifier developed especially for low-voltage applications where internal speakers. Operating with a 5V supply, Low Shutdown Current - IDD=0.1A Low Distortion the APA3010/1 can deliver 3.3W of continuous power into a BTL 3 load at 10% THD+N throughout voice band - 2.5W, at VDD=5V, BTL, RL=3, THD+N=0.1% - 2.1W, at VDD=5V, BTL, RL=4, THD+N=0.1% frequencies. Although this device is characterized out to 20kHz, its operation is optimized for narrow band appli- Output Power at 1% THD+N cations such as wireless communications. The BTL configuration eliminates the need for external coupling ca- - 2.6W, at VDD=5V, BTL, RL=3 - 2.3W, at VDD=5V, BTL, RL=4 pacitors on the output in most applications, which is particularly important for small battery-powered equipment. at 10% THD+N -3.3W at VDD=5V, BTL, RL=3 This device features a shutdown mode for power sensitive applications with special depop circuitry to eliminate -2.7W at VDD=5V, BTL, RL=4 Depop Circuitry Integrated speaker noise when exiting shutdown mode. The APA3010/1 are available in a SOP-8, SOP-8P or Thermal Shutdown Protection and Over-Current Protection Circuitry MSOP-8P. High Supply Voltage Ripple Rejection Surface-Mount Packaging Applications - MSOP-8P (with Enhanced Thermal Pad) - SOP-8P (with Enhanced Thermal Pad) * * * * * - SOP-8 Lead Free and Green Devices Available (RoHS Compliant) Mobil Phones PDAs Portable Electronic Devices Desktop Computers Pin Configuration APA3010 APA3011 SHUTDOWN 1 8 VON SHUTDOWN 1 8 VON BYPASS 2 7 GND BYPASS 2 7 GND INP 3 6 VDD INP 3 6 VDD INN 4 5 VOP INN 4 5 VOP MSOP-8P / SOP-8P TOP VIEW MSOP-8P / SOP-8P TOP VIEW = Thermal Pad (connected to the GND plane for better heat dissipation) ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright ANPEC Electronics Corp. Rev. A.7 - Dec., 2010 1 www.anpec.com.tw APA3010/1 Pin Configuration (Cont.) APA3010 SHUTDOWN 1 8 VON BYPASS 2 7 GND INP 3 6 VDD INN 4 5 VOP SOP-8 TOP VIEW Ordering and Marking Information Package Code K : SOP-8 KA : SOP-8P XA : MSOP-8P Operating Ambient Temperature Range I : -40 to 85 oC Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device APA3010/1 Assembly Material Handling Code Temperature Range Package Code APA3010/1 K / KA : APA3010/1 XA : APA3010/1 XXXXX XXXXX - Date Code A3010/1 XXX XX XXXXX - Date Code Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for MSL classification at lead-free peak reflow temperature. ANPEC defines "Green" to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight). Absolute Maximum Ratings (Over operating free-air temperature range unless otherwise noted.) Symbol VDD VIN, VO Parameter Supply Voltage Input Voltage Range, SHUTDOWN, SHUTDOWN, BYPASS, VO TA Operating Junction Temperature Range TJ Maximum Junction Temperature TSTG Storage Temperature Range TS Soldering Temperature Range PD Power Dissipation Copyright ANPEC Electronics Corp. Rev. A.7 - Dec., 2010 2 Rating Unit -0.3 to 6 V -0.3 to VDD+0.3 V -40 to 85 C Internally Limited C -65 to +150 C 260 C Internally Limited W www.anpec.com.tw APA3010/1 Thermal Characteristics Symbol Parameter Thermal Resistance - Junction to Ambient Typical Value Unit 50 56 160 C/W (Note 1) MSOP-8P SOP-8P SOP-8 JA Note 1 : Please refer to "Thermal Pad Consideration." 2 layered 5 in2 printed circuit board with 2oz trace and copper through several thermal vias. The thermal pad is solder on the PCB. Recommended Operating Conditions Symbol Parameter Test Conditions VDD Supply Voltage VIH High-Level Voltage SHUTDOWN, SHUTDOWN VIL Low-Level Voltage SHUTDOWN, SHUTDOWN Range Unit 2.5 ~ 5.5 V 2.2 ~ V V ~ 0.4 Electrical Characteristics Unless otherwise noted these specifications apply over full temperature VDD= 5V, TA= 25C (unless otherwise noted). Symbol Parameter APA3010/1 Test Conditions Unit Min. Typ. Max. VOS Output Offset Voltage RL=8, Ri=Rf=20k - - 20 mV IDD Supply Current IO=0mA - 7 14 mA IDD(SD) Supply Current Shutdown Mode - 0.1 - A SHUTDOWN, Vi=VDD - 0.1 - SHUTDOWN, Vi=VDD - 0.1 - SHUTDOWN, Vi=0V - 0.1 - SHUTDOWN, Vi=0V - 0.1 - |IH| |IL| A A OPERATING CHARACTERISTICS, VDD=5V,TA=25C PO THD+N B1 PSRR Vn TWU Output Power Total Harmonic Distortion Plus Noise THD+N=1%, fin=1kHz, RL=3 RL=4 RL=8 THD+N=10%, fin =1kHz, RL=3 RL=4 RL=8 fin =1kHz, PO=2W, RL=3 PO=1.6W, RL=4 PO=1W, RL=8 - - - 2.6 2.3 1.3 3.3 2.7 1.7 0.06 0.04 0.03 W - - % - MHz Unity-Gain Bandwidth Open Loop - 2 Power Supply Rejection Ratio CB=1F, RL=8, fin =120kHz - 60 - dB Noise Output Voltage AV=6dB, CB=1F, RL=8 - 28 - V(rms) Wake-Up Time CB=1F - 380 - ms Copyright ANPEC Electronics Corp. Rev. A.7 - Dec., 2010 3 www.anpec.com.tw APA3010/1 Typical Operating Characteristics THD+N vs. Output Power THD+N vs. Output Power 10 VDD=5V AV=6dB fin=1kHz THD+N (%) THD+N (%) 10 1 RL=8 RL=4 RL=3 0.1 VDD=5V AV=6dB RL=3 1 fin=20kHz fin=20Hz 0.1 fin=1kHz 0.010 0.5 1 1.5 2 2.5 Output Power (W) 3 0.01 10m 3.5 THD+N vs. Frequency 2 5 THD+N vs. Frequency 10 VDD=5V AV=6dB RL=3 THD+N (%) THD+N (%) 10 100m 1 Output Power (W) 1 0.1 VDD=5V PO=2W RL=3 1 AV=20dB 0.1 PO=1W AV=6dB PO=2W 0.0120 100 1k Frequency (Hz) 0.01 10k 20k 20 THD+N vs. Output Power 10 10 VDD=5V AV=6dB RL=4 VDD=5V AV=6dB RL=4 1 THD+N (%) fin= 20kHz fin= 20Hz 0.1 PO=0.8W 0.1 fin= 1kHz 0.0 1 10m 10k 20k THD+N vs. Frequency 1 THD+N (%) 100 1k Frequency (Hz) 100m PO=1.6W 1 2 0.01 20 5 Output Power (W) Copyright ANPEC Electronics Corp. Rev. A.7 - Dec., 2010 100 1k 10k 20k Frequency (Hz) 4 www.anpec.com.tw APA3010/1 Typical Operating Characteristics (Cont.) THD+N vs. Frequency 10 VDD=5V PO=1.6W RL=4 THD+N (%) THD+N (%) 10 1 0.1 10 1 fin= 20kHz 1k fin= 20Hz fin= 1kHz AV=6dB 100 VDD=5V AV=6dB RL=8 0.1 AV=20dB 0.01 20 0.01 10m 10k 20k 100m 1 Frequency (Hz) Output Power (W) THD+N vs. Frequency THD+N vs. Frequency 10 VDD=5V AV=6dB RL=8 THD+N (%) THD+N (%) THD+N vs. Output Power 1 0.1 2 5 VDD=5V PO=1W RL=8 1 0.1 AV=20dB PO=0.5W PO=1W 0.01 0.005 20 100 1k AV=6dB 0.01 0.005 20 10k 20k 100 Frequency (Hz) 10k 20k Frequency Response Frequency Response +6 1k Frequency (Hz) +6 +220 +220 Gain Gain +210 +190 +4 Phase +3 VDD=5V RL=3 PO=1W 10 100 1k 10k Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.7 - Dec., 2010 Gain(dB) +200 +5 +200 +190 +4 Phase VDD=5V RL=4 PO=0.8W +3 10 100 +180 +170 100k 200k Phase(Degrees) +5 Phase(Degrees) Gain(dB) +210 +180 1k 10k +170 100k 200k Frequency (Hz) 5 www.anpec.com.tw APA3010/1 Typical Operating Characteristics (Cont.) Frequency Response Input Capacitor vs. Frequency Response +6 +220 +10 +210 +5 Ri=Rf=20k Gain +190 +4 Phase VDD=5V RL=8 PO=0.5W +3 10 100 1k 10k Frequency (Hz) Gain(dB) Gain(dB) +200 Phase(Degrees) +5 +0 -5 +180 -10 +170 100k 200k -15 VDD=5V RL=8 AV=6dB PO=0.5W 10 100 1k Frequency (Hz) 10k 20k Shutdown Attenuation vs. Frequency PSRR vs. Frequency +0 +0 VDD=5V RL=8 -20 CB=1F Shutdown Attenuation(dB) -10 PSRR(dB) Ci=2.2F Ci=1F Ci=0.47F Ci=0.1F -30 -40 -50 -60 -70 -80 VDD=5V A =6dB -20 RV=8 L -40 -60 -80 -100 -90 -100 20 100 1k Frequency (Hz) -120 10k 20k 20 Output Noise Voltage vs.Frequency 1k Frequency (Hz) 10k 20k Power Dissipation vs. Output Power 1.8 100 VDD=5V 1.6 THD+N<1% 50 Power Dissipation(W) Output Noise Voltage(V) 100 LPF BW<22kHz 20 A-Weighting 10 5 1.4 RL=3 RL=4 1.2 1.0 0.8 RL=8 0.6 0.4 2 1 20 0.2 100 1k 0 10k 20k Frequency (Hz) Copyright ANPEC Electronics Corp. Rev. A.7 - Dec., 2010 0 0.25 0.500.75 1.00 1.25 1.501.752.00 2.25 2.50 Output Power(W) 6 www.anpec.com.tw APA3010/1 Typical Operating Characteristics (Cont.) Supply Current vs. Supply Voltage 4.0 AV=6dB No Load 7.0 Output Power(W) Supply Current(mA) 8.0 Supply Voltage vs. Output Power 6.0 5.0 VDD=5V 3.5 AV=6dB RL=3 3.0 fin=1kHz BW<80kHz 2.5 THD+N=10% 2.0 1.5 THD+N=1% 1.0 0.5 Output Power(W) 3.5 3.0 2.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 0.0 2.5 5.5 Supply Voltage(V) 3.5 4.0 4.5 Supply Voltage(V) Power Dissipation vs. Output Power Supply Current vs. Supply Voltage 1.5 3.0 5.0 5.5 2.5 VDD=5V AV=6dB RL=4 fin=1kHz BW<80kHz THD+N=10% Output Power(W) 4.0 THD+N=1% 1.0 VDD=5V AV=6dB 2.0 RL=8 fin=1kHz BW<80kHz 1.5 THD+N=10% 1.0 THD+N=1% 0.5 0.5 0.0 2.5 3.0 3.5 4.0 4.5 5.0 0.0 2.5 5.5 Supply Voltage(V) Copyright ANPEC Electronics Corp. Rev. A.7 - Dec., 2010 3.0 3.5 4.0 4.5 5.0 5.5 Supply Voltage(V) 7 www.anpec.com.tw APA3010/1 Pin Description PIN NO. 1 I/O FUNCTION I Shutdown mode control signal input, place entire IC in shutdown mode when held high in APA3010 (APA3011 held low). NAME SHUTDOWN (APA3010) SHUTDOWN (APA3011) 2 BYPASS I Bypass pin. 3 INP I INP is the non-inverting input. INP is typically tied to the Bypass terminal. 4 INN I INN is the inverting input. INN is typically used as the audio input terminal. 5 VOP O VOP is the positive BTL output. 6 VDD - Supply voltage input pin. 7 GND - Ground connection for circuitry. 8 VON O VON is the negative BTL output. Block Diagram 4 INN 3 INP 2 1 BYPASS VOP 5 VON 8 VDD 6 GND 7 Vbias SHUTDOWN* Power and Depop Ckt Shutdown Ckt Note * : APA3011 is SHUTDOWN Copyright ANPEC Electronics Corp. Rev. A.7 - Dec., 2010 8 www.anpec.com.tw APA3010/1 Typical Application Circuit Rf 20k For SE input signal Audio IN Ci 0.47F Ri 4 INN 20k 3 INP 2 BYPASS CB 1F VOP 5 Vbias 4 VON 8 VDD VDD 100k 0.1F VDD 6 1 SHUTDOWN* Shutdown Ckt Shutdown Signal Power and Depop Ckt CS 10F GND 7 *Only for APA3011 Rf 20k For Differential input signal Audio IN Ci 0.47F Audio IN Ci 0.47F Ri 20k 4 INN Ri 3 INP VOP 5 20k Rf 20k 2 BYPASS CB 1F Vbias 4 VON 8 VDD VDD 100k Shutdown Signal 1 SHUTDOWN* Shutdown Ckt Power and Depop Ckt VDD 6 0.1F GND 7 CS 10F *Only for APA3011 Copyright ANPEC Electronics Corp. Rev. A.7 - Dec., 2010 9 www.anpec.com.tw APA3010/1 Application Information BTL Operation Input Resistance, Ri The APA3010/1 output stage (power amplifier) has two pairs of operational amplifiers internally, allowed for dif- The gain for audio input of the APA3010/1 is set by the external resistors (Ri and Rf). ferent amplifier configurations. BTL Gain = -2 x OUTP Rf Ri (1) BTL mode operation brings the factor of 2 in the gain equation due to the inverting amplifier mirroring the voltage swing across the load. The input resistance will af- OP1 fect the low frequency performance of audio signal. RL Input Capacitor, Ci OUTN Vbias Circuit In the typical application, an input capacitor, Ci, is required to allow the amplifier to bias the input signal to the proper OP2 DC level for optimum operation. In this case, Ci and the input impedance Ri (20k) form a high-pass filter with Figure 1. APA3010/1 Internal Configuration the corner frequency determined in the following equation : The power amplifier's OP1 gain is setting by Ri and Rf while the second amplifier OP2 is internally fixed in a unity-gain, inverting configuration. Figure 1 shows that fC(highpass)= 1 2x20kxCi (2) the output of OP1 is connected to the input to OP2, which results in the output signals of with both amplifiers with The value of Ci must be considered carefully because it identical in magnitude but out of phase 180. Consequently, the differential gain for each channel is 2 x (Gain of SE directly affects the low frequency performance of the circuit. Consider the example where Ri is 10k and the specifi- mode). By driving the load differentially through outputs OUTP cation calls for a flat bass response down to 50Hz. Equation is reconfigured as below : and OUTN, an amplifier configuration commonly referred to bridged mode is established. BTL mode operation is Ci = 1 2x20kxfC (3) different from the classical single-ended SE amplifier configuration where one side of its load is connected to When input resistance is considered, the Ci is 0.16F, so a value in the range of 0.22F to 1.0F would be chosen. the ground. A BTL amplifier design has few distinct advantages over the SE configuration, as it provides differential drive to the A further consideration for this capacitor is the leakage path from the input source through the input network load, thus, doubling the output swing for a specified supply voltage. (Ri+Rf, Ci) to the load. This leakage current creates a DC offset voltage at the input to the amplifier that reduces useful headroom, es- When placed under the same conditions, a BTL amplifier has four times the output power of a SE amplifier. A BTL pecially in high gain applications. For this reason, a lowleakage tantalum or ceramic capacitor is the best choice. configuration, such as the one used in APA3010/1, also creates a second advantage over SE amplifiers. Since When polarized capacitors are used, the positive side of the capacitor should face the amplifier input in most appli- the differential outputs, OUTP and OUTN, are biased at half-supply, it is not necessary for DC voltage to be across cations as the DC level of the amplifier input is held at VDD/2. Please note that it is important to confirm the ca- the load. This eliminates the need for an output coupling capacitor which is required in a single supply, SE pacitor polarity in the application. configuration. Copyright ANPEC Electronics Corp. Rev. A.7 - Dec., 2010 10 www.anpec.com.tw APA3010/1 Application Information (Cont.) Effective Bypass Capacitor, CB capacitor of 10F or greater placed near the audio power amplifier is recommended. As other power amplifiers, proper supply bypassing is critical for low noise performance and high power supply rejection. Optimizing Depop Circuitry Circuitry has been included in the APA3010/1 to minimize the amount of popping noise at power-up and when com- The capacitors located on both the bypass and power supply pins should be as close to the device as possible. ing out of shutdown mode. Popping occurs whenever a voltage step is applied to the speaker. In order to elimi- The effect of a larger bypass capacitor will improve PSRR due to increased supply stability. Typical applications em- nate clicks and pops, all capacitors must be fully discharged before turn-on. Rapid on/off switching of the de- ploy a 5V regulator with 1.0F and a 0.1F bypass capacitor as supply filtering. This does not eliminate the need vice or the shutdown function will cause the click and pop circuitry. for bypassing the supply nodes of the APA3010/1. The selection of bypass capacitors, especially CB, is thus de- The value of Ci will also affect turn-on pops. (Refer to Effective Bypass Capacitance) The bypass voltage ramp pendent upon desired PSRR requirements, click and pop performance. up should be slower than input bias voltage. Although the bypass pin current source cannot be modified, the size of To avoid the start-up pop noise occurred, the bypass voltage should rise slower than the input bias voltage and the CB can be changed to alter the device turn-on time and the amount of clicks and pops. By increasing the value of CB, relationship shown in equation (4) should be maintained. 1 CB x 125k << 1 40k x Ci turn-on pop can be reduced. However, the tradeoff for using a larger bypass capacitor is to increase the turn-on (4) time for this device. There is a linear relationship between the size of CB and the turn-on time. The bypass capacitor is fed thru from a 125k resistor inside the amplifier and the 40k is maximum input resistance of (Ri+ Rf). Bypass capacitor, CB, values of 3.3F A high gain amplifier intensifies the problem as the small delta in voltage is multiplied by the gain. Therefore, it is advantageous to use low-gain configurations. to 10F ceramic or tantalum low-ESR capacitors are recommended for the best THD and noise performance. The bypass capacitance also effects to the start-up time. Shutdown Function In order to reduce power consumption while not in use, It is determined in the following equation : Tstart up = 5 x (CB x 125k) the APA3010/1 contain a SHUTDOWN pin to externally turn off the amplifier bias circuitry. This shutdown feature (5) turns the amplifier off when a logic high (APA3011 held low) is placed on the SHUTDOWN pin. The trigger point Power Supply Decoupling, CS The APA3010/1 is a high-performance CMOS audio amplifier that requires adequate power supply decoupling between a logic high and logic low level is typically 2.0V. It is best to switch between the ground and the supply VDD to ensure the output total harmonic distortion (THD) is as low as possible. Power supply decoupling also prevents to provide maximum device performance. the oscillations being caused by long lead length between the amplifier and the speaker. The optimum By switching the SHUTDOWN pin to high, the amplifier enters a low-current state, IDD< 0.1A. APA3010 is in shut- decoupling is achieved by using two different types of capacitors that target on different types of noise on the down mode. On normal operating, the SHUTDOWN pin pulls to a low level to keep the IC out of the shutdown power supply leads. For higher frequency transients, spikes, or digital hash mode. The SHUTDOWN pin should be tied to a definite voltage to avoid unwanted state change. on the line, a good low equivalent-series-resistance(ESR) ceramic capacitor, typically 0.1F placed as close as pos- BTL Amplifier Efficiency An easy-to-use equation to calculate efficiency starts out as being equal to the ratio of power from the power sup- sible to the device VDD lead works best. For filtering lowerfrequency noise signals, a large aluminum electrolytic Copyright ANPEC Electronics Corp. Rev. A.7 - Dec., 2010 ply to the power delivered to the load. 11 www.anpec.com.tw APA3010/1 Application Information (Cont.) BTL Amplifier Efficiency (Cont.) Power Dissipation In BTL mode operation, the output voltage swing is doubled as in SE mode. Thus, the maximum power dis- The following equations are the basis for calculating amplifier efficiency. Efficiency = PO PSUP sipation point for a BTL mode operating at the same given conditions is 4 times as in SE mode. 4VDD2 BTL mode : PD,MAX= (10) 22RL Even with this substantial increase in power dissipation, (6) Where : PO = VOrms = VOrms x VOrms RL = VP x VP 2R L VP the APA3010/1 do not require extra heatsink. The power dissipation from equation11, assuming a 5V-power sup- (7) 2 PSUP = VDD x IDDAVG = VDD x 2VP ply and an 8 load, must not be greater than the power dissipation that results from the equation11 : TJ,MAX - TA PD,MAX= (11) JA (8) R L Efficiency of a BTL configuration : PO V xV 2V = ( P P ) / (VDD x P ) = PSUP 2R L RL VP 4VDD For MSOP-8P package with thermal pad, the thermal re- (9) sistance (JA) is equal to 48C/W. Table 1 calculates efficiencies for four different output power levels. Note that the efficiency of the amplifier is quite low for Since the maximum junction temperature (TJ,MAX ) of lower power levels and rises sharply as power to the load is increased resulting in a nearly flat internal power dissi- dissipation which the IC package is able to handle can be obtained from equation11. Once the power dissipation is greater than the maximum APA3010/1 is 150C and the ambient temperature (TA) is defined by the power system design, the maximum power pation over the normal operating range. Note that the internal dissipation at full output power is limit (P D,MAX ), either the supply voltage (V DD) must be decreased, the load impedance (RL) must be increased less than in the half power range. Calculating the efficiency for a specific system is the key to proper power or the ambient temperature should be reduced. supply design. A final point to remember about linear amplifiers (either Thermal Pad Consideration The thermal pad must be connected to the ground. The SE or BTL) is how to manipulate the terms in the efficiency equation to an utmost advantage when possible. package with thermal pad of the APA3010/1 requires special attention on thermal design. If the thermal design Note that in equation, VDD is in the denominator. This indicates that as VDD goes down, efficiency goes up. In other issues are not properly addressed, the APA3010/1 4 will go into thermal shutdown when driving a 4 load. words, use the efficiency analysis to choose the correct supply voltage and speaker impedance for the application. The thermal pad must be connected to the ground. The package with thermal pad of the APA3010/1 requires special attention on thermal design. The thermal pad on the bottom of the APA3010/1 should PO (W) Efficiency (%) IDD(A) VPP(V) PD (W) 0.25 31.25 0.16 2.00 0.55 be soldered down to a copper pad on the circuit board. Heat can be conducted away from the thermal pad through 0.50 47.62 0.21 2.83 0.55 the copper plane to ambient. If the copper plane is not on the top surface of the circuit board, 8 to 12 vias of 15 mil or 1.00 66.67 0.30 4.00 0.5 1.25 78.13 0.32 4.47 0.35 smaller in diameter should be used to thermally couple the thermal pad to the bottom plane. ** High peak voltages cause the THD to increase. For good thermal conduction, the vias must be plated through and solder filled. The copper plane used to con- Table 1. Efficiency Vs Output Power in 5-V/8 BTL Systems. duct heat away from the thermal pad should be as large as practical. Copyright ANPEC Electronics Corp. Rev. A.7 - Dec., 2010 12 www.anpec.com.tw APA3010/1 Application Information (Cont.) Thermal Pad Consideration (Cont.) Thermal Consideration For good thermal conduction, the vias must be plated through and solder filled. The copper plane used to con- Linear power amplifiers dissipate a significant amount of heat in the package under normal operating conditions. duct heat away from the thermal pad should be as large as practical. To calculate maximum ambient temperatures, refer the "Power Dissipation vs. Output Power" graphs. Given If the ambient temperature is higher than 25C, a larger copper plane or forced-air cooling will be required to keep JA, the maximum allowable junction temperature (TJMAX), and the total internal dissipation (PD), the maximum am- the APA3010/1 junction temperature below the thermal shutdown temperature (150C). In higher ambient bient temperature can be calculated with the following equation. The maximum recommended junction tem- temperature, higher airflow rate and/or larger copper area will be required to keep the IC out of thermal shutdown. perature for the APA3010/1 is 150C. The internal dissipation figures are taken from the Power Dissipation vs. Output Power graphs. ThermalVia diameter 12mil X 5 TAMax = TJMax -JAPD Ground plane for ThermalPAD 0.65mm 150 - 50(1.3) = 85C 0.4mm 1.0mm (12) The APA3010/1 is designed with a thermal shutdown pro- 0.65mm 2.5mm tection that turns the device off when the junction temperature surpasses 150C to prevent damaging the IC. 2.5mm MSOP-8P Land Pattern Recommendation ThermalVia diameter 12mil X 15 Ground plane for ThermalPAD 5mm 1.27mm 0.7mm 2.0mm 3mm 0.25mm SOP-8P Land Pattern Recommendation Copyright ANPEC Electronics Corp. Rev. A.7 - Dec., 2010 13 www.anpec.com.tw APA3010/1 Package Information SOP-8 -T- SEATING PLANE < 4 mils D E E1 SEE VIEW A h X 45 c A 0.25 b GAUGE PLANE SEATING PLANE A1 A2 e L VIEW A S Y M B O L SOP-8 INCHES MILLIMETERS MIN. MAX. A MIN. MAX. 1.75 0.069 0.004 0.25 0.010 A1 0.10 A2 1.25 b 0.31 0.51 0.012 0.020 c 0.17 0.25 0.007 0.010 D 4.80 5.00 0.189 0.197 5.80 6.20 0.228 0.244 3.80 4.00 0.150 0.157 0.020 0.050 E E1 e 0.049 1.27 BSC 0.050 BSC h 0.25 0.50 0.010 L 0.40 1.27 0.016 0 0 8 0 8 Note: 1. Follow JEDEC MS-012 AA. 2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side. 3. Dimension "E" does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side. Copyright ANPEC Electronics Corp. Rev. A.7 - Dec., 2010 14 www.anpec.com.tw APA3010/1 Package Information SOP-8P -T- SEATING PLANE < 4 mils D SEE VIEW A h X 45o E THERMAL PAD E1 E2 D1 c A1 0.25 A2 A b e GAUGE PLANE SEATING PLANE L VIEW A S Y M B O L A SOP-8P INCHES MILLIMETERS MAX. MIN. MIN. MAX. 1.60 A1 0.00 0.063 0.15 0.000 0.006 0.049 A2 1.25 b 0.31 0.51 0.012 0.020 c 0.17 0.25 0.007 0.010 D 4.80 5.00 0.189 0.197 0.138 D1 2.50 3.50 0.098 E 5.80 6.20 0.228 0.244 E1 3.80 4.00 0.150 0.157 E2 2.00 3.00 0.079 e 1.27 BSC 0.118 0.050 BSC h 0.25 0.50 0.010 0.020 L 0.40 1.27 0.016 0.050 0o C 8o C 0oC 8o C Note : 1. Followed from JEDEC MS-012 BA. 2. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not exceed 6 mil per side . 3. Dimension "E" does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 10 mil per side. Copyright ANPEC Electronics Corp. Rev. A.7 - Dec., 2010 15 www.anpec.com.tw APA3010/1 Package Information MSOP-8P D SEE VIEW A E c A 0.25 b GAUGE PLANE SEATING PLANE A1 L 0 A2 e E1 EXPOSED PAD E2 D1 VIEW A S Y M B O L A A1 MSOP-8P INCHES MILLIMETERS MIN. MAX. MIN. MAX. 1.10 0.00 0.043 0.15 0.000 0.006 0.037 0.015 A2 0.75 0.95 0.030 b 0.22 0.38 0.009 c 0.08 0.23 0.003 0.009 D 2.90 3.10 0.114 0.122 D1 1.50 2.50 0.059 0.098 0.201 0.122 E 4.70 5.10 0.185 E1 2.90 3.10 0.114 E2 1.50 2.50 0.059 e 0.65 BSC 0.098 0.026 BSC L 0.40 0.80 0.016 0.031 0 0 8 0 8 Note: 1. Follow JEDEC MO-187 AA-T 2. Dimension "D"does not include mold flash, protrusions or gate burrs. Mold flash, protrusion or gate burrs shall not flash or protrusions. 3. Dimension "E1" does not include inter-lead flash or protrusions. Inter-lead flash and protrusions shall not exceed 6 mil per side. Copyright ANPEC Electronics Corp. Rev. A.7 - Dec., 2010 16 www.anpec.com.tw APA3010/1 Carrier Tape & Reel Dimensions P0 P2 P1 A B0 W F E1 OD0 K0 A0 A OD1 B B T SECTION A-A SECTION B-B H A d T1 Application SOP-8(P) Application MSOP-8P A H T1 C d D W E1 F 330.02.00 50 MIN. 12.4+2.00 -0.00 13.0+0.50 -0.20 1.5 MIN. 20.2 MIN. 12.00.30 1.750.10 5.50.05 P0 P1 P2 D0 D1 T A0 B0 K0 2.00.05 1.5+0.10 -0.00 1.5 MIN. 0.6+0.00 -0.40 6.400.20 5.200.20 2.100.20 T1 C d D W E1 F 1.5 MIN. 20.2 MIN. 12.00.30 1.750.10 5.50.05 D1 T A0 B0 K0 1.5 MIN. 0.6+0.00 -0.40 5.300.20 3.300.20 1.400.20 4.00.10 8.00.10 A H 330.02.00 50 MIN. P0 P1 4.000.10 8.000.10 12.4+2.00 13.0+0.50 -0.00 -0.20 P2 D0 2.000.05 1.5+0.10 -0.00 (mm) Devices Per Unit Package Type Unit Quantity SOP-8(P) Tape & Reel 2500 MSOP-8P Tape & Reel 3000 Copyright ANPEC Electronics Corp. Rev. A.7 - Dec., 2010 17 www.anpec.com.tw APA3010/1 Taping Direction Information SOP-8(P) USER DIRECTION OF FEED MSOP-8P USER DIRECTION OF FEED Copyright ANPEC Electronics Corp. Rev. A.7 - Dec., 2010 18 www.anpec.com.tw APA3010/1 Classification Profile Classification Reflow Profiles Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly 100 C 150 C 60-120 seconds 150 C 200 C 60-120 seconds 3 C/second max. 3 C/second max. 183 C 60-150 seconds 217 C 60-150 seconds See Classification Temp in table 1 See Classification Temp in table 2 Time (tP)** within 5C of the specified classification temperature (Tc) 20** seconds 30** seconds Average ramp-down rate (Tp to Tsmax) 6 C/second max. 6 C/second max. 6 minutes max. 8 minutes max. Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak package body Temperature (Tp)* Time 25C to peak temperature * Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Copyright ANPEC Electronics Corp. Rev. A.7 - Dec., 2010 19 www.anpec.com.tw APA3010/1 Classification Reflow Profiles Table 1. SnPb Eutectic Process - Classification Temperatures (Tc) Package Thickness <2.5 mm 2.5 mm Volume mm <350 235 C 220 C 3 Volume mm 350 220 C 220 C 3 Table 2. Pb-free Process - Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm - 2.5 mm 2.5 mm Volume mm <350 260 C 260 C 250 C 3 Volume mm 350-2000 260 C 250 C 245 C 3 Volume mm >2000 260 C 245 C 245 C 3 Reliability Test Program Test item SOLDERABILITY HOLT PCT TCT HBM MM Latch-Up Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD-22, A115 JESD 78 Description 5 Sec, 245C 1000 Hrs, Bias @ Tj=125C 168 Hrs, 100%RH, 2atm, 121C 500 Cycles, -65C~150C VHBM2KV VMM200V 10ms, 1tr100mA Customer Service Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan, R.O.C. Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838 Copyright ANPEC Electronics Corp. Rev. A.7 - Dec., 2010 20 www.anpec.com.tw