APA3010XAI-G - Anpec Electronics Corp.

Rev. A.7 - Dec., 2010 www.anpec.com.tw1

ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise

customers to obtain the latest version of relevant information to verify before placing orders.

3W Mono Low-Voltage Audio Power Amplifier

APA3010/1

The APA3010/1 is a bridged-tied load (BTL) audio power

amplifier developed especially for low-voltage applica-

tions where internal speakers. Operating with a 5V supply,

the APA3010/1 can deliver 3.3W of continuous power into

a BTL 3Ω load at 10% THD+N throughout voice band

frequencies. Although this device is characterized out to

20kHz, its operation is optimized for narrow band appli-

cations such as wireless communications. The BTL con-

figuration eliminates the need for external coupling ca-

pacitors on the output in most applications, which is par-

ticularly important for small battery-powered equipment.

This device features a shutdown mode for power sensi-

tive applications with special depop circuitry to eliminate

speaker noise when exiting shutdown mode. The

APA3010/1 are available in a SOP-8, SOP-8P or

MSOP-8P.

• Operating Voltage : 2.5V-5.5V

• Bridge-Tied Load (BTL) Mode Operation

• Supply Current – IDD=7mA at VDD=5V

• Low Shutdown Current – IDD=0.1µA

• Low Distortion

–2.5W, at VDD=5V, BTL, RL=3Ω, THD+N=0.1%

–2.1W, at VDD=5V, BTL, RL=4Ω, THD+N=0.1%

• Output Power

at 1% THD+N

–2.6W, at VDD=5V, BTL, RL=3Ω

–2.3W, at VDD=5V, BTL, RL=4Ω

at 10% THD+N

–3.3W at VDD=5V, BTL, RL=3Ω

–2.7W at VDD=5V, BTL, RL=4Ω

• Depop Circuitry Integrated

• Thermal Shutdown Protection and Over-Current

Protection Circuitry

• High Supply Voltage Ripple Rejection

• Surface-Mount Packaging

–MSOP-8P (with Enhanced Thermal Pad)

–SOP-8P (with Enhanced Thermal Pad)

–SOP-8

• Lead Free and Green Devices Available

(RoHS Compliant)

FeaturesGeneral Description

Applications

•Mobil Phones

•PDAs

•Portable Electronic Devices

•Desktop Computers

SHUTDOWN

BYPASS

INP

VOP

GND

VDD

INN

VON

MSOP-8P / SOP-8P

TOP VIEW

= Thermal Pad (connected to the GND

plane for better heat dissipation)

APA3010

SHUTDOWN

BYPASS

INP

VOP

GND

VDD

INN

VON

MSOP-8P / SOP-8P

TOP VIEW

APA3011

Pin Configuration

Rev. A.7 - Dec., 2010 www.anpec.com.tw2

APA3010/1

Ordering and Marking Information

Note : ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which

are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for

MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen

free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by

weight).

APA3010/1 Package Code

K : SOP-8 KA : SOP-8P XA : MSOP-8P

Operating Ambient Temperature Range

I : -40 to 85 oC

Handling Code

TR : Tape & Reel

Assembly Material

G : Halogen and Lead Free Device

Handling Code

Temperature Range

Package Code

Assembly Material

APA3010/1 K / KA : APA3010/1

XXXXX XXXXX - Date Code

XXXXX - Date Code

APA3010/1 XA : A3010/1

XXX

Pin Configuration (Cont.)

SHUTDOWN

BYPASS

INP

VOP

GND

VDD

INN

VON

SOP-8

TOP VIEW

APA3010

Symbol Parameter Rating Unit

VDD Supply Voltage -0.3 to 6 V

VIN, VO Input Voltage Range, SHUTDOWN, SHUTDOWN, BYPASS, VO -0.3 to VDD+0.3 V

TA Operating Junction Temperature Range -40 to 85 °C

TJ Maximum Junction Temperature Internally Limited °C

TSTG Storage Temperature Range -65 to +150 °C

TS Soldering Temperature Range 260 °C

PD Power Dissipation Internally Limited W

Absolute Maximum Ratings

(Over operating free-air temperature range unless otherwise noted.)

Rev. A.7 - Dec., 2010 www.anpec.com.tw3

APA3010/1

Symbol

Parameter Test Conditions Range Unit

VDD Supply Voltage 2.5

5.5 V

VIH High-Level Voltage SHUTDOWN, SHUTDOWN 2.2

VIL Low-Level Voltage SHUTDOWN, SHUTDOWN

0.4 V

Recommended Operating Conditions

Thermal Characteristics

Symbol

Parameter Typical Value Unit

θJA

Thermal Resistance - Junction to Ambient (Note 1)

MSOP-8P

SOP-8P

SOP-8

160 °C/W

Note 1 : Please refer to “Thermal Pad Consideration.” 2 layered 5 in2 printed circuit board with 2oz trace and copper through

several thermal vias. The thermal pad is solder on the PCB.

Electrical Characteristics

Unless otherwise noted these specifications apply over full temperature VDD= 5V, TA= 25°C (unless otherwise noted).

APA3010/1

Symbol

Parameter Test Conditions Min. Typ. Max.

Unit

VOS Output Offset Voltage RL=8Ω, Ri=Rf=20kΩ - - 20 mV

IDD Supply Current IO=0mA - 7 14 mA

IDD(SD) Supply Current Shutdown Mode - 0.1 - µA

SHUTDOWN, Vi=VDD - 0.1 -

|IH|

SHUTDOWN, Vi=VDD - 0.1 - µA

SHUTDOWN, Vi=0V - 0.1 -

|IL|

SHUTDOWN, Vi=0V - 0.1 - µA

OPERATING CHARACTERISTICS, VDD=5V,TA=25°C

THD+N=1%, fin=1kHz,

RL=3Ω

RL=4Ω

RL=8Ω

2.6

2.3

1.3

PO Output Power THD+N=10%, fin =1kHz,

RL=3Ω

RL=4Ω

RL=8Ω

3.3

2.7

1.7

THD+N

Total Harmonic Distortion Plus Noise

fin =1kHz,

PO=2W, RL=3Ω

PO=1.6W, RL=4Ω

PO=1W, RL=8Ω

0.06

0.04

0.03

- %

B1 Unity-Gain Bandwidth Open Loop - 2 - MHz

PSRR Power Supply Rejection Ratio CB=1µF, RL=8Ω, fin =120kHz - 60 - dB

Vn Noise Output Voltage AV=6dB, CB=1µF, RL=8Ω - 28 - µV(rms)

TWU Wake-Up Time CB=1µF - 380 - ms

Rev. A.7 - Dec., 2010 www.anpec.com.tw4

APA3010/1

Typical Operating Characteristics

THD+N (%)

Output Power (W)Output Power (W)

THD+N (%)THD+N (%)

THD+N (%)

THD+N vs. Output Power

Frequency (Hz)Frequency (Hz)

THD+N vs. Output Power

THD+N vs. Frequency THD+N vs. Frequency

THD+N (%)

Output Power (W)Frequency (Hz)

THD+N vs. Output PowerTHD+N vs. Frequency

0.01

0.1

03.50.5 11.5 22.5 3

RL=8ΩRL=4ΩRL=3Ω

VDD=5V

AV=6dB

fin=1kHz

0.01

0.1

10m

100m 1 2

VDD=5V

AV=6dB

RL=3Ω

fin=20kHz

fin=20Hz

fin=1kHz

0.01

0.1

20 20k100 1k 10k

VDD=5V

AV=6dB

RL=3Ω

PO=2W

PO=1W

0.01

0.1

20 20k100 1k 10k

VDD=5V

PO=2W

RL=3Ω

AV=6dB

AV=20dB

0.0

0.1

10m

100m 1 2

VDD=5V

AV=6dB

RL=4Ω

fin= 20kHz

fin= 20Hz

fin= 1kHz

0.01

0.1

20 20k100 1k 10k

VDD=5V

AV=6dB

RL=4Ω

PO=1.6W

PO=0.8W

Rev. A.7 - Dec., 2010 www.anpec.com.tw5

APA3010/1

Typical Operating Characteristics (Cont.)

Output Power (W)

THD+N (%)

Frequency (Hz)

THD+N vs. Output PowerTHD+N vs. Frequency

THD+N (%)

Frequency (Hz)Frequency (Hz)

THD+N vs. Frequency THD+N vs. Frequency

Frequency Response Frequency Response

Gain(dB)

Frequency (Hz)Frequency (Hz)

Gain(dB)

Phase(Degrees)

0.01

0.1

20 20k100 1k 10k

VDD=5V

PO=1.6W

RL=4Ω

AV=6dB

AV=20dB

0.01

0.1

10m

100m 1 2

VDD=5V

AV=6dB

RL=8Ω

fin= 20kHz

fin= 20Hz

fin= 1kHz

0.005

0.01

0.1

20 20k100 1k 10k

VDD=5V

AV=6dB

RL=8Ω

PO=0.5W PO=1W

0.005

0.01

0.1

20 20k100 1k 10k

VDD=5V

PO=1W

RL=8Ω

AV=20dB

AV=6dB

+170

+220

+180

+190

+200

+210

10 200k100 1k 10k 100k

Gain

Phase

VDD=5V

RL=3Ω

PO=1W +170

+220

+180

+190

+200

+210

10 200k100 1k 10k 100k

VDD=5V

RL=4Ω

PO=0.8W

Gain

Phase

Rev. A.7 - Dec., 2010 www.anpec.com.tw6

APA3010/1

PSRR vs. Frequency Shutdown Attenuation vs. Frequency

Gain(dB)

Frequency (Hz)Frequency (Hz)

Gain(dB)

Phase(Degrees)

Frequency Response Input Capacitor vs. Frequency Response

Frequency (Hz)Frequency (Hz)

Shutdown Attenuation(dB)

PSRR(dB)

Typical Operating Characteristics (Cont.)

Output Noise Voltage vs.Frequency Power Dissipation vs. Output Power

Output Noise Voltage(V)

Frequency (Hz)

Power Dissipation(W)

Output Power(W)

+170

+220

+180

+190

+200

+210

10 200k100 1k 10k 100k

Gain

Phase

VDD=5V

RL=8Ω

PO=0.5W

-120

-100

-80

-60

-40

-20

20 20k

100 1k 10k

VDD=5V

AV=6dB

RL=8Ω

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

00.25 0.500.751.001.251.501.752.002.252.50

RL=3Ω

RL=4Ω

RL=8Ω

VDD=5V

THD+N<1%

-15

+10

-10

-5

10 20k

100 1k 10k

Ci=2.2µF

Ci=0.47µF

Ci=0.1µF

Ci=1µF

VDD=5V

RL=8Ω

AV=6dB

PO=0.5W

Ri=Rf=20kΩ

-100

-90

-80

-70

-60

-50

-40

-30

-20

-10

20 20k

100 1k 10k

VDD=5V

RL=8Ω

CB=1µF

1µ

100µ

2µ

5µ

10µ

20µ

50µ

20 20k

100 1k 10k

LPF BW<22kHz

A-Weighting

Rev. A.7 - Dec., 2010 www.anpec.com.tw7

APA3010/1

Supply Voltage(V)

Supply Current(mA)

Supply Current vs. Supply Voltage Supply Voltage vs. Output Power

Output Power(W)

Supply Voltage(V)

Typical Operating Characteristics (Cont.)

Power Dissipation vs. Output PowerSupply Current vs. Supply Voltage

Output Power(W)

Supply Voltage(V)

Output Power(W)

Supply Voltage(V)

4.0

5.0

6.0

7.0

8.0

2.5 3.0 3.5 4.0 4.5 5.0 5.5

AV=6dB

No Load

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD=5V

AV=6dB

RL=3Ω

fin=1kHz

BW<80kHz

THD+N=1%

THD+N=10%

0.0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD=5V

AV=6dB

RL=4Ω

fin=1kHz

BW<80kHz

THD+N=10%

THD+N=1%

0.0

0.5

1.0

1.5

2.0

2.5

2.5 3.0 3.5 4.0 4.5 5.0 5.5

VDD=5V

AV=6dB

RL=8Ω

fin=1kHz

BW<80kHz

THD+N=10%

THD+N=1%

Rev. A.7 - Dec., 2010 www.anpec.com.tw8

APA3010/1

Block Diagram

Note * : APA3011 is SHUTDOWN

Vbias

Shutdown Ckt

BYPASS

INN

SHUTDOWN*

VOP

VON

Power and Depop

Ckt

INP

VDD

GND

Pin Description

NO. NAME I/O FUNCTION

SHUTDOWN (APA3010)

1 SHUTDOWN (APA3011)

I Shutdown mode control signal input, place entire IC in

shutdown mode when held

high in APA3010 (APA3011 held low).

2 BYPASS I Bypass pin.

3 INP I INP is the non-inverting input. INP is typically tied to the Bypass terminal.

4 INN I INN is the inverting input. INN is typically used as the audio input terminal.

5 VOP O VOP is the positive BTL output.

6 VDD - Supply voltage input pin.

7 GND - Ground connection for circuitry.

8 VON O VON is the negative BTL output.

Rev. A.7 - Dec., 2010 www.anpec.com.tw9

APA3010/1

Typical Application Circuit

4Ω

VDD

Audio

1µF

100kΩ

20kΩ

0.47µF

Vbias

Shutdown

Ckt

BYPASS

INN

SHUTDOWN*

VOP

VON

Power and

Depop Ckt

INP

VDD

GND

20kΩ

10µF

0.1µF

Shutdown

Signal

*Only for APA3011

For SE input signal

VDD

4Ω

VDD

Audio

1µF

100kΩ

20kΩ

0.47µF

Vbias

Shutdown

Ckt

BYPASS

INN

SHUTDOWN*

VOP

VON

Power and

Depop Ckt

INP

VDD

GND

20kΩ

10µF

0.1µF

Shutdown

Signal

Audio

IN 20kΩ

0.47µF

20kΩ

*Only for APA3011

For Differential input signal

VDD

Rev. A.7 - Dec., 2010 www.anpec.com.tw10

APA3010/1

Application Information

BTL Operation

The APA3010/1 output stage (power amplifier) has two

pairs of operational amplifiers internally, allowed for dif-

ferent amplifier configurations.

Figure 1. APA3010/1 Internal Configuration

The power amplifier’s OP1 gain is setting by Ri and Rf

while the second amplifier OP2 is internally fixed in a

unity-gain, inverting configuration. Figure 1 shows that

the output of OP1 is connected to the input to OP2, which

results in the output signals of with both amplifiers with

identical in magnitude but out of phase 180°. Consequently,

the differential gain for each channel is 2 x (Gain of SE

mode).

By driving the load differentially through outputs OUTP

and OUTN, an amplifier configuration commonly referred

to bridged mode is established. BTL mode operation is

different from the classical single-ended SE amplifier

configuration where one side of its load is connected to

the ground.

A BTL amplifier design has few distinct advantages over

the SE configuration, as it provides differential drive to the

load, thus, doubling the output swing for a specified sup-

ply voltage.

When placed under the same conditions, a BTL amplifier

has four times the output power of a SE amplifier. A BTL

configuration, such as the one used in APA3010/1, also

creates a second advantage over SE amplifiers. Since

the differential outputs, OUTP and OUTN, are biased at

half-supply, it is not necessary for DC voltage to be across

the load. This eliminates the need for an output coupling

capacitor which is required in a single supply, SE

configuration.

Input Resistance, Ri

The gain for audio input of the APA3010/1 is set by the

external resistors (Ri and Rf).

Ri(1)

BTL Gain=-2 x

BTL mode operation brings the factor of 2 in the gain

equation due to the inverting amplifier mirroring the volt-

age swing across the load. The input resistance will af-

fect the low frequency performance of audio signal.

Input Capacitor, Ci

In the typical application, an input capacitor, Ci, is required

to allow the amplifier to bias the input signal to the proper

DC level for optimum operation. In this case, Ci and the

input impedance Ri (20kΩ) form a high-pass filter with

the corner frequency determined in the following equa-

tion :1

2πx20kΩxCi(2)

fC(highpass)=

The value of Ci must be considered carefully because it

directly affects the low frequency performance of the circuit.

Consider the example where Ri is 10kΩ and the specifi-

cation calls for a flat bass response down to 50Hz. Equa-

tion is reconfigured as below :

2πx20kΩxfC(3)

Ci=

When input resistance is considered, the Ci is 0.16µF, so

a value in the range of 0.22µF to 1.0µF would be chosen.

A further consideration for this capacitor is the leakage

path from the input source through the input network

(Ri+Rf, Ci) to the load.

This leakage current creates a DC offset voltage at the

input to the amplifier that reduces useful headroom, es-

pecially in high gain applications. For this reason, a low-

leakage tantalum or ceramic capacitor is the best choice.

When polarized capacitors are used, the positive side of

the capacitor should face the amplifier input in most appli-

cations as the DC level of the amplifier input is held at

VDD/2. Please note that it is important to confirm the ca-

pacitor polarity in the application.

Vbias

Circuit

OUTP

OUTN RL

OP1

OP2

Rev. A.7 - Dec., 2010 www.anpec.com.tw11

APA3010/1

Application Information (Cont.)

The effect of a larger bypass capacitor will improve PSRR

due to increased supply stability. Typical applications em-

ploy a 5V regulator with 1.0µF and a 0.1µF bypass capaci-

tor as supply filtering. This does not eliminate the need

for bypassing the supply nodes of the APA3010/1. The

selection of bypass capacitors, especially CB, is thus de-

pendent upon desired PSRR requirements, click and pop

performance.

To avoid the start-up pop noise occurred, the bypass volt-

age should rise slower than the input bias voltage and the

relationship shown in equation (4) should be maintained.

CB x 125kΩ<< 1

40kΩ x Ci(4)

The bypass capacitor is fed thru from a 125kΩ resistor

inside the amplifier and the 40kΩ is maximum input re-

sistance of (Ri+ Rf). Bypass capacitor, CB, values of 3.3µF

to 10µF ceramic or tantalum low-ESR capacitors are rec-

ommended for the best THD and noise performance.

The bypass capacitance also effects to the start-up time.

It is determined in the following equation :

Tstart up = 5 x (CB x 125kΩ)(5)

Power Supply Decoupling, CS

The APA3010/1 is a high-performance CMOS audio am-

plifier that requires adequate power supply decoupling

to ensure the output total harmonic distortion (THD) is as

low as possible. Power supply decoupling also prevents

the oscillations being caused by long lead length be-

tween the amplifier and the speaker. The optimum

decoupling is achieved by using two different types of

capacitors that target on different types of noise on the

power supply leads.

For higher frequency transients, spikes, or digital hash

on the line, a good low equivalent-series-resistance(ESR)

ceramic capacitor, typically 0.1µF placed as close as pos-

sible to the device VDD lead works best. For filtering lower-

frequency noise signals, a large aluminum electrolytic

Optimizing Depop Circuitry

Circuitry has been included in the APA3010/1 to minimize

the amount of popping noise at power-up and when com-

ing out of shutdown mode. Popping occurs whenever a

voltage step is applied to the speaker. In order to elimi-

nate clicks and pops, all capacitors must be fully dis-

charged before turn-on. Rapid on/off switching of the de-

vice or the shutdown function will cause the click and pop

circuitry.

The value of Ci will also affect turn-on pops. (Refer to

Effective Bypass Capacitance) The bypass voltage ramp

up should be slower than input bias voltage. Although the

bypass pin current source cannot be modified, the size of

CB can be changed to alter the device turn-on time and the

amount of clicks and pops. By increasing the value of CB,

turn-on pop can be reduced. However, the tradeoff for

using a larger bypass capacitor is to increase the turn-on

time for this device. There is a linear relationship be-

tween the size of CB and the turn-on time.

A high gain amplifier intensifies the problem as the small

delta in voltage is multiplied by the gain. Therefore, it is

advantageous to use low-gain configurations.

Shutdown Function

In order to reduce power consumption while not in use,

the APA3010/1 contain a SHUTDOWN pin to externally

turn off the amplifier bias circuitry. This shutdown feature

turns the amplifier off when a logic high (APA3011 held

low) is placed on the SHUTDOWN pin. The trigger point

between a logic high and logic low level is typically 2.0V.

It is best to switch between the ground and the supply VDD

to provide maximum device performance.

By switching the SHUTDOWN pin to high, the amplifier

enters a low-current state, IDD< 0.1µA. APA3010 is in shut-

down mode. On normal operating, the SHUTDOWN pin

pulls to a low level to keep the IC out of the shutdown

mode. The SHUTDOWN pin should be tied to a definite

voltage to avoid unwanted state change.

BTL Amplifier Efficiency

An easy-to-use equation to calculate efficiency starts out

as being equal to the ratio of power from the power sup-

ply to the power delivered to the load.

Effective Bypass Capacitor, CB

As other power amplifiers, proper supply bypassing is

critical for low noise performance and high power supply

rejection.

The capacitors located on both the bypass and power

supply pins should be as close to the device as possible.

capacitor of 10µF or greater placed near the audio power

amplifier is recommended.

Rev. A.7 - Dec., 2010 www.anpec.com.tw12

APA3010/1

Application Information (Cont.)

BTL Amplifier Efficiency (Cont.)

Where :

VOrms =√2

PSUP = VDD x IDDAVG = VDD x2VP

πRL

(7)

(8)

Efficiency of a BTL configuration :

( ) / (VDD x ) =

PSUP=VPx VP

2RL

2VP

πRL

πVP

4VDD (9)

Table 1 calculates efficiencies for four different output

power levels.

Note that the efficiency of the amplifier is quite low for

lower power levels and rises sharply as power to the load

is increased resulting in a nearly flat internal power dissi-

pation over the normal operating range.

Note that the internal dissipation at full output power is

less than in the half power range. Calculating the effi-

ciency for a specific system is the key to proper power

supply design.

A final point to remember about linear amplifiers (either

SE or BTL) is how to manipulate the terms in the effi-

ciency equation to an utmost advantage when possible.

Note that in equation, VDD is in the denominator. This indi-

cates that as VDD goes down, efficiency goes up. In other

words, use the efficiency analysis to choose the correct

supply voltage and speaker impedance for the application.

PO (W)

Efficiency (%)

IDD(A)

VPP(V)

PD (W)

0.25 31.25 0.16

2.00

0.55

0.50 47.62 0.21

2.83

0.55

1.00 66.67 0.30

4.00

0.5

1.25 78.13 0.32

4.47

0.35

** High peak voltages cause the THD to increase.

Table 1. Efficiency Vs Output Power in 5-V/8Ω BTL

Systems.

Power Dissipation

In BTL mode operation, the output voltage swing is

doubled as in SE mode. Thus, the maximum power dis-

sipation point for a BTL mode operating at the same given

conditions is 4 times as in SE mode.

BTL mode : PD,MAX=(10)

4VDD2

2π2RL

Even with this substantial increase in power dissipation,

the APA3010/1 do not require extra heatsink. The power

dissipation from equation11, assuming a 5V-power sup-

ply and an 8Ω load, must not be greater than the power

dissipation that results from the equation11 :

PD,MAX=TJ,MAX - TA

θJA(11)

For MSOP-8P package with thermal pad, the thermal re-

sistance (θJA) is equal to 48οC/W.

Since the maximum junction temperature (TJ,MAX) of

APA3010/1 is 150οC and the ambient temperature (TA) is

defined by the power system design, the maximum power

dissipation which the IC package is able to handle can be

obtained from equation11.

Once the power dissipation is greater than the maximum

limit (PD,MAX), either the supply voltage (VDD) must be

decreased, the load impedance (RL) must be increased

or the ambient temperature should be reduced.

Thermal Pad Consideration

The thermal pad must be connected to the ground. The

package with thermal pad of the APA3010/1 requires spe-

cial attention on thermal design. If the thermal design

issues are not properly addressed, the APA3010/1 4Ω

will go into thermal shutdown when driving a 4Ω load.

The thermal pad must be connected to the ground. The

package with thermal pad of the APA3010/1 requires spe-

cial attention on thermal design.

The thermal pad on the bottom of the APA3010/1 should

be soldered down to a copper pad on the circuit board.

Heat can be conducted away from the thermal pad through

the copper plane to ambient. If the copper plane is not on

the top surface of the circuit board, 8 to 12 vias of 15 mil or

smaller in diameter should be used to thermally couple

the thermal pad to the bottom plane.

PO =RL=

VOrms x VOrms

2RL

VP x VP

The following equations are the basis for calculating

amplifier efficiency.

(6)

Efficiency =PSUP

For good thermal conduction, the vias must be plated

through and solder filled. The copper plane used to con-

duct heat away from the thermal pad should be as large

as practical.

Rev. A.7 - Dec., 2010 www.anpec.com.tw13

APA3010/1

Thermal Pad Consideration (Cont.)

Application Information (Cont.)

For good thermal conduction, the vias must be plated

through and solder filled. The copper plane used to con-

duct heat away from the thermal pad should be as large

as practical.

If the ambient temperature is higher than 25°C, a larger

copper plane or forced-air cooling will be required to keep

the APA3010/1 junction temperature below the thermal

shutdown temperature (150°C). In higher ambient

temperature, higher airflow rate and/or larger copper area

will be required to keep the IC out of thermal shutdown.

Thermal Consideration

Linear power amplifiers dissipate a significant amount of

heat in the package under normal operating conditions.

To calculate maximum ambient temperatures, refer the

“Power Dissipation vs. Output Power” graphs. Given

θJA, the maximum allowable junction temperature (TJMAX),

and the total internal dissipation (PD), the maximum am-

bient temperature can be calculated with the following

equation. The maximum recommended junction tem-

perature for the APA3010/1 is 150°C. The internal dissi-

pation figures are taken from the Power Dissipation vs.

Output Power graphs.

TAMax = TJMax -θJAPD (12)

150 - 50(1.3) = 85°C

The APA3010/1 is designed with a thermal shutdown pro-

tection that turns the device off when the junction tem-

perature surpasses 150°C to prevent damaging the IC.

0.65mm

1.0mm

2.5mm

Ground plane

for ThermalPAD

ThermalVia diameter

12mil X 5

2.5mm

0.65mm 0.4mm

MSOP-8P Land Pattern Recommendation

2.0mm

3mm

Ground plane for ThermalPAD

ThermalVia diameter

12mil X 15

1.27mm 0.7mm

0.25mm

5mm

SOP-8P Land Pattern Recommendation

Rev. A.7 - Dec., 2010 www.anpec.com.tw14

APA3010/1

Package Information

SOP-8

A1A2

VIEW A

0.25

SEATING PLANE

GAUGE PLANE

Note: 1. Follow JEDEC MS-012 AA.

2. Dimension “D” does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion or gate burrs shall not exceed 6 mil per side.

3. Dimension “E” does not include inter-lead flash or protrusions.

Inter-lead flash and protrusions shall not exceed 10 mil per side.

LMIN. MAX.

1.75

0.10

0.17 0.25

0.25

MILLIMETERS

b0.31 0.51

SOP-8

0.25 0.50

0.40 1.27

MIN. MAX.

INCHES

0.069

0.004

0.012 0.020

0.007 0.010

0.010 0.020

0.016 0.050

0.010

1.27 BSC 0.050 BSC

A2 1.25 0.049

3.80

5.80

4.80

4.00

6.20

5.00 0.189 0.197

0.228 0.244

0.150 0.157

SEE VIEW A

h X 45

SEATING PLANE < 4 mils-T-

Rev. A.7 - Dec., 2010 www.anpec.com.tw15

APA3010/1

Package Information

SOP-8P

THERMAL

PAD

VIEW AL

0.25

GAUGE PLANE

SEATING PLANE

Note : 1. Followed from JEDEC MS-012 BA.

2. Dimension "D" does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion or gate burrs shall not exceed 6 mil per side .

3. Dimension "E" does not include inter-lead flash or protrusions.

Inter-lead flash and protrusions shall not exceed 10 mil per side.

0.020

0.010

0.020

0.050

0.006

0.063

MAX.

0.40L

θ0oC

0.25

0.17

0.31

0.016

1.27

8oC0oC8oC

0.50

1.27 BSC

0.51

0.25

0.050 BSC

0.010

0.012

0.007

MILLIMETERS

MIN.

0.00

1.25

SOP-8P

MAX.

0.15

1.60

MIN.

0.000

0.049

INCHES

D1 2.50 0.098

2.00 0.079E2

3.50

3.00

0.138

0.118

4.80 5.00 0.189 0.197

3.80 4.00 0.150 0.157

5.80 6.20 0.228 0.244

h X 45o

SEE VIEW A

-T- SEATING PLANE < 4 mils

Rev. A.7 - Dec., 2010 www.anpec.com.tw16

APA3010/1

Package Information

MSOP-8P

VIEW A

0.25

SEATING PLANE

GAUGE PLANE

SEE VIEW A

EXPOSED

PAD

LMIN. MAX.

1.10

0.00

0.22 0.38

0.08 0.23

0.15

MILLIMETERS

A2 0.75 0.95

0.65 BSC

MSOP-8P

0.40 0.80 0.026 BSC

MIN. MAX.

INCHES

0.043

0.000

0.030 0.037

0.009 0.015

0.003 0.009

0.016 0.031

0.006

1.50 2.50 0.059 0.098

2.90 3.10

4.70 5.10

0.114 0.122

0.185 0.201

0.114 0.122

Note: 1. Follow JEDEC MO-187 AA-T

2. Dimension “D”does not include mold flash, protrusions or gate burrs.

Mold flash, protrusion or gate burrs shall not flash or protrusions.

3. Dimension “E1” does not include inter-lead flash or protrusions.

Inter-lead flash and protrusions shall not exceed 6 mil per side.

Rev. A.7 - Dec., 2010 www.anpec.com.tw17

APA3010/1

Application

A H T1 C d D W E1 F

330.0±2.00

50 MIN.

12.4+2.00

-0.00

13.0+0.50

-0.20

1.5 MIN.

20.2 MIN.

12.0±0.30

1.75±0.10

5.5±0.05

P0 P1 P2 D0 D1 T A0 B0 K0

SOP-8(P)

4.0±0.10

8.0±0.10

2.0±0.05

1.5+0.10

-0.00

1.5 MIN.

0.6+0.00

-0.40

6.40±0.20

5.20±0.20

2.10±0.20

Application

A H T1 C d D W E1 F

330.0±2.00

50 MIN.

12.4+2.00

0.00

13.0+0.50

-0.20

1.5 MIN.

20.2 MIN.

12.0±0.30

1.75±0.10

5.5±0.05

P0 P1 P2 D0 D1 T A0 B0 K0

MSOP-8P

4.00±0.10

8.00±0.10

2.00±0.05

1.5+0.10

-0.00

1.5 MIN.

0.6+0.00

-0.40

5.30±0.20

3.30±0.20

1.40±0.20

Carrier Tape & Reel Dimensions

Devices Per Unit(mm)

Package Type Unit Quantity

SOP-8(P) Tape & Reel 2500

MSOP-8P Tape & Reel 3000

OD0

BA0

SECTION B-B

SECTION A-A

OD1

Rev. A.7 - Dec., 2010 www.anpec.com.tw18

APA3010/1

Taping Direction Information

SOP-8(P)

MSOP-8P

USER DIRECTION OF FEED

Rev. A.7 - Dec., 2010 www.anpec.com.tw19

APA3010/1

Classification Profile

Classification Reflow Profiles

Profile Feature Sn-Pb Eutectic Assembly Pb-Free Assembly

Preheat & Soak

Temperature min (Tsmin)

Temperature max (Tsmax)

Time (Tsmin to Tsmax) (ts)

100 °C

150 °C

60-120 seconds

150 °C

200 °C

60-120 seconds

Average ramp-up rate

(Tsmax to TP) 3 °C/second max. 3 °C/second max.

Liquidous temperature (TL)

Time at liquidous (tL) 183 °C

60-150 seconds 217 °C

60-150 seconds

Peak package body Temperature

(Tp)* See Classification Temp in table 1 See Classification Temp in table 2

Time (tP)** within 5°C of the specified

classification temperature (Tc) 20** seconds 30** seconds

Average ramp-down rate (Tp to Tsmax)

6 °C/second max. 6 °C/second max.

Time 25°C to peak temperature 6 minutes max. 8 minutes max.

* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.

** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.

Rev. A.7 - Dec., 2010 www.anpec.com.tw20

APA3010/1

Classification Reflow Profiles

Table 2. Pb-free Process – Classification Temperatures (Tc)

Package

Thickness Volume mm3

<350 Volume mm3

350-2000 Volume mm3

>2000

<1.6 mm 260 °C 260 °C 260 °C

1.6 mm – 2.5 mm 260 °C 250 °C 245 °C

≥2.5 mm 250 °C 245 °C 245 °C

Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)

Package

Thickness Volume mm3

<350 Volume mm3

≥350

<2.5 mm 235 °C 220 °C

≥2.5 mm 220 °C 220 °C

Test item Method Description

SOLDERABILITY JESD-22, B102 5 Sec, 245°C

HOLT JESD-22, A108 1000 Hrs, Bias @ Tj=125°C

PCT JESD-22, A102 168 Hrs, 100%RH, 2atm, 121°C

TCT JESD-22, A104 500 Cycles, -65°C~150°C

HBM MIL-STD-883-3015.7 VHBM≧2KV

MM JESD-22, A115 VMM≧200V

Latch-Up JESD 78 10ms, 1tr≧100mA

Reliability Test Program

Customer Service

Anpec Electronics Corp.

Head Office :

No.6, Dusing 1st Road, SBIP,

Hsin-Chu, Taiwan, R.O.C.

Tel : 886-3-5642000

Fax : 886-3-5642050

Taipei Branch :

2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,

Sindian City, Taipei County 23146, Taiwan

Tel : 886-2-2910-3838

Fax : 886-2-2917-3838