N08M1618L1A AMI Semiconductor, Inc. ULP Memory Solutions 670 North McCarthy Blvd. Suite 220 Milpitas, CA 95035 PH: 408-935-7777, FAX: 408-935-7770 Advance Information 8Mb Ultra-Low Power Asynchronous Medical CMOS SRAM 512K x 16 bit Overview Features The N08M1618L1A is an integrated memory device intended for non life-support medical applications. This device is a 8 megabit memory organized as 524,288 words by 16 bits. The device is designed and fabricated using AMI Semiconductor's advanced CMOS technology with reliability inhancements for medical users. The device operates with two chip enable (CE1 and CE2) controls and output enable (OE) to allow for easy memory expansion. Byte controls (UB and LB) allow the upper and lower bytes to be accessed independently and can also be used to deselect the device. This device is optimal for various applications where low-power is critical such as battery backup and hand-held devices. The device can operate over a very wide temperature range of -40oC to +85oC and is available in a JEDEC standard BGA package. * Dual voltage for Optimum Performance: Vccq - 2.3 to 3.6 Volts Vcc - 1.4 to 2.2 Volts * Very low standby current 0.5A at 1.8V and 37 deg C * Very low operating current 1.0mA at 1.8V and 1s (Typical) * Very low Page Mode operating current 0.5mA at 1.8V and 1s (Typical) * Simple memory control Dual Chip Enables (CE1 and CE2) Byte control for independent byte operation Output Enable (OE) for memory expansion * Low voltage data retention Vcc = 1.2V * Special Processing to reduce Soft Error Rate (SER) * Automatic power down to standby mode Product Family Part Number Package Type N08M1618L1AB 48 - BGA Operating Temperature Power Supply Speed 2.3V-3.6V(VCCQ) 85ns @ 1.7V -40oC to +85oC 1.4V-2.2V(V ) 150ns @ 1.4V CC N08M1618L1AW 20 A 2.5 mA @ 1MHz Wafer Pin Configuration Pin Descriptions 1 2 3 4 5 6 A LB OE A0 A1 A2 CE2 B I/O8 UB A3 A4 CE1 I/O0 C I/O9 I/O10 A5 A6 I/O1 I/O2 VSS D Standby Operating Current (ISB), Current (Icc), Max Max I/O11 A17 A7 I/O3 VCC E VCCQ I/O12 NC A16 I/O4 VSS F I/O14 I/O13 A14 A15 I/O5 I/O6 G I/O15 NC A12 A13 WE I/O7 H A18 A8 A9 A10 A11 NC 48 Pin BGA (top) 8 x 10 mm Pin Name Pin Function A0-A18 Address Inputs WE CE1, CE2 OE LB UB I/O0-I/O15 Write Enable Input Chip Enable Input Output Enable Input Lower Byte Enable Input Upper Byte Enable Input Data Inputs/Outputs VCC Power VSS Ground VCCQ Power I/O pins only NC Not Connected Stock No. 23211-03 9/21/06 ADVANCE INFORMATION The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com. 1 N08M1618L1A AMI Semiconductor, Inc. Advance Information Functional Block Diagram Word Address Decode Logic Address Inputs A4 - A18 Page Address Decode Logic 32K Page x 16 word x 16 bit RAM Array Input/ Output Mux and Buffers Word Mux Address Inputs A0 - A3 I/O0 - I/O7 I/O8 - I/O15 CE1 CE2 WE OE UB LB Control Logic Functional Description CE1 CE2 WE OE UB LB I/O0 - I/O151 MODE POWER H X X X X X High Z Standby2 Standby X L X X X X High Z Standby2 Standby X X X X H H High Z Standby2 Standby L H L X3 L1 L1 Data In Write3 Active -> Standby4 L H H L L1 L1 Data Out Read Active -> Standby4 L H H H L1 L1 High Z Active Standby4 1. When UB and LB are in select mode (low), I/O0 - I/O15 are affected as shown. When LB only is in the select mode only I/O0 - I/O7 are affected as shown. When UB is in the select mode only I/O8 - I/O15 are affected as shown. 2. When the device is in standby mode, control inputs (WE, OE, UB, and LB), address inputs and data input/outputs are internally isolated from any external influence and disabled from exerting any influence externally. 3. When WE is invoked, the OE input is internally disabled and has no effect on the circuit. 4. The device will consume active power in this mode whenever addresses are changed. Data inputs are internally isolated from any expernal influence. Capacitance1 Item Symbol Test Condition Input Capacitance CIN I/O Capacitance CI/O Min Max Unit VIN = 0V, f = 1 MHz, TA = 25oC 8 pF VIN = 0V, f = 1 MHz, TA = 25oC 8 pF 1. These parameters are verified in device characterization and are not 100% tested Stock No. 23211-03 9/21/06 ADVANCE INFORMATION The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com. 2 N08M1618L1A AMI Semiconductor, Inc. Advance Information Absolute Maximum Ratings1 Item Symbol Rating Unit Voltage on any pin relative to VSS VIN,OUT -0.3 to VCC+0.3 V Voltage on VCC Supply Relative to VSS VCC -0.3 to 4.5 V Power Dissipation PD 500 mW Storage Temperature TSTG -40 to 125 o Operating Temperature TA -40 to +85 oC Soldering Temperature and Time TSOLDER 10sec(Lead only) oC 240oC, C 1. Stresses greater than those listed above may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Operating Characteristics (Over Specified Temperature Range) Typ1 Max Unit 1.4 1.8 2.2 V 3.6 V Symbol Core Supply Voltage VCC I/O Supply Voltage VCCQ VCCQ > or = VCC 2.3 Data Retention Voltage VDR Chip Disabled3 1.2 Input High Voltage VIH VCCQ-0.6 VCCQ+0.3 V Input Low Voltage VIL -0.3 0.6 V Output High Voltage VOH IOH = 0.2mA Output Low Voltage VOL IOL = -0.2mA 0.2 V Input Leakage Current ILI VIN = 0 to VCC 0.1 A Output Leakage Current ILO OE = VIH or Chip Disabled 0.1 A Read/Write Operating Supply Current @ 1 s Cycle Time2 ICC1 VCC=2.2 V, VIN=VIH or VIL Chip Enabled, IOUT = 0 1.5 2.5 mA Read/Write Operating Supply Current @ 85 ns Cycle Time2 ICC2 VCC=2.2 V, VIN=VIH or VIL Chip Enabled, IOUT = 0 10.0 13.0 mA Page Mode Operating Supply Current @ 85 ns Cycle Time2 (Refer to Power Savings with Page Mode Operation diagram) ICC3 VCC=2.2 V, VIN=VIH or VIL Chip Enabled, IOUT = 0 3.5 mA Read/Write Quiescent Operating Supply Current3 ICC4 VCC=2.2 V, VIN=VIH or VIL Chip Enabled, IOUT = 0, f=0 1 A ISB1 VIN = VCC or 0V Chip Disabled tA= 85oC, VCC = 2.2 V 0.5 20.0 A 0.1 1.0 A Standby Current3 Data Retention Current3 IDR Test Conditions Min. Item VCC = 1.2V, VIN = VCC or 0 Chip Disabled, tA= 85oC V VCCQ-0.2 V 1. Typical values are measured at Vcc=Vcc Typ., TA=25C and not 100% tested. 2. This parameter is specified with the outputs disabled to avoid external loading effects. The user must add current required to drive output capacitance expected in the actual system. 3. This device assumes a standby mode if the chip is disabled (CE1 high or CE2 low). In order to achieve low standby current all inputs must be within 0.2 volts of either VCC or VSS. Stock No. 23211-03 9/21/06 ADVANCE INFORMATION The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com. 3 N08M1618L1A AMI Semiconductor, Inc. Advance Information Power Savings with Page Mode Operation (WE = VIH) Page Address (A4 - A18) Word Address (A0 - A3) Open page Word 1 Word 2 ... Word 16 CE1 CE2 OE Note: Page mode operation is a method of addressing the SRAM to save operating current. The internal organization of the SRAM is optimized to allow this unique operating mode to be used as a valuable power saving feature. The only thing that needs to be done is to address the SRAM in a manner that the internal page is left open and 8-bit words of data are read from the open page. By treating addresses A0-A3 as the least significant bits and addressing the 16 words within the open page, power is reduced to the page mode value which is considerably lower than standard operating currents for low power SRAMs. Stock No. 23211-03 9/21/06 ADVANCE INFORMATION The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com. 4 N08M1618L1A AMI Semiconductor, Inc. Advance Information Timing Test Conditions Item Input Pulse Level 0.1VCC to 0.9 VCC Input Rise and Fall Time 5ns Input and Output Timing Reference Levels 0.5 VCC Output Load CL = 30pF Operating Temperature -40 to +85 oC Timing VCCQ > or = VCC Item Symbol Read Cycle Time tRC VCC = 1.4 - 2.2 V Min. Max. 150 VCC = 1.7 - 2.2 V Min. Max. 85 Units ns Address Access Time tAA 150 85 ns Address Access Time (Page Mode) tAAP 30 30 ns Chip Enable to Valid Output tCO 150 85 ns Output Enable to Valid Output tOE 50 40 ns Byte Select to Valid Output tLB, tUB 150 85 ns Chip Enable to Low-Z output tLZ 20 10 ns Output Enable to Low-Z Output tOLZ 20 5 ns Byte Select to Low-Z Output tLBZ, tUBZ 20 10 ns Chip Disable to High-Z Output tHZ 0 30 0 15 ns Output Disable to High-Z Output tOHZ 0 30 0 15 ns Byte Select Disable to High-Z Output tLBHZ, tUBHZ 0 30 0 15 ns Output Hold from Address Change tOH 20 10 ns Write Cycle Time tWC 150 85 ns Chip Enable to End of Write tCW 75 50 ns Address Valid to End of Write tAW 75 50 ns Byte Select to End of Write tLBW, tUBW 75 50 ns Write Pulse Width tWP 50 40 ns Address Setup Time tAS 0 0 ns Write Recovery Time tWR 0 0 ns Write to High-Z Output tWHZ Data to Write Time Overlap tDW 50 40 ns Data Hold from Write Time tDH 0 0 ns End Write to Low-Z Output tOW 10 5 ns 30 15 Stock No. 23211-03 9/21/06 ADVANCE INFORMATION The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com. ns 5 N08M1618L1A AMI Semiconductor, Inc. Advance Information Timing of Read Cycle (CE1 = OE = VIL, WE = CE2 = VIH) tRC Address tAA tOH Data Out Previous Data Valid Data Valid Timing Waveform of Read Cycle (WE=VIH) tRC Address tAA tHZ(1,2) CE1 tCO CE2 tLZ(2) tOHZ(1) tOE OE tOLZ tLB, tUB LB, UB tLBLZ, tUBLZ Data Out High-Z tLBHZ, tUBHZ Data Valid Stock No. 23211-03 9/21/06 ADVANCE INFORMATION The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com. 6 N08M1618L1A AMI Semiconductor, Inc. Advance Information Timing Waveform of Page Mode Read Cycle (WE = VIH) tRC Page Address (A4 - A18) tAAP tAA Word Address (A0 - A3) tHZ CE1 tCO CE2 tOE tOHZ OE tOLZ tLB, tUB LB, UB tLBLZ, tUBLZ Data Out tLBHZ, tUBHZ High-Z Stock No. 23211-03 9/21/06 ADVANCE INFORMATION The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com. 7 N08M1618L1A AMI Semiconductor, Inc. Advance Information Timing Waveform of Write Cycle (WE control) tWC Address tWR tAW CE1 tCW CE2 tLBW, tUBW LB, UB tAS tWP WE tDW High-Z tDH Data Valid Data In tWHZ Data Out tOW High-Z Stock No. 23211-03 9/21/06 ADVANCE INFORMATION The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com. 8 N08M1618L1A AMI Semiconductor, Inc. Advance Information Timing Waveform of Write Cycle (CE1 Control) tWC Address tAW CE1 (for CE2 Control, use inverted signal) tWR tCW tAS tLBW, tUBW LB, UB tWP WE tDW Data Valid Data In tLZ Data Out tDH tWHZ High-Z Stock No. 23211-03 9/21/06 ADVANCE INFORMATION The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com. 9 N08M1618L1A AMI Semiconductor, Inc. Advance Information Ball Grid Array Package 0.200.05 1.100.10 D A1 BALL PAD CORNER (3) 1. 0.300.05 DIA. E 2. SEATING PLANE - Z 0.15 Z 0.05 TOP VIEW Z SIDE VIEW 1. DIMENSION IS MEASURED AT THE A1 BALL PAD MAXIMUM SOLDER BALL DIAMETER. CORNER PARALLEL TO PRIMARY Z. SD e SE 2. PRIMARY DATUM Z AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 3. A1 BALL PAD CORNER I.D. TO BE MARKED BY INK. K TYP J TYP e BOTTOM VIEW Dimensions (mm) e = 0.75 D 80.10 SD SE J K BALL MATRIX TYPE 0.375 0.375 2.125 2.375 FULL E 100.10 Stock No. 23211-03 9/21/06 ADVANCE INFORMATION The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com. 10 N08M1618L1A AMI Semiconductor, Inc. Advance Information Ordering Information N08M1618L1AX-XX X Temperature Performance Package Type I = Industrial, -40C to 85C 85 = 85ns @ 1.7V B = 48-ball BGA D = Known Good Die Revision History Revision # Date Change Description 01 11/01/02 Initial Release 02 3/03/05 General Update: Updated ICC4 typical and ISB1 typical value Updated Block Diagram, Functional Description Table. Added tAAP, tLB, tUB, tLBZ, tUBZ, tLBHZ, tUBHZ, tLBW, tUBW timing parameters. Added Page Mode Read Timing Waveform Updated BGA 8X10 Package Drawing Updated VccQ range on DC Parameters Table 03 9/21/2006 Converted to AMI Semiconductor (c) 2006 AMI Semiconductor, Inc. All rights reserved. AMI Semiconductor, Inc. ("AMIS") reserves the right to change or modify the information contained in this data sheet and the products described therein, without prior notice. AMIS does not convey any license under its patent rights nor the rights of others. Charts, drawings and schedules contained in this data sheet are provided for illustration purposes only and they vary depending upon specific applications. AMIS makes no warranty or guarantee regarding suitability of these products for any particular purpose, nor does AMIS assume any liability arising out of the application or use of any product or circuit described herein. AMIS does not authorize use of its products as critical components in any application in which the failure of the AMIS product may be expected to result in significant injury or death, including life support systems and critical medical instruments. Stock No. 23211-03 9/21/06 ADVANCE INFORMATION The specifications of this device are subject to change without notice. For latest documentation see http://www.amis.com. 11