BCM8210
®
2.488 GBPS FULLY INTEGRATED LOW POWER SONET/SDH TRANSCEIVER
Application Block Diagram
•Fully integrated OC-48/STM-16 SONET/SDH transceiver with
CDR, MUX, DEMUX, and CMU
•16-bit, 155.52-Mbps LVPECL interfaceUse Bullet for these
•On-chip, PLL-based clock generator
• Loss-of-signal (LOSB) output
•Line and system loopback modes
•Lock detect
•Meets SONET, Telcordia, and ITU-T jitter requirements
•Powe r supply: 2.5V (co re ), 3.3V (LVP E CL I/O )
•Power dissipation: 1.2W typical
•14 ¥ 20 mm,128-pin PQFP package
•Standard CMOS fabrication process
•First CMOS OC-48 transceiver in the world.
•Low power consumption eliminates external heat sink, fans for
system airf low, and expensive high current power supplies.
•High integration reduce s design cycle and tim e to market.
•Increased port density per board and system.
•CMOS-based devi ce takes advantag e of the m ost effective
silicon economy of scale .
•Features low-jitter CMU: 3 mUIRMS typical.
•Target applications:
•OC-4 8/S TM- 1 6 tra nsm is s ion eq uip m en t
•SONET/SDH optical module s and test equ ipment
•ADD/DROP multiplexers
•Digital cross-connects
•ATM switch backbones
•Terabit routers
•Edge routers
FEATURES SUMMARY OF BENEFITS
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BCM8210
BCM8210
16
16
16
16
BCM8210 OVERVIEW
®
Phone: 949-450-8700
Fax: 949-450-8710
E-mail: info@broadcom.com
Web: www.broadcom.com
BROADCOM CORPORATION
16215 Alton Parkway, P.O. Box 57013
Irvine, California 92619-7013
© 2004 by BROADCOM CORPORATION. All rights reserved.
8210-PB07-R 04/15/03
Broadcom®, the pulse logo, and Connecting everything® are trademarks of Broadcom Corporation and/
or its subsidiaries in the United States and certain other countries. All other trademarks mentioned are the
property of their respective owners.
The BCM8210 SONET/SDH transceiver is a fully integrated
serialization/deserialization SONET OC-48 and STM SDH-16 (2.488
Gbps) interface device with an integrated clock multiplication unit
(CMU) and an integrated clock and data recovery circuit (CDR). On-
chip clock synthesis is performed by the high-frequency, low-jitter,
phase-locked loop on the BCM8210 transceiver chip, allowing the use of
a slower 77.76 MHz external transmit clock reference. Clock recovery is
performed on the device by synchronizing its on-chip VCO directly to
the incoming data stream. The low-jitter LVPECL interface guarantees
compliance with the bit error rate requiremen ts of the Telcordia GR-2 53-
CORE, ANSI, and ITU-T standards. The BCM8210 is packaged in a 14
¥ 20 mm, 128-pin PQFP.
Transmitter Functions
•16-bit parallel input
•2.488-GHz clo ck generation
•Elastic buffering
•Parallel-to -serial conversion
•Serial differential data output
Receiver Functions
•16-bit parallel output
•2.488-Gbps differential data input
•Clock and data recovery (CDR)
•Serial-to-parallel conversion
16
x
5
FIFO
VCP_CDR
VCN_CDR
RESETB
CLK16IP
CLK16IN
DI0
DI15
REFCKP
REFCKN
RDINP
RDINN
LPBKFB
LPBKSB
TXDP
TXDN
TXCKP
TXCKN
TCK16O
LOSB
DO0
DO15
RCK16OP
RCK16ON
LCKDET
FIFO
Control
Write
Pointer
Read
Pointer
Output
Retime
Input Register
2.488-GHz PLL DIVIDE-BY-16
16:1 Parallel-
to-Serial
LOS Detect
1:16 Serial-
to-Parallel
Output Register
DIVIDE-BY-16
CDR
Loop-
back
Logic
