W9816G6IB
512K × 2 BANKS × 16 BITS SDRAM
Publication Release Date: Dec. 24, 2009
- 1 - Revision A01
Table of Contents-
1. GENERAL DESCRIPTION ......................................................................................................... 3
2. FEATURES ................................................................................................................................. 3
3. AVAILABLE PART NUMBER ..................................................................................................... 3
4. BALL CONFIGURATION ............................................................................................................ 4
5. BALL DESCRIPTION.................................................................................................................. 5
6. BLOCK DIAGRAM ...................................................................................................................... 6
7. FUNCTIONAL DESCRIPTION ................................................................................................... 7
7.1 Power Up and Initialization ............................................................................................. 7
7.2 Programming Mode Register.......................................................................................... 7
7.3 Bank Activate Command ................................................................................................ 7
7.4 Read and Write Access Modes ...................................................................................... 7
7.5 Burst Read Command .................................................................................................... 8
7.6 Burst Write Command .................................................................................................... 8
7.7 Read Interrupted by a Read ........................................................................................... 8
7.8 Read Interrupted by a Write............................................................................................ 8
7.9 Write Interrupted by a Write............................................................................................ 8
7.10 Write Interrupted by a Read............................................................................................ 8
7.11 Burst Stop Command ..................................................................................................... 9
7.12 Addressing Sequence of Sequential Mode .................................................................... 9
7.13 Addressing Sequence of Interleave Mode ..................................................................... 9
7.14 Auto-precharge Command ........................................................................................... 10
7.15 Precharge Command.................................................................................................... 10
7.16 Self Refresh Command ................................................................................................ 10
7.17 Power Down Mode ....................................................................................................... 11
7.18 No Operation Command............................................................................................... 11
7.19 Deselect Command ...................................................................................................... 11
7.20 Clock Suspend Mode.................................................................................................... 11
8. OPERATION MODE ................................................................................................................. 12
9. ELECTRICAL CHARACTERISTICS......................................................................................... 13
9.1 Absolute Maximum Ratings .......................................................................................... 13
9.2 Recommended DC Operating Conditions .................................................................... 13
W9816G6IB
Publication Release Date: Dec. 24, 2009
- 2 - Revision A01
9.3 Capacitance.................................................................................................................. 13
9.4 DC Characteristics........................................................................................................ 14
9.5 AC Characteristics ........................................................................................................ 15
10. TIMING WAVEFORMS............................................................................................................. 17
10.1 Command Input Timing ................................................................................................ 17
10.2 Read Timing.................................................................................................................. 18
10.3 Control Timing of Input/Output Data............................................................................. 19
10.4 Mode Register Set Cycle .............................................................................................. 20
11. OPERATING TIMING EXAMPLE ............................................................................................. 21
11.1 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)...................................... 21
11.2 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto-precharge)........... 22
11.3 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3)...................................... 23
11.4 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto-precharge)........... 24
11.5 Interleaved Bank Write (Burst Length = 8) ................................................................... 25
11.6 Interleaved Bank Write (Burst Length = 8, Auto-precharge) ........................................ 26
11.7 Page Mode Read (Burst Length = 4, CAS Latency = 3) .............................................. 27
11.8 Page Mode Read / Write (Burst Length = 8, CAS Latency = 3)................................... 28
11.9 Auto Precharge Read (Burst Length = 4, CAS Latency = 3)........................................ 29
11.10 Auto Precharge Write (Burst Length = 4).................................................................... 30
11.11 Auto Refresh Cycle ..................................................................................................... 31
11.12 Self Refresh Cycle....................................................................................................... 32
11.13 Burst Read and Single Write (Burst Length = 4, CAS Latency = 3) ........................... 33
11.14 Power Down Mode ...................................................................................................... 34
11.15 Auto-precharge Timing (Read Cycle) ......................................................................... 35
11.16 Auto-precharge Timing (Write Cycle).......................................................................... 36
11.17 Timing Chart of Read to Write Cycle........................................................................... 37
11.18 Timing Chart of Write to Read Cycle........................................................................... 37
11.19 Timing Chart of Burst Stop Cycle (Burst Stop Command).......................................... 38
11.20 Timing Chart of Burst Stop Cycle (Precharge Command).......................................... 38
11.21 CKE/DQM Input Timing (Write Cycle)......................................................................... 39
11.22 CKE/DQM Input Timing (Read Cycle)......................................................................... 40
12. PACKAGE SPECIFICATION .................................................................................................... 41
12.1 VFBGA 60 Ball (6.4X10.10 mm, Ball pitch:0.65mm, Ø=0.4mm).................................. 41
13. REVISION HISTORY ................................................................................................................42
W9816G6IB
Publication Release Date: Dec. 24, 2009
- 3 - Revision A01
1. GENERAL DESCRIPTION
W9816G6IB is a high-speed synchronous dynamic random access memory (SDRAM), organized as
512K words × 2 banks × 16 bits. W9816G6IB delivers a data bandwidth of up to 166M words per
second (-6). For different applications the W9816G6IB is sorted into two speed grades: -6 and -7. The
-6 parts can run up to 166MHz/CL3. The -7 parts can run up to 143MHz/CL3.
Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be
accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE
command. Column addresses are automatically generated by the SDRAM internal counter in burst
operation. Random column read is also possible by providing its address at each clock cycle. The
multiple bank nature enables interleaving among internal banks to hide the precharging time.
By having a programmable Mode Register, the system can change burst length, latency cycle,
interleave or sequential burst to maximize its performance. W9816G6IB is ideal for main memory in
high performance applications.
2. FEATURES
• 2.7V~3.6V power supply for -7 speed grade
• 3.3V ± 0.3V power supply for -6 speed grade
• 524,288 words x 2 banks x 16 bits organization
• Self Refresh current: standard and low power
• CAS Latency: 2 and 3
• Burst Length: 1, 2, 4, 8 and Full Page
• Burst Read, Single Writes Mode
• Byte Data Controlled by LDQM, UDQM
• Auto-precharge and Controlled Precharge
• 4K Refresh Cycles/64 mS
• Interface: LVTTL
• Packaged in VFBGA 60 balls pitch=0.65mm, using Lead free materials with RoHS compliant
3. AVAILABLE PART NUMBER
PART NUMBER SPEED GRADE SELF REFRESH CURRENT
(MAX.)
OPERATING
TEMPERATURE
W9816G6IB-6 166MHz/CL3 2mA 0°C ~ 70°C
W9816G6IB-7 143MHz/CL3 2mA 0°C ~ 70°C
W9816G6IB
Publication Release Date: Dec. 24, 2009
- 4 - Revision A01
4. BALL CONFIGURATION
Bottom View
76 21
C
B
A
P
N
G
D
E
M
H
L
F
K
R
J
Vss
Vss
DQ14
DQ13
DQ12
DQ10
DQ8
NC
NC
NC
CKE
BA
A8
A6
DQ9
DQ15
A4
VssQ
VDDQ
DQ11
VssQ
NC
NC
UDQM
CLK
NC
A9
A7
A5
VDDQ
VDD
VDD
DQ1
DQ2
DQ3
DQ5
DQ7
NC
WE#
CAS#
CS#
NC
A10
A1
DQ6
DQ0
A3
VDDQ
VssQ
DQ4
VDDQ
NC
NC
LDQM
RAS#
NC
NC
A0
A2
VssQ
Top View
7621
C
B
A
P
N
G
D
E
M
H
L
F
K
R
J
Vss
Vss
DQ14
DQ13
DQ12
DQ10
DQ8
NC
NC
NC
CKE
BA
A8
A6
DQ9
DQ15
A4
VssQ
VDDQ
DQ11
VssQ
NC
NC
UDQM
CLK
NC
A9
A7
A5
VDDQ
VDD
VDD
DQ1
DQ2
DQ3
DQ5
DQ7
NC
WE#
CAS#
CS#
NC
A10
A1
DQ6
DQ0
A3
VDDQ
VssQ
DQ4
VDDQ
NC
NC
LDQM
RAS#
NC
NC
A0
A2
VssQ
W9816G6IB
Publication Release Date: Dec. 24, 2009
- 5 - Revision A01
5. BALL DESCRIPTION
Ball-Location Ball Name Function Description
N6, P7, P6, R6,
R2, P2, P1, N2,
N1, M2, N7
A0−A10 Address Multiplexed pins for row and column address.
Row address: A0−A10. Column address: A0−A7.
M1 BA Bank Address
Select bank to activate during row address latch
time, or bank to read/write during column address
latch time.
A6, B7, C7, D7,
D6, E7, F7, G7,
G1, F1, E1, D2,
D1, C1, B1, A2,
DQ0−DQ15 Data Input/
Output Multiplexed pins for data input and output.
L7 CS Chip Select
Disable or enable the command decoder. When
command decoder is disabled, new command is
ignored and previous operation continues.
K6 RAS Row Address
Strobe
Command input. When sampled at the rising edge o
f
the clock, RAS , CAS and WE define the
operation to be executed.
K7 CAS Column Address
Strobe Referred to RAS
J7 WE Write Enable Referred to RAS
J2/J6 UDQM/
LDQM
Input/Output
Mask
The output buffer is placed at Hi-Z (with latency of 2)
when DQM is sampled high in read cycle. In write
cycle, sampling DQM high will block the write
operation with zero latency.
K2 CLK Clock Inputs
System clock used to sample inputs on the rising
edge of clock.
L1 CKE Clock Enable
CKE controls the clock activation and deactivation.
When CKE is low, Power Down mode, Suspend
mode, or Self Refresh mode is entered.
A7, R7 VCC Power (+3.3V)
Power for input buffers and logic circuit inside
DRAM.
A1, R1 VSS Ground
Ground for input buffers and logic circuit inside
DRAM.
B6, C2, E6, F2 VCCQ Power (+3.3V) for
I/O buffer
Separated power from VCC, used for output buffers
to improve noise immunity.
B2, C6, E2, F6 VSSQ Ground for I/O
buffer
Separated ground from VSS, used for output buffers
to improve noise immunity.
G2, G6, H1, H2,
H6, H7, J1, K1,
L2, L6, M6, M7
NC No Connection
No connection. (NC pin should be connected to
GND
or floating)
W9816G6IB
Publication Release Date: Dec. 24, 2009
- 6 - Revision A01
6. BLOCK DIAGRAM
CLK
CKE
A10
CLOCK
BUFFER
COMMAND
DECODER
ADDRESS
BUFFER
REFRESH
COUNTER
COLUMN
COUNTER
CONTROL
SIGNAL
GENERATOR
MODE
REGISTER
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #0
R
O
W
D
E
C
O
D
E
R
DQ0
DQ15
LDQM
UDQM
DQ
BUFFER
CS
RAS
CAS
WE
DATA CONTROL
CIRCUIT
Note: The cell array configuration is 2048 * 256 * 16
COLUMN DECODER
SENSE AMPLIFIER
CELL ARRAY
BANK #1
A0
A9
BA
R
O
W
D
E
C
O
D
E
R
W9816G6IB
Publication Release Date: Dec. 24, 2009
- 7 - Revision A01
7. FUNCTIONAL DESCRIPTION
7.1 Power Up and Initialization
The default power up state of the mode register is unspecified. The following power up and
initialization sequence need to be followed to guarantee the device being preconditioned to each user
specific needs during power up, all VCC and VCCQ pins must be ramp up simultaneously to the
specified voltage when the input signals are held in the "NOP" state. The power up voltage must not
exceed VCC + 0.3V on any of the input pins or VCC supplies. After power up, an initial pause of 200 µS
is required followed by a precharge of all banks using the precharge command. To prevent data
contention on the DQ bus during power up, it is required that the DQM and CKE pins be held high
during the initial pause period. Once all banks have been precharged, the Mode Register Set
Command must be issued to initialize the Mode Register. An additional eight Auto Refresh cycles
(CBR) are also required before or after programming the Mode Register to ensure proper subsequent
operation.
7.2 Programming Mode Register
After initial power up, the Mode Register Set Command must be issued for proper device operation.
All banks must be in a precharged state and CKE must be high at least one cycle before the Mode
Register Set Command can be issued. The Mode Register Set Command is activated by the low
signals of RAS , CAS , CS and WE at the positive edge of the clock. The address input data
during this cycle defines the parameters to be set as shown in the Mode Register Operation table. A
new command may be issued following the mode register set command once a delay equal to tRSC
has elapsed. Please refer to the next page for Mode Register Set Cycle and Operation Table.
7.3 Bank Activate Command
The Bank Activate command must be applied before any Read or Write operation can be executed.
The operation is similar to RAS activate in EDO DRAM. The delay from when the Bank Activate
command is applied to when the first read or write operation can begin must not be less than the RAS
to CAS delay time (tRCD). Once a bank has been activated it must be precharged before another Bank
Activate command can be issued to the same bank. The minimum time interval between successive
Bank Activate commands to the same bank is determined by the RAS cycle time of the device (tRC).
The minimum time interval between interleaved Bank Activate commands (Bank A to Bank B and vice
versa) is the Bank-to-Bank delay time (tRRD). The maximum time that each bank can be held active is
specified as tRAS(max.).
7.4 Read and Write Access Modes
After a bank has been activated, a read or write cycle can be followed. This is accomplished by setting
RAS high and CAS low at the clock rising edge after minimum of tRCD delay. WE pin voltage level
defines whether the access cycle is a read operation ( WE high), or a write operation ( WE low). The
address inputs determine the starting column address. Reading or writing to a different row within an
activated bank requires the bank be precharged and a new Bank Activate command be issued. When
more than one bank is activated, interleaved bank Read or Write operations are possible. By using the
programmed burst length and alternating the access and precharge operations between multiple
banks, seamless data access operation among many different pages can be realized. Read or Write
Commands can also be issued to the same bank or between active banks on every clock cycle.
W9816G6IB
Publication Release Date: Dec. 24, 2009
- 8 - Revision A01
7.5 Burst Read Command
The Burst Read command is initiated by applying logic low level to CS and CAS while holding
RAS and WE high at the rising edge of the clock. The address inputs determine the starting column
address for the burst. The Mode Register sets type of burst (sequential or interleave) and the burst
length (1, 2, 4, 8 and full page) during the Mode Register Set Up cycle. Table 2 and 3 in the next page
explain the address sequence of interleave mode and sequence mode.
7.6 Burst Write Command
The Burst Write command is initiated by applying logic low level to CS , CAS and WE while
holding RAS high at the rising edge of the clock. The address inputs determine the starting column
address. Data for the first burst write cycle must be applied on the DQ pins on the same clock cycle
that the Write Command is issued. The remaining data inputs must be supplied on each subsequent
rising clock edge until the burst length is completed. Data supplied to the DQ pins after burst finishes
will be ignored.
7.7 Read Interrupted by a Read
A Burst Read may be interrupted by another Read Command. When the previous burst is interrupted,
the remaining addresses are overridden by the new read address with the full burst length. The data
from the first Read Command continues to appear on the outputs until the CAS Latency from the
interrupting Read Command the is satisfied.
7.8 Read Interrupted by a Write
To interrupt a burst read with a Write Command, DQM may be needed to place the DQs (output
drivers) in a high impedance state to avoid data contention on the DQ bus. If a Read Command will
issue data on the first and second clocks cycles of the write operation, DQM is needed to insure the
DQs are tri-stated. After that point the Write Command will have control of the DQ bus and DQM
masking is no longer needed.
7.9 Write Interrupted by a Write
A burst write may be interrupted before completion of the burst by another Write Command. When the
previous burst is interrupted, the remaining addresses are overridden by the new address and data
will be written into the device until the programmed burst length is satisfied.
7.10 Write Interrupted by a Read
A Read Command will interrupt a burst write operation on the same clock cycle that the Read
Command is activated. The DQs must be in the high impedance state at least one cycle before the
new read data appears on the outputs to avoid data contention. When the Read Command is
activated, any residual data from the burst write cycle will be ignored.
W9816G6IB
Publication Release Date: Dec. 24, 2009
- 9 - Revision A01
7.11 Burst Stop Command
A Burst Stop Command may be used to terminate the existing burst operation but leave the bank
open for future Read or Write Commands to the same page of the active bank, if the burst length is full
page. Use of the Burst Stop Command during other burst length operations is illegal. The Burst Stop
Command is defined by having RAS and CAS high with CS and WE low at the rising edge of
the clock. The data DQs go to a high impedance state after a delay, which is equal to the CAS
Latency in a burst read cycle, interrupted by Burst Stop. If a Burst Stop Command is issued during a
full page burst write operation, then any residual data from the burst write cycle will be ignored.
7.12 Addressing Sequence of Sequential Mode
A column access is performed by increasing the address from the column address, which is input to
the device. The disturb address is varied by the Burst Length as shown in Table 2.
Table 2 Address Sequence of Sequential Mode
DATA ACCESS ADDRESS BURST LENGTH
Data 0 n BL = 2 (disturb address is A0)
Data 1 n + 1 No address carry from A0 to A1
Data 2 n + 2 BL = 4 (disturb addresses are A0 and A1)
Data 3 n + 3 No address carry from A1 to A2
Data 4 n + 4
Data 5 n + 5 BL = 8 (disturb addresses are A0, A1 and A2)
Data 6 n + 6 No address carry from A2 to A3
Data 7 n + 7
7.13 Addressing Sequence of Interleave Mode
A column access is started in the input column address and is performed by inverting the address bit
in the sequence shown in Table 3.
Table 3 Address Sequence of Interleave Mode
DATA ACCESS ADDRESS BURST LENGTH
Data 0 A8 A7 A6 A5 A4 A3 A2 A1 A0 BL = 2
Data 1 A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 2 A8 A7 A6 A5 A4 A3 A2 A1 A0 BL = 4
Data 3 A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 4 A8 A7 A6 A5 A4 A3 A2 A1 A0 BL = 8
Data 5 A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 6 A8 A7 A6 A5 A4 A3 A2 A1 A0
Data 7
A
8 A7 A6 A5 A4 A3 A2 A1 A0
W9816G6IB
Publication Release Date: Dec. 24, 2009
- 10 - Revision A01
7.14 Auto-precharge Command
If A10 is set to high when the Read or Write Command is issued, then the Auto-precharge function is
entered. During Auto-precharge, a Read Command will execute as normal with the exception that the
active bank will begin to precharge automatically before all burst read cycles have been completed.
Regardless of burst length, it will begin a certain number of clocks prior to the end of the scheduled
burst cycle. The number of clocks is determined by CAS Latency.
A Read or Write Command with Auto-precharge can not be interrupted before the entire burst
operation is completed. Therefore, use of a Read, Write, or Precharge Command is prohibited during
a read or write cycle with Auto-precharge. Once the precharge operation has started, the bank cannot
be reactivated until the Precharge time (tRP) has been satisfied. Issue of Auto-precharge command is
illegal if the burst is set to full page length. If A10 is high when a Write Command is issued, the Write
with Auto-precharge function is initiated. The SDRAM automatically enters the precharge operation
two clock delay from the last burst write cycle. This delay is referred to as Write tWR. The bank
undergoing Auto-precharge can not be reactivated until tWR and tRP are satisfied. This is referred to as
tDAL, Data-in to Active delay (tDAL = tWR + tRP). When using the Auto-precharge Command, the interval
between the Bank Activate Command and the beginning of the internal precharge operation must
satisfy tRAS(min).
7.15 Precharge Command
The Precharge Command is used to precharge or close a bank that has been activated. The
Precharge Command is entered when CS , RAS and WE are low and CAS is high at the rising
edge of the clock. The Precharge Command can be used to precharge each bank separately or all
banks simultaneously. The address bits, A10, and BA, are used to define which bank(s) is to be
precharged when the command is issued. After the Precharge Command is issued, the precharged
bank must be reactivated before a new read or write access can be executed. The delay between the
Precharge Command and the Activate Command must be greater than or equal to the Precharge time
(tRP).
7.16 Self Refresh Command
The Self-Refresh Command is defined by having CS , RAS , CAS and CKE held low with WE
high at the rising edge of the clock. All banks must be idle prior to issuing the Self-Refresh Command.
Once the command is registered, CKE must be held low to keep the device in Self-Refresh mode.
When the SDRAM has entered Self Refresh mode all of the external control signals, except CKE, are
disabled. The clock is internally disabled during Self-Refresh Operation to save power. The device will
exit Self-Refresh operation after CKE is returned high. Any subsequent commands can be issued
after tXSR from the end of Self Refresh command.
If, during normal operation, Auto-Refresh cycles are issued in bursts (as opposed to being evenly
distributed), a burst of 2,048 Auto-Refresh cycles should be completed just prior to entering and just
after exiting the Self-Refresh mode.
W9816G6IB
Publication Release Date: Dec. 24, 2009
- 11 - Revision A01
7.17 Power Down Mode
The Power Down mode is initiated by holding CKE low. All of the receiver circuits except CKE are
gated off to reduce the power. The Power Down mode does not perform any refresh operations;
therefore the device can not remain in Power Down mode longer than the Refresh period (tREF) of the
device.
The Power Down mode is exited by bringing CKE high. When CKE goes high, a No Operation
Command is required on the next rising clock edge, depending on tCK. The input buffers need to be
enabled with CKE held high for a period equal to tCKS(min) + tCK(min).
7.18 No Operation Command
The No Operation Command should be used in cases when the SDRAM is in an idle or a wait state to
prevent the SDRAM from registering any unwanted commands between operations. A No Operation
Command is registered when CS is low with RAS , CAS and WE held high at the rising edge of
the clock. A No Operation Command will not terminate a previous operation that is still executing,
such as a burst read or write cycle.
7.19 Deselect Command
The Deselect Command performs the same function as a No Operation Command. Deselect
Command occurs when CS is brought high, the RAS , CAS and WE signals become don't cares.
7.20 Clock Suspend Mode
During normal access mode, CKE must be held high enabling the clock. When CKE is registered low
while at least one of the banks is active, Clock Suspend Mode is entered. The Clock Suspend mode
deactivates the internal clock and suspends any clocked operation that was currently being executed.
There is a one-clock delay between the registration of CKE low and the time at which the SDRAM
operation suspends. While in Clock Suspend mode, the SDRAM ignores any new commands that are
issued. The Clock Suspend mode is exited by bringing CKE high. There is a one-clock cycle delay
from when CKE returns high to when Clock Suspend mode is exited.
W9816G6IB
Publication Release Date: Dec. 24, 2009
- 12 - Revision A01
8. OPERATION MODE
Fully synchronous operations are performed to latch the commands at the positive edges of CLK.
Table 1 shows the truth table for the operation commands.
TABLE 1 TRUTH TABLE (NOTE 1, 2)
COMMAND DEVICE
STATE CKEn-1 CKEn DQM BA A10 A9-A0 CS RAS CAS WE
Bank Active Idle H X X V V V L L H H
Bank Precharge Any H X X V L X L L H L
Precharge All Any H X X X H X L L H L
Write Active
(3) H X X V L V L H L L
Write with Auto-precharge Active (3) H X X V H V L H L L
Read Active
(3) H X X V L V L H L H
Read with Auto-precharge Active (3) H X X V H V L H L H
Mode Register Set Idle H X X V V V L L L L
No-Operation Any H X X X X X L H H H
Burst Stop Active (4) H X X X X X L H H L
Device Deselect Any H X X X X X H X X X
Auto-Refresh Idle H H X X X X L L L H
Self-Refresh Entry Idle H L X X X X L L L H
Self-Refresh Exit Idle
(S.R)
L
L
H
H
X
X
X
X
X
X
X
X
H
L
X
H
X
H
X
X
Clock Suspend Mode
Entry Active H L X X X X X X X X
Power Down Mode Entry Idle
Active (5)
H
H
L
L
X
X
X
X
X
X
X
X
H
L
X
H
X
H
X
X
Clock Suspend Mode Exit Active L H X X X X X X X X
Power Down Mode Exit Any
(power down)
L
L
H
H
X
X
X
X
X
X
X
X
H
L
X
H
X
H
X
X
Data Write/Output Enable Active H X L X X X X X X X
Data Write/Output Disable Active H X H X X X X X X X
Notes：(1) V = Valid, X = Don't care, L = Low Level, H = High Level
(2) CKEn signal is input level when commands are provided.
CKEn-1 signal is the input level one clock cycle before the command is issued.
(3) These are state of bank designated by BA signals.
(4) Device state is full page burst operation.
(5) Power Down Mode can not be entered in the burst cycle.
When this command asserts in the burst cycle, device state is clock suspend mode.
W9816G6IB
Publication Release Date: Dec. 24, 2009
- 13 - Revision A01
9. ELECTRICAL CHARACTERISTICS
9.1 Absolute Maximum Ratings
PARAMETER SYMBOL RATING UNIT NOTES
Input, Output Voltage VIN, VOUT -1 ~ VCC + 0.3 V 1
Power Supply Voltage VCC, VCCQ -1~ 4.6 V 1
Operating Temperature TOPR 0 ~ 70 °C 1
Storage Temperature TSTG -55 ~ 150 °C 1
Soldering Temperature (10s) TSOLDER 260 °C 1
Power Dissipation PD 1 W 1
Short Circuit Output Current IOUT 50 mA 1
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability
of the device.
9.2 Recommended DC Operating Conditions
(TA = 0 to 70°C)
PARAMETER SYM. MIN. TYP. MAX. UNIT NOTES
Power Supply Voltage for -6 VCC 3.0 3.3 3.6 V 2
Power Supply Voltage for -7 VCC 2.7 3.3 3.6 V 2
Power Supply Voltage for -6 (for I/O Buffer) VCCQ 3.0 3.3 3.6 V 2
Power Supply Voltage for -7 (for I/O Buffer) VCCQ 2.7 3.3 3.6 V 2
Input High Voltage VIH 2.0 - VCC + 0.3 V 2
Input Low Voltage VIL -0.3 - 0.8 V 2
Note: VIH (max.) = VCC/VCCQ +1.5V for pulse width < 5 nS
VIL (min.) = VSS/VSSQ -1.5V for pulse width < 5 nS
9.3 Capacitance
(VCC = 3.3V, TA = 25 °C, f = 1MHz)
PARAMETER SYM. MIN. MAX. UNIT
Input Capacitance (A0 to A10, BA, CS , RAS , CAS , WE ,
UDQM, LDQM, CKE) CI - 4 pf
Input Capacitance (CLK) - 4 pf
Input/Output capacitance (DQ0 to DQ15) CIO - 5.5 pf
Note: These parameters are periodically sampled and not 100% tested
W9816G6IB
Publication Release Date: Dec. 24, 2009
- 14 - Revision A01
9.4 DC Characteristics
(VCC = 3.3V ±0.3V for -6I, VCC = 2.7V to 3.6V for -7, TA = 0 to 70°C)
PARAMETER SYM.
-6
MAX.
-7
MAX. UNIT NOTES
Operating Current
tCK = min., tRC = min.
Active precharge command cycling
without burst operation
1 Bank Operation ICC1 60 50 3
CKE = VIH I
CC2 30 25 3
Standby Current
tCK = min., CS = VIH
VIH /L = VIH (min.) / VIL (max.)
Bank: inactive state
CKE = VIL
(Power Down mode) ICC2P 2 2 3
CKE = VIH
ICC2S 10 10
Standby Current
CLK = VIL, CS = VIH
VIH/L = VIH (min.) / VIL (max.)
Bank: inactive state
CKE = VIL
(Power Down mode) ICC2PS 2 2 mA
CKE = VIH I
CC3 40 35
No Operating Current
tCK = min., CS = VIH (min.)
Bank: active state (2 Banks) CKE = VIL
(Power Down mode) ICC3P 10 10
Burst Operating Current
(tCK = min.)
Read/ Write command cycling
ICC4 110 100 3, 4
Auto Refresh Current
(tCK = min.)
Auto refresh command cycling
ICC5 55 50 3
Self Refresh Current
(CKE = 0.2V)
Self refresh mode
ICC6 2 2 mA
PARAMETER SYM. MIN. MAX. UNIT NOTES
Input Leakage Current
(0V ≤ VIN ≤ VCC, all other pins not under test = 0V) II(L) -5 5 µA
Output Leakage Current
(Output disable , 0V ≤ VOUT ≤ VCCQ ) IO(L) -5 5 µA
LVTTL Output ″H″ Level Voltage
(IOUT = -2 mA) VOH 2.4 - V
LVTTL Output ″L″ Level Voltage
(IOUT = 2 mA) VOL - 0.4 V
W9816G6IB
Publication Release Date: Dec. 24, 2009
- 15 - Revision A01
9.5 AC Characteristics
(VCC = 3.3V ±0.3V for -6I, VCC = 2.7V to 3.6V for -7, TA = 0 to 70°C)
-6 -7
PARAMETER SYM.
MIN. MAX. MIN. MAX.
UNIT NOTES
Ref/Active to Ref/Active Command Period tRC 60 65
Active to Precharge Command Period tRAS 42 100000 45 100000
Active to Read/Write Command Delay Time tRCD 18 20
nS
Read/Write(a) to Read/Write(b)Command Period tCCD 1 1 tCK
Precharge to Active(b) Command Period tRP 18 18
Active(a) to Active(b) Command Period tRRD 12 14 nS
CL* = 2 2 2
Write Recovery Time CL* = 3 tWR 2 2
tCK
CL* = 2 8 1000 10 1000
CLK Cycle Time CL* = 3 tCK 6 1000 7 1000
CLK High Level Width tCH 2 2 8
CLK Low Level Width tCL 2 2 8
CL* = 2 5.5 5.5 9
Access Time from CLK CL* = 3 tAC 5 5 9
Output Data Hold Time tOH 2 2 9
Output Data High Impedance Time tHZ 2 6 2.5 7 7
Output Data Low Impedance Time tLZ 0 0 9
Power Down Mode Entry Time tSB 0 6 0 7
Data-in-Set-up Time tDS 1.5 1.5 8
Data-in Hold Time tDH 0.7 1 8
Address Set-up Time tAS 1.5 1.5 8
Address Hold Time tAH 0.7 1 8
CKE Set-up Time tCKS 1.5 1.5 8
CKE Hold Time tCKH 0.7 1 8
Command Set-up Time tCMS 1.5 1.5 8
Command Hold Time tCMH 0.7 1
nS
8
Refresh Time tREF 64 64 mS
Mode Register Set Cycle Time tRSC 2 2 tCK
Exit self refresh to ACTIVE command tXSR 72 75 nS
W9816G6IB
Publication Release Date: Dec. 24, 2009
- 16 - Revision A01
Notes:
1. Operation exceeds "Absolute Maximum Ratings" may cause permanent damage to the devices.
2. All voltages are referenced to VSS.
• 2.7V~3.6V power supply for -7 speed grade.
• 3.3V ± 0.3V power supply for -6 speed grades.
3. These parameters depend on the cycle rate and listed values are measured at a cycle rate with the
minimum values of tCK and tRC.
4. These parameters depend on the output loading conditions. Specified values are obtained with
output open.
5. Power up sequence please refer to "Functional Description" section described before.
6. AC Test Load diagram.
50 ohms
1.4 V
AC TEST LOAD
Z = 50 ohmsoutput
30pF
7. tHZ defines the time at which the outputs achieve the open circuit condition and is not referenced
to output level.
8. Assumed input rise and fall time (tT ) = 1nS.
If tr & tf is longer than 1nS, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]nS should be added to the parameter
( The tT maximum can’t be more than 10nS for low frequency application. )
9. If clock rising time (tT) is longer than 1nS, (tT /2-0.5)nS should be added to the parameter.
W9816G6IB
Publication Release Date: Dec. 24, 2009
- 17 - Revision A01
10. TIMING WAVEFORMS
10.1 Command Input Timing
t
CK
CLK
A0-A10
BA
VIH
VIL
tCMH tCMS
tCHtCL
tTtT
tCKS tCKH
tCKH
tCKS
tCKS tCKH
CS
RAS
CAS
WE
CKE
tCMS tCMH
tCMS tCMH
tCMS tCMH
tCMS tCMH
tAS tAH
W9816G6IB
Publication Release Date: Dec. 24, 2009
- 18 - Revision A01
10.2 Read Timing
Read CAS Latency
tAC
tLZ
tAC
tOH
tHZ
tOH
Burst Length
Read Command
CLK
CS
RAS
CAS
WE
A0-A10
BA
DQ
Valid
Data-Out
Valid
Data-Out
W9816G6IB
Publication Release Date: Dec. 24, 2009
- 19 - Revision A01
10.3 Control Timing of Input/Output Data
tCMH tCMS tCMH tCMS
tDS tDH tDS tDH tDS tDH tDS tDH
Valid
Data-Out
Valid
Data-Out
Valid
Data-Out
Valid
Data-in
Valid
Data-in
Valid
Data-in
Valid
Data-in
tCKH tCKS tCKH tCKS
tDS tDH tDS tDH tDH
tDS tDS tDH
Valid
Data-in
Valid
Data-in
Valid
Data-in
Valid
Data-in
tCMH tCMS tCMH tCMS
tOH
tAC
tOH
tAC
tOH
tHZ
OPEN
tLZ
tAC
tOH
tAC
tCKH tCKS tCKH tCKS
tOH
tAC
tOH
tAC
tOH
tAC
tOH
tAC
Valid
Data-Out
Valid
Data-Out
Valid
Data-Out
CLK
DQM
DQ0 -15
(Word Mask)
(Clock Mask)
CLK
CKE
DQ0 -15
CLK
Control Timing of Input Data
Control Timing of Output Data
(Output Enable)
(Clock Mask)
DQM
DQ0 -15
CKE
CLK
DQ0 -15
W9816G6IB
Publication Release Date: Dec. 24, 2009
- 20 - Revision A01
10.4 Mode Register Set Cycle
A0
A3 A0
Addressing Mode
A0
0A0
Sequential
A0
1A0
Interleave
A0A9 Single Write Mode
A00A0Burst read and Burst write
A01A0Burst read and single write
A0
A0A2 A1 A0
A00 0 0
A00 0 1
A0
0 1 0
A0
0 1 1
A01 0 0
A0
1 0 1
A0
1 1 0
A0
1 1 1
A0Burst Length
A0Sequential A0Interleave
1A01
A02A02
A0
4A0
4
A08A08
A0
Reserved A0
Reserved
A0
Full Page
A0
CAS Latency
A0Reserved
A0Reserved
2
A03
Reserved
A0
A6 A5 A4
A00 0 0
A00 1 0
A00 1 1
A01 0 0
A00 0 1
tRSC
tCMS tCMH
tCMS tCMH
tCMS tCMH
tCMS tCMH
tAS tAH
CLK
CS
RAS
CAS
WE
A0-A10
BA
Register
set data
next
command
A0
A1
A2
A3
A4
A5
A6
Burst Length
Addressing Mode
CAS Latency
(Test Mode)
A8 Reserved
A0
A7
A0
A9 A0
Write Mode
A10
A0
BA
"0"
"0"
"0"
Reserved
"0"
W9816G6IB
Publication Release Date: Dec. 24, 2009
- 21 - Revision A01
11. OPERATING TIMING EXAMPLE
11.1 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)
W9816G6IB
Publication Release Date: Dec. 24, 2009
- 22 - Revision A01
11.2 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto-precharge)
W9816G6IB
Publication Release Date: Dec. 24, 2009
- 23 - Revision A01
11.3 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
tRC
tRAS tRP
tRP tRAS
tRCD tRCD tRCD
tRRD tRRD
RAa
RAa CAx
RBb
RBb CBy
RAc
RAc CAz
ax0 ax1 ax2 ax3 ax4 ax5 ax6 by0 by1 by4 by5 by6 by7 CZ0
CLK
DQ
CKE
DQM
A0-A9
A10
WE
CAS
RAS
CS
BA
Active Read
Precharge Active Read
Precharge Active
tAC tAC
Read
Precharge
tAC
Bank #0
Bank #1
W9816G6IB
Publication Release Date: Dec. 24, 2009
- 24 - Revision A01
11.4 Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto-precharge)
A0-A9
Bank #0
Bank #1
012345678910 11 12 13 14 15 16 17 18 19 20 21 22 23
tRC
tRAS tRP
tRAS
tRCD tRCD tRCD
tRRD tRRD
ax0 ax1 ax2 ax3 ax4 ax5 ax6 ax7 by0 by1 by4 by5 by6 CZ0
RAa
RAa
CAx
RBb
RBb CBy
RAc
RAc CAz
* AP is the internal precharge start timing
Active Read
Active
Active Read
tAC tAC
tAC
CLK
DQ
CKE
DQM
A10
WE
CAS
RAS
CS
Read
AP*
AP*
BA
tRAS
tRP
W9816G6IB
Publication Release Date: Dec. 24, 2009
- 25 - Revision A01
11.5 Interleaved Bank Write (Burst Length = 8)
012345678910 11 12 13 14 15 16 17 18 19 20 21 22 23
tRC
tRAS tRP
tRAS
tRCD tRCD tRCD
tRRD tRRD
RAa
RAa CAx
RBb
RBb CBy
RAc
RAc CAz
ax0 ax1 by4 by5 by6 by7 CZ0 CZ1 CZ2
Write
Precharge
Active
Active Write
Precharge
Active Write
CLK
DQ
CKE
DQM
A0-A9
A10
WE
CAS
RAS
CS
Bank #0
Bank #1
BA
ax4 ax5 ax6 ax7 by0 by1 by2 by3
W9816G6IB
Publication Release Date: Dec. 24, 2009
- 26 - Revision A01
11.6 Interleaved Bank Write (Burst Length = 8, Auto-precharge)
W9816G6IB
Publication Release Date: Dec. 24, 2009
- 27 - Revision A01
11.7 Page Mode Read (Burst Length = 4, CAS Latency = 3)
W9816G6IB
Publication Release Date: Dec. 24, 2009
- 28 - Revision A01
11.8 Page Mode Read / Write (Burst Length = 8, CAS Latency = 3)
012345678910 11 12 13 14 15 16 17 18 19 20 21 22 23
tRAS
tRCD
tWR
RAa
RAa CAx CAy
ax0 ax1 ax2 ax3 ax4 ax5 ay1
ay0 ay2 ay4ay3
QQ Q Q Q Q DDD
D
D
CLK
DQ
CKE
DQM
A0-A9
A10
WE
CAS
RAS
CS
Active Read Write Precharge
tAC
Bank #0
Bank #1
BA
W9816G6IB
Publication Release Date: Dec. 24, 2009
- 29 - Revision A01
11.9 Auto Precharge Read (Burst Length = 4, CAS Latency = 3)
012345678910 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
DQ
CKE
DQM
A0-A9
A10
BA
WE
CAS
RAS
CS
tRC
tRAS tRP tRAS
tRCD tRCD
tAC
Active Read AP* Active Read
RAa RAb
RAa CAw RAb CAx
aw0 aw1 aw2 aw3
* AP is the internal precharge start timing
Bank #0
Bank #1
tAC
AP*
bx0 bx1 bx2 bx3
W9816G6IB
Publication Release Date: Dec. 24, 2009
- 30 - Revision A01
11.10 Auto Precharge Write (Burst Length = 4)
012345678910 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
DQ
CKE
DQM
A0-A9
A10
BA
WE
CAS
RAS
CS
tRC tRC
tRAS tRP tRAS tRP
RAa
tRCD tRCD
RAb RAc
RAa CAw RAb CAx RAc
aw0 aw1 aw2 aw3 bx0 bx1 bx2 bx3
Active
Active Write AP* Active Write AP*
* AP is the internal precharge start timing
Bank #0
Bank #1
W9816G6IB
Publication Release Date: Dec. 24, 2009
- 31 - Revision A01
11.11 Auto Refresh Cycle
012345678910 11 12 13 14 15 16 17 18 19 20 21 22 23
All Banks
Prechage
Auto
Refresh Auto Refresh (Arbitrary Cycle)
tRCtRP tRC
CLK
DQ
CKE
DQM
A0-A9
A10
WE
CAS
RAS
CS
BA
W9816G6IB
Publication Release Date: Dec. 24, 2009
- 32 - Revision A01
11.12 Self Refresh Cycle
CLK
DQ
CKE
DQM
A0-A9
A10
BA
WE
CAS
RAS
CS
tCKS
tSB tCKS
All Banks
Precharge
Self Refresh
Entry
Arbitrary Cycle
tRP
Self Refresh Cycle
tXSR
No Operation / Command Inhibit
Self Refresh
Exit
W9816G6IB
Publication Release Date: Dec. 24, 2009
- 33 - Revision A01
11.13 Burst Read and Single Write (Burst Length = 4, CAS Latency = 3)
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
CS
RAS
CAS
WE
BA
A10
A0-A9
DQM
CKE
DQ
tRCD
RBa
RBa CBv CBw CBx CBy CBz
av0 av1 av2 av3 aw0 ax0 ay0 az0 az1 az2 az3
QQ Q Q D DDQQQQ
tAC tAC
Read Read
Single Write
Active
Bank #0
Bank #1
W9816G6IB
Publication Release Date: Dec. 24, 2009
- 34 - Revision A01
11.14 Power Down Mode
012345678910 11 12 13 14 15 16 17 18 19 20 21 22 23
RAa CAa RAa CAx
RAa RAa
ax0 ax1 ax2 ax3
tSB
tCKS tCKS tCKS
tSB
tCKS
Active Standby
Power Down mode
Precharge Standby
Power Down mode
Active NOP Precharge NOP Active
Note: The PowerDown Mode is entered by asserting CKE "low".
All Input/Output buffers (except CKE buffers) are turned off in the Power Down mode.
When CKE goes high, command input must be No operation at next CLK rising edge.
Violating refresh requirements during power-down may result in a loss of data.
CLK
DQ
CKE
DQM
A0-A9
A10
BA
WE
CAS
RAS
CS
Read
W9816G6IB
Publication Release Date: Dec. 24, 2009
- 35 - Revision A01
11.15 Auto-precharge Timing (Read Cycle)
Read AP
0 1110987654321
Q0
Q0
Read AP Act
Q1
Read AP Act
Q1 Q2
AP ActRead
Act
Q0
Q3
(1) CAS Latency=2
Read
Act
AP
When the Auto precharge command is asserted, the period from Bank Activate command to
the start of internal precgarging must be at least t
RAS
(min).
represents the Read with Auto precharge command.
represents the start of internal precharging.
represents the Bank Activate command.
Note:
t
RP
t
RP
t
RP
( a ) burst length = 1
Command
( b ) burst length = 2
Command
( c ) burst length = 4
Command
( d ) burst length = 8
Command
DQ
DQ
DQ
DQ
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
t
RP
Q0
Read AP Act
Q0
Read AP Act
Q1
Q0
Read AP Act
Q1 Q2 Q3
Read AP Act
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
(2) CAS Latency=3
t
RP
t
RP
t
RP
t
RP
( a ) burst length = 1
Command
( b ) burst length = 2
Command
( c ) burst length = 4
Command
( d ) burst length = 8
Command
DQ
DQ
DQ
DQ
W9816G6IB
Publication Release Date: Dec. 24, 2009
- 36 - Revision A01
11.16 Auto-precharge Timing (Write Cycle)
Act
01 32
(1) CAS Latency = 2
(a) burst length = 1
DQ
45 76891110
Write
D0
ActAP
Command
(b) burst length = 2
DQ
Write
D0
ActAP
Command
tRP
tRP
D1
(c) burst length = 4
DQ
Write
D0
ActAP
Command
tRP
D1
(d) burst length = 8
DQ
Write
D0
ActAP
Command
tRP
D1
D2 D3
D2 D3 D4 D5 D6 D7
(2) CAS Latency = 3
(a) burst length = 1
DQ
Write
D0
ActAP
Command
(b) burst length = 2
DQ
Write
D0
ActAP
Command
tRP
tRP
D1
(c) burst length = 4
DQ
Write
D0
ActAP
Command
tRP
D1
(d) burst length = 8
DQ
Write
D0
AP
Command
tRP
D1
D2 D3
D2 D3 D4 D5 D6 D7
tWR
tWR
tWR
tWR
tWR
tWR
tWR
tWR
12
Act
represents the Write with Auto precharge command.
represents the start of internal precharing.
represents the Bank Active command.
Write
AP
Act
Act
When the /auto precharge command is asserted,the period from Bank Activate
command to the start of intermal precgarging must be at least tRAS (min).
Note )
CLK
W9816G6IB
Publication Release Date: Dec. 24, 2009
- 37 - Revision A01
11.17 Timing Chart of Read to Write Cycle
Note: The Output data must be masked by DQM to avoid I/O conflict
1110987654321
0
(1) CAS Latency=2
In the case of Burst Length = 4
Read
Read
Write
Write
DQ
DQ
( b ) Command
DQM
DQM
D0 D1 D2 D3
D0 D1 D2 D3
( a ) Command
(2) CAS Latency=3
Read Write
Read Write
D0 D1 D2 D3
( a ) Command
DQ
DQ
DQM
( b ) Command
DQM
D0 D1 D2 D3
11.18 Timing Chart of Write to Read Cycle
ReadWrite
01110987654321
Q0
Read
Q1 Q2 Q3
Read
Read
Write
Write
Q0 Q1 Q2 Q3
Write
Q0 Q1 Q2 Q3
D0 D1
DQ
DQ
( a ) Command
DQ
DQ
DQM
( b ) Command
DQM
( a ) Command
( b ) Command
DQM
DQM
In the case of Burst Length=4
(1) CAS Latency=2
(2) CAS Latency=3
D0
D0 D1
Q0 Q1 Q2 Q3D0
W9816G6IB
Publication Release Date: Dec. 24, 2009
- 38 - Revision A01
11.19 Timing Chart of Burst Stop Cycle (Burst Stop Command)
Read BST
0 1110987654321
DQ
Q0 Q1 Q2 Q3
BST
( a ) CAS latency =2
Command
( b )CAS latency = 3
(1) Read cycle
Q4
(2) Write cycle
Command
Read
Command
Q0 Q1 Q2 Q3 Q4
Q0 Q1 Q2 Q3 Q4
DQ
DQ
Write BST
Note: represents the Burst stop command
BST
11.20 Timing Chart of Burst Stop Cycle (Precharge Command)
01 111098765432
(1) Read cycle
(a) CA S latency = 2
C om m and
Q0 Q1 Q2 Q3 Q4
PRCGRead
(b) CA S latency = 3
C om m and
Q0 Q1 Q2 Q3 Q4
PRCGRead
DQ
DQ
(2) Write cycle
Command
Q0 Q1 Q2 Q3 Q4
PRCG
Write
DQ
DQM
tW R
W9816G6IB
Publication Release Date: Dec. 24, 2009
- 39 - Revision A01
11.21 CKE/DQM Input Timing (Write Cycle)
7
6
5432
1
CKE MASK
( 1 )
D1 D6D5D3D2
CLK cycle No.
External
Internal
CKE
DQM
DQ
7
6
5432
1
( 2 )
D1 D6
D5
D3D2
CLK cycle No.
External
Internal
CKE
DQM
DQ
76
5432
1
( 3 )
D1 D6D5D4
D3D2
CLK cycle No.
External
CKE
DQM
DQ
DQM MASK
DQM MASK CKE MASK
CKE MASK
Internal
CLK
CLK
CLK
W9816G6IB
Publication Release Date: Dec. 24, 2009
- 40 - Revision A01
11.22 CKE/DQM Input Timing (Read Cycle)
7
6
5432
1
( 1 )
Q1 Q6
Q4Q3Q2
CLK cycle No.
External
Internal
CKE
DQM
DQ
Open Open
7
6
5432
1
Q1 Q6
Q3
Q2
CLK cycle No.
External
Internal
CKE
DQM
DQ
Open
( 2 )
765432
1
Q1 Q6
Q3
Q2
CLK cycle No.
External
Internal
CKE
DQM
DQ
Q5Q4
( 3 )
Q4
CLK
CLK
CLK
W9816G6IB
Publication Release Date: Dec. 24, 2009
- 41 - Revision A01
12. PACKAGE SPECIFICATION
12.1 VFBGA 60 Ball (6.4X10.10 mm, Ball pitch:0.65mm, Ø=0.4mm)
W9816G6IB
Publication Release Date: Dec. 24, 2009
- 42 - Revision A01
13. REVISION HISTORY
VERSION DATE PAGE DESCRIPTION
A01 Dec. 24, 2009 All Initial formal data sheet
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components
in systems or equipment intended for surgical implantation, atomic energy control
instruments, airplane or spaceship instruments, transportation instruments, traffic signal
instruments, combustion control instruments, or for other applications intended to support or
sustain life. Further more, Winbond products are not intended for applications wherein failure
of Winbond products could result or lead to a situation wherein personal injury, death or
severe property or environmental damage could occur.
Winbond customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Winbond for any damages resulting from such improper
use or sales.
