NEC NEC Electronics Inc. yuPD71051 Serial Control Unit Description The #PD71051 serial control unit is a CMOS USART designed to provide serial data communications in microcomputer systems. The CPU uses it as a peri- pheral I/O device and programs it to communicate in synchronous or asynchronous serial data transmission protocols, including IBM bisync. The USART receives serial data streams and converts them into parallel data characters for the CPU. While receiving serial data, the USART can also accept parallel data from the CPU, convert it to serial, and transmit the data. The USART signals the CPU when it has received or transmitted a character and requires service. The CPU may read complete USART status data at any time. Features O Synchronous operation One or two SYNC characters Internal/external synchronization Automatic SYNC character insertion CO Asynchronous operation Clock rate: (baud rate) x1, x16, or x64 Send stop bits: 1, 1.5, or 2 bits Break transmission Automatic break detection Valid start bit detection CO Baud rate: DC - 240 kbit/s at x1 clock O Full duplex, double-buffered transmitter/receiver O Error detection: parity, overrun, and framing OX Five- to eight-bit characters 1 Low-power standby mode O Compatible with standard microcomputers O Functionally equivalent to (except standby mode) and can replace the wPD8251AF C1 CMOS technology O Single +5 V + 10% power supply C1 Industrial temperature range 40 to +85C CO 28-pin plastic DIP or PLCC or 44-pin plastic QFP 0 8 MHz and 10 MHz 50011 (NECEL-000138) Ordering Information Part Number Clock [MHz] Package uPD71051C-8 8 28-pin plastic DIP C-10 10 GB-8 8 44-pin plastic QFP GB-10 10 L-8 8 28-pin PLCC L-10 10 Pin Configurations 28-Pin Plastic DIP D1 bp, Ds] 2 F Do RxDATA [] 3 P] Yop GND] 4 ] AxClk D5 7] OTR BOs & 2 AtTs o7 & 22 dsr do] 3 a 210] RESET TxCLk Cr] CLK WR [] TxDATA cs [) TxEMP c/o [] CTS Ao [] SYNC/BRK RxRDY ] TxROY 83-0D0781A 5-|uPD71051 NEC . Pin Configurations (cont) 44-Pin Plastic QFP en 14) NC TxEMP SYNC/BRK TXRDY NC RxRDY uPD71051 esa e2aa > NG RxCLK cD cs NG RAxDATA GND Nc NC NC WR TxCLK D7 nc Ds Ds NC NC 83-001574A, 28-Pin Plastic Leaded Chip Carrier (PLCC) TxDATA RxClLK OTR ATS DSR RESET CLK Haag 2 VoD 26 18 Do 27 7 D4 28 16 D2 O11 wPD71051 D3 Rx DATA GND 1 TxEMP [| CTs 1] SYNC/BRK C] TxRDY T] AxRDY 1 AD 1 c/D 83-004212A 5-2 Pin Identification Symbol Function TxDATA Transmit data output CLK Clock input RESET Reset input DSR Data set ready input RTS Request to send output DTR Data terminal ready output RxCLK Receiver clock input Vop +5 V power supply D7-Do Data bus IG Internally connected (Do not connect any signal to an IC pin) RxDATA Receive data input GND Ground TxCLK Transmitter clock input WR Write strobe input cs Chip select input c/D Control or data input RD Read strobe input RxRDY Receiver ready output TxRDY Transmitter ready output SYNC/BRK Synchronization/Break input/output CTs Clear to send input TxEMP Transmitter empty output NC Not connected Pin Functions D7-Dp [Data Bus] D7-Dg are an 8-bit, 3-state, bidirectional data bus. The bus transfers data by connecting to the CPU data bus. RESET [Reset] A high level to the RESET input resets the uPD71051 and puts it in an idle state. It performs no operations in the idle state. The wPD71051 enters standby mode when this signal falls from a high level to a low level. Standby mode is released when the CPU writes a mode byte to the uPD71051. The reset pulse width must be at least 6 icyx cycles and the clock must be enabled.NEC vPD71051 CLK [Clock] This clock input produces internal timing for the uPD71051. The clock frequency should be at least 30 times the transmitter or receiver clock input frequency (TxCLK, RxCLK) in sync or async mode with the X1 clock. This assures stable operation. The clock frequency must be more than 4.5 times the TxCLK or RxCLK in async mode using x16 or x64 clock mode. CS [Chip Select] The CS input selects the uPD71051. The wPD71051 is selected by setting CS = 0. When CS = 1, the wPD71051 is not selected, the data bus (D7-Dg) is in the high impedance state, and the RD and WR signals are ignored. RD [Read Strobe] The RD input is low when reading data or status information from the 7.PD71051. WR [Write Strobe] The WR input is low when writing data or acontrol byte to the wPD71051. c/D [Control or Data] TheC/D input determines the data type when accessing the uPD71051. When C/D = 1, the data is a control byte (table 1) or status. When C/D = 0, the data is character data. This pin is normally connected to the least significant bit (Ag) of the CPU address bus. Control Signais and Operations Table 1. cS RO WR Cc uPOT1051 CPU Operation Receive data buffer a 0 1 0 Read receive data Data bus Status register 0 0 1 1 Read status Data bus Data bus 0 1 0 0 << Write transmit data Transmit data butter Oata bus 0 1 0 1 LY Write control byte Control byte register Data bus a 1 | x High impedance None 1 x x x Data bus None High impedance DSR [Data Set Ready] DSR is a general-purpose input pin that can be used for modem control. The status of this pin can be determined by reading bit 7 of the status byte. DTR [Data Terminal Ready] DTR is a general-purpose output pin that can be used for modem control. The state of this pin can be controlled by writing bit 1 of the command byte. If bit 7 = 0, then DTR = 1. If bit 1 = 1, then DTR = 0. RTS (Request to Send] RTS isa general-purpose output pin that can be used for modem control. The status of this pin can be controlled by writing bit 5 of the command byte. If bit5 = 1, then RTS = 0. If bit 5= 0, then RTS = 1. CTS [Clear to Send] The CTS input controls data transmission. The puPD71051 is able to transmit serial data when CTS =0 and the command byte sets TxEN = 1. if CTS is set equal to 1 during transmission, the sending operation stops after sending all currently written data and the TxDATA pin goes high. TxDATA [Transmit Data] The uwPD71051 sends serial data over the TxDATA output. TxRDY [Transmitter Ready] The TxRDY output tells the CPU that the transmit data buffer in the wPD71051 is empty; that is, that new transmit data can be written. This signal is masked by the TxEN bit of the command byte and by the CTS input. It can be used as an interrupt signal to request data from the CPU. The status of TxRDY can be determined by reading bit 0 of the status byte. This allows the PD71051 to be polled. Note that TxRDY of the status byte is not masked by CTS or TxEN. TxRDY is cleared to 0 by the falling edge of WR when the CPU writes transmit data to the wPD71051. Data in the transmit data buffer that has not been sent is destroyed if transmit data is written while TXRDY = 0. SE-3yvPD71051 NEC TxEMP [Transmitter Empty] The yPD71051 reduces CPU overhead by using a double buffer; the transmit data buffer (second buffer) and the transmit buffer (first buffer) in the transmitter. When the CPU writes transmit data to the transmit data buffer (second buffer), the #PD71051 sends data by transferring the contents of the second buffer to the first buffer, after transmitting the contents of the first buffer. This empties the second buffer and TxRDY is set to 1. The TxEMP output becomes 1 when the contents of the first buffer are sent and the second buffer is empty. Thus, TXEMP = 1 shows that both buffers are empty. In half-duplex operation, you can determine when to change from sending to receiving by testing TxEMP = 1. When TxEMP = 1 occurs in async mode, the TxDATA pin goes high. When the CPU writes transmit data, TxEMP is set to 0 and data transmission resumes. When TxEMP = 1 occurs in syne mode, the uPD71051 loads SYNC characters from the SYNC character register and sends them through the TxDATA pin. TxEMP is set to 0 and resumes sending data after sending {one or two) SYNC characters and the CPU writes new transmit data to the wPD71051. TxCLK [Transmitter Clock] The TxCLK input is the reference clock input that determines the transmission rate. Data is transmitted at the same rate as TxCLK in sync mode. In async mode, set TxCLK to 1, 16, or 64 times the transmission rate. Serial data from TxDATA is sent at the falling edge of TxCLK. For example, arate of 19200 baud in sync mode means that TXCLK is 19.2 kHz. A rate of 2400 baud in async mode can represent a TxCLK of: x1 clock = 2.4 kHz x16 clock = 38.4 kHz x64 clock = 153.6 kHz RxDATA [Receive Data] The uPD71051 receives serial data through the RxDATA input. RxRDY [Receiver Ready] The RxRDY output becomes 1 when the wPD71051 receives one character of data and transfers that data to the receive data buffer; that is, when the receive data can be read. This signal can be used as an interrupt signal for a data read request to the CPU. You can C=4 determine the status of RXRDY by reading bit 1 of the status byte and use the uPD71051 in a polling applica- tion. RxRDY becomes 0 when the CPU reads the receive data. Unless the CPU reads the receive data (after RxRDY = 1is set) before the next single character is received and transferred to the receive buffer, an overrun error occurs, and the OVE status bit is set. The unread data in the receive data buffer is overwritten by newly transferred data and lost. RxRDY is set to Oin the receive disable state. This state is set by changing the RxEN bit to 0 through the command byte. After RxEN is set to 1 (making receiving possible), RXxRDY becomes 1 whenever new characters are received and transferred to the receive data buffer. SYNC/BRK [Synchronization/Break] The SYNC pin detects synchronization characters in sync mode. The SYNC mode byte selects internal or external SYNC detection. Tne SYNC pin becomes an output when internal synchronization is set, and an input when external synchronization is set. The SYNC output goes high when the wPD71051 detects a SYNC character in interna! synchronization. When two SYNC characters are used, SYNC goes high when the last bit of the two consecutive SYNC characters is detected. You can read the status of the SYNC signal in bit 6 of the status byte. Both the SYNC pin and status are set to 0 by a read status operation. In external synchronization, in order for the external circuit to detect synchronization, a high level of atleast one period of RxCLK must be input to the SYNC pin. When the pPD71051 detects the high level, it begins to receive data, starting at the rising edge of the next RxCLK. The high level input may be removed when synchronization is released. The BRK output is used only in async mode and shows the detection of a break state. BRK goes high when a low level signal is input to the RxDATA pin for two character bit lengths (including the start, stop, and parity bits). As with SYNC, you can read the status of BRK in bit 6 of the status byte. BRK is not cleared by the read operation. The set BRK signal is cleared when the RxDATA pin returns to high level, or when the zPD71051 is reset by hardware or software. The SYNC/BRK pin goes low on reset, regardless of previous mode. Figure 1 shows the break state and BRK signal.NEC uPD71051 RxCLK [Receiver Clock] Block Diagram RxCLK is a reference clock input that controls the ~ receive data rate. In sync mode, the receiving rate is the Status LH] same as RxCLK. In async mode, RxCLK can be 1, 16, or Register yo Nc Syne 64 times the receive rate. Serial data from RxDATA is Receive al 8 Register input by the rising edge of RxCLK. D; = Da Sutter el it Tranemit Lisl Ly Jo TxDATA Vop [Power] Suter Sep] teanarn Co as 1 Control 8 3 Buffer] peo TxCLK Regist vy 5 V power supply. egister : __omebaTa - [with f RxRDY GND [Ground] Receive [ere SYNC/BRK pao Rx Ground. wot o*} controt 4 7 Logic |_| CTs Figure 1. Break Status and Break Signal Wa o+ 4 ak doses, Pooees 7 V v p+ OTR cs 8-bit Character, No Parity ~ W Stop Bit [2] 83-000782A, Stop Bit Start Bit |: Character Bits : Character Bits 4 _ _ RxDATA LLDo D7 | | Do | D7 rc }First Data le Second Data +1 6-bit Character with Parity [oe Character Bis Block Block [1] Parity Bit Parity Bit Stop Bit (2) Stop Bit E Bit Bit Character Character Bits RRDATA 25 }e_First =e Second Data ul Block Block [1] | BRK Start Bit BRK Note: [1] When RxDATA goes high in the stop bit position of the second data block, the BRK signal level may [but does not always] become high for a maximum of one bit time. [2] Only one bit of the stop bit is checked. 83-000783A vPD71051 Functions The uPD71051 is a CMOS serial control (USART) unit that provides serial communications in microcomputer systems. The CPU handles the uPD71051 as an ordinary 1/0 device. The uPD71051 can operate in synchronous or asynchro- nous systems. In sync mode, the character bit length, number of sync characters, and sync detection mode must be designated. In async mode, the communication rate, character bit length, stop bit length, etc., must be designated. The parity bit may be designated in either mode. The uPD71051 converts parallel data received from the CPU into serial transmitted data (from the TxDATA pin), and converts serial input data (from the RxDATA pin) into parallel data so that the CPU can read it (receiving operation). The CPU can read the current status of the wPD71051 and can process data after checking the status, after checking for transfer errors, and u.PD71051 data buffer status. The uPD71051 can be reset under hardware or software control to a standby mode that consumes less power and removes the device from system operation. In this mode, the uPD71051s previous operating mode is released and it waits for a mode byte to set the mode. The PD71051 leaves standby mode and shifts to a designated operating mode when the CPU writes a mode byte to it. Status Register The status register allows the CPU to read the status of the uPD71051 except in standby mode. This register indicates status and allows the CPU to manage data reading, writing, and error handling during operations. Receive Data Buffer When the receiver has converted the serial data input from the RxDATA pin into parallel data, the converted data is stored in the receive data buffer. The CPU can then read it. Data for one character entering the receive buffer is transferred to the receive data buffer and RxRDY becomes 1, requesting that the CPU read the data. 5e~-5yPD71051 NEC Transmit Data Buffer The transmit data buffer holds the parallel data from the CPU that the transmitter will convert to serial data and output from the TxDATA pin. When the CPU writes transmit data to the uPD71051, the wPD71051 stores data in the transmit data buffer. The transmit data buffer transfers the data to the transmitter, which sends the data from the TxDATA pin. Control Register This register stores the mode and the command bytes. Control Logic The control logic sends control signals to the internal blocks and controls the operation of the wPD71051 based on internal and external signals. Synchronous Character Register This register stores one or two SYNC characters used in syne mode. During transmission, the SYNC characters stored in this register are output from the TxDATA pin when the CPU does not send a new character and TxEMP status is set. During receiving, synchronization is established when the characters received and the SYNC characters stored in this register are the same. Transmitter The contents of the transmit data buffer are transferred to the transmitter, converted from paratlel to serial, and output from the TxDATA pin. The transmitter adds start, stop, and parity bits. Receiver The receiver converts serial data input from the RxDATA pin into parallel data and transfers the paraliel data to the receive data buffer, allowing the CPU to read it. The receiver detects SYNC characters and checks parity bits in sync mode. It detects the start and stop bits, and checks parity in the async mode. In async mode, receiving does not begin (the start bitis not detected) until one effective stop bit (high level) is input to the RxDATA pin and Receive Enable (RxEN = 1) is set after setting up the mode. Modem Control This block controls the CTS, RTS, DSR, and OTR modem interface pins. The RTS, DSR, and DTR pins can also be used as general-purpose I/O pins. 5C-6 Absolute Maximum Ratings Ta = +25C Rower supply voltage, Vop 0.5 to +7.0V Input voltage, V| 0.5 to Vpp +: 0.3 V Output voltage, Vo 0.5 to Vpp + 0.3 V Operating temperature, Topt 40C to +85C Storage temperature, Tstg 65C to +150C Power dissipation, PDyax 1.0W Comment: Exposing the device to stresses above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational sections of this specification. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Capacitance Ta = +25C, Vpp = OV Limits Test Parameter Symbol Min Max Unit Conditions Input capacitance C 10 oF ononanre d pins 1/0 capacitance Cio 20 pF returned to0V DC Characteristics Ta = 40C to +85C, Vop = +5 V + 10% Limits Parameter Symbol Min Typ Max Unit Test Conditions Input voltage = Vin 2.2 Vppt0.3 V high Input voltage = Vi 05 0.8 V low Output voltage Voy 0.7 x Vop Vo Igy = 400 pA high Output voltage Vor 0.4 Vo lop =2.5mA low Input leakage = I1j4 10 uA Vi =Vop current high Inputleakage = Iyt 10 wA VW=0V current low Output leakage ILoH 10 vA Vo= po current high Output leakage Ito -10 pA Vo=0V current low Supply current wPD71051 \pp1 10 mA Normal mode Ipp2 50 100 wA Stand-by mode wPD71051-10 Ipp1 10. mA Normal mode (poz 2 50 uA Stand-by modeNEC vPD71051 AC Characteristics Ta = 40C to +85C, Vpn = 5 V 10% 8 MHz Limits 10 MHz Limits Parameter Symbol Min Max Min Max Unit Test Conditions Read Cycle Address setup to RD { tsar 0 0 ns s, C/D Address hold from RD t tyra 0 0 ns s, c/D RD low level width trac 150 95 ns Data delay from RD | toro 120 85 ns C = 150 pF Data float from RD t trap 10 80 10 65 ns Port (DSR, CTS) set-up to RD | tspp 20 20 tcvK Write Cycle Address setup to WR | tsaw 0 0 ns cS, c/D Address hold from WR thwa 0 0 ns ts, c/D WR low level width twwi 150 95 ns Data setup to WR t tspw 80 80 ns Data hold from WR t tuwp 0 0 toyk Port (DTR, RTS), delay from WRt towp 8 8 tovK Write recovery time try 6 6 toyk Mode initialize 8 8 tcvK Async mode 16 16 tovk Sync mode Serial Transfer Timing CLK cycle time toyK 125 DC 100 DC ns CLK high level width tkkH 50 35 ns CLK low level width tKKL 35 25 ns CLK rise time tke 5 20 5 20 ns CLK fall time ter 5 20 5 20 ns TXDATA delay trom TxCLK tpTKTD 0.5 05 us Transmitter input clock pulse tTKTKL 12 12 toyk 1xBR (Note 1) width low levet 1 1 tevK 46x. 64xBR Transmitter input clock pulse tTKTKH 15 15 tcyk 1xBR width high level 3 3 tovK 16x, 64xBR Transmitter input clock ftk DC 240 oC 300 kHZ 1xBR frequency (Note 2) DC 1536 DC 1920 kHz 16xBR dC 1536 oc 1920 kHz 64xBR Receiver input clock pulse tRKRKL 12 12 toyk 1xBR width tow level 1 1 tovk 16x, 64xBR Receiver input clock pulse tRKRKH 15 15 tcyK 1xBR width high level 3 3 tov 16x, 64xBR s-TuPD71051 NEC AC Characteristics (cont) 8 Miz Limits 10 MHz Limits Parameter Symbol Min Max Min Max Unit Test Conditions Serial Transfer Timing [cont) Receiver input clock frequency fark pc 240 DC 300 kHz 1xBR (Note 2) oc 1536 DC 1920 kHz 16xBR bc 1536 dC 1920 kHz 64xBR RxDATA set-up to Sampling pulse {sapsp 1 1 BS RxDATA hold from sampling tHSPRD 1 1 us pulse TxEMP delay time (TxDATA) tpTxer 20 20 teyK TxRDY delay time (TxRDY f) torxr 8 8 tok TxRDY delay time (TxRDY!) towTxr 200 100 ns RxADY delay time (RxRDYT} torxr 26 26 tovK RxADY delay time (RxRDY }} tpRRXR 200 100 ns SYNC output delay time torKSY 26 26 tok (for internal sync) SYNC input set-up time tssyRK 18 18 tcyK (for external sync) RESET pulse width 6 6 tcykK Notes: (1) BR = Baud rate (2) 1xBR: frx orfaK = 1/30 tcLK, 16x, 64xBR: few or fa = 1/4.5toLK (3) System CLK is needed during reset operation (4) Status update can have a maximum delay of 28 toy from the event effecting the status. Timing Waveforms Write Data Cycle Read Data Cycle os % xc as =" tuwa MT tne | nis D7 - Do x KT | [+towe ors | XC |. ___towrxar TxADY 89-01913A 5t-8 \ ' c/B KK [tsar | HRA & TY boi | m voy D7 - Do DSA, CTS x toRRxXR RxRDY / \ 83-000767ANEC vPD71051 Timing Waveforms (cont) Transmitter Clock and TxDATA . trevKL f rere TxCLK [1x BR] Lome retoraro-y TXDATA D4 1 46TXTIR STKTML | frKTKH Cycle le tor To- TxDATA x | 83-000769B Receiver Clock and RxDATA Timing be tAKRIL tmerur - RxCLK {1 x BR] 3tev txky StevK Internal Sampling Pulse tsapsp t ia t RxDATA Start Bit Ist Data Bit x me TAKRKL RKAKH k aRxClk i SRxCLk I 16 RxCLlK Cycle Cycle KH 3terk Internal Sampling / \ Pulse tsapspP. tuspRo- RxDATA Start Bit 1st Data Bit J xX 83-000768B AC Test Input Write Recovery Time 24aVv WR 0.45 V O8V tey Main Clock 83-000766A, kn tke CLK 83-000770A 52 ~9-pPD71051 NEC Connecting the u.PD71051 to the System The CPU uses the uPD71051 as an I/O device by allocating two I/O addresses, set by the value of c/D. One I/O address is allocated when the level of C/D is low and becomes a port to the transmit and receive data register. The other I/O address is allocated when C/D is high and becomes a port to the mode, command, and status registers. Generally, the least significant bit (Ap) of the CPU address bus is connected to C/D to get a continuous I/O address. This is shown in figure 2. Pins TXRDY and RxRDY are connected to the CPU or, when interrupts are used, to the interrupt pin of the interrupt controller. Operating the PD71051 Start with a hardware reset (set the RESET pin high) after powering on the wPD71051. This puts the uPD71051 into standby mode and it waits for a mode byte. In async mode, the uPD71051 is ready for a command byte after the mode byte; the mode byte sets the communication protocol to the async mode. In sync mode, the #PD71051 waits for one or two SYNG characters to be sent after the mode byte; set C/D = 1. Acommand byte may be sent after the SYNC characters are written. Figure 3 shows this operation sequence. In both modes, it is possible to write transmit data, read receive data, read status, and write more command bytes after the first command byte is written. The uPD71051 performs a reset, enters standby mode, and returns to a state where it waits for a mode byte when the command byte performs a software reset. Figure 2. System Connection #PD71051 Decoder D7-Do 83-0007844 Figure 3. uPD71051 Operating Procedure 5 ~ 10 Hardware Reset |}_______, Write Mode Byte Double Sync Character, Write Sync Character 1 Sync Character 1 i Write Sync Character 2 | Write Command Byte __} tatus: Data: Command: [Note 1] Write Read Status Command Byte Write/Read Data Software Reset? Note: [1] This is done with C/D = 0. Others are operated with c/D=1. 83-000785BNEC yvPD71051 Mode Register When the #PD71051 is in standby mode, writing a mode byte to it will release standby mode. Figure 4 shows the mode byte format for designating async mode. Figure 5 shows the mode byte format for designating sync mode. Bits 0 and 1 must be 00 to designate sync mode. Async mode is designated by all! other combinations of bits 0 and 1. The P1, PO and L1, LO bits are common to both modes. Bits P1 and PO (parity) control the generation and checking (sending and receiving) functions. These parity bit functions do not operate when PO = 0. When P1, PO = 01, the 4PD71051 generates and checks odd parity. When P1, PO= 11, it generates and checks even parity. Bits L1 and LO set the number of bits per character (n). Additional bits such as parity bits are not included in this number. Given n bits, the 4PD71051 receives the lower n bits of the 8-bit data written by the CPU. The upper bits (8 -n) of data that the CPU reads from the uPD71051 are set to zero. The ST1, STO and B1, BO bits are used in async mode. The ST1 and STO bits determine the number of stop bits added by the PD71051 during transmission. The B1 and BO bits determine the relationship between the baud rates for sending and receiving, and the clocks TxCLK and RxCLK. B1 and BO select a multi- plication rate of 1, 16, or 64 for the frequency of the sending and receiving clock relative to the baud rate. Multiplication by 1 is not normally used in async mode. Note that the data and clock must be synchronized on the sending and receiving sides when multiplication by 1 is used. The SSC and EXSYNC bits are used in sync mode. The SSC bit determines the number of SYNC characters. SSG = 1 designates one SYNC character. SSC = 0 designates two SYNC characters. The number of SYNC characters determined by the SSC bit are written to the uPD71051 immediately after writing the mode byte. The EXSYNC bit determines whether sync detection during receiving operations is internal or external. EXSYNC = 1 selects external sync detection and EXSYNC = 0 selects internal sync detection. Figure 4. Mode Byte for Setting Asynchronous Mode c/D=1 . 7 6 5S 4 3.2 ~=4 Qo [sts]sro] ps] po | er[ co]: | Bo} B1 | Bo Baud Rate of 1 x1 Clock 1 a x 16 Clock 1 1 x 64 Clock Li] Lo Character Length oO] 0 S-bit Qo 1 6-bit 1 0 7-bit q 1 8-bit P1] PO | Parity Generate/Check x o No Parity o|1t Odd Parity 1 1 Even Parity STI/STO Transmit Stop Bits Use Illegal 1-bit 1-1/2 bit 2-bit wlolalo =|[=]oalo x: don'tcare 83-000786A Figure 5. Mode byte for Setting Synchronous Mode c/D=1 7 6 5 4 3 2 1 ~0 {ssclexsync] P1] Po | M1 | Lo] 0 ] 0 ] TE Character Length 5-bit 6-bit 7-bit 8-bit alajolo sal[op=alo Pi j PO [Parity Generate/Check x Q No Parity of1 Odd Parity 1 1 Even Parity EXSYNC Sync Detect 0 Internally [Output) 1 Externally [Input] ssc Sync Characters 0 2 (BSC) 1 1 x: don't care 83-D00787A @-11#PD71051 NEC Command Register Commands are issued to the uPD71051 by the CPU by command bytes that control the sending and receiving operations of the uPD71051. A command byte is sent after the mode byte (in sync mode, a command byte may only be sent after writing SYNC characters) and the CPU must set C/D = 1. Figure 6 shows the command byte format. Bit EH is set to 1 when entering hunt phase to synchronize in sync mode. Bit RxEN should also be set to 1 at that time. Data reception begins when SYNC characters are detected and synchronization is achieved, thus releasing hunt phase. When bit SRES is set to 1, a software reset is executed, and the uPD71051 goes into standby mode and waits for a mode byte. Bit RTS controls the RTS output pin. RTS is low when the RTS bit = 1, and goes high when RTS = 0. Setting bit ECL to 1 clears the error flags (PE, OVE, and FE) in the status register. Set ECL to 1 when entering the hunt phase or enabling the receiver. Bit SBRK sends a break. When SBRK = 1, the data currently being sent is destroyed and the TXDATA pin goes low. Set SBRK = 0 to release a break. Break also works when TxEN = 0 (send disable). Bit RxEN enables and disables the receiver. RxEN = 1 enables the receiver and RxEN = 0 disables the receiver. Synchronization is lost if RxEN = 0 during sync mode. Bit DTR controls the DTR output pin. DTR goes low when the DTR bit = 1 and goes high when the DTR bit = 0. The TxEN bit enables and disables the transmitter. TxEN = 1 enables the transmitter and TxEN = 0 disables the transmitter. When TxEN = 0, sending stops and the TxDATA pin goes high (mark status) after all the currently written data is sent. Status Register The CPU can read the status of the wPD71051 at any time except when the #PD71051 is in standby mode. Status can be read after setting C/D = 1 and RD=0. Status is not updated while being read. Status updating is delayed at least 28 clock periods after an event that affects the status. Figure 7 shows the format of the status register. a -12 The TxEMP and RxRDY bits have the same meaning as the pins of the same name. The SYNC/BRK bit generally has the same meaning as the SYNC/BRK pin. In external synchronization mode, the status of this bit does not always coincide with the pin. In this case, the SYNC pin becomes an input and the status bit goes to 1 when a rising edge is detected at the input. The status bit remains at 1 until it is read, even when the input level at the SYNC pin goes low. The status bit becomes 1 when a SYNC character is input with the RxDATA input, even when the pin is at a low level. The DSR bit shows the status of the DSR input pin. The status bit is 1 when the DSR pin is low. The FE bit (framing error) becomes 1 when less than one stop bit is detected at the end of each data block during asynchronous receiving. Figure 8 shows how a framing error can happen. Figure 6. Command Byte Format cib=1 7 6 5 4 3 2 1 oO [ EH ] SARES [rrsfeci] SBRK | RxEN [oral TxEN | Ly TXEN| Transmit Enable oO Disable 1 Enable OTA | OTR Pin Control 0 OTR =1 1 OTR=0 RxEN] Receive Enable 0 Disable 1 Enable SBRK Send Break TxDATA Pin Normal Operation 1 TxDATA =0 ECL Ercor Clear 0 No Operation 1 Error Flag Clear RTS | RATS Pin Control o RTS =1 1 RTS =0 SRES Reset oO No Operation 1 feset Operation EH [1]| Enter Hunt Phase 0 No Operation 1 Enter Hunt Phase Note: [1] The EH bit is effective only in SYNC mode. 83-000788BNEC yPD71051 The OVE bit (overrun error) becomes 1 when the CPU delays reading the received data and two new data bytes have been received. In this case, the first data byte received is overwritten and lost in the receive data buffer. Figure 9 shows how an overrun can happen. The PE bit (parity error) becomes 1t when a parity error occurs in a receive state. Figure 7. Status Register Format ci =1 7 6 5 4 3 2 1 0 psp [SNC Ire fove|Pe [TxEMP| RxRDY | TxADY | I I Same as the Outpul Pin Function with the Same Name Trasmit Data TxRDY Buffer State culver sige 0 Full 1 Empty PE Parity Error Q ~ No Error 1 - Error Framing, overrun, and parity errors do not disable the uPD71051s operations. All three error flags are cleared to by a command byte that sets the ECL bit to 1. The TxRDY bit becomes 1 when the transmit data buffer is empty. The TxRDY output pin becomes 1 when the transmit data buffer is empty, the CTS pin is low, and TxEN = 1. Thatis, bit TxRDY = Transmit Data Buffer Empty, pin TxRDY = (Transmit Data Buffer Empty)e(GTS = 0)0(TxEN = 1). Figure 8. Framing Error 1 Character = 5-bit, No Parity, 1 Stop Bit 41 : [1] !n the break state: Enter the Break State RXDATA EGES x Start Stop Start FE=+1 Bit Bit Bit Set because a stop bit should be here. [2] A large frequency difference between RxCLK and TxCLK: td i FE=1 ia tL SANS / this pulse samples the stop bit. Because of OVE | Overrun Error 0 - No Error 1 - Error FE Framing Error the frequency of RxCLK is lower than that of TxCLK the start bit is sampled too late in time. Pulse [3] When data is changed during transmission; (Using less rellable transmission circuit, etc.] : _ Shan sty sin Stop Start Dan DSR input enara Bil Bit Bit Bit Bit 1 DSR -0 Bit Change change Bit Change Figure 9. Overrun Error OVE RxRDY cPU ie eeen Date fer Aiet putter? Ax Data o 4 CAME 9 ALAC LLC Chas 0 0 resacnaros{ | 1-1 1111) CY nant a Lif | | | | AA Sha AAA Chart o 4 \ ACA CAE SAGA 7 o 4 KALA ALAC LL ee char o 1 CMA TONAL _IACAT TTC Ba Char 2 0 ced =~ ALe L nar 14 ens VACA LL | | tT ee cnars Char 1 is not read by the CPU and is discarded on receipt of Char 2 SO713uPD71051 NEC Sending in Asynchronous Mode The TXDATA pin is typically in the high state (marking) when data is not being sent. When the CPU writes transmit data to the vPD71051, the 4PD71051 transfers the transmit data from the transmit data buffer to the send buffer and sends the data from the TxDATA pin after adding one start bit (low level) and a programmed stop bit. If parity is used, a parity bit is inserted between the character and the stop bit. Figure 10 shows the data format for async mode characters. Serial data is sent by the falling edge of the signal that divided TxCLK (1/1, 1/16, or 1/64). When bit SBRK is set to 1, the TxDATA pin goes low (break status), regardless of whether data is being sent. Figure 11 is a fragment of a typical program to send data in the async mode. Figure 12 shows the output from pin TXxDATA. Figure 10, Asynchronous Mode Data Format No Parity D Dy Da On Start 0 Stop Mark | Bit Data Bits With Parity D, Start Bit Dy Do-1 On Mark Stop | Parity Bit{s] Bit Data Bits n=4,5,6,7 Stop Bit = 1 bit, 1.5 bit, 2 bit 83-000789A Figure 11. Asynchronous Transmitter Example ASYNTX: CALL ASYNMOD ;Set async mode MOV AL, 000100018 Command: clear error flag, transmit enable OUT PCTRL,AL MOV BW, OFFSET TXDADR ;Transmit data area TXSTART : IN AL, PCTRL TEST1 AL, 0 ;Read status BNE TXSTART ;Wait until TxRDY = 1 MOV AL, [BW] Write transmit data OUT PDATA, AL ING BW ;Set next data address CMP AL, 00H BNE TXSTART ;End if data = 0 RET TXDADR DB NEC Transmit data 4EH, 45H, 43H, 00 DB 0 ASYNMOD: MOV AL, 0 :Writes control bytes three times OUT PCTRL, AL :with OOH to unconditionally OUT PCTRL, AL -accept the new command byte OUT PCTRL, AL MOV AL, 01000000B ;Software reset OUT PCTRL, AL MOV AL, 11111010B Write mode byte OUT PCTRL, AL Stop bit = 2 bits, even parity RET :7 bits/character, x16 clock Figure 12. TxDATA Pin Output TxDATA Mark - , 4EH 45H a We e Start Start Tle qe Stop Stop Stop Stop Parity Parity Parity Parity 83-000790B S@14NEC #PD71051 Receiving in Asynchronous Mode The RxDATA pin is normally in the high state when data is not being received, as shown in figure 13. The uPD71051 detects the falling edge of a low level signal when a low level signal enters it. The wPD71051 samples the level of the RxDATA input (only when x16 or x64 clock is selected) in a position 1/2 bit time after the falling edge of the RxDATA input to check whether this low level is a valid start bit. It is considered a valid start bit if a low level is detected at that time. If a low level is not detected, it is not regarded as a start bit and the yPD71051 continues testing fora valid start bit. When a start bit is detected, the sampling points of the data bits, parity bit (when used), and stop bit are decided by a bit counter. The sampling is performed by the rising edge of the RxCLK when an X1 clock is used. When a x16 or x64 clock is used, it is sampled at the nominal middle of RxCLK. Figure 13. Start Bit Detection RxDATA [1] Yr i Sampling Rx DATA [2] : LH to | Sampling Bit Boundary L____1__|___ Note: {1] Start bit is not recognized because R x Data is high at the sampling time. (2] Start is recognized because R x Data is low at the sampling time. 83-000791A Figure 14. Asynchronous Receiver Example Data for one character entering the receive buffer is transferred to the receive data buffer and causes RxRDY = 1, requesting that the CPU read the data. When the CPU reads the data, RxRDY becomes 0. When a valid stop bit is detected, the wPD71051 waits for the start bit of the next data. Ifa low level is detected in the stop bit, a framing error flag is set; however, the receiving operation continues as if the correct high level had been detected. A parity error flag is set if a parity error is detected. An overrun error flag is set when the CPU does not read the data in time, and the next receiving data is transferred to the receive data buffer, overwriting the unread data. The wPD71051's sending and receiving operations are not affected by these errors. If a low level is input to the RxDATA pin for more than two data blocks during a receive operation, the uPD71051 considers it a break state and the SYNCG/BRK pin status becomes 1. In async mode, the start bit is not detected until a high level of more than one bit is input to the RxDATA pin and the receiver is enabled. Figure 14is a fragment ofa typical program to receive the data sent in the previous async transmit example. ASYNRX: CALL ASYNMOD MOV __ AL, 00010100B OUT PCTRL,AL MOV __ BW, OFFSET RXDADR RXSTART : IN AL, PCTRL TEST1 AL,1 BNE RXSTART IN AL, PDATA MOV [BW], AL INC BW CMP AL, 00H BNE RXSTART RET RXDADR DB 256 DUP ;Set ASYNC mode ;Command: clear error flag, receive enable ;Data store area ;Read status ;Wait until RxRDY = 1 ;Read and store the receive data ;Set next store address End if data = 0 ;Reserve receive data area 50-15yPD71051 NEC Sending in Synchronous Mode Figure 15. Synchronous Mode Data Format Following the establishment of sync mode and the enabling of the transmitter, the TxDATA pin stays high f Character Data without Parity until the CPU writes the first character (normally, [om | om | [| mm | Pn | SYNC characters). When data is written, the TxDATA | One Char | pin sends one bit for each falling edge of TxCLK if the Character Data with Parity CTS pin is low. Unlike async mode, start and stop bits [mo | % | | Der | On q Parity | are not used. However, a parity bit may be set. Figure | one Character with Parity | 15 shows these data formats. nase? Once sending begins, the CPU must write data to the 83-000T92A uPD71051 at the same rate as that of TxCLK. lf TxEMP goes to 1 because of a delay in writing by the CPU, the uPD71051 sends SYNC characters until the CPU writes data. TXEMP goes to 0 when data is written, and the data is sent as soon as transmission of SYNC characters stops. Figure 16. Synchronous Mode Transmit Timing No. of Sync characters = 2 [BSC] Ts=0 puPD71051 Transmits Automatically TXDATA Mark | Datao | Oeta1 | dataz | Ddataa J vatas | sync | syNc [| oatas | oatas | SYNC Chri) SNC Chr2 Chrt Chr2 TxRDY [Pin] TxEMP | Data 4 LI DataO Datat Data 2 LI Data 3 L ~ LILILIS Ww lu | FLT 1 J} Command TxEN =0 LU Data5 uo Data6 LU So 83-0007938 Figure17. Issuinga Command During SYNC Character Transmission No. of Sync Characters = 1 Data By the 71051 By the 71051 By the CPU TxDaTa | Sync I Sync [Syne Character Character Character terpy | | J TxEMP j | (2} [4] WR {1) [3] a i Note: [1] Confirm the automatic trasmission ot the SYNC character by the TxEMP status. [2] Write SYNC character data. [3] Confirm the beginning of SYNC character trasmission by the CPU by reading the status. [4] Write command word. 83-000794A St-16NEC uPD71051 Automatic transmission of SYNC characters begins after the CPU sends new data. SYNC characters are not automatically sent by enabling the transmitter. Figure 16 shows these timing sequences. If a command is sent to the wPD71051 while SYNC characters are automatically being sent and TxEMP = 1, the uwPD71051 may interpret the command as a data byte and transmit it as data. |fa command must be sent under these conditions, the CPU should senda SYNC character to the wPD71051 and send the command while the SYNC character is being transmitted. This is shown in figure 17. Figure 18 is a fragment of a typical program for sending in sync mode. Figure 18. Synchronous Transmitter Example SYNTX: CALL SYNMOD ;Set sync mode MOV AL, 00010001B ;Commang; clear error OUT PCTRL, AL ;flags, transmit enable MOV BW, OFFSET TXDADR ;Start location of data area TxDADR MOV CL, LDLEN ;Set number of bytes (LDLEN) to be transmitted MOV CH, 00H TXLEN : IN AL, PCTRL ;Transmit the length byte TEST1 AL, 0 BZ TXLEN MOV AL, LDLEN OUT PDATA, AL TXDATA : IN AL, PCTRL TEST1 AL, 0 BZ TXDATA ;Transmit the number of MOV AL, (BW) i:bytes specified by LDLEN OUT PDATA, AL INC BW DBNZ TXDATA MOV AL, 00010000B ;Command; clear error OUT PCTRL, AL flags, transmit disable RET SYNC1 DB ? ;SYNC character 1 SYNC2 DB ? ;SYNC character 2 LDLEN DB ? ;transmit data count TXDADR DB 255 DUP (?) ;transmit data SYNMOD: MOV AL, 00H OUT PCTRL, AL ;Write control bytes OUT PCTRL, AL ;three times with OOH to OUT PCTRL, AL unconditionally accept the new ;command byte MOV AL, 01000000B Software reset OUT PCTRL, AL MOV AL, 00111100B ;Write mode byte: 2 SYNC OUT PCTRL, AL ;characters, internal sync detect, seven parity, 8 bits/character MOV AL, SYNC1 OUT PCTRL, AL ;Write SYNC characters MOV AL, SYNC2 OUT PCTRL, AL RET Se~i7yPD71051 NEC Receiving in Synchronous Mode In order to receive in sync mode, synchronization must be established with the sending side. The first command after setting sync mode and writing the SYNC character must be EH = 1, ECL = 1, and RxEN = 1. When hunt phase is entered alt the bits in the receive buffer are set to 1. In internal synchronization, data on the RxDATA pin is input to the receive buffer for each rising edge of RxCLK and is compared with the SYNC character at the same time. Figure 19 shows this interna! sync detection. When the receive buffer and the SYNC character coincide, and parity is not used, the yPD71051 ends hunt phase and SYNC is set to 1 in the center of the last SYNC bit. When parity is used, SYNC becomes 1 in the center of the parity bit. Receiving starts with the bit which follows the bit when SYNC is set to 1. In external sync detection, synchronization is achieved by setting the SYNC pin high from an external circuit for at least one period of RxCLK. Hunt phase ends, and data reception can start. At this time, the SYNC status Figure 19. Internal Sync Detection Example bit becomes +, and goes to 0 when the status is read. The SYNC status bit is set to 1 when the SYNC input has a rising edge followed by a high level of more than one period of RxCLK, even after synchronization is achieved. The uPD71051 can regain lost synchronization anytime by issuing an enter hunt phase command. After synchronization, the SYNC character is compared with each character regardless of whether internal or external synchronization is used. When the characters coincide, SYNC becomes 1, indicating that a SYNC character has been received. SYNC (SYNC status bit only in external detection) becomes 0 when the status is read. Overrun and parity errors are checked the same way as in async mode, affecting only the status flag. Parity checking is not performed in the hunt phase. Figure 20 is a fragment of a typical program that receives the data sent by the previous sync transmit program example. Note that the frequencies of TxCLK on the transmitter and RxCLK on the receiver must be the same. Sync Character 1 5-bit Character, No Parity, 2 Sync Characters Sync Character 1 -- 01100B, Sync Character 2 110018 Sync Character 2 Note: Since the character is 5 bits, part 1 of the sync character register [lower five bits] is valid and part 2 doesn't matter. Similarly, in the receive buffer, part 3 is valid and part 4 is not used. SYNC 1 when part 1 = 3. With parity, the LSB af part 4is the parity bit, but itis not compared with the SYNC character. LSB MSB LSB MSB All bits are set to 1 by Tatatpl x x? To aia Y EH = 1. Oro; ria; xX, xX tigi oj; titi t = CPU Operation @ @ SYNC Receive Buffer RxDATA tnput tet 1 4 Command EH=1 o fx tt xt Po et xy xP xt x ee ' RxEN=1 0 Popatar aaa ait it [ti set iat tit 1 } Mark ECL=1 0 Priaiata apt te tity tits itisia ie Paneer ar areal 0 (atatataiaia at ititlaitisitiotiitiiisho] 0 Trapt a dT itittartp tt toot titi ifea 0 fatatar a tiaras ttf ae ty opayat stay ti tfet Ff Sync Charactert 0 faraiapalara ait t pts opova tits iaiifet 0 [araraia ata aya topo agai titi tiifeoy 0 fata ataolaia ai tport tiolatititith'] 0 [rrttilororataia tft ties toytiniits 0 o Privterorrialarart]1errieret tiv, ait }eo | synechwacter2 ooo a 0 RECS TETSTEDEE SEED CPOE UCUETELSSTE a t eo oo Read Status 1 Poforaeaioia;artitparoforata i aiti tis iet Tt Tt + St fo Loraitiortrayyy ty [Toforrrioristitii- 9 | pata @ Cleared by Status Read X: don't care 83-000795B S~-18NEC vPD71051 Figure 20. Synchronous Receiver Example SYNRX : CALL SYNMOD MOV AL, 10010100B OUT PCTRL, AL MOV BW, OFFSET RXDADR RXLEN : IN AL, PCTRL TESTI AL, 1 BZ RXLEN IN AL, DATA MOV STLEN, AL MOV CL, AL MOV CH, 00H RXDATA: IN AL, PCTRL TESTI AL, 1 BZ RXDATA iN AL, PDATA MOV [BW],AL ING BW DBNZ RXDATA MOV AL, 00000000B OUT PCTRL, AL RET STLEN DB 2 RXDADR DB 256 DUP (0) ;Set sync mode ;Command: enter hunt ;phase, clear error flags, receive enable ;Set receive data store address sReceive the number of sreceive data ;Set the number of sreceive data to both variable and ;counter ;Receive and store the ;number of data bytes ;stated by the counter ;Command: receive disable Set number of receiver data Reserve receive data area Standby Mode TheyPD71051 isa low-power CMOS device. In standby mode, it disables the external input clocks to the inside circuitry (CLK, TxCLK, and RxCLK), thereby con- suming less power. A hardware reset is one way to enter standby mode. The input of a high level to the RESET pin causes the uPD71051 to enter standby mode at the falling edge of the high level. A software reset command is the other way to enter standby mode. The only way to take the #PD71051 out of standby mode is to write a mode byte. In standby mode, the TxRDY, TxEMP, RxRDY, and SYNC/BRK pins are at low level and the TxDATA, DTS, and RTS pins are at high level. Figure 21 shows the timing for standby mode. While the internal standby signal is high, the external clocks to the 4PD71051 are ignored. If data (C/D =0) is written to the uPD71051 in standby mode, the operations are undefined and unpredictable operation may result. Figure 21. Standby Made Timing Hardware Reset cs << te te WR ( Internal Standby Signal -_ Mode Word Software Reset OO Wa Software Reset Mode Word Command Internal Standby Signat 83-000799A sc~19