Eice DR IV ER TM Co m pac t High voltage gate driver IC 2E DL fa mi ly 600 V half bridge gate drive IC 2EDL05I06PF 2EDL05I06PJ 2EDL05I06BF 2EDL05N06PF 2EDL05N06PJ EiceDRIVERTM Compact Final dat a sheet <Revision 2.5>, 17.07.2014 Final Indust rial Po wer C o ntrol Edition 17.07.2014 Published by Infineon Technologies AG 81726 Munich, Germany (c) 2015 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation, warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices, please contact the nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact the nearest Infineon Technologies Office. Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. EiceDRIVERTM Compact 2EDL family Revision History Page or Item Subjects (major changes since previous revision) <Revision 0.85>, 16.04.2013 all change term VCC in VDD pp.16 Introduced Iopk+ and Iopk- values all introduced 2EDL05N06PJ all introduced 2EDL05I06PJ Trademarks of Infineon Technologies AG AURIXTM, BlueMoonTM, C166TM, CanPAKTM, CIPOSTM, CIPURSETM, COMNEONTM, EconoPACKTM, CoolMOSTM, CoolSETTM, CORECONTROLTM, CROSSAVETM, DAVETM, EasyPIMTM, EconoBRIDGETM, EconoDUALTM, EconoPIMTM, EiceDRIVERTM, eupecTM, FCOSTM, HITFETTM, HybridPACKTM, IRFTM, ISOFACETM, IsoPACKTM, MIPAQTM, ModSTACKTM, my-dTM, NovalithICTM, OmniTuneTM, OptiMOSTM, ORIGATM, PRIMARIONTM, PrimePACKTM, PrimeSTACKTM, PRO-SILTM, PROFETTM, RASICTM, ReverSaveTM, SatRICTM, SIEGETTM, SINDRIONTM, SIPMOSTM, SMARTiTM, SmartLEWISTM, SOLID FLASHTM, TEMPFETTM, thinQ!TM, TRENCHSTOPTM, TriCoreTM, X-GOLDTM, X-PMUTM, XMMTM, XPOSYSTM. Other Trademarks Advance Design SystemTM (ADS) of Agilent Technologies, AMBATM, ARMTM, MULTI-ICETM, KEILTM, PRIMECELLTM, REALVIEWTM, THUMBTM, VisionTM of ARM Limited, UK. AUTOSARTM is licensed by AUTOSAR development partnership. BluetoothTM of Bluetooth SIG Inc. CAT-iqTM of DECT Forum. COLOSSUSTM, FirstGPSTM of Trimble Navigation Ltd. EMVTM of EMVCo, LLC (Visa Holdings Inc.). EPCOSTM of Epcos AG. FLEXGOTM of Microsoft Corporation. FlexRayTM is licensed by FlexRay Consortium. HYPERTERMINALTM of Hilgraeve Incorporated. IECTM of Commission Electrotechnique Internationale. IrDATM of Infrared Data Association Corporation. ISOTM of INTERNATIONAL ORGANIZATION FOR STANDARDIZATION. MATLABTM of MathWorks, Inc. MAXIMTM of Maxim Integrated Products, Inc. MICROTECTM, NUCLEUSTM of Mentor Graphics Corporation. MifareTM of NXP. MIPITM of MIPI Alliance, Inc. MIPSTM of MIPS Technologies, Inc., USA. muRataTM of MURATA MANUFACTURING CO., MICROWAVE OFFICETM (MWO) of Applied Wave Research Inc., OmniVisionTM of OmniVision Technologies, Inc. OpenwaveTM Openwave Systems Inc. RED HATTM Red Hat, Inc. RFMDTM RF Micro Devices, Inc. SIRIUSTM of Sirius Satellite Radio Inc. SOLARISTM of Sun Microsystems, Inc. SPANSIONTM of Spansion LLC Ltd. SymbianTM of Symbian Software Limited. TAIYO YUDENTM of Taiyo Yuden Co. TEAKLITETM of CEVA, Inc. TEKTRONIXTM of Tektronix Inc. TOKOTM of TOKO KABUSHIKI KAISHA TA. UNIXTM of X/Open Company Limited. VERILOGTM, PALLADIUMTM of Cadence Design Systems, Inc. VLYNQTM of Texas Instruments Incorporated. VXWORKSTM, WIND RIVERTM of WIND RIVER SYSTEMS, INC. ZETEXTM of Diodes Zetex Limited. Last Trademarks Update 2010-10-26 Final datasheet 3 <Revision 2.5>, 17.07.2014 EiceDRIVERTM Compact 2EDL family Table of Contents 1 Overview ............................................................................................................................................. 7 2 Blockdiagram...................................................................................................................................... 9 3 3.1 3.2 3.2.1 3.2.2 3.2.3 3.3 3.4 3.5 3.6 3.7 3.8 Pin configuration, description, and functionality ......................................................................... 10 Pin Configuration and Description...................................................................................................... 10 Low Side and High Side Control Pins (LIN, HIN) ............................................................................... 10 Input voltage range ............................................................................................................................ 10 Switching levels .................................................................................................................................. 10 Input filter time .................................................................................................................................... 11 VDD and GND .................................................................................................................................... 11 VB and VS (High Side Supplies) ........................................................................................................ 11 LO and HO (Low and High Side Outputs) .......................................................................................... 11 Undervoltage lockout (UVLO) ............................................................................................................ 12 Bootstrap diode .................................................................................................................................. 12 Deadtime and interlock function ......................................................................................................... 12 4 4.1 4.2 4.3 4.4 4.5 4.6 Electrical Parameters ....................................................................................................................... 13 Absolute Maximum Ratings ............................................................................................................... 13 Required operation conditions ........................................................................................................... 14 Operating Range ................................................................................................................................ 14 Static logic function table ................................................................................................................... 15 Static parameters ............................................................................................................................... 15 Dynamic parameters .......................................................................................................................... 17 5 Timing diagrams............................................................................................................................... 18 6 6.1 6.2 Package ............................................................................................................................................. 20 PG-DSO-8 .......................................................................................................................................... 20 PG-DSO-14 ........................................................................................................................................ 21 Final datasheet 4 <Revision 2.5>, 17.07.2014 EiceDRIVERTM Compact 2EDL family List of Figures Figure 1 Figure 2 Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 8 Figure 9 Figure 10 Figure 11 Figure 12 Figure 13 Figure 14 Figure 15 Typical Application SO8 / SO14 package 0.5 A .................................................................................. 8 Block diagram for 2EDL05x06Py ......................................................................................................... 9 Pin Configuration of 2EDL family ....................................................................................................... 10 Input pin structure............................................................................................................................... 11 Input filter timing diagram ................................................................................................................... 11 Timing of short pulse suppression ..................................................................................................... 18 Timing of of internal deadtime ............................................................................................................ 18 Input to output propagation delay times and switching times definition ............................................. 18 Operating areas (IGBT UVLO levels)................................................................................................. 19 Operating areas (MOSFET UVLO levels) .......................................................................................... 19 Output pulse width timing and matching delay timing diagram for positive logic ............................... 19 Package drawing ................................................................................................................................ 20 PCB reference layout left: Reference layout right: detail of footprint .............................................. 20 Package drawing ................................................................................................................................ 21 PCB reference layout (according to JEDEC 1s0P) left: Reference layout right: detail of footprint .... 21 Final datasheet 5 <Revision 2.5>, 17.07.2014 EiceDRIVERTM Compact 2EDL family List of Tables Table 1 Table 2 Table 3 Table 4 Table 5 Table 6 Table 7 Table 8 Table 9 Members of 2EDL family ...................................................................................................................... 7 Pin Description ................................................................................................................................... 10 Abs. maximum ratings ........................................................................................................................ 13 Required Operation Conditions .......................................................................................................... 14 Operating range ................................................................................................................................. 14 Static parameters ............................................................................................................................... 15 Dynamic parameters .......................................................................................................................... 17 Data of reference layout ..................................................................................................................... 20 Data of reference layout ..................................................................................................................... 21 Final datasheet 6 <Revision 2.5>, 17.07.2014 EiceDRIVERTM Compact 2EDL family EiceDRIVERTM Compact 600 V half bridge gate drive IC Overview 1 PG-DSO-8 Main features Thin-film-SOI-technology Maximum blocking voltage +600V Individual control circuits for both outputs Filtered detection of under voltage supply All inputs clamped by diodes Active shut down function Asymmetric undervoltage lockout thresholds for high side and low PG-DSO-14 side 1 Qualified according to JEDEC (high temperature stress tests for 1000h) for target applications Product highlights Insensitivity of the bridge output to negative transient voltages up to -50V given by SOI-technology Ultra fast bootstrap diode Typical applications Home appliances Consumer electronics Fans, pumps General purpose drives Product family Table 1 Members of 2EDL family Sales Name 2EDL05I06PF Special function output current Target transistor typ. LS UVLOthresholds deadtime, interlock 0.5 A IGBT 12.5 V / 11.6 V Bootstrap Package diode Yes 2EDL05I06PJ DSO-14 2EDL05I06BF - 0.5 A IGBT 12.5 V / 11.6 V Yes DSO-8 2EDL05N06PF deadtime, interlock 0.5 A MOSFET 9.1 V / 8.3 V Yes DSO-8 2EDL05N06PJ 1 DSO-8 0.5 A DSO-14 J-STD-020 and JESD-022 Final datasheet 7 <Revision 2.5>, 17.07.2014 EiceDRIVERTM Compact 2EDL family Description The 2EDL family contains devices, which control power devices like MOS-transistors or IGBTs with a maximum blocking voltage of +600V in half bridge configurations. Based on the used SOI-technology there is an excellent ruggedness on transient voltages. No parasitic thyristor structures are present in the device. Hence, no parasitic latch up may occur at all temperature and voltage conditions. The two independent drivers outputs are controlled at the low-side using two different CMOS resp. LSTTL compatible signals, down up to 3.3V logic. The device includes an under-voltage detection unit with hysteresis characteristic which are optimised either for IGBT or MOSFET. Those parts, which are designed for IGBT have asymmetric undervoltage lockout levels, which support strongly the integrated ultrafast bootstrap diode. Additionally, the offline gate clamping function provides an inherent protection of the transistors for parasitic turn-on by floating gate conditions, when the IC is not supplied via VDD. DC-Bus VCC +5V VB HO 2EDL05x06yy VS VCC VDD To Load C PWM_H HIN PWM_L LIN GND LO To Opamp / Comparator GND - DC-Bus Figure 1 Typical Application SO8 / SO14 package 0.5 A Final datasheet 8 <Revision 2.5>, 17.07.2014 EiceDRIVERTM Compact 2EDL family 2 Figure 2 Blockdiagram Block diagram for 2EDL05x06Py Final datasheet 9 <Revision 2.5>, 17.07.2014 EiceDRIVERTM Compact 2EDL family 3 Pin configuration, description, and functionality 3.1 Pin Configuration and Description 2EDL (SO8) Figure 3 Table 2 2EDL (0.5A, SO14) 2EDL (2.3A, SO14) 1 VDD VB 8 1 nc nc 14 1 VDD nc 14 2 HIN HO 7 2 VDD nc 13 2 HIN nc 13 3 LIN VS 6 3 HIN VB 12 3 LIN VB 12 4 GND LO 5 4 LIN HO 11 4 EN-/FLT HO 11 5 GND VS 10 5 GND VS 10 6 LO nc 9 6 PGND nc 9 7 nc nc 8 7 nc 8 LO Pin Configuration of 2EDL family Pin Description Symbol Description VDD Low side power supply GND Logic ground HIN High side logic input LIN Low side logic input VB High side positive power supply HO High side gate driver output VS High side negative power supply LO Low side gate driver output nc Not Connected 3.2 Low Side and High Side Control Pins (LIN, HIN) 3.2.1 Input voltage range All input pins have the capability to process input voltages up to the supply voltage of the IC. The inputs are therefore internally clamped to VDD and GND by diodes. An internal pull-down resistor is high ohmic, so that it can keep the IC in a safe state in case of PCB crack. 3.2.2 Switching levels The Schmitt trigger input threshold is such to guarantee LSTTL and CMOS compatibility down to 3.3 V controller outputs. The input Schmitt trigger and noise filter provide beneficial noise rejection to short input pulses according to Figure 4 and Figure 5. Please note, that the switching levels of the input structures remain constant even though they can accept amplitudes up to the IC supply level. Final datasheet 10 <Revision 2.5>, 17.07.2014 EiceDRIVERTM Compact 2EDL family 2EDL-family ILIN IHIN HINx LINx Vcc V ; V IH IL INPUT NOISE FILTER VZ=5.25 V Figure 4 3.2.3 Input pin structure Input filter time a) b) tFILIN tFILIN HIN LIN LIN high LO Figure 5 HO LO low Input filter timing diagram Short pulses are suppressed by means of an input filter. All IC, which have undervoltage lockout (UVLO) thresholds for MOSFET, have an input filter time of tFILIN = 75ns typ. and 150ns max. All IC having UVLO thresholds for IGBT have filter times of tFILIN = 150ns min and 200ns typ. 3.3 VDD and GND VDD is the low side supply and it provides power to both the input logic and the low side output power stage. The input logic is referenced to GND ground as well as the under-voltage detection circuit. Output power stage is also referenced to GND ground. The undervoltage lockout circuit enables the device to operate at power on when a typical supply voltage higher than VDDUV+ is present. Please see section 3.6 "Undervoltage lockout"" for further information. 1 A filter time of typ. 1.8s helps to suppress noise from the UVLO circuit, so that negative going voltage spikes at the supply pins will avoid parasitic UVLO events. 3.4 VB and VS (High Side Supplies) VB to VS is the high side supply voltage. The high side circuit can float with respect to GND following the external high side power device emitter/source voltage. Due to the low power consumption, the floating driver 1 stage can be supplied by bootstrap topology connected to VDD. A filter time of typ. 1.8s helps to suppress noise from the UVLO circuit, so that negative going voltage spikes at the supply pins will avoid parasitic UVLO events. The under-voltage circuit enables the device to operate at power on when a typical supply voltage higher than VDDUV+ is present. Please see section 3.6 "Undervoltage lockout" for further information. Details on bootstrap supply section and transient immunity can be found in application note EiceDRIVERTM 2EDL family: Technical description. 3.5 LO and HO (Low and High Side Outputs) Low side and high side power outputs are specifically designed for pulse operation such as gate drive for IGBT and MOSFET devices. Low side output is state triggered by the respective input, while high side output is edge triggered by the respective input. In particular, after an undervoltage condition of the VBS supply, a new turn-on signal (edge) is necessary to activate the high side output. In contrast, the low side outputs switch to the state of their respective inputs after an undervoltage condition of the VDD supply. The output current specification IO+ and IO- is defined in a way, which considers the power transistors miller voltage.This helps to design the gate drive better in terms of the application needs. Nevertheless, the devices are also characterised for the value of the pulse short circuit value IOpk+ and IOpk-. Final datasheet 11 <Revision 2.5>, 17.07.2014 EiceDRIVERTM Compact 2EDL family 3.6 Undervoltage lockout (UVLO) Two different UVLO options are required for IGBT and MOSFET. The types 2EDL05I06Px and 2EDL05I06BF are designed to drive IGBT. There are higher levels of undervoltage lockout for the low side UVLO than for the high side. This supports an improved start up of the IC, when bootstrapping is used. The thresholds for the low side are typically VDDUV+ = 12.5 V (positive going) and VDDUV- = 11.6 V (negative going). The thresholds for the high side are typically VBSUV+ = 11.6 V (positive going) and VBSUV- = 10.7 V (negative going). The types 2EDL05N06Px are designed to drive power MOSFET. A similar distinction for the high side and low side UVLO threshold as for IGBT is not realised here. The IC shuts down all the gate drivers power outputs, when the supply voltage is below typ. VDDUV- = 8.3 V (min. / max. = 7.5 V / 9 V). The turn-on threshold is typ. VDDUV+ = 9.1 V (min. / max. = 8.3 V / 9.9 V) 3.7 Bootstrap diode An ultra fast bootstrap diode is monolithically integrated for establishing the high side supply. The differential resistor of the diode helps to avoid extremely high inrush currents when charging the bootstrap capacitor initially. 3.8 Deadtime and interlock function The IC provides a hardware fixed deadtime. The deadtime is different for the two MOSFET types (2EDL05N06Px) and for the two IGBT types (2EDL05I06Px). The deadtimes are particularly typ. 380 ns for IGBT and typ. 75 ns for MOSFET. An additional interlock function prevents the two outputs from being activated simultaneously. The part 2EDL05I06BF does not have the deadtime feature and also not the interlock function. Here, the two outpus can be activated simultaneously. _________________________________ 1 Not subject of production test, verified by characterisation Final datasheet 12 <Revision 2.5>, 17.07.2014 EiceDRIVERTM Compact 2EDL family 4 Electrical Parameters 4.1 Absolute Maximum Ratings All voltages are absolute voltages referenced to VGND -potential unless otherwise specified. (Ta=25C) Table 3 Abs. maximum ratings Parameter Symbol VS High side offset voltage(Note 1) Min. Max. Unit VDD-VBS-6 600 V VDD -VBS - 50 - High side offset voltage (tp<500ns, Note 1) High side offset voltage(Note 1) VB High side offset voltage (tp<500ns, Note 1) VDD - 6 620 VDD - 50 - 20 VB + 0.5 High side floating supply voltage (VB vs. VS) (internally clamped) VBS -1 High side output voltage (VHO vs. VS) VHO -0.5 Low side supply voltage (internally clamped) Low side output voltage (VLO vs. VGND) VDD -1 VLO -0.5 Input voltage LIN,HIN VIN -0.5 - - - - VDD + 0.5 0.6 0.85 195 139 W C Power dissipation (to package) (Note 2) Thermal resistance (junction to ambient, see section 6) DSO8 DSO14 DSO8 DSO14 PD Rth(j-a) 20 VGND + 0.5 Junction temperature (Note 3) TJ - 150 Storage temperature TS dVS/dt - 40 - 150 offset voltage slew rate (Note 4) 50 K/W V/ns Note :The minimum value for ESD immunity is 1.0kV (Human Body Model). ESD immunity inside pins connected to the low side (VDD, HIN, LIN, GND, LO) and pins connected inside each high side itself (VB, HO, VS) is guaranteed up to 1.5kV (Human Body Model) respectively. Note 1 : In case VDD > VB there is an additional power dissipation in the internal bootstrap diode between pins VDD and VB in case of activated bootstrap diode. Insensitivity of bridge output to negative transient voltage up to -50V is not subject to production test - verified by design / characterization. Note 2: Consistent power dissipation of all outputs. All parameters are inside operating range. Note 3: Qualification stress tests cover a max. junction temperature of 150C for 1000 h. Note 4: Not subject of production test, verified by characterisation. Final datasheet 13 <Revision 2.5>, 17.07.2014 EiceDRIVERTM Compact 2EDL family 4.2 Required operation conditions All voltages are absolute voltages referenced to VGND -potential unless otherwise specified. (Ta = 25C) Table 4 Required Operation Conditions Parameter Min. Max. Unit High side offset voltage (Note 1) Symbol VB 7 620 V Low side supply voltage (internally clamped) VDD 10 20 4.3 Operating Range All voltages are absolute voltages referenced to VGND -potential unless otherwise specified. (Ta = 25C) Table 5 Operating range Parameter Symbol VS Min. Max. High side floating supply offset voltage (VB vs. VDD, statically) VBDD VDD VBS -1 500 -1.0 500 High side floating supply voltage (VB vs. VS, Note 1) VBS 13 17.5 10 High side floating supply offset voltage IGBT-Types MOSFET-Types High side output voltage (VHO vs. VS) Low side output voltage (VLO vs. VGND) Low side supply voltage IGBT-Types Pulse width for ON or OFF (Note 3) IGBT-Types VHO 10 VLO 0 VDD VDD 13 17.5 10 17.5 VIN 0 17.5 tIN 0.8 - 0.3 - -40 - - 95 C 8.0 6.0 K/W MOSFET-Types Ambient temperature Ta Thermal coefficient (junction to top, see section 6) DSO8 DSO14 V 17.5 VBS MOSFET-Types Logic input voltages LIN,HIN (Note 2) Unit th(j-top) s Note 1 : Logic operational for VB (VB vs. VGND) > 7.0V Note 2 : All input pins (HIN, LIN) are internally clamped (see abs. maximum ratings) Note 3 : The input pulse may not be transmitted properly in case of input pulse width at LIN and HIN below 0.8s (IGBT types) or 0.3 s (MOSFET) respectively Final datasheet 14 <Revision 2.5>, 17.07.2014 EiceDRIVERTM Compact 2EDL family 4.4 Static logic function table VDD VBS LO HO <VDDUV- X 0 0 15V <VBSUV- LIN 0 15V 15V 0 0 15V 15V 0 0 15V 15V LIN HIN all voltages with reference to GND 4.5 Static parameters VDD = VBS = 15V unless otherwise specified. (Ta = 25C) Table 6 Static parameters Parameter Symbol Values Min. Typ. Max. Unit Test condition V High level input voltage VIH 1.7 2.1 2.4 Low level input voltage VIL 0.7 - - 0.9 VDD -0.45 VB -0.45 1.1 VDD -1 VB -1 - - VGND+0.13 VS+0.13 VGND+0.3 VS +0.3 11.8 12.5 13.2 8.3 9.1 9.9 10.9 11.6 12.4 8.3 9.1 9.9 10.9 11.6 12.4 7.5 8.3 9 High level output voltage LO VOH HO LO VOL HO Low level output voltage IO = - 20 mA IO = 20 mA VDD supply undervoltage positive going threshold IGBT-types VBS supply undervoltage positive going threshold IGBT-types VDD supply undervoltage negative going threshold IGBT-types VBS supply undervoltage negative going threshold IGBT-types 10 10.7 11.7 MOSFET types 7.5 8.3 9 VDD and VBS supply UVLO hysteresis IGBT-types VDDUVH MOSFET types VBSUVH ILVS+ High side leakage current betw. VS and GND 1 ILVS+ High side leakage current betw. VS and GND IQBS1 Quiescent current VBS supply (VB only) 0.5 0.9 - 0.5 0.9 - - 1 12.5 - 10 - TJ = 125 C, VS = 600 V - 170 300 HO = low depending on current types Quiescent current VBS supply (VB only) - 170 300 HO = high depending on 1 VDDUV+ MOSFET types VBSUV+ MOSFET types VDDUV- MOSFET types VBSUV- IQBS2 A VS = 600V Not subject of production test, verified by characterisation Final datasheet 15 <Revision 2.5>, 17.07.2014 EiceDRIVERTM Compact 2EDL family Table 6 Static parameters Parameter Symbol Values Min. Typ. Max. Unit Test condition mA current types VLIN = float. Quiescent current VDD supply (VDD only) IQDD1 - 0.3 0.6 Quiescent current VDD supply (VDD only) IQDD2 - 0.28 0.6 VLIN = 3.3 V, VHIN=0 Quiescent current VDD supply (VDD only) IQDD3 - 0.28 0.6 VLIN=0 , VHIN=3.3 V Input bias current ILIN+ 15 35 60 Input bias current ILIN- - 0 - VLIN = 0 Input bias current IHIN+ 15 35 60 VHIN = 3.3 V Input bias current IHIN- - 0 - VHIN = 0 Mean output current for load capacity charging in range from 3 V (20%) to 6 V (40%) Peak output current turn on (single pulse) IO+ 0.18 0.23 - IOpk+1 - 0.36 - IO- Mean output current for load capacity discharging in range from 12 V (80%) to 9 V (60%) IOpk-1 Peak output current turn off (single pulse) 0.39 0.48 - - 0.70 - Bootstrap diode forward voltage between VDD and VB Bootstrap diode forward current between VDD and VB VF,BSD - 1.0 1.2 V RL = 0 , tp <10 s IF = 0.3 mA IF,BSD 30 55 80 mA VDD - VB = 4 V Bootstrap diode resistance RBSD 20 36 54 VF1 = 4 V, VF2 =5V 1 A A VLIN = 3.3 V CL = 22 nF RL = 0 , tp <10 s CL = 22 nF Not subject of production test, verified by characterisation Final datasheet 16 <Revision 2.5>, 17.07.2014 EiceDRIVERTM Compact 2EDL family 4.6 Dynamic parameters VDD = VBS = 15 V, VS = VGND, CL = 180 pF unless otherwise specified. (TA=25C) Table 7 Dynamic parameters Parameter Symbol ton Turn-on propagation delay IGBT types MOSFET types toff Turn-off propagation delay IGBT types MOSFET types Values Min. Typ. Max. 280 210 420 310 610 460 260 400 590 200 300 440 Turn-on rise time tr - 48 80 Turn-off fall time tf - 24 40 tFILIN Input filter time at LIN/HIN IGBT types for turn on and off MOSFET types HIN LIN DT Dead time IGBT types (not for 2EDL05I06BF) MOSFET types 120 192 - 50 100 100 150 170 250 260 380 540 30 75 140 Dead time matching abs(DT_LH - DT_HL) for single IC (not for 2EDL05I06BF) - 10 80 10 50 IGBT types MDT MOSFET types Matching delay ON, abs(ton_HS - ton_LS) MTON - 10 60 Matching delay OFF, abs(toff_HS-toff_LS) MTOFF - 10 60 Output pulse width matching. PW in-PW out PM - 20 80 - 20 70 Final datasheet IGBT types MOSFET types 17 Unit Test condition ns VLIN/HIN = 0 or 3.3 V VLIN/HIN = 0 or 3.3 V CL = 1 nF VLIN/HIN = 0 & 3.3 V ns VLIN/HIN = 0 & 3.3 V ext. dead time 0ns external dead time > 500 ns external dead time >500 ns PW in > 1 s <Revision 2.5>, 17.07.2014 EiceDRIVERTM Compact 2EDL family Timing diagrams 5 tFILIN HIN/LIN tFILIN tIN tIN HIN/LIN tIN < tFILIN tIN < tFILIN high HO/LO HO/LO low tIN HIN/LIN tIN HIN/LIN tIN > tFILIN tIN > tFILIN HO/LO HO/LO Figure 6 Timing of short pulse suppression LIN1,2,3 1.65V 1.65V HIN1,2,3 12V HO1,2,3 3V DT DT 12 V LO1,2,3 3V Figure 7 Timing of of internal deadtime LIN 1.65V 1.65V HIN PWIN ton tr toff 80% tf 80% HO LO 20% Figure 8 PWOUT 20% Input to output propagation delay times and switching times definition Final datasheet 18 <Revision 2.5>, 17.07.2014 EiceDRIVERTM Compact 2EDL family Figure 9 Operating areas (IGBT UVLO levels) Figure 10 Operating areas (MOSFET UVLO levels) HIN/LIN PWIN PM = PWIN - PWOUT PWOUT HO/LO HIN/LIN PWIN PM = PWIN - PWOUT MToff PWOUT HO/LO Figure 11 MTon Output pulse width timing and matching delay timing diagram for positive logic Final datasheet 19 <Revision 2.5>, 17.07.2014 EiceDRIVERTM Compact 2EDL family 6 Package 6.1 PG-DSO-8 Max. reflow solder temperature: Max. wave solder temperature: Figure 12 Package drawing Figure 13 PCB reference layout left: Reference layout right: detail of footprint 265C acc. JEDEC 245C acc. JEDEC The thermal coefficient is used to calculate the junction temperature, when the IC surface temperature is measured. The junction temperature is j = th(j-top) + top Table 8 Data of reference layout Dimensions Material Metal (Copper) 76.2 114.3 1.5 mm FR4 (therm = 0.3 W/mK) 70m (therm = 388 W/mK) Final datasheet 20 <Revision 2.5>, 17.07.2014 EiceDRIVERTM Compact 2EDL family 6.2 PG-DSO-14 Max. reflow solder temperature: Max. wave solder temperature: Figure 14 Package drawing Figure 15 265C acc. JEDEC 245C acc. JEDEC PCB reference layout (according to JEDEC 1s0P) left: Reference layout right: detail of footprint The thermal coefficient is used to calculate the junction temperature, when the IC surface temperature is measured. The junction temperature is j = th(j-top) + top Table 9 Data of reference layout Dimensions Material Metal (Copper) 76.2 114.3 1.5 mm FR4 (therm = 0.3 W/mK) 70m (therm = 388 W/mK) Final datasheet 21 <Revision 2.5>, 17.07.2014 w w w . i n f i n e o n . c o m Published by Infineon Technologies AG Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Infineon: 2EDL05N06PJXUMA1 2EDL05I06PJXUMA1 2EDL05I06PFXUMA1 2EDL05N06PFXUMA1 2EDL05I06BFXUMA1 2EDL05I06PF 2EDL05I06PJ 2EDL05I06BF 2EDL05N06PF