Industrial Power Control
EiceDRIVER™ Compact
High voltage gate driver IC
Final datasheet
<Revision 2.5>, 17.07.2014
Final
2EDL family
600 V half bridge gate drive IC
2EDL05I06PF
2EDL05I06PJ
2EDL05I06BF
2EDL05N06PF
2EDL05N06PJ
EiceDRIVER™ Compact
Edition 17.07.2014
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2015 Infineon Technologies AG
All Rights Reserved.
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EiceDRIVER™ Compact
2EDL family
Final datasheet 3 <Revision 2.5>, 17.07.2014
Revision History
Page or Item
Subjects (major changes since previous revision)
<Revision 0.85>, 16.04.2013
all
change term VCC in VDD
pp.16
Introduced Iopk+ and Iopk- values
all
introduced 2EDL05N06PJ
all
introduced 2EDL05I06PJ
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Last Trademarks Update 2010-10-26
EiceDRIVER™ Compact
2EDL family
Final datasheet 4 <Revision 2.5>, 17.07.2014
Table of Contents
1 Overview ............................................................................................................................................. 7
2 Blockdiagram ...................................................................................................................................... 9
3 Pin configuration, description, and functionality ......................................................................... 10
3.1 Pin Configuration and Description...................................................................................................... 10
3.2 Low Side and High Side Control Pins (LIN, HIN) ............................................................................... 10
3.2.1 Input voltage range ............................................................................................................................ 10
3.2.2 Switching levels .................................................................................................................................. 10
3.2.3 Input filter time .................................................................................................................................... 11
3.3 VDD and GND .................................................................................................................................... 11
3.4 VB and VS (High Side Supplies) ........................................................................................................ 11
3.5 LO and HO (Low and High Side Outputs) .......................................................................................... 11
3.6 Undervoltage lockout (UVLO) ............................................................................................................ 12
3.7 Bootstrap diode .................................................................................................................................. 12
3.8 Deadtime and interlock function ......................................................................................................... 12
4 Electrical Parameters ....................................................................................................................... 13
4.1 Absolute Maximum Ratings ............................................................................................................... 13
4.2 Required operation conditions ........................................................................................................... 14
4.3 Operating Range ................................................................................................................................ 14
4.4 Static logic function table ................................................................................................................... 15
4.5 Static parameters ............................................................................................................................... 15
4.6 Dynamic parameters .......................................................................................................................... 17
5 Timing diagrams............................................................................................................................... 18
6 Package ............................................................................................................................................. 20
6.1 PG-DSO-8 .......................................................................................................................................... 20
6.2 PG-DSO-14 ........................................................................................................................................ 21
EiceDRIVER™ Compact
2EDL family
Final datasheet 5 <Revision 2.5>, 17.07.2014
List of Figures
Figure 1 Typical Application SO8 / SO14 package 0.5 A .................................................................................. 8
Figure 2 Block diagram for 2EDL05x06Py ......................................................................................................... 9
Figure 3 Pin Configuration of 2EDL family ....................................................................................................... 10
Figure 4 Input pin structure............................................................................................................................... 11
Figure 5 Input filter timing diagram ................................................................................................................... 11
Figure 6 Timing of short pulse suppression ..................................................................................................... 18
Figure 7 Timing of of internal deadtime ............................................................................................................ 18
Figure 8 Input to output propagation delay times and switching times definition ............................................. 18
Figure 9 Operating areas (IGBT UVLO levels)................................................................................................. 19
Figure 10 Operating areas (MOSFET UVLO levels) .......................................................................................... 19
Figure 11 Output pulse width timing and matching delay timing diagram for positive logic ............................... 19
Figure 12 Package drawing ................................................................................................................................ 20
Figure 13 PCB reference layout left: Reference layout right: detail of footprint .............................................. 20
Figure 14 Package drawing ................................................................................................................................ 21
Figure 15 PCB reference layout (according to JEDEC 1s0P) left: Reference layout right: detail of footprint .... 21
EiceDRIVER™ Compact
2EDL family
Final datasheet 6 <Revision 2.5>, 17.07.2014
List of Tables
Table 1 Members of 2EDL family ...................................................................................................................... 7
Table 2 Pin Description ................................................................................................................................... 10
Table 3 Abs. maximum ratings ........................................................................................................................ 13
Table 4 Required Operation Conditions .......................................................................................................... 14
Table 5 Operating range ................................................................................................................................. 14
Table 6 Static parameters ............................................................................................................................... 15
Table 7 Dynamic parameters .......................................................................................................................... 17
Table 8 Data of reference layout ..................................................................................................................... 20
Table 9 Data of reference layout ..................................................................................................................... 21
EiceDRIVER™ Compact
2EDL family
Final datasheet 7 <Revision 2.5>, 17.07.2014
EiceDRIVER™ Compact
600 V half bridge gate drive IC
1 Overview
Main features
Thin-film-SOI-technology
Maximum blocking voltage +600V
Individual control circuits for both outputs
Filtered detection of under voltage supply
All inputs clamped by diodes
Active shut down function
Asymmetric undervoltage lockout thresholds for high side and low
side
Qualified according to JEDEC
1
(high temperature stress tests for 1000h) for target applications
Product highlights
Insensitivity of the bridge output to negative transient voltages up to -50V given by SOI-technology
Ultra fast bootstrap diode
Typical applications
Home appliances
Consumer electronics
Fans, pumps
General purpose drives
Product family
Table 1 Members of 2EDL family
Sales Name
Special function
output
current
Target
transistor
Bootstrap
diode
Package
2EDL05I06PF
2EDL05I06PJ
deadtime, interlock
0.5 A
IGBT
Yes
DSO-8
DSO-14
2EDL05I06BF
–
0.5 A
IGBT
Yes
DSO-8
2EDL05N06PF
2EDL05N06PJ
deadtime, interlock
0.5 A
0.5 A
MOSFET
Yes
DSO-8
DSO-14
1
J-STD-020 and JESD-022
PG-DSO-8
PG-DSO-14
EiceDRIVER™ Compact
2EDL family
Final datasheet 8 <Revision 2.5>, 17.07.2014
Description
The 2EDL family contains devices, which control power devices like MOS-transistors or IGBTs with a maximum
blocking voltage of +600V in half bridge configurations. Based on the used SOI-technology there is an excellent
ruggedness on transient voltages. No parasitic thyristor structures are present in the device. Hence, no parasitic
latch up may occur at all temperature and voltage conditions.
The two independent drivers outputs are controlled at the low-side using two different CMOS resp. LSTTL
compatible signals, down up to 3.3V logic. The device includes an under-voltage detection unit with hysteresis
characteristic which are optimised either for IGBT or MOSFET.
Those parts, which are designed for IGBT have asymmetric undervoltage lockout levels, which support strongly
the integrated ultrafast bootstrap diode. Additionally, the offline gate clamping function provides an inherent
protection of the transistors for parasitic turn-on by floating gate conditions, when the IC is not supplied via VDD.
Figure 1 Typical Application
SO8 / SO14 package 0.5 A
LIN
HO
VS
LO
GND
To
Load
HIN
VCC
DC-Bus
- DC-Bus
2EDL05x06yy
To Opamp /
Comparator
VB
VB
VCC
µC
PWM_H
PWM_L
GND
+5V
VDD
EiceDRIVER™ Compact
2EDL family
Final datasheet 9 <Revision 2.5>, 17.07.2014
2 Blockdiagram
Figure 2 Block diagram for 2EDL05x06Py
EiceDRIVER™ Compact
2EDL family
Final datasheet 10 <Revision 2.5>, 17.07.2014
3 Pin configuration, description, and functionality
3.1 Pin Configuration and Description
Figure 3 Pin Configuration of 2EDL family
Table 2 Pin Description
Symbol
Description
VDD
Low side power supply
GND
Logic ground
HIN
High side logic input
LIN
Low side logic input
VB
High side positive power supply
HO
High side gate driver output
VS
High side negative power supply
LO
Low side gate driver output
nc
Not Connected
3.2 Low Side and High Side Control Pins (LIN, HIN)
3.2.1 Input voltage range
All input pins have the capability to process input voltages up to the supply voltage of the IC. The inputs are
therefore internally clamped to VDD and GND by diodes. An internal pull-down resistor is high ohmic, so that it
can keep the IC in a safe state in case of PCB crack.
3.2.2 Switching levels
The Schmitt trigger input threshold is such to guarantee LSTTL and CMOS compatibility down to 3.3 V
controller outputs. The input Schmitt trigger and noise filter provide beneficial noise rejection to short input
pulses according to Figure 4 and Figure 5. Please note, that the switching levels of the input structures remain
constant even though they can accept amplitudes up to the IC supply level.
VDD
1 14
HIN
2 13
3 12
4 11
LIN
5 10
6 9
7 8
GND
LO
nc
nc
1 8
2 7
3 6
4 5
2EDL (SO8) 2EDL (0.5A, SO14) 2EDL (2.3A, SO14)
nc
VB
HO
VS
nc VDD1 14
HIN2 13
3 12
4 11
LIN
5 10
6 9
7 8
GND
PGND
LO
nc
nc
EN-/FLT
nc
VB
HO
VS
nc
nc
nc
VDD VB
HIN HO
VS
LIN
GND LO
EiceDRIVER™ Compact
2EDL family
Final datasheet 11 <Revision 2.5>, 17.07.2014
Figure 4 Input pin structure
3.2.3 Input filter time
Figure 5 Input filter timing diagram
Short pulses are suppressed by means of an input filter. All IC, which have undervoltage lockout (UVLO)
thresholds for MOSFET, have an input filter time of tFILIN = 75ns typ. and 150ns max. All IC having UVLO
thresholds for IGBT have filter times of tFILIN = 150ns min and 200ns typ.
3.3 VDD and GND
VDD is the low side supply and it provides power to both the input logic and the low side output power stage.
The input logic is referenced to GND ground as well as the under-voltage detection circuit. Output power stage
is also referenced to GND ground.
The undervoltage lockout circuit enables the device to operate at power on when a typical supply voltage higher
than VDDUV+ is present. Please see section 3.6 “Undervoltage lockout”” for further information.
A filter time of typ. 1.8µs1 helps to suppress noise from the UVLO circuit, so that negative going voltage spikes
at the supply pins will avoid parasitic UVLO events.
3.4 VB and VS (High Side Supplies)
VB to VS is the high side supply voltage. The high side circuit can float with respect to GND following the
external high side power device emitter/source voltage. Due to the low power consumption, the floating driver
stage can be supplied by bootstrap topology connected to VDD. A filter time of typ. 1.8µs1 helps to suppress
noise from the UVLO circuit, so that negative going voltage spikes at the supply pins will avoid parasitic UVLO
events.
The under-voltage circuit enables the device to operate at power on when a typical supply voltage higher than
VDDUV+ is present. Please see section 3.6 “Undervoltage lockout” for further information. Details on bootstrap
supply section and transient immunity can be found in application note EiceDRIVER™ 2EDL family: Technical
description.
3.5 LO and HO (Low and High Side Outputs)
Low side and high side power outputs are specifically designed for pulse operation such as gate drive for IGBT
and MOSFET devices. Low side output is state triggered by the respective input, while high side output is edge
triggered by the respective input. In particular, after an undervoltage condition of the VBS supply, a new turn-on
signal (edge) is necessary to activate the high side output. In contrast, the low side outputs switch to the state of
their respective inputs after an undervoltage condition of the VDD supply.
The output current specification IO+ and IO- is defined in a way, which considers the power transistors miller
voltage.This helps to design the gate drive better in terms of the application needs. Nevertheless, the devices
are also characterised for the value of the pulse short circuit value IOpk+ and IOpk–.
VZ=5.25 V
INPUT
NOISE
FILTER
VIH; VIL
ILIN
IHIN
LINx
HINx
Vcc
2EDL-family
LIN HIN
LIN
LO HO
LO
high
low
tFILIN tFILIN
a) b)
EiceDRIVER™ Compact
2EDL family
Final datasheet 12 <Revision 2.5>, 17.07.2014
3.6 Undervoltage lockout (UVLO)
Two different UVLO options are required for IGBT and MOSFET. The types 2EDL05I06Px and 2EDL05I06BF
are designed to drive IGBT. There are higher levels of undervoltage lockout for the low side UVLO than for the
high side. This supports an improved start up of the IC, when bootstrapping is used. The thresholds for the low
side are typically VDDUV+ = 12.5 V (positive going) and VDDUV– = 11.6 V (negative going). The thresholds for the
high side are typically VBSUV+ = 11.6 V (positive going) and VBSUV– = 10.7 V (negative going).
The types 2EDL05N06Px are designed to drive power MOSFET. A similar distinction for the high side and low
side UVLO threshold as for IGBT is not realised here. The IC shuts down all the gate drivers power outputs,
when the supply voltage is below typ. VDDUV- = 8.3 V (min. / max. = 7.5 V / 9 V). The turn-on threshold is typ.
VDDUV+ = 9.1 V (min. / max. = 8.3 V / 9.9 V)
3.7 Bootstrap diode
An ultra fast bootstrap diode is monolithically integrated for establishing the high side supply. The differential
resistor of the diode helps to avoid extremely high inrush currents when charging the bootstrap capacitor
initially.
3.8 Deadtime and interlock function
The IC provides a hardware fixed deadtime. The deadtime is different for the two MOSFET types
(2EDL05N06Px) and for the two IGBT types (2EDL05I06Px). The deadtimes are particularly typ. 380 ns for
IGBT and typ. 75 ns for MOSFET. An additional interlock function prevents the two outputs from being activated
simultaneously.
The part 2EDL05I06BF does not have the deadtime feature and also not the interlock function. Here, the two
outpus can be activated simultaneously.
_________________________________
1
Not subject of production test, verified by characterisation
EiceDRIVER™ Compact
2EDL family
Final datasheet 13 <Revision 2.5>, 17.07.2014
4 Electrical Parameters
4.1 Absolute Maximum Ratings
All voltages are absolute voltages referenced to VGND -potential unless otherwise specified. (Ta=25°C)
Table 3 Abs. maximum ratings
Parameter
Symbol
Min.
Max.
Unit
High side offset voltage(Note 1)
VS
VDD-VBS-6
600
V
High side offset voltage (tp<500ns, Note 1)
VDD -VBS – 50
–
High side offset voltage(Note 1)
VB
VDD – 6
620
High side offset voltage (tp<500ns, Note 1)
VDD – 50
–
High side floating supply voltage (VB vs. VS) (internally clamped)
VBS
-1
20
High side output voltage (VHO vs. VS)
VHO
-0.5
VB + 0.5
Low side supply voltage (internally clamped)
VDD
-1
20
Low side output voltage (VLO vs. VGND)
VLO
-0.5
VGND + 0.5
Input voltage LIN,HIN
VIN
-0.5
VDD + 0.5
Power dissipation (to package) (Note 2) DSO8
DSO14
PD
–
–
0.6
0.85
W
Thermal resistance DSO8
(junction to ambient, see section 6) DSO14
Rth(j-a)
–
–
195
139
K/W
Junction temperature (Note 3)
TJ
–
150
°C
Storage temperature
TS
- 40
150
offset voltage slew rate (Note 4)
dVS/dt
–
50
V/ns
Note :The minimum value for ESD immunity is 1.0kV (Human Body Model). ESD immunity inside pins connected to the low side (VDD, HIN,
LIN, GND, LO) and pins connected inside each high side itself (VB, HO, VS) is guaranteed up to 1.5kV (Human Body Model) respectively.
Note 1 : In case VDD > VB there is an additional power dissipation in the internal bootstrap diode between pins VDD and VB in case of
activated bootstrap diode. Insensitivity of bridge output to negative transient voltage up to –50V is not subject to production test – verified by
design / characterization.
Note 2: Consistent power dissipation of all outputs. All parameters are inside operating range.
Note 3: Qualification stress tests cover a max. junction temperature of 150°C for 1000 h.
Note 4: Not subject of production test, verified by characterisation.
EiceDRIVER™ Compact
2EDL family
Final datasheet 14 <Revision 2.5>, 17.07.2014
4.2 Required operation conditions
All voltages are absolute voltages referenced to VGND -potential unless otherwise specified. (Ta = 25°C)
Table 4 Required Operation Conditions
Parameter
Symbol
Min.
Max.
Unit
High side offset voltage (Note 1)
VB
7
620
V
Low side supply voltage (internally clamped)
VDD
10
20
4.3 Operating Range
All voltages are absolute voltages referenced to VGND -potential unless otherwise specified. (Ta = 25°C)
Table 5 Operating range
Parameter
Symbol
Min.
Max.
Unit
High side floating supply offset voltage
VS
VDD -
VBS -1
500
V
High side floating supply offset voltage (VB vs. VDD, statically)
VBDD
-1.0
500
High side floating supply voltage (VB vs. VS, Note 1)
IGBT-Types
VBS
13
17.5
MOSFET-Types
10
17.5
High side output voltage (VHO vs. VS)
VHO
10
VBS
Low side output voltage (VLO vs. VGND)
VLO
0
VDD
Low side supply voltage
IGBT-Types
VDD
13
17.5
MOSFET-Types
10
17.5
Logic input voltages LIN,HIN (Note 2)
VIN
0
17.5
Pulse width for ON or OFF (Note 3)
IGBT-Types
tIN
0.8
–
µs
MOSFET-Types
0.3
–
Ambient temperature
Ta
-40
95
°C
Thermal coefficient DSO8
(junction to top, see section 6) DSO14
th(j-top)
–
–
8.0
6.0
K/W
Note 1 : Logic operational for VB (VB vs. VGND) > 7.0V
Note 2 : All input pins (HIN, LIN) are internally clamped (see abs. maximum ratings)
Note 3 : The input pulse may not be transmitted properly in case of input pulse width at LIN and HIN below 0.8µs (IGBT types) or 0.3 µs
(MOSFET) respectively
EiceDRIVER™ Compact
2EDL family
Final datasheet 15 <Revision 2.5>, 17.07.2014
4.4 Static logic function table
VDD
VBS
LO
HO
<VDDUV–
X
0
0
15V
<VBSUV–
LIN
0
15V
15V
0
0
15V
15V
0
0
15V
15V
LIN
HIN
all voltages with reference to GND
4.5 Static parameters
VDD = VBS = 15V unless otherwise specified. (Ta = 25°C)
Table 6 Static parameters
Parameter
Symbol
Values
Unit
Test
condition
Min.
Typ.
Max.
High level input voltage
VIH
1.7
2.1
2.4
V
Low level input voltage
VIL
0.7
0.9
1.1
High level output voltage LO
HO
VOH
–
–
VDD -0.45
VB -0.45
VDD -1
VB -1
IO = - 20 mA
Low level output voltage LO
HO
VOL
–
–
VGND+0.13
VS+0.13
VGND+0.3
VS +0.3
IO = 20 mA
VDD supply undervoltage
positive going threshold
IGBT-types
VDDUV+
11.8
12.5
13.2
MOSFET types
8.3
9.1
9.9
VBS supply undervoltage
positive going threshold
IGBT-types
VBSUV+
10.9
11.6
12.4
MOSFET types
8.3
9.1
9.9
VDD supply undervoltage
negative going threshold
IGBT-types
VDDUV–
10.9
11.6
12.4
MOSFET types
7.5
8.3
9
VBS supply undervoltage
negative going threshold
IGBT-types
VBSUV–
10
10.7
11.7
MOSFET types
7.5
8.3
9
VDD and VBS supply UVLO
hysteresis
IGBT-types
VDDUVH
VBSUVH
0.5
0.9
–
MOSFET types
0.5
0.9
–
High side leakage current betw. VS and
GND
ILVS+
–
1
12.5
µA
VS = 600V
High side leakage current betw. VS and
GND
ILVS+1
–
10
–
TJ = 125 °C,
VS = 600 V
Quiescent current VBS supply (VB only)
IQBS1
–
170
300
HO = low
depending on
current types
Quiescent current VBS supply (VB only)
IQBS2
–
170
300
HO = high
depending on
1
Not subject of production test, verified by characterisation
EiceDRIVER™ Compact
2EDL family
Final datasheet 16 <Revision 2.5>, 17.07.2014
Table 6 Static parameters
Parameter
Symbol
Values
Unit
Test
condition
Min.
Typ.
Max.
current types
Quiescent current VDD supply (VDD only)
IQDD1
–
0.3
0.6
mA
VLIN = float.
Quiescent current VDD supply (VDD only)
IQDD2
–
0.28
0.6
VLIN = 3.3 V,
VHIN=0
Quiescent current VDD supply (VDD only)
IQDD3
–
0.28
0.6
VLIN=0 ,
VHIN=3.3 V
Input bias current
ILIN+
15
35
60
µA
VLIN = 3.3 V
Input bias current
ILIN–
–
0
–
VLIN = 0
Input bias current
IHIN+
15
35
60
VHIN = 3.3 V
Input bias current
IHIN–
–
0
–
VHIN = 0
Mean output current for load capacity
charging in range from 3 V (20%) to 6 V
(40%)
IO+
0.18
0.23
–
A
CL = 22 nF
Peak output current turn on (single pulse)
IOpk+1
–
0.36
–
RL = 0 , tp
<10 µs
Mean output current for load capacity
discharging in range from 12 V (80%) to 9 V
(60%)
IO–
0.39
0.48
–
CL = 22 nF
Peak output current turn off (single pulse)
IOpk–1
–
0.70
–
RL = 0 , tp
<10 µs
Bootstrap diode forward voltage between
VDD and VB
VF,BSD
–
1.0
1.2
V
IF = 0.3 mA
Bootstrap diode forward current between
VDD and VB
IF,BSD
30
55
80
mA
VDD – VB = 4 V
Bootstrap diode resistance
RBSD
20
36
54
VF1 = 4 V, VF2
= 5 V
1
Not subject of production test, verified by characterisation
EiceDRIVER™ Compact
2EDL family
Final datasheet 17 <Revision 2.5>, 17.07.2014
4.6 Dynamic parameters
VDD = VBS = 15 V, VS = VGND, CL = 180 pF unless otherwise specified. (TA=25°C)
Table 7 Dynamic parameters
Parameter
Symbol
Values
Unit
Test
condition
Min.
Typ.
Max.
Turn-on propagation delay
IGBT types
ton
280
420
610
ns
VLIN/HIN = 0 or
3.3 V
MOSFET types
210
310
460
Turn-off propagation delay
IGBT types
toff
260
400
590
MOSFET types
200
300
440
Turn-on rise time
tr
–
48
80
VLIN/HIN = 0 or
3.3 V
CL = 1 nF
Turn-off fall time
tf
–
24
40
Input filter time at LIN/HIN
for turn on and off
IGBT types
tFILIN
120
192
–
VLIN/HIN = 0 &
3.3 V
MOSFET types
HIN
LIN
50
100
100
150
170
250
Dead time
(not for 2EDL05I06BF)
IGBT types
DT
260
380
540
ns
VLIN/HIN = 0 &
3.3 V
MOSFET types
30
75
140
Dead time matching
abs(DT_LH – DT_HL)
for single IC (not for
2EDL05I06BF)
IGBT types
MDT
–
10
80
ext. dead time
0ns
MOSFET types
10
50
Matching delay ON, abs(ton_HS - ton_LS)
MTON
–
10
60
external dead
time > 500 ns
Matching delay OFF, abs(toff_HS-toff_LS)
MTOFF
–
10
60
external dead
time >500 ns
Output pulse width
matching. PWin-PWout
IGBT types
PM
–
20
80
PWin > 1 µs
MOSFET types
–
20
70
EiceDRIVER™ Compact
2EDL family
Final datasheet 18 <Revision 2.5>, 17.07.2014
LIN1,2,3
HIN1,2,3
HO1,2,3
LO1,2,3 12 V
3V
3V
12V
1.65V 1.65V
DT DT
5 Timing diagrams
Figure 6 Timing of short pulse suppression
Figure 7 Timing of of internal deadtime
LIN
HIN
HO
LO
1.65V 1.65V
80%
20% 20%
80%
PWOUT
ton toff
trtf
PWIN
Figure 8 Input to output propagation delay times and switching times definition
HIN/LIN
HIN/LIN
HO/LO
HO/LO
low
tIN < tFILIN
tIN
tIN > tFILIN
tFILIN
tIN
HIN/LIN
HIN/LIN
HO/LO
HO/LO
high
tFILIN
tIN < tFILIN
tIN
tIN > tFILIN
tIN
EiceDRIVER™ Compact
2EDL family
Final datasheet 19 <Revision 2.5>, 17.07.2014
Figure 9 Operating areas (IGBT UVLO levels)
Figure 10 Operating areas (MOSFET UVLO levels)
HIN/LIN
HO/LO
PWIN
PWOUT
MTon
PM = PWIN - PWOUT
HIN/LIN PWIN
HO/LO
MToff
PM = PWIN - PWOUT
PWOUT
Figure 11 Output pulse width timing and matching delay timing diagram for positive logic
EiceDRIVER™ Compact
2EDL family
Final datasheet 20 <Revision 2.5>, 17.07.2014
6 Package
6.1 PG-DSO-8
Max. reflow solder temperature: 265°C acc. JEDEC
Max. wave solder temperature: 245°C acc. JEDEC
Figure 12 Package drawing
Figure 13 PCB reference layout
left: Reference layout
right: detail of footprint
The thermal coefficient is used to calculate the junction temperature, when the IC surface temperature is
measured. The junction temperature is
𝑇j=
Ψ
th(j-top) ∙ 𝑃𝑑+ 𝑇top
Table 8 Data of reference layout
Dimensions
Material
Metal (Copper)
76.2 114.3 1.5 mm³
FR4 (therm = 0.3 W/mK)
70µm (therm = 388 W/mK)
EiceDRIVER™ Compact
2EDL family
Final datasheet 21 <Revision 2.5>, 17.07.2014
6.2 PG-DSO-14
Max. reflow solder temperature: 265°C acc. JEDEC
Max. wave solder temperature: 245°C acc. JEDEC
Figure 14 Package drawing
Figure 15 PCB reference layout (according to JEDEC 1s0P)
left: Reference layout
right: detail of footprint
The thermal coefficient is used to calculate the junction temperature, when the IC surface temperature is
measured. The junction temperature is
𝑇j=
Ψ
th(j-top) ∙ 𝑃𝑑+ 𝑇top
Table 9 Data of reference layout
Dimensions
Material
Metal (Copper)
76.2 114.3 1.5 mm³
FR4 (therm = 0.3 W/mK)
70µm (therm = 388 W/mK)
w w w . i n f i n e o n . c o m
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