Revision History
2G DDR3L AS4C128M16D3LB-12BIN 96ball FBGA PACKAGE
Revision Details Date
Rev 1.0 Preliminary datasheet Dec. 2017
Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice
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128M x 16 bit DDR3L Synchronous DRAM (SDRAM)
Advance (Rev. 1.0, Dec. /2017)
Features
JEDEC Standard Compliant
Power supplies: VDD & VDDQ = +1.35V (1.283V ~ 1.45V)
Backward compatible to VDD & VDDQ = +1.5V ±0.075V
Operating temperature: TC = -40~95°C (Industrial)
Supports JEDEC clock jitter specification
Fully synchronous operation
Fast clock rate: 800MHz
Differential Clock, CK & CK#
Bidirectional differential data strobe
- DQS & DQS#
8 internal banks for concurrent operation
8n-bit prefetch architecture
Pipelined internal architecture
Precharge & active power down
Programmable Mode & Extended Mode registers
Additive Latency (AL): 0, CL-1, CL-2
Programmable Burst lengths: 4, 8
Burst type: Sequential / Interleave
Output Driver Impedance Control
Average refresh period
- 8192 cycles/64ms (7.8us at -40°C ≦ TC ≦ +85°C)
- 8192 cycles/32ms (3.9us at +85°C ≦ TC ≦ +95°C)
Write Leveling
ZQ Calibration
Dynamic ODT (Rtt_Nom & Rtt_WR)
RoHS compliant
Auto Refresh and Self Refresh
96-ball 9 x 13 x 1.2mm FBGA package
- Pb and Halogen Free
Overview
The 2Gb Double-Data-Rate-3L (DDR3L) DRAMs is
double data rate architecture to achieve high-speed
operation. It is internally configured as an eight bank
DRAM.
The 2Gb chip is organized as 16Mbit x 16 I/Os x 8 bank
devices. These synchronous devices achieve high speed
double-data-rate transfer rates of up to 1600 Mb/sec/pin
for general applications.
The chip is designed to comply with all key DDR3L
DRAM key features and all of the control and address
inputs are synchronized with a pair of externally supplied
differential clocks. Inputs are latched at the cross point
of differential clocks (CK rising and CK# falling). All I/Os
are synchronized with differential DQS pair in a source
synchronous fashion.
These devices operate with a single 1.35V -0.067V /
+0.1V power supply.
Table&1.&Ordering&Information&
Product part No Org Temperature Max Clock (MHz)
128M x 16 800
Package
96-ball FBGA
Table&2.&Speed&Grade&Information&
Speed Grade Clock Frequency CAS Latency tRCD (ns) tRP (ns)
DDR3L-1600 800 MHz 1113.75 13.75
Industrial -40°C to 95°C
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Figure 1. Ball Assignment (FBGA Top View)
…
A
B
C
D
E
1 2 3 7 8 9
VDDQ DQ13
VSSQ VDD
VDDQ DQ11
VSSQ VDDQ
VSS VSSQ
DQ15
VSS
DQ9
UDM
DQ0
DQ12 VDDQ
UDQS# DQ14
UDQS DQ10
DQ8 VSSQ
LDM VSSQ
VSS
VSSQ
VDDQ
VDD
VDDQ
FVDDQ DQ2 LDQS DQ1 DQ3 VSSQ
GVSSQ DQ6 LDQS# VDD VSS VSSQ
HVREFDQ VDDQ DQ4 DQ7 DQ5 VDDQ
JNC VSS RAS# CK VSS NC
KVDD CAS# CK# VDD CKE
LNC CS# WE# A10/AP ZQ
MBA0 BA2 NC VREFCA VSS
NVDD A3 A0 A12/BC # BA1
PA5 A2 A1 A4 VSS
RVDD A7 A9 A11 A6
ODT
VSS
VSS
VSS
TRESET# A13 NC A8 VSS
NC
VDD
VDD
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Figure 2. Block Diagram
CK#
CKE
CS#
RAS#
CAS#
WE#
DLL
CLOCK
BUFFER
COMMAND
DECODER
COLUMN
COUNTER
ADDRESS
BUFFER
A10/AP
A12/BC#
A0 A9
A11
A13
BA0
BA1
BA2
CK
LDQS
LDQS#
UDQS
UDQS#
DQ
Buffer
LDM
UDM
ODT
~
16M x 16
CELL ARRAY
(BANK #0)
Row
Decoder
Column Decoder
16M x 16
CELL ARRAY
(BANK #1)
Row
Decoder
Column Decoder
16M x 16
CELL ARRAY
(BANK #2)
Row
Decoder
Column Decoder
16M x 16
CELL ARRAY
(BANK #3)
Row
Decoder
Column Decoder
16M x 16
CELL ARRAY
(BANK #4)
Row
Decoder
Column Decoder
16M x 16
CELL ARRAY
(BANK #5)
Row
Decoder
Column Decoder
16M x 16
CELL ARRAY
(BANK #6)
Row
Decoder
Column Decoder
16M x 16
CELL ARRAY
(BANK #7)
Row
Decoder
Column Decoder
CONTROL
SIGNAL
GENERATOR
REFRESH
COUNTER
DATA
STROBE
BUFFER
MODE
REGISTER
ZQ
CAL
ZQCS
ZQCL
RESET#
VSSQ
RZQ
DQ15
DQ0
~
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Figure 3. State Diagram
This simplified State Diagram is intended to provide an overview of the possible state transitions and the
commands to control them. In particular, situations involving more than one bank, the enabling or disabling of on-die
termination, and some other events are not captured in full detail
SRE
SRX
PDX
PDX
READ
WRITE
PDE
PDE
ZQCL,ZQCS
Power
On
Automatic Sequence
Command Sequence
Power
applied Reset
Procedure Initialization
RESET
from any
state ZQCL
ZQ
Calibration Idle
Self
Refresh
Refreshing
MRS
REF
Active
Power
Down
Activating
Precharge
Power
Down
ACT
Bank
Activating
Writing Reading
Precharging
READ
READ
READ A
WRITE
WRITE
WRITE A
READ A
PRE, PREA
WRITE A
WRITE A
PRE, PREA
PRE, PREA
ACT = Active
PRE = Precharge
PREA = Precharge All
MRS = Mode Register Set
REF = Refresh
RESET = Start RESET Procedure
Read = RD, RDS4, RDS8
Read A = RDA, RDAS4, RDAS8
Write = WR, WRS4, WRS8
Write A = WRA, WRAS4, WRAS8
ZQCL = ZQ Calibration Long
ZQCS = ZQ Calibration Short
PDE = Enter Power-down
PDX = Exit Power-down
SRE = Self-Refresh entry
SRX = Self-Refresh exit
MPR = Multi-Purpose Register
Reading
MRS,MPR,
Write
Leveling
READ A
Writing
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Pad Descriptions
Table 3. Pad Details
Symbol
Type
Description
CK, CK#
Input
Differential Clock: CK and CK# are driven by the system clock. All SDRAM input signals
are sampled on the crossing of positive edge of CK and negative edge of CK#. Output
(Read) data is referenced to the crossings of CK and CK# (both directions of crossing).
CKE
Input
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CK signal. If CKE goes
LOW synchronously with clock, the internal clock is suspended from the next clock cycle
and the state of output and burst address is frozen as long as the CKE remains LOW.
When all banks are in the idle state, deactivating the clock controls the entry to the Power
Down and Self Refresh modes.
BA0-BA2
Input
Bank Address: BA0-BA2 define to which bank the BankActivate, Read, Write, or Bank
Precharge command is being applied.
A0-A13
Input
Address Inputs: Provide the row address (A0-13) for Active commands and the column
address (A0-9) for Read/Write commands to select one location out of the memory array
in the respective bank. (A10/AP and A12/BC# have additional functions). The address
inputs also provide the op-code during Mode Register Set commands.
A10/AP
Input
Auto-Precharge: A10 is sampled during Read/Write commands to determine whether
Autoprecharge should be performed to the accessed bank after the Read/Write operation.
(HIGH: Autoprecharge; LOW: no Autoprecharge). A10 is sampled during a Precharge
command to determine whether the Precharge applies to one bank (A10 LOW) or all
banks (A10 HIGH).
A12/BC#
Input
Burst Chop: A12/BC# is sampled during Read and Write commands to determine if burst
chop (on the fly) will be performed. (HIGH - no burst chop; LOW - burst chopped).
CS#
Input
Chip Select: CS# enables (sampled LOW) and disables (sampled HIGH) the command
decoder. All commands are masked when CS# is sampled HIGH. It is considered part of
the command code.
RAS#
Input
Row Address Strobe: The RAS# signal defines the operation commands in conjunction
with the CAS# and WE# signals and is latched at the crossing of positive edges of CK and
negative edge of CK#. When RAS# and CS# are asserted "LOW" and CAS# is asserted
"HIGH" either the BankActivate command or the Precharge command is selected by the
WE# signal. When the WE# is asserted "HIGH" the BankActivate command is selected
and the bank designated by BA is turned on to the active state. When the WE# is asserted
"LOW" the Precharge command is selected and the bank designated by BA is switched to
the idle state after the precharge operation.
CAS#
Input
Column Address Strobe: The CAS# signal defines the operation commands in
conjunction with the RAS# and WE# signals and is latched at the crossing of positive
edges of CK and negative edge of CK#. When RAS# is held "HIGH" and CS# is asserted
"LOW" the column access is started by asserting CAS# "LOW". Then, the Read or Write
command is selected by asserting WE# “HIGH" or “LOW".
WE#
Input
Write Enable: The WE# signal defines the operation commands in conjunction with the
RAS# and CAS# signals and is latched at the crossing of positive edges of CK and
negative edge of CK#. The WE# input is used to select the BankActivate or Precharge
command and Read or Write command.
LDQS,
LDQS#
UDQS
UDQS#
Input /
Output
Bidirectional Data Strobe: Specifies timing for Input and Output data. Read Data Strobe
is edge triggered. Write Data Strobe provides a setup and hold time for data and DQM.
LDQS is for DQ0~7, UDQS is for DQ8~15. The data strobes LDOS and UDQS are paired
with LDQS# and UDQS# to provide differential pair signaling to the system during both
reads and writes.
LDM, UDM
Input
Data Input Mask: Input data is masked when DM is sampled HIGH during a write cycle.
LDM masks DQ0-DQ7, UDM masks DQ8-DQ15.
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DQ0-DQ15
Input /
Output
Data I/O: The DQ0-DQ15 input and output data are synchronized with positive and
negative edges of DQS and DQS#. TheI/Os are byte-maskable during Writes.
ODT
Input
On Die Termination: ODT (registered HIGH) enables termination resistance internal to
the DDR3L SDRAM. When enabled, ODT is applied to each DQ, DQS, DQS#. The ODT
pin will be ignored if Mode-registers, MR1and MR2, are programmed to disable RTT.
RESET#
Input
Active Low Asynchronous Reset: Reset is active when RESET# is LOW, and inactive
when RESET# is HIGH. RESET# must be HIGH during normal operation. RESET# is a
CMOS rail to rail signal with DC high and low at 80% and 20% of VDD.
VDD
Supply
Power Supply: +1.35V -0.067V / +0.1V.
VSS
Supply
Ground
VDDQ
Supply
DQ Power: +1.35V -0.067V / +0.1V.
VSSQ
Supply
DQ Ground
VREFCA
Supply
Reference voltage for CA
VREFDQ
Supply
Reference voltage for DQ
ZQ
Supply
Reference pin for ZQ calibration.
NC
-
No Connect: These pins should be left unconnected.
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Operation Mode Truth Table
The following tables provide a quick reference of available DDR3L SDRAM commands, including CKE power-
down modes and bank-to-bank commands.
Table 4. Truth Table (Note (1), (2))
Command
State
CKEn-1(3)
CKEn
DM
BA0-2
A10/AP
A0-9, 11, 13
A12/BC#
CS#
RAS#
CAS#
WE#
BankActivate
Idle(4)
H
H
X
V
Row address
L
L
H
H
Single Bank Precharge
Any
H
H
X
V
L
V
V
L
L
H
L
All Banks Precharge
Any
H
H
X
V
H
V
V
L
L
H
L
Write (Fixed BL8 or BC4)
Active(4)
H
H
X
V
L
V
V
L
H
L
L
Write (BC4, on the fly)
Active(4)
H
H
X
V
L
V
L
L
H
L
L
Write (BL8, on the fly)
Active(4)
H
H
X
V
L
V
H
L
H
L
L
Write with Autoprecharge
(Fixed BL8 or BC4)
Active(4)
H
H
X
V
H
V
V
L
H
L
L
Write with Autoprecharge
(BC4, on the fly)
Active(4)
H
H
X
V
H
V
L
L
H
L
L
Write with Autoprecharge
(BL8, on the fly)
Active(4)
H
H
X
V
H
V
H
L
H
L
L
Read (Fixed BL8 or BC4)
Active(4)
H
H
X
V
L
V
V
L
H
L
H
Read (BC4, on the fly)
Active(4)
H
H
X
V
L
V
L
L
H
L
H
Read (BL8, on the fly)
Active(4)
H
H
X
V
L
V
H
L
H
L
H
Read with Autoprecharge
(Fixed BL8 or BC4)
Active(4)
H
H
X
V
H
V
V
L
H
L
H
Read with Autoprecharge
(BC4, on the fly)
Active(4)
H
H
X
V
H
V
L
L
H
L
H
Read with Autoprecharge
(BL8, on the fly)
Active(4)
H
H
X
V
H
V
H
L
H
L
H
(Extended) Mode Register Set
Idle
H
H
X
V
OP code
L
L
L
L
No-Operation
Any
H
H
X
V
V
V
V
L
H
H
H
Device Deselect
Any
H
H
X
X
X
X
X
H
X
X
X
Refresh
Idle
H
H
X
V
V
V
V
L
L
L
H
SelfRefresh Entry
Idle
H
L
X
V
V
V
V
L
L
L
H
SelfRefresh Exit
Idle
L
H
X
X
X
X
X
H
X
X
X
V
V
V
V
L
H
H
H
Power Down Mode Entry
Idle
H
L
X
X
X
X
X
H
X
X
X
V
V
V
V
L
H
H
H
Power Down Mode Exit
Any
L
H
X
X
X
X
X
H
X
X
X
V
V
V
V
L
H
H
H
Data Input Mask Disable
Active
H
X
L
X
X
X
X
X
X
X
X
Data Input Mask Enable(5)
Active
H
X
H
X
X
X
X
X
X
X
X
ZQ Calibration Long
Idle
H
H
X
X
H
X
X
L
H
H
L
ZQ Calibration Short
Idle
H
H
X
X
L
X
X
L
H
H
L
NOTE 1: V=Valid data, X=Don't Care, L=Low level, H=High level
NOTE 2: CKEn signal is input level when commands are provided.
NOTE 3: CKEn-1 signal is input level one clock cycle before the commands are provided.
NOTE 4: These are states of bank designated by BA signal.
NOTE 5: LDM and UDM can be enabled respectively.
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Functional Description
The DDR3L SDRAM is a high-speed dynamic random access memory internally configured as an eight-bank
DRAM. The DDR3L SDRAM uses an 8n prefetch architecture to achieve high speed operation. The 8n Prefetch
architecture is combined with an interface designed to transfer two data words per clock cycle at the I/O pins. A
single read or write operation for the DDR3L SDRAM consists of a single 8n-bit wide, four clock data transfer at the
internal DRAM core and two corresponding n-bit wide, one-half clock cycle data transfers at the I/O pins.
Read and write operation to the DDR3L SDRAM are burst oriented, start at a selected location, and continue for a
burst length of eight or a ‘chopped’ burst of four in a programmed sequence. Operation begins with the registration
of an Active command, which is then followed by a Read or Write command. The address bits registered coincident
with the Active command are used to select the bank and row to be activated (BA0-BA2 select the bank; A0-A13
select the row). The address bit registered coincident with the Read or Write command are used to select the
starting column location for the burst operation, determine if the auto precharge command is to be issued (via A10),
and select BC4 or BL8 mode ‘on the fly’ (via A12) if enabled in the mode register.
Prior to normal operation, the DDR3L SDRAM must be powered up and initialized in a predefined manner. The
following sections provide detailed information covering device reset and initialization, register definition, command
descriptions and device operation.
Figure 4. Reset and Initialization Sequence at Power-on Ramping
CK#
VDDQ
Tb Tc Td Te Tf Tg Th Ti TjTa
RESET#
CK
tCKSRX
Tk
T=200μs T=500μs
tDLLK
tXPR tMRD tMRD tMRD tMOD tZQinit
MRSNote 1 MRS MRS MRS ZQCL Note 1 VALID
MR3MR2 MR1 MR0 VALID
VALID
VDD
COMMAND
CKE
BA
ODT
RTT
Tmin=10ns tIS
tIS
tIS
tIS
Static LOW in case RTT_Nom is enabled at time Tg, otherwise static HIGH or LOW
Don't CareTIME BREAK
NOTE 1. From time point "Td" until "Tk " NOP or DES commands must be applied between MRS and ZQCL commands.
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Power-up and Initialization
The Following sequence is required for POWER UP and Initialization
1. Apply power (RESET# is recommended to be maintained below 0.2 x VDD, all other inputs may be undefined).
RESET# needs to be maintained for minimum 200us with stable power. CKE is pulled “Low” anytime before
RESET# being de-asserted (min. time 10ns). The power voltage ramp time between 300mV to VDDmin must be
no greater than 200ms; and during the ramp, VDD>VDDQ and (VDD-VDDQ) <0.3 Volts.
- VDD and VDDQ are driven from a single power converter output, AND
- The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to VDDQ and
VDD on one side and must be larger than or equal to VSSQ and VSS on the other side. In addition, VTT is
limited to 0.95V max once power ramp is finished, AND
- Vref tracks VDDQ/2.
OR
- Apply VDD without any slope reversal before or at the same time as VDDQ.
- Apply VDDQ without any slope reversal before or at the same time as VTT & Vref.
- The voltage levels on all pins other than VDD, VDDQ, VSS, VSSQ must be less than or equal to VDDQ and
VDD on one side and must be larger than or equal to VSSQ and VSS on the other side.
2. After RESET# is de-asserted, wait for another 500us until CKE become active. During this time, the DRAM will
start internal state initialization; this will be done independently of external clocks.
3. Clock (CK, CK#) need to be started and stabilized for at least 10ns or 5tCK (which is larger) before CKE goes
active. Since CKE is a synchronous signal, the corresponding set up time to clock (tIS) must be meeting. Also a
NOP or Deselect command must be registered (with tIS set up time to clock) before CKE goes active. Once the
CKE registered “High” after Reset, CKE needs to be continuously registered “High” until the initialization sequence
is finished, including expiration of tDLLK and tZQinit.
4. The DDR3L DRAM will keep its on-die termination in high impedance state as long as RESET# is asserted.
Further, the DRAM keeps its on-die termination in high impedance state after RESET# deassertion until CKE is
registered HIGH. The ODT input signal may be in undefined state until tIS before CKE is registered HIGH. When
CKE is registered HIGH, the ODT input signal may be statically held at either LOW or HIGH. If RTT_NOM is to be
enabled in MR1, the ODT input signal must be statically held LOW. In all cases, the ODT input signal remains
static until the power up initialization sequence is finished, including the expiration of tDLLK and tZQinit.
5. After CKE being registered high, wait minimum of Reset CKE Exit time, tXPR, before issuing the first MRS
command to load mode register.(tXPR=max (tXS, 5tCK))
6. Issue MRS command to load MR2 with all application settings. (To issue MRS command for MR2, provide “Low”
to BA0 and BA2, “High” to BA1)
7. Issue MRS Command to load MR3 with all application settings. (To issue MRS command for MR3, provide “Low”
to BA2, “High” to BA0 and BA1)
8. Issue MRS Command to load MR1 with all application settings and DLL enabled. (To issue “DLL Enable”
command, provide “Low” to A0, “High” to BA0 and “Low” to BA1 and BA2)
9. Issue MRS Command to load MR0 with all application settings and “DLL reset”. (To issue DLL reset command
provide “High” to A8 and “Low” to BA0-BA2)
10. Issue ZQCL command to starting ZQ calibration.
11. Wait for both tDLLK and tZQinit completed.
12. The DDR3L SDRAM is now ready for normal operation.
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Reset Procedure at Stable Power
The following sequence is required for RESET at no power interruption initialization.
1. Asserted RESET below 0.2*VDD anytime when reset is needed (all other inputs may be undefined). RESET
needs to be maintained for minimum 100ns. CKE is pulled “Low” before RESET being de-asserted (min. time
10ns).
2. Follow Power-up Initialization Sequence step 2 to 11.
3. The Reset sequence is now completed. DDR3L SDRAM is ready for normal operation.
Figure 5. Reset Procedure at Power Stable Condition
CK#
VDDQ
Tb Tc Td Te Tf Tg Th Ti TjTa
RESET#
CK
tCKSRX
Tk
T=100ns T=500μs
tDLLK
tXPR tMRD tMRD tMRD tMOD tZQinit
MRSNote 1 MRS MRS MRS ZQCL Note 1 VALID
MR3MR2 MR1 MR0 VALID
VALID
VDD
COMMAND
CKE
BA
ODT
RTT
tIS
tIS
tIS
tIS
Static LOW in case RTT_Nom is enabled at time Tg, otherwise static HIGH or LOW
Don't CareTIME BREAK
NOTE 1. From time point "Td" until "Tk" NOP or DES commands must be applied between MRS and ZQCL commands.
Tmin=10ns
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Register Definition
Programming the Mode Registers
For application flexibility, various functions, features, and modes are programmable in four Mode Registers,
provided by the DDR3L SDRAM, as user defined variables and they must be programmed via a Mode Register Set
(MRS) command. As the default values of the Mode Registers are not defined, contents of Mode Registers must be
fully initialized and/or re-initialized, i.e., written, after power up and/or reset for proper operation. Also the contents of
the Mode Registers can be altered by re-executing the MRS command during normal operation. When programming
the mode registers, even if the user chooses to modify only a sub-set of the MRS fields, all address fields within the
accessed mode register must be redefined when the MRS command is issued. MRS command and DLL Reset do
not affect array contents, which mean these commands can be executed any time after power-up without affecting
the array contents.
The mode register set command cycle time, tMRD is required to complete the write operation to the mode
register and is the minimum time required between two MRS commands shown in Figure of tMRD timing.
Figure 6. tMRD timing
T1 T2 Ta0 Ta1 Tb0 Tb1 Tb2 Tc0 Tc1T0 Tc2
VALID
tMRD
ODTLoff + 1
Don't CareTIME BREAK
VALIDVALID VALID MRS NOP/DES NOP/DES MRS NOP/DES NOP/DES VALID VALID
VALIDVALID VALID VALID VALID VALID VALID VALID VALID VALID VALID
Old Settings Updating Settings
VALIDVALID
VALIDVALID VALID VALID VALID VALID VALID VALID VALID VALID VALID
tMOD
New Settings
RTT_Nom ENABLED prior and/or after MRS command
RTT_Nom DISABLED prior and after MRS command
CK#
ADDRESS
CK
COMMAND
CKE
Settings
ODT
ODT
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The MRS command to Non-MRS command delay, tMOD, is require for the DRAM to update the features except
DLL reset, and is the minimum time required from an MRS command to a non-MRS command excluding NOP and
DES shown in Figure of tMOD timing.
Figure 7. tMOD timing
CK#
T1 T2 Ta0 Ta1 Ta2 Ta3 Ta4 Tb0 Tb1T0
ADDRESS
CK
Tb2
VALID
COMMAND
CKE
Settings
ODT
ODT
ODTLoff + 1
Don't CareTIME BREAK
VALIDVALID VALID MRS NOP/DES NOP/DES NOP/DES NOP/DES NOP/DES VALID VALID
VALIDVALID VALID VALID VALID VALID VALID VALID VALID VALID VALID
Old Settings Updating Settings
VALIDVALID
VALIDVALID VALID VALID VALID VALID VALID VALID VALID VALID VALID
tMOD
New Settings
RTT_Nom ENABLED prior and/or after MRS command
RTT_Nom DISABLED prior and after MRS command
The mode register contents can be changed using the same command and timing requirements during normal
operation as long as the DRAM is in idle state, i.e., all banks are in the precharged state with tRP satisfied, all data
bursts are completed and CKE is high prior to writing into the mode register. The mode registers are divided into
various fields depending on the functionality and/or modes.
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Mode Register MR0
The mode-register MR0 stores data for controlling various operating modes of DDR3L SDRAM. It controls burst
length, read burst type, CAS latency, test mode, DLL reset, WR, and DLL control for precharge Power-Down, which
include various vendor specific options to make DDR3L DRAM useful for various applications. The mode register is
written by asserting low on CS#, RAS#, CAS#, WE#, BA0, BA1, and BA2, while controlling the states of address pins
according to the following figure.
Table 5. Mode Register Bitmap
BA2
BA1
BA0
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Field
0*1
0
0
0*1
PPD
WR
DLL
TM
CAS Latency
RBT
CL
BL
Mode Register (0)
BA1
BA0
MRS mode
A7
Mode
A3
Read Burst Type
A1
A0
BL
0
0
MR0
0
Normal
0
Nibble Sequential
0
0
8 (Fixed)
0
1
MR1
1
Test
1
Interleave
0
1
BC4 or 8 (on the fly)
1
0
MR2
1
0
BC4 (Fixed)
1
1
MR3
1
1
Reserved
A11
A10
A9
WR (cycles) *2
A6
A5
A4
A2
CAS Latency
0
0
0
Reserved
0
0
1
5
0
0
0
0
Reserved
0
1
0
6
0
0
1
0
5
0
1
1
7
0
1
0
0
6
1
0
0
8
0
1
1
0
7
1
0
1
10
1
0
0
0
8
1
1
0
12
1
0
1
0
9
1
1
1
14
1
1
0
0
10
1
1
1
0
11
A12
DLL Control for Precharge PD
0
0
0
1
Reserved
0
Slow exit (DLL off)
0
0
1
1
Reserved
A8
DLL Reset
1
Fast exit (DLL on)
0
1
0
1
Reserved
0
No
0
1
1
1
Reserved
1
Yes
1
0
0
1
Reserved
1
0
1
1
Reserved
1
1
0
1
Reserved
1
1
1
1
Reserved
Note 1. Reserved for future use and must be set to 0 when programming the MR.
Note 2. WR (write recovery for autoprecharge) min in clock cycles is calculated by dividing tWR (ns) by tCK (ns) and rounding up to the
next integer WRmin [cycles] =Roundup (tWR / tCK). The value in the mode register must be programmed to be equal or larger
than WRmin. The programmed WR value is used with tRP to determine tDAL.
- CAS Latency
The CAS Latency is defined by MR0 (bit A2, A4~A6) as shown in the MR0 Definition figure. CAS Latency is the delay,
in clock cycles, between the internal Read command and the availability of the first bit of output data. DDR3L
SDRAM does not support any half clock latencies. The overall Read Latency (RL) is defined as Additive Latency (AL)
+ CAS Latency (CL); RL = AL + CL.
- Test Mode
The normal operating mode is selected by MR0 (bit7=0) and all other bits set to the desired values shown in the
MR0 definition figure. Programming bit A7 to a ‘1’ places the DDR3L SDRAM into a test mode that is only used by
the DRAM manufacturer and should not be used. No operations or functionality is guaranteed if A7=1.
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- Burst Length, Type, and Order
Accesses within a given burst may be programmed to sequential or interleaved order. The burst type is selected via
bit A3 as shown in the MR0 Definition as above figure. The ordering of access within a burst is determined by the
burst length, burst type, and the starting column address. The burst length is defined by bits A0-A1. Burst lengths
options include fix BC4, fixed BL8, and on the fly which allow BC4 or BL8 to be selected coincident with the
registration of a Read or Write command via A12/BC#
Table 6. Burst Type and Burst Order
Burst Length
Read
Write
Starting Column
Address
Sequential
A3=0
Interleave
A3=1
Note
A2
A1
A0
4
Chop
Read
0
0
0
0, 1, 2, 3, T, T, T, T
0, 1, 2, 3, T, T, T, T
1, 2, 3
0
0
1
1, 2, 3, 0, T, T, T, T
1, 0, 3, 2, T, T, T, T
0
1
0
2, 3, 0, 1, T, T, T, T
2, 3, 0, 1, T, T, T, T
0
1
1
3, 0, 1, 2, T, T, T, T
3, 2, 1, 0, T, T, T, T
1
0
0
4, 5, 6, 7, T, T, T, T
4, 5, 6, 7, T, T, T, T
1
0
1
5, 6, 7, 4, T, T, T, T
5, 4, 7, 6, T, T, T, T
1
1
0
6, 7, 4, 5, T, T, T, T
6, 7, 4, 5, T, T, T, T
1
1
1
7, 4, 5, 6, T, T, T, T
7, 6, 5, 4, T, T, T, T
Write
0
V
V
0, 1, 2, 3, X, X, X, X
0, 1, 2, 3, X, X, X, X
1, 2, 4, 5
1
V
V
4, 5, 6, 7, X, X, X, X
4, 5, 6, 7, X, X, X, X
8
Read
0
0
0
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
2
0
0
1
1, 2, 3, 0, 5, 6, 7, 4
1, 0, 3, 2, 5, 4, 7, 6
0
1
0
2, 3, 0, 1, 6, 7, 4, 5
2, 3, 0, 1, 6, 7, 4, 5
0
1
1
3, 0, 1, 2, 7, 4, 5, 6
3, 2, 1, 0, 7, 6, 5, 4
1
0
0
4, 5, 6, 7, 0, 1, 2, 3
4, 5, 6, 7, 0, 1, 2, 3
1
0
1
5, 6, 7, 4, 1, 2, 3, 0
5, 4, 7, 6, 1, 0, 3, 2
1
1
0
6, 7, 4, 5, 2, 3, 0, 1
6, 7, 4, 5, 2, 3, 0, 1
1
1
1
7, 4, 5, 6, 3, 0, 1, 2
7, 6, 5, 4, 3, 2, 1, 0
Write
V
V
V
0, 1, 2, 3, 4, 5, 6, 7
0, 1, 2, 3, 4, 5, 6, 7
2, 4
Note 1. In case of burst length being fixed to 4 by MR0 setting, the internal write operation starts two clock cycles earlier than for the
BL8 mode. This means that the starting point for tWR and tWTR will be pulled in by two clocks. In case of burst length being
selected on-the-fly via A12/BC#, the internal write operation starts at the same point in time like a burst of 8 write operation. This
means that during on-the-fly control, the starting point for tWR and tWTR will not be pulled in by two clocks.
Note 2. 0~7 bit number is value of CA[2:0] that causes this bit to be the first read during a burst.
Note 3. T: Output driver for data and strobes are in high impedance.
Note 4. V: a valid logic level (0 or 1), but respective buffer input ignores level on input pins.
Note 5. X: Don’t Care.
- DLL Reset
The DLL Reset bit is self-clearing, meaning it returns back to the value of ‘0’ after the DLL reset function has been
issued. Once the DLL is enabled, a subsequent DLL Reset should be applied. Anytime the DLL reset function is
used, tDLLK must be met before any functions that require the DLL can be used (i.e. Read commands or ODT
synchronous operations.)
- Write Recovery
The programmed WR value MR0 (bits A9, A10, and A11) is used for the auto precharge feature along with tRP to
determine tDAL. WR (write recovery for auto-precharge) min in clock cycles is calculated by dividing tWR (ns) by
tCK (ns) and rounding up to the next integer: WR min [cycles] = Roundup (tWR [ns]/tCK [ns]). The WR must be
programmed to be equal or larger than tWR (min).
- Precharge PD DLL
MR0 (bit A12) is used to select the DLL usage during precharge power-down mode. When MR0 (A12=0), or ‘slow-
exit’, the DLL is frozen after entering precharge power-down (for potential power savings) and upon exit requires
tXPDLL to be met prior to the next valid command. When MR0 (A12=1), or ‘fast-exit’, the DLL is maintained after
entering precharge power-down and upon exiting power-down requires tXP to be met prior to the next valid
command.
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Mode Register MR1
The Mode Register MR1 stores the data for enabling or disabling the DLL, output strength, Rtt_Nom impedance,
additive latency, WRITE leveling enable and Qoff. The Mode Register 1 is written by asserting low on CS#, RAS#,
CAS#, WE#, high on BA0 and low on BA1 and BA2, while controlling the states of address pins according to the
following figure.
Table 7. Extended Mode Register EMR (1) Bitmap
BA2
BA1
BA0
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Field
0*1
0
1
0*1
Qoff
0*1
0*1
Rtt
0*1
Level
Rtt
D.I.C
AL
Rtt
D.I.C
DLL
Mode Register (1)
BA1
BA0
MRS mode
A4
A3
Additive Latency
A0
DLL Enable
0
0
MR0
0
0
0 (AL disabled)
0
Enable
0
1
MR1
0
1
CL – 1
1
Disable
1
0
MR2
1
0
CL – 2
1
1
MR3
1
1
Reserved
A12
Qoff *2
A9
A6
A2
Rtt_Nom *3
0
Output buffer enabled
1
Output buffer disabled
0
0
0
Rtt_Nom disabled
0
0
1
RZQ/4
A7
Write leveling enable
0
1
0
RZQ/2
0
Disabled
0
1
1
RZQ/6
1
Enabled
1
0
0
RZQ/12 *4
Note: RZQ = 240 Ω
1
0
1
RZQ/8 *4
A5
A1
Output Driver Impedance Control
1
1
0
Reserved
0
0
RZQ/6
1
1
1
Reserved
0
1
RZQ/7
Note: RZQ = 240 Ω
1
0
Reserved
1
1
Reserved
Note 1. Reserved for future use and must be set to 0 when programming the MR.
Note 2. Outputs disabled - DQs, DQSs, DQS#s.
Note 3. In Write leveling Mode (MR1 [bit7] = 1) with MR1 [bit12] =1, all RTT_Nom settings are allowed; in Write Leveling Mode
(MR1 [bit7] = 1) with MR1 [bit12]=0, only RTT_Nom settings of RZQ/2, RZQ/4 and RZQ/6 are allowed.
Note 4. If RTT_Nom is used during Writes, only the values RZQ/2, RZQ/4 and RZQ/6 are allowed.
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- DLL Enable/Disable
The DLL must be enabled for normal operation. DLL enable is required during power up initialization, and upon
returning to normal operation after having the DLL disabled. During normal operation (DLL-on) with MR1 (A0=0), the
DLL is automatically disabled when entering Self-Refresh operation and is automatically re-enable upon exit of Self-
Refresh operation. Any time the DLL is enabled and subsequently reset, tDLLK clock cycles must occur before a
Read or synchronous ODT command can be issued to allow time for the internal clock to be synchronized with the
external clock. Failing to wait for synchronization to occur may result in a violation of the tDQSCK, tAON, or tAOF
parameters. During tDLLK, CKE must continuously be registered high. DDR3L SDRAM does not require DLL for any
Write operation, expect when RTT_WR is enabled and the DLL is required for proper ODT operation. For more
detailed information on DLL Disable operation are described in DLL-off Mode. The direct ODT feature is not
supported during DLL-off mode. The on-die termination resistors must be disabled by continuously registering the
ODT pin low and/or by programming the RTT_Nom bits MR1{A9,A6,A2} to {0,0,0} via a mode register set command
during DLL-off mode.
The dynamic ODT feature is not supported at DLL-off mode. User must use MRS command to set Rtt_WR, MR2
{A10, A9} = {0, 0}, to disable Dynamic ODT externally
- Output Driver Impedance Control
The output driver impedance of the DDR3L SDRAM device is selected by MR1 (bit A1 and A5) as shown in MR1
definition figure.
- ODT Rtt Values
DDR3L SDRAM is capable of providing two different termination values (Rtt_Nom and Rtt_WR). The nominal
termination value Rtt_Nom is programmable in MR1. A separate value (Rtt_WR) may be programmable in MR2 to
enable a unique Rtt value when ODT is enabled during writes. The Rtt_WR value can be applied during writes even
when Rtt_Nom is disabled.
- Additive Latency (AL)
Additive Latency (AL) operation is supported to make command and data bus efficient for sustainable bandwidth in
DDR3L SDRAM. In this operation, the DDR3L SDRAM allows a read or write command (either with or without auto-
precharge) to be issued immediately after the active command. The command is held for the time of the Additive
Latency (AL) before it is issued inside the device. The Read Latency (RL) is controlled by the sum of the AL and
CAS Latency (CL) register settings. Write Latency (WL) is controlled by the sum of the AL and CAS Write Latency
(CWL) register settings. A summary of the AL register options are shown in MR.
- Write leveling
For better signal integrity, DDR3L memory module adopted fly-by topology for the commands, addresses, control
signals, and clocks. The fly-by topology has benefits from reducing number of stubs and their length but in other
aspect, causes flight time skew between clock and strobe at every DRAM on DIMM. It makes difficult for the
Controller to maintain tDQSS, tDSS, and tDSH specification. Therefore, the controller should support ‘write leveling’
in DDR3L SDRAM to compensate for skew.
- Output Disable
The DDR3L SDRAM outputs maybe enable/disabled by MR1 (bit 12) as shown in MR1 definition. When this feature
is enabled (A12=1) all output pins (DQs, DQS, DQS#, etc.) are disconnected from the device removing any loading
of the output drivers. This feature may be useful when measuring modules power for example. For normal operation
A12 should be set to ‘0’.
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Mode Register MR2
The Mode Register MR2 stores the data for controlling refresh related features, Rtt_WR impedance, and CAS write
latency. The Mode Register 2 is written by asserting low on CS#, RAS#, CAS#, WE#, high on BA1 and low on BA0
and BA2, while controlling the states of address pins according to the table below.
Table 8. Extended Mode Register EMR (2) Bitmap
BA2
BA1
BA0
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Field
0*1
1
0
0*1
Rtt_WR
0*1
SRT
0*1
CWL
PASR
Mode Register (2)
BA1
BA0
MRS mode
A2
A1
A0
Partial Array Self-Refresh (Optional)
0
0
MR0
0
0
0
Full Array
0
1
MR1
0
0
1
Half Array (BA[2:0]=000,001,010,&011)
1
0
MR2
0
1
0
Quarter Array (BA[2:0]=000,&001)
1
1
MR3
0
1
1
1/8th Array (BA[2:0]=000)
1
0
0
3/4 Array (BA[2:0]=010,011,100.101,110,&111)
1
0
1
Half Array (BA[2:0]=100,101,110,&111)
A10
A9
RTT_WR *2
1
1
0
Quarter Array (BA[2:0]=110,&111)
0
0
Dynamic ODT off (Write does not affect Rtt value)
1
1
1
1/8th Array (BA[2:0]=111)
0
1
RZQ/4
1
0
RZQ/2
A5
A4
A3
CAS write Latency (CWL)
1
1
Reserved
0
0
0
5 (tCK(avg)≧2.5ns)
0
0
1
6 (2.5ns＞tCK(avg)≧1.875ns)
0
1
0
7 (1.875ns＞tCK(avg)≧1.5ns)
A7
Self-Refresh Temperature (SRT) Range
0
1
1
8 (1.5ns＞tCK(avg)≧1.25ns)
0
Normal operating temperature range
1
0
0
Reserved
1
Extended (optional) operating temperature range
1
0
1
Reserved
1
1
0
Reserved
1
1
1
Reserved
Note 1. BA2, A6, A8 and A11~ A13 are RFU and must be programmed to 0 during MRS.
Note 2. The Rtt_WR value can be applied during writes even when Rtt_Nom is disabled.
During write leveling, Dynamic ODT is not available.
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- Partial Array Self-Refresh (PASR)
If PASR (Partial Array Self-Refresh) is enabled, data located in areas of the array beyond the specified address
range will be lost if Self-Refresh is entered. Data integrity will be maintained if tREFI conditions are met and no Self-
Refresh command is issued.
- CAS Write Latency (CWL)
The CAS Write Latency is defined by MR2 (bits A3-A5) shown in MR2. CAS Write Latency is the delay, in clock
cycles, between the internal Write command and the availability of the first bit of input data. DDR3L DRAM does not
support any half clock latencies. The overall Write Latency (WL) is defined as Additive Latency (AL) + CAS Write
Latency (CWL); WL=AL+CWL.
For more information on the supported CWL and AL settings based on the operating clock frequency, refer to
“Standard Speed Bins”. For detailed Write operation refer to “WRITE Operation”.
- Dynamic ODT (Rtt_WR)
DDR3L SDRAM introduces a new feature “Dynamic ODT”. In certain application cases and to further enhance signal
integrity on the data bus, it is desirable that the termination strength of the DDR3L SDRAM can be changed without
issuing an MRS command. MR2 Register locations A9 and A10 configure the Dynamic ODT settings.
DDR3L SDRAM introduces a new feature “Dynamic ODT”. In certain application cases and to further enhance signal
integrity on the data bus, it is desirable that the termination strength of the DDR3L SDRAM can be changed without
issuing an MRS command. MR2 Register locations A9 and A10 configure the Dynamic ODT settings. In Write
leveling mode, only RTT_Nom is available. For details on Dynamic ODT operation, refer to “Dynamic ODT”.
- Self-Refresh Temperature (SRT)
Mode register MR2[7] is used to disable/enable the SRT function. When SRT is disabled, the self refresh mode’s
refresh rate is assumed to be at the normal 85°C limit (sometimes referred to as 1x refresh rate). In the disabled
mode, SRT requires the user to ensure the DRAM never exceeds a TC of 85°C while in self refresh mode.
When SRT is enabled, the DRAM self refresh is changed internally from 1x to 2x, regardless of the case
temperature. This enables the user to operate the DRAM beyond the standard 85°C limit up to the optional extended
temperature range of 95°C while in self refresh mode. The standard self refresh current test specifies test conditions
to normal case temperature (85°C) only, meaning if SRT is enabled, the standard self refresh current specifications
do not apply (see Extended Temperature Usage).
Extended Temperature Usage
DDR3 SDRAM supports the optional extended case temperature (TC) range of 0°C to 95°C. The extended
temperature range DRAM must be refreshed externally at 2x (double refresh) anytime the case temperature is
above 85°C (and does not exceed 95°C). The external refresh requirement is accomplished by reducing the refresh
period from 64ms to 32ms. Thus, SRT must be enabled when TC is above 85°C or self refresh cannot be used until
TC is at or below 85°C.
Table 9. Self-Refresh mode summary
MR2
A[7]
Self-Refresh operation
Allowed Operating Temperature
Range for Self-Refresh mode
0
Self-Refresh rate appropriate for the Normal Temperature Range
Normal (0 ~ 85C)
1
Self-Refresh appropriate for either the Normal or Extended Temperature
Ranges.The DRAM must support Extended Temperature Range. The
value of the SRT bit can effect self-refresh power consumption, please
refer to the IDD table for details.
Normal and Extended
(0 ~ 95C)
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Mode Register MR3
The Mode Register MR3 controls Multi-purpose registers. The Mode Register 3 is written by asserting low on CS#,
RAS#, CAS#, WE#, high on BA1 and BA0, and low on BA2 while controlling the states of address pins according to
the table below
Table 10. Extended Mode Register EMR (3) Bitmap
BA2
BA1
BA0
A13
A12
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
Address Field
0*1
1
1
0*1
MPR
MPR Loc
Mode Register (3)
BA1
BA0
MRS mode
A2
MPR
A1
A0
MPR location
0
0
MR0
0
Normal operation *3
0
0
Predefined pattern *2
0
1
MR1
1
Dataflow from MPR
0
1
RFU
1
0
MR2
1
0
RFU
1
1
MR3
1
1
RFU
Note 1. BA2, A3 - A13 are RFU and must be programmed to 0 during MRS.
Note 2. The predefined pattern will be used for read synchronization.
Note 3. When MPR control is set for normal operation (MR3 A[2] = 0) then MR3 A[1:0] will be ignored.
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Table 11. Absolute Maximum DC Ratings
Symbol
Parameter
Values
Unit
Note
VDD
Voltage on VDD pin relative to Vss
-0.4 ~ 1.8
V
1,3
VDDQ
Voltage on VDDQ pin relative to Vss
-0.4 ~ 1.8
V
1,3
VIN, VOUT
Voltage on any pin relative to Vss
-0.4 ~ 1.8
V
1
TSTG
Storage temperature
-55 ~ 100
°C
1,2
Note 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.This
is a stress rating only and functional operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect reliability.
Note 2. Storage Temperature is the case surface temperature on the center/top side of the DRAM.
Note 3. VDD and VDDQ must be within 300mV of each other at all times; and Vref must be not greater than 0.6VDDQ, when
VDD and VDDQ are less than 500mV; Vref may be equal to or less than 300mV.
Table 12. Temperature Range
Symbol
Parameter
Values
Unit
Note
TOPER
Operating Temperature Range
-40 ~ 95
°C
1-4
Note 1. Operating temperature is the case surface temperature on center/top of the DRAM.
Note 2. The operating temperature range is the temperature where all DRAM specification will be supported. Outside of this
temperature range, even if it is still within the limit of stress condition, some deviation on portion of operating
specification may be required. During operation, the DRAM case temperature must be maintained between 0-85°C
under all other specification parameter. Supporting 0 - 85 °C with full JEDEC AC & DC specifications.
Note 3. Some applications require operation of the DRAM in the Extended Temperature Range between 85 °C and 95 °C case
temperature. Full specifications are guaranteed in this range, but the following additional apply.
a. Refresh commands must be doubled in frequency, therefore, reducing the Refresh interval tREFI to 3.9us. It is also
possible to specify a component with 1x refresh (tREFI to 7.8us) in the Extended Temperature Range.
b. Supporting extended temperature Self-Refresh entry via the control of MR2 bit A7.
Note 4. During Industrial Temperature Operation Range, the DRAM case temperature must be maintained between -40°C ~
95°C under all operating Conditions.
Table 13. Recommended DC Operating Conditions
Symbol
Parameter
Min.
Typ.
Max.
Unit
Note
VDD
Power supply voltage
1.283
1.35
1.45
V
1,2
VDDQ
Power supply voltage for output
1.283
1.35
1.45
V
1,2
Note 1. Under all conditions VDDQ must be less than or equal to VDD.
Note 2. VDDQ tracks with VDD. AC parameters are measured with VDD and VDDQ tied together.
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Table 14. Single-Ended AC and DC Input Levels for Command and Address
Symbol
Parameter
DDR3L-1600
Unit
Note
Min.
Max.
VIH.CA(DC90)
DC input logic high
VREF+0.9
VDD
V
1,5
VIL.CA(DC90)
DC input logic low
VSS
VREF-0.9
V
1,6
VIH.CA(AC160)
AC input logic high
VREF+0.16
-
V
1,2
VIL.CA(AC160)
AC input logic low
-
VREF-0.16
V
1,2
VIH.CA(AC135)
AC input logic high
VREF+0.135
-
V
1,2
VIL.CA(AC135)
AC input logic low
-
VREF-0.135
V
1,2
VRefCA(DC)
Reference Voltage for ADD, CMD inputs
0.49xVDD
0.51xVDD
V
3,4
Note 1. For input only pins except RESET#. Vref = VrefCA(DC).
Note 2. See “Overshoot and Undershoot Specifications”.
Note 3. The ac peak noise on VRef may not allow VRef to deviate from VRefCA(DC) by more than ±1% VDD.
Note 4. For reference: approx. VDD/2 ±13.5 mV.
Note 5. VIH(dc) is used as a simplified symbol for VIH.CA(DC90)
Note 6. VIL(dc) is used as a simplified symbol for VIL.CA(DC90)
Note 7. VIH(ac) is used as a simplified symbol for VIH.CA(AC160), VIH.CA(AC135) and VIH.CA(AC160) value is used when
Vref + 0.160V is referenced, VIH.CA(AC135) value is used when Vref + 0.135V is referenced.
Note 8. VIL(ac) is used as a simplified symbol for VIL.CA(AC160), VIL.CA(AC135) and VIL.CA(AC160) value is used when Vref
- 0.160V is referenced, VIL.CA(AC135) value is used when Vref - 0.135V is referenced.
Table 15. Single-Ended AC and DC Input Levels for DQ and DM
Symbol
Parameter
DDR3L-1600
Unit
Note
Min.
Max.
VIH.DQ(DC90)
DC input logic high
VREF+0.9
VDD
V
1,5
VIL.DQ(DC90)
DC input logic low
VSS
VREF-0.9
V
1,6
VIH.DQ(AC135)
AC input logic high
VREF+0.135
-
V
1,2
VIL.DQ(AC135)
AC input logic low
-
VREF-0.135
V
1,2
VRefDQ(DC)
Reference Voltage for DQ, DM inputs
0.49xVDD
0.51xVDD
V
3,4
Note 1. Vref = VrefDQ(DC).
Note 2. See “Overshoot and Undershoot Specifications”.
Note 3. The ac peak noise on VRef may not allow VRef to deviate from VRefDQ(DC) by more than ±1% VDD.
Note 4. For reference: approx. VDD/2 ±13.5 mV.
Note 5. VIH(dc) is used as a simplified symbol for VIH.DQ(DC90)
Note 6. VIL(dc) is used as a simplified symbol for VIL.DQ(DC90)
Note 7. VIH(ac) is used as a simplified symbol for VIH.DQ(AC135) and VIH.DQ(AC135) value is used when Vref + 0.135V is
referenced.
Note 8. VIL(ac) is used as a simplified symbol for VIL.DQ(AC135) and VIL.DQ(AC135) value is used when Vref - 0.135V is
referenced.
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Table 16. Differential AC and DC Input Levels
Symbol
Parameter
Values
Unit
Note
Min.
Max.
VIHdiff
Differential input high
+ 0.18
Note 3
V
1
VILdiff
Differential input logic low
Note 3
-0.18
V
1
VIHdiff(ac)
Differential input high ac
2 x (VIH(ac) - VREF)
Notes 3
V
2
VILdiff(ac)
Differential input low ac
Note 3
2 x (VIL(ac) - VREF)
V
2
Note 1. Used to define a differential signal slew-rate.
Note 2. For CK - CK# use VIH/VIL(ac) of ADD/CMD and VREFCA; for DQSL, DQSL#, DQSU, DQSU# use VIH/VIL(ac) of DQs
and VREFDQ; if a reduced ac-high or ac-low level is used for a signal group, then the reduced level applies also here.
Note 3. These values are not defined; however, the single-ended signals CK, CK#, DQSL, DQSL#, DQSU, DQSU# need to be
within the respective limits (VIH(dc) max, VIL(dc)min) for single-ended signals as well as the limitations for overshoot
and undershoot.
Note 1. Although the DM pins have different functions, the loading matches DQ and DQS.
Note 2. This parameter is not subject to production test. It is verified by design and characterization. VDD=VDDQ=1.35V,
VBIAS=VDD/2 and ondie termination off.
Note 3. This parameter applies to monolithic devices only; stacked/dual-die devices are not covered here.
Note 4. Absolute value of CCK-CCK#.
Note 5. Absolute value of CIO(DQS)-CIO(DQS#).
Note 6. CI applies to ODT, CS#, CKE, A0-A13, BA0-BA2, RAS#, CAS#, WE#.
Note 7. CDI_CTRL applies to ODT, CS# and CKE.
Note 8. CDI_CTRL=CI(CTRL)-0.5*(CI(CK)+CI(CK#)).
Note 9. CDI_ADD_CMD applies to A0-A13, BA0-BA2, RAS#, CAS# and WE#.
Note 10. CDI_ADD_CMD=CI(ADD_CMD) - 0.5*(CI(CK)+CI(CK#)).
Note 11. CDIO=CIO(DQ,DM) - 0.5*(CIO(DQS)+CIO(DQS#)).
Note 12. Maximum external load capacitance on ZQ pin: 5 pF.
!
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Table 17. Capacitance (VDD = 1.35V, TOPER = 25 C)
Symbol Parameter DDR3L-1600 Unit
Min. Max.
CIO Input/output capacitance,
(DQ, DM, DQS, DQS#) 1.4 2.2 pF 1, 2, 3
CCK Input capacitance, CK and CK# 0.8 1.4 pF 2, 3
CDCK Input capacitance delta,
CK and CK# 0 0.15 pF 2, 3, 4
CDDQS Input/output capacitance delta,
DQS and DQS# 0 0.15 pF 2, 3, 5
CI Input capacitance,
(CTRL, ADD, CMD input-only pins) 0.75 1.2 pF 2, 3, 6
CDI_CTRL Input capacitance delta,
(All CTRL input-only pins) -0.4 0.2 pF 2, 3,
7, 8
CDI_ADD_CMD Input capacitance delta,
(All ADD, CMD input-only pins) -0.4 0.4 pF 2, 3,
9, 10
CDIO Input/output capacitance delta,
(DQ, DM, DQS, DQS#) -0.5 0.3 pF 2, 3,
11
CZQ Input/output capacitance of ZQ pin - 3 pF 2, 3,
12
Note
Table 18. IDD specification parameters and test conditions (VDD = 1.35V, TOPER = -40~95 C)
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Parameter & Test Condition Symbol -12 Unit
Max.
Operating One Bank Active-Precharge Current
CKE: High; External clock: On; BL: 8*1; AL: 0; CS#: High between ACT and
PRE; Command, Address, Bank Address Inputs: partially toggling; Data IO:
MID-LEVEL; DM:stable at 0; Bank Activity: Cycling with one bank active at a
time: 0,0,1,1,2,2,...;Output Buffer and RTT: Enabled in Mode Registers*2;
ODT Signal: stable at 0.
IDD0 75 mA
Operating One Bank Active-Read-Precharge Current
CKE: High; External clock: On; BL: 8*1, 5; AL:0; CS#: High between ACT, RD
and PRE; Command, Address, Bank Address Inputs, Data IO: partially
toggling; DM:stable at 0; Bank Activity: Cycling with one bank active at a
time: 0,0,1,1,2,2,...; Output Buffer and RTT: Enabled in Mode Registers*2;
ODT Signal: stable at 0.
IDD1 96 mA
Precharge Standby Current
CKE: High; External clock: On; BL: 8*1; AL: 0; CS#: stable at 1; Command,
Address, Bank Address Inputs: partially toggling; Data IO: MID-LEVEL;
DM:stable at 0; Bank Activity: all banks closed; Output Buffer and RTT:
Enabled in Mode Registers*2; ODT Signal: stable at 0.
IDD2N 45 mA
Precharge Power-Down Current Slow Exit
CKE: Low; External clock: On; BL: 8*1; AL: 0; CS#: stable at 1; Command,
Address, Bank Address Inputs: stable at 0; Data IO: MID-LEVEL; DM:stable
at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in
Mode Registers*2; ODT Signal: stable at 0; Pecharge Power Down Mode:
Slow Exit.*3
IDD2P0 12 mA
Precharge Power-Down Current Fast Exit
CKE: Low; External clock: On; BL: 8*1; AL: 0; CS#: stable at 1; Command,
Address, Bank Address Inputs: stable at 0; Data IO: MID-LEVEL; DM:stable
at 0; Bank Activity: all banks closed; Output Buffer and RTT: Enabled in
Mode Registers*2; ODT Signal: stable at 0; Pecharge Power Down Mode:
Fast Exit.*3
IDD2P1 12 mA
Precharge Quiet Standby Current
CKE: High; External clock: On; BL: 8*1; AL: 0; CS#: stable at 1; Command,
Address, Bank Address Inputs: stable at 0; Data IO: MID-LEVEL; DM:stable
at 0;Bank Activity: all banks closed; Output Buffer and RTT: Enabled in
Mode Registers*2; ODT Signal: stable at 0.
IDD2Q 45 mA
Active Standby Current
CKE: High; External clock: On; BL: 8*1; AL: 0; CS#: stable at 1; Command,
Address, Bank Address Inputs: partially toggling; Data IO: MID-LEVEL;
DM:stable at 0;Bank Activity: all banks open; Output Buffer and RTT:
Enabled in Mode Registers*2; ODT Signal: stable at 0.
IDD3N 52 mA
Active Power-Down Current
CKE: Low; External clock: On; BL: 8*1; AL: 0; CS#: stable at 1; Command,
Address, Bank Address Inputs: stable at 0; Data IO: MID-LEVEL;DM:stable
at 0; Bank Activity: all banks open; Output Buffer and RTT: Enabled in
Mode Registers*2; ODT Signal: stable at 0
IDD3P 20 mA
Operating Burst Read Current
CKE: High; External clock: On; BL: 8*1, 5; AL: 0; CS#: High between RD;
Command, Address, Bank Address Inputs: partially toggling; DM:stable at
0; Bank Activity: all banks open, RD commands cycling through banks:
0,0,1,1,2,2,...; tput Buffer and RTT: Enabled in Mode Registers*2; ODT
Signal: stable at 0.
IDD4R 188 mA
Operating Burst Write Current
CKE: High; External clock: On; BL: 8*1; AL: 0; CS#: High between WR;
Command, Address, Bank Address Inputs: partially toggling; DM: stable at
0; Bank Activity: all banks open. Output Buffer and RTT: Enabled in Mode
Registers*2; ODT Signal: stable at HIGH.
IDD4W 189 mA
Note 1. Burst Length: BL8 fixed by MRS: set MR0 A[1,0]=00B.
Note 2. Output Buffer Enable: set MR1 A[12] = 0B; set MR1 A[5,1] = 01B; RTT_Nom enable: set MR1 A[9,6,2] = 011B; RTT_Wr
enable: set MR2 A[10,9] = 10B.
Note 3. Pecharge Power Down Mode: set MR0 A12=0B for Slow Exit or MR0 A12=1B for Fast Exit.
Note 4. Self-Refresh Temperature Range (SRT): set MR2 A7=0B for normal or 1B for extended temperature range.
Note 5. Read Burst Type: Nibble Sequential, set MR0 A[3] = 0B.
Note 6. Supporting 0 - 85 °C with full JEDEC AC & DC specifications. This is the minimum requirements for all operating
temperature options. However, for applications operating in Extended Temperature 85°C ~ 95°C , some optional spec
are required.
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Burst Refresh Current
CKE: High; External clock: On; BL: 8*1; AL: 0; CS#: High between tREF;
Command, Address, Bank Address Inputs: partially toggling; Data IO: MID-
LEVEL;DM:stable at 0; Bank Activity: REF command every tRFC; Output
Buffer and RTT: Enabled in Mode Registers*2; ODT Signal: stable at 0.
IDD5B 222 mA
Self Refresh Current:
Self-Refresh Temperature Range (SRT): Normal*4; CKE:
Low; External clock: Off; CK and CK#: LOW; BL: 8*1; AL:
0; CS#, Command, Address, Bank Address, Data IO:
MID-LEVEL;DM:stable at 0; Bank Activity: Self-Refresh
operation; Output Buffer and RTT: Enabled in Mode
Registers*2; ODT Signal: MID-LEVEL
TCASE: 0 - 85°C IDD6 15 mA
TCASE: -40 - 95°C IDD6ET 19 mA
Operating Bank Interleave Read Current
CKE: High; External clock: On; BL: 8*1, 5; AL: CL-1; CS#: High between ACT
and RDA; Command, Address, Bank Address Inputs: partially toggling;
DM:stable at 0; Output Buffer and RTT: Enabled in Mode Registers*2; ODT
Signal: stable at 0.
IDD7 275 mA
RESET Low Current
RESET: LOW; External clock: Off; CK and CK#: LOW; CKE: FLOATING;
CS#, Command, Address, Bank Address, Data IO: FLOATING; ODT
Signal: FLOATING RESET Low current reading is valid once power is stable
and RESET has been LOW for at least 1ms.
IDD8 12 mA
Table 19. Electrical Characteristics and Recommended A.C. Operating Conditions
(VDD = 1.35V, TOPER = -40~95 C)
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Symbol Parameter -12 Unit
Min. Max.
tAA Internal read command to first data 13.75 20 ns
tRCD ACT to internal read or write delay time 13.75 - ns
tRP PRE command period 13.75 - ns
tRC ACT to ACT or REF command period 48.75 - ns
tRAS ACTIVE to PRECHARGE command period 35 9 x tREFI ns
tCK(avg) Average clock period
CL=5, CWL=5 3.0 3.3 ns 33
CL=6, CWL=5 2.5 3.3 ns 33
CL=7, CWL=6 1.875 <2.5 ns 33
CL=8, CWL=6 1.875 <2.5 ns 33
CL=9, CWL=7 1.5 <1.875 ns 33
CL=10, CWL=7 1.5 <1.875 ns 33
CL=11, CWL=8 1.25 <1. 5 ns 33
tCK (DLL_OFF) Minimum Clock Cycle Time (DLL off mode) 8 - ns 6
tCH(avg) Average clock HIGH pulse width 0.47 0.53 tCK
tCL(avg) Average Clock LOW pulse width 0.47 0.53 tCK
tDQSQ DQS, DQS# to DQ skew, per group, per access - 100 ps 13
tQH DQ output hold time from DQS, DQS# 0.38 - tCK 13
tLZ(DQ) DQ low-impedance time from CK, CK# -450 225 ps 13,14
tHZ(DQ) DQ high impedance time from CK, CK# - 225 ps 13,14
tDS(base) Data setup time to DQS, DQS# referenced
to Vih(ac) / Vil(ac) levels AC135 25 - ps 17
tDH(base) Data hold time from DQS, DQS#
referenced to Vih(dc) / Vil(dc) levels DC90 55 - ps 17
tDIPW DQ and DM Input pulse width for each input 360 - ps
tRPRE DQS,DQS# differential READ Preamble 0.9 - tCK 13,19
tRPST DQS, DQS# differential READ Postamble 0.3 - tCK 11,13
tQSH DQS, DQS# differential output high time 0.4 - tCK 13
tQSL DQS, DQS# differential output low time 0.4 - tCK 13
tWPRE DQS, DQS# differential WRITE Preamble 0.9 - tCK 1
tWPST DQS, DQS# differential WRITE Postamble 0.3 - tCK 1
tDQSCK DQS, DQS# rising edge output access
time from rising CK, CK# -225 225 ps 13
tLZ(DQS) DQS and DQS# low-impedance time
(Referenced from RL - 1) -450 225 ps 13,
14
tHZ(DQS) DQS and DQS# high-impedance time
(Referenced from RL + BL/2) - 225 ps 13,
14
tDQSL DQS, DQS# differential input low pulse width 0.45 0.55 tCK 29,
31
tDQSH DQS, DQS# differential input high pulse width 0.45 0.55 tCK 30,
31
tDQSS DQS, DQS# rising edge to CK, CK# rising edge -0.27 0.27 tCK
tDSS DQS, DQS# falling edge setup time to
CK, CK# rising edge 0.18 - tCK 32
tDSH DQS, DQS# falling edge hold time from
CK, CK# rising edge 0.18 - tCK 32
tDLLK DLL locking time 512 - tCK
tRTP Internal READ Command to
PRECHARGE Command delay max (4tCK,
7.5ns) - tCK
tWTR Delay from start of internal write
transaction to internal read command max (4tCK,
7.5ns) - tCK 18
tWR WRITE recovery time 15 - ns 18
tMRD Mode Register Set command cycle time 4 - tCK
Note
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tMOD Mode Register Set command update delay max
(12tCK,
15ns) - tCK
tCCD CAS# to CAS# command delay 4 - tCK
tDAL(min) Auto precharge write recovery + prechargetime WR + tRP tCK
tMPRR Multi-Purpose Register Recovery Time 1 - tCK 22
tRRD ACTIVE to ACTIVE command period max (4tCK,
7.5ns) - tCK
tFAW Four activate window 40 - ns
tIS(base) Command and Address setup time to CK,
CK# referenced to Vih(ac) / Vil(ac) levels AC160 60 - ps 16
AC135 185 - ps 16,27
tIH(base) Command and Address hold time from CK,
CK# referenced to Vih(dc) / Vil(dc) levels DC90 130 - ps 16
tIPW Control and Address Input pulse width for each input 560 - ps 28
tZQinit Power-up and RESET calibration time 512 - tCK
tZQoper Normal operation Full calibration time 256 - tCK
tZQCS Normal operation Short calibration time 64 - tCK 23
tXPR Exit Reset from CKE HIGH to a valid command max (5tCK,
tRFC(min) +
10ns) - tCK
tXS Exit Self Refresh to commands not
requiring a locked DLL max (5tCK,
tRFC(min) +
10ns) - tCK
tXSDLL Exit Self Refresh to commands requiring a
locked DLL tDLLK(min) - tCK
tCKESR Minimum CKE low width for Self Refresh
entry to exit timing tCKE(min) +
1tCK - tCK
tCKSRE Valid Clock Requirement after Self Refresh Entry
(SRE) or Power-Down Entry (PDE) max (5tCK,
10 ns) - tCK
tCKSRX Valid Clock Requirement before Self Refresh Exit
(SRX) or Power-Down Exit (PDX) or Reset Exit max (5tCK,
10 ns) - tCK
tXP Exit Power Down with DLL on to any valid command;
Exit Precharge Power Down with DLL frozen to
commands not requiring a locked DLL
max (3tCK,
6 ns) - tCK
tXPDLL Exit Precharge Power Down with DLL
frozen to commands requiring a lockedDLL max (10tCK,
24 ns) - tCK 2
tCKE CKE minimum pulse width max (3tCK,
5 ns) - tCK
tCPDED Command pass disable delay 1 - tCK
tPD Power Down Entry to Exit Timing tCKE (min) 9 x tREFI 15
tACTPDEN Timing of ACT command to Power Down
entry 1 - tCK 20
tPRPDEN Timing of PRE or PREA command to
Power Down entry 1 - tCK 20
tRDPDEN Timing of RD/RDA command to Power
Down entry RL+4+1 - tCK
tWRPDEN Timing of WR command to Power Down
entry (BL8OTF, BL8MRS, BC4OTF) WL+4+
(tWR/tCK) - tCK 9
tWRAPDEN Timing of WRA command to Power
Down entry (BL8OTF, BL8MRS,BC4OTF) WL+4+WR
+1 - tCK 10
tWRPDEN Timing of WR command to Power Down entry
(BC4MRS) WL+2+
(tWR/tCK) - tCK 9
tWRAPDEN Timing of WRA command to Power Down entry
(BC4MRS) WL+2+WR
+1 - tCK 10
tREFPDEN Timing of REF command to Power Down entry 1 - tCK 20,
21
tMRSPDEN Timing of MRS command to Power Down entry tMOD(min) -
ODTLon ODT turn on Latency WL - 2 = CWL + AL - 2 tCK
ODTLoff ODT turn off Latency WL - 2 = CWL + AL - 2
ODTH4 ODT high time without write command or
with write command and BC4 4 - tCK
ODTH8 ODT high time with Write command and BL8 6 - tCK
Note 1. Actual value dependant upon measurement level.
Note 2. Commands requiring a locked DLL are: READ (and RAP) and synchronous ODT commands.
Note 3. The max values are system dependent.
Note 4. WR as programmed in mode register.
Note 5. Value must be rounded-up to next higher integer value.
Note 6. There is no maximum cycle time limit besides the need to satisfy the refresh interval, tREFI.
Note 7. For definition of RTT turn-on time tAON See “Timing Parameters”.
Note 8. For definition of RTT turn-off time tAOF See “Timing Parameters”.
Note 9. tWR is defined in ns, for calculation of tWRPDEN it is necessary to round up tWR / tCK to the next integer.
Note 10. WR in clock cycles as programmed in MR0.
Note 11. The maximum read postamble is bound by tDQSCK(min) plus tQSH(min) on the left side and tHZ(DQS)max on the
right side. See “Clock to Data Strobe Relationship”.
Note 12. Output timing deratings are relative to the SDRAM input clock. When the device is operated with input clock jitter, this
parameter needs to be derated by t.b.d.
Note 13. Value is only valid for RON34.
Note 14. Single ended signal parameter.
Note 15. tREFI depends on TOPER.
Note 16. tIS(base) and tIH(base) values are for 1V/ns CMD/ADD single-ended slew rate and 2V/ns CK, CK# differential slew
rate. Note for DQ and DM signals, VREF(DC) = VRefDQ(DC). For input only pins except RESET#, VRef(DC) =
VRefCA(DC). See “Address / Command Setup, Hold and Derating”.
Note 17. tDS(base) and tDH(base) values are for 1V/ns DQ single-ended slew rate and 2V/ns DQS, DQS# differential slew rate.
Note for DQ and DM signals, VREF(DC) = VRefDQ(DC). For input only pins except RESET#, VRef(DC) = VRefCA(DC).
See “Data Setup, Hold and Slew Rate Derating”.
Note 18. Start of internal write transaction is defined as follows:
- For BL8 (fixed by MRS and on- the-fly): Rising clock edge 4 clock cycles after WL.
- For BC4 (on- the- fly): Rising clock edge 4 clock cycles after WL.
- For BC4 (fixed by MRS): Rising clock edge 2 clock cycles after WL.
Note 19. The maximum read preamble is bound by tLZ(DQS)min on the left side and tDQSCK(max) on the right side. See
“Clock to Data Strobe Relationship”.
Note 20. CKE is allowed to be registered low while operations such as row activation, precharge, autoprecharge or refresh are
in progress, but power-down IDD spec will not be applied until finishing those operations.
Note 21. Although CKE is allowed to be registered LOW after a REFRESH command once tREFPDEN(min) is satisfied, there
are cases where additional time such as tXPDLL(min) is also required. See “Power-Down clarifications-Case 2”.
Note 22. Defined between end of MPR read burst and MRS which reloads MPR or disables MPR function.
Note 23. One ZQCS command can effectively correct a minimum of 0.5 % (ZQ Correction) of RON and RTT impedance error
within 64 nCK for all speed bins assuming the maximum sensitivities specified in the ‘Output Driver Voltage and
Temperature Sensitivity’ and ‘ODT Voltage and Temperature Sensitivity’ tables. The appropriate interval between
ZQCS commands can be determined from these tables and other application-specific parameters.
One method for calculating the interval between ZQCS commands, given the temperature (Tdriftrate) and voltage
(Vdriftrate) drift rates that the SDRAM is subject to in the application, is illustrated. The interval could be defined by the
following formula:
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tAONPD Asynchronous RTT turn-on delay (Power- Down with
DLL frozen) 2 8.5 ns
tAOFPD Asynchronous RTT turn-off delay (Power-
Down with DLL frozen) 2 8.5 ns
tAON RTT turn-on -225 225 ps 7
tAOF RTT_Nom and RTT_WR turn-off time
from ODTLoff reference 0.3 0.7 tCK 8
tADC RTT dynamic change skew 0.3 0.7 tCK
tWLMRD First DQS/DQS# rising edge after write
leveling mode is programmed 40 - tCK 3
tWLDQSEN DQS/DQS# delay after write leveling
mode is programmed 25 - tCK 3
tWLS Write leveling setup time from rising CK,
CK# crossing to rising DQS, DQS# crossing 165 - ps
tWLH Write leveling hold time from rising DQS,
DQS# crossing to rising CK, CK# crossing 165 - ps
tWLO Write leveling output delay 0 7.5 ns
tWLOE Write leveling output error 0 2 ns
tRFC REF command to ACT or REF command time 160 - ns
tREFI Average periodic refresh interval -40°C to 85°C - 7.8 μs
85°C to 95°C - 3.9 μs
(TSens × Tdriftrate) + (VSens × Vdriftrate)
ZQCorrection
Where TSens = max(dRTTdT, dRONdTM) and VSens = max(dRTTdV, dRONdVM) define the SDRAM temperature
and voltage sensitivities.
For example, if TSens = 1.5% / °C, VSens = 0.15% / mV, Tdriftrate = 1 °C / sec and Vdriftrate = 15 mV / sec, then the
interval between ZQCS commands is calculated as:
(1.5 × 1) + (0.15 × 15)
0.5 = 0.133 128ms
Note 24. n = from 13 cycles to 50 cycles. This row defines 38 parameters.
Note 25. tCH(abs) is the absolute instantaneous clock high pulse width, as measured from one rising edge to the following
falling edge.
Note 26. tCL(abs) is the absolute instantaneous clock low pulse width, as measured from one falling edge to the following rising
edge.
Note 27. The tIS(base) AC135 specifications are adjusted from the tIS(base) specification by adding an additional 100 ps of
derating to accommodate for the lower alternate threshold of 135 mV and another 25 ps to account for the earlier
reference point [(160 mv - 135 mV) / 1 V/ns].
Note 28. Pulse width of a input signal is defined as the width between the first crossing of Vref(dc) and the consecutive crossing
of Vref(dc).
Note 29. tDQSL describes the instantaneous differential input low pulse width on DQS - DQS#, as measured from one falling
edge to the next consecutive rising edge.
Note 30. tDQSH describes the instantaneous differential input high pulse width on DQS - DQS#, as measured from one rising
edge to the next consecutive falling edge.
Note 31. tDQSH,act + tDQSL,act = 1 tCK,act ; with tXYZ,act being the actual measured value of the respective timing parameter
in the application.
Note 32. tDSH,act + tDSS,act = 1 tCK,act ; with tXYZ,act being the actual measured value of the respective timing parameter in
the application.
Note 33. The CL and CWL settings result in tCK requirements. When making a selection of tCK, both CL and CWL requirement
settings need to be fulfilled.
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- Multi-Purpose Register (MPR)
The Multi Purpose Register (MPR) function is used to Read out a predefined system timing calibration bit sequence.
Figure 8. MPR Block Diagram
Memory Core
(all banks precharged)
MRS 3
【A2】
DQ, DM, DQS, DQS#
Multipurpose register
Pre-defined data for Reads
To enable the MPR, a MODE Register Set (MRS) command must be issued to MR3 Register with bit A2 = 1. Prior to
issuing the MRS command, all banks must be in the idle state (all banks precharged and tRP met). Once the MPR is
enabled, any subsequent RD or RDA commands will be redirected to the Multi Purpose Register. The resulting
operation, when a RD or RDA command is issued, is defined by MR3 bits A[1:0] when the MPR is enabled as shown
in table 20. When the MPR is enabled, only RD or RDA commands are allowed until a subsequent MRS command is
issued with the MPR disabled (MR3 bit A2 = 0). Note that in MPR mode RDA has the same functionality as a READ
command which means the auto precharge part of RDA is ignored. Power-Down mode, Self-Refresh and any other
non-RD/RDA command is not allowed during MPR enable mode. The RESET function is supported during MPR
enable mode.
Table 20. MPR MR3 Register Definition
MR3 A[2]
MR3 A[1:0]
Function
MPR
MPR-Loc
0b
Don’t care (0b or 1b)
Normal operation, no MPR transaction.
All subsequent Reads will come from DRAM array.
All subsequent Write will go to DRAM array.
1b
See the table 20
Enable MPR mode, subsequent RD/RDA commands defined by
MR3 A[1:0].
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- MPR Functional Description
One bit wide logical interface via all DQ pins during READ operation.
Register Read on x16:
DQL[0] and DQU[0] drive information from MPR.
DQL[7:1] and DQU[7:1] either drive the same information as DQL [0], or they drive 0b.
Addressing during for Multi Purpose Register reads for all MPR agents:
BA [2:0]: don’t care
A[1:0]: A[1:0] must be equal to ‘00’b. Data read burst order in nibble is fixed
A[2]: For BL=8, A[2] must be equal to 0b, burst order is fixed to [0,1,2,3,4,5,6,7], *) For Burst Chop 4 cases, the
burst order is switched on nibble base A [2]=0b, Burst order: 0,1,2,3 *) A[2]=1b, Burst order: 4,5,6,7 *)
A[9:3]: don’t care
A10/AP: don’t care
A12/BC: Selects burst chop mode on-the-fly, if enabled within MR0.
A11, A13, … (if available): don’t care
Regular interface functionality during register reads:
Support two Burst Ordering which are switched with A2 and A[1:0]=00b.
Support of read burst chop (MRS and on-the-fly via A12/BC)
All other address bits (remaining column address bits including A10, all bank address bits) will be ignored by the
DDR3L SDRAM.
Regular read latencies and AC timings apply.
DLL must be locked prior to MPR Reads.
NOTE: *) Burst order bit 0 is assigned to LSB and burst order bit 7 is assigned to MSB of the selected MPR agent.
Table 21. MPR MR3 Register Definition
MR3
A[2]
MR3
A[1:0]
Function
Burst Length
Read Address
A[2:0]
Burst Order and Data Pattern
1b
00b
Read Predefined
Pattern for
System
Calibration
BL8
000b
Burst order 0, 1, 2, 3, 4, 5, 6, 7
Pre-defined Data Pattern
[0, 1, 0, 1, 0, 1, 0, 1]
BC4
000b
Burst order 0, 1, 2, 3
Pre-defined Data Pattern
[0, 1, 0, 1]
BC4
100b
Burst order 4, 5, 6, 7
Pre-defined Data Pattern
[0, 1, 0, 1]
1b
01b
RFU
BL8
000b
Burst order 0, 1, 2, 3, 4, 5, 6, 7
BC4
000b
Burst order 0, 1, 2, 3
BC4
100b
Burst order 4, 5, 6, 7
1b
10b
RFU
BL8
000b
Burst order 0, 1, 2, 3, 4, 5, 6, 7
BC4
000b
Burst order 0, 1, 2, 3
BC4
100b
Burst order 4, 5, 6, 7
1b
11b
RFU
BL8
000b
Burst order 0, 1, 2, 3, 4, 5, 6, 7
BC4
000b
Burst order 0, 1, 2, 3
BC4
100b
Burst order 4, 5, 6, 7
No Operation (NOP) Command
The No operation (NOP) command is used to instruct the selected DDR3L SDRAM to perform a NOP (CS# low and
RAS#, CAS# and WE# high). This prevents unwanted commands from being registered during idle or wait states.
Operations already in progress are not affected.
Deselect Command
The Deselect function (CS# HIGH) prevents new commands from being executed by the DDR3L SDRAM. The
DDR3L SDRAM is effectively deselected. Operations already in progress are not affected.
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DLL- Off Mode
DDR3L DLL-off mode is entered by setting MR1 bit A0 to “1”; this will disable the DLL for subsequent operations until
A0 bit set back to “0”. The MR1 A0 bit for DLL control can be switched either during initialization or later.
The DLL-off Mode operations listed below are an optional feature for DDR3L. The maximum clock frequency for
DLL-off Mode is specified by the parameter tCKDLL_OFF. There is no minimum frequency limit besides the need to
satisfy the refresh interval, tREFI.
Due to latency counter and timing restrictions, only one value of CAS Latency (CL) in MR0 and CAS Write Latency
(CWL) in MR2 are supported. The DLL-off mode is only required to support setting of both CL=6 and CWL=6.
DLL-off mode will affect the Read data Clock to Data Strobe relationship (tDQSCK) but not the data Strobe to Data
relationship (tDQSQ, tQH). Special attention is needed to line up Read data to controller time domain. Comparing
with DLL-on mode, where tDQSCK starts from the rising clock edge (AL+CL) cycles after the Read command, the
DLL-off mode tDQSCK starts (AL+CL-1) cycles after the read command. Another difference is that tDQSCK may not
be small compared to tCK (it might even be larger than tCK) and the difference between tDQSCKmin and
tDQSCKmax is significantly larger than in DLL-on mode.
The timing relations on DLL-off mode READ operation have shown at the following Timing Diagram (CL=6, BL=8)
Figure 9. DLL-off mode READ Timing Operation
CK#
T1 T2 T3 T4 T5 T6 T7 T8 T9T0
ADDRESS
CK
T10
COMMAND
DQS#
DQS
Don't Care
NOPREAD NOP NOP NOP NOP NOP NOP NOP NOP NOP
Bank,
Col b
RL (DLL_on) = AL + CL = 6 (CL = 6, AL = 0)
CL = 6
Din
b
Din
b+1
Din
b+2
Din
b+3
Din
b+4
Din
b+5
Din
b+6
Din
b+7
DQ
Din
b
Din
b+1
Din
b+2
Din
b+3
Din
b+4
Din
b+5
Din
b+6
Din
b+7
DQS#
DQS
DQ
Din
b
Din
b+1
Din
b+2
Din
b+3
Din
b+4
Din
b+5
Din
b+6
Din
b+7
DQS#
DQS
DQ
(DLL_on)
(DLL_on)
(DLL_off)
(DLL_off)
(DLL_off)
(DLL_off)
RL (DLL_off) = AL + (CL-1) = 5 tDQSCK(DLL_off)_min
tDQSCK(DLL_off)_max
NOTE 1. The tDQSCK is used here for DQS, DQS# and DQ to have a simplified diagram; the DLL_off shift will affect
both timings in the same way and the skew between all DQ and DQS, DQS# signals will still be tDQSQ.
TRANSITIONING DATA
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DLL on/off switching procedure
DDR3L DLL-off mode is entered by setting MR1 bit A0 to “1”; this will disable the DLL for subsequent operation until
A0 bit set back to “0”.
DLL “on” to DLL “off” Procedure
To switch from DLL “on” to DLL “off” requires the frequency to be changed during Self-Refresh outlined in the following
procedure:
1. Starting from Idle state (all banks pre-charged, all timing fulfilled, and DRAMs On-die Termination resistors, RTT,
must be in high impedance state before MRS to MR1 to disable the DLL).
2. Set MR1 Bit A0 to “1” to disable the DLL.
3. Wait tMOD.
4. Enter Self Refresh Mode; wait until (tCKSRE) satisfied.
5. Change frequency, in guidance with “Input Clock Frequency Change” section.
6. Wait until a stable clock is available for at least (tCKSRX) at DRAM inputs.
7. Starting with the Self Refresh Exit command, CKE must continuously be registered HIGH until all tMOD timings
from any MRS command are satisfied. In addition, if any ODT features were enabled in the mode registers when
Self Refresh mode was entered, the ODT signal must continuously be registered LOW until all tMOD timings from
any MRS command are satisfied. If both ODT features were disabled in the mode registers when Self Refresh
mode was entered, ODT signal can be registered LOW or HIGH.
8. Wait tXS, and then set Mode Registers with appropriate values (especially an update of CL, CWL, and WR may
be necessary. A ZQCL command may also be issued after tXS).
9. Wait for tMOD, and then DRAM is ready for next command.
Figure 10. DLL Switch Sequence from DLL-on to DLL-off
T1 Ta0 Ta1 Tb0 Tc0 Td0 Td1 Te0 Te1T0 Tf0
tMOD
Notes 1
Don't CareTIME BREAK
NOPMRS SRE NOP SRX NOP MRS NOP
VALID
VALID
tCKSRE
Notes 2 Notes 3 Notes 6 Notes 7
Notes 8
Notes 8
Notes 4 tCKSRX
Notes 5
tXS tMOD
tCKESR
VALID
Notes 8
NOTES:
1. Starting with Idle State, RTT in Hi-Z state
2. Disable DLL by setting MR1 Bit A0 to 1
3. Enter SR
4. Change Frequency
5. Clock must be stable tCKSRX
6. Exit SR
7. Update Mode registers with DLL off parameters setting
8. Any valid command
ODT: Static LOW in case RTT_Nom and RTT_WR is enabled, otherwise static Low or High
CK#
CK
COMMAND
CKE
ODT
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DLL “off” to DLL “on” Procedure
To switch from DLL “off” to DLL “on” (with requires frequency change) during Self-Refresh:
1. Starting from Idle state (all banks pre-charged, all timings fulfilled and DRAMs On-die Termination resistors (RTT)
must be in high impedance state before Self-Refresh mode is entered).
2. Enter Self Refresh Mode, wait until tCKSRE satisfied.
3. Change frequency, in guidance with “Input clock frequency change” section.
4. Wait until a stable clock is available for at least (tCKSRX) at DRAM inputs.
5. Starting with the Self Refresh Exit command, CKE must continuously be registered HIGH until tDLLK timing from
subsequent DLL Reset command is satisfied. In addition, if any ODT features were enabled in the mode registers
when Self Refresh mode was entered, the ODT signal must continuously be registered LOW until tDLLK timings
from subsequent DLL Reset command is satisfied. If both ODT features are disabled in the mode registers when
Self Refresh mode was entered, ODT signal can be registered LOW or HIGH.
6. Wait tXS, then set MR1 Bit A0 to “0” to enable the DLL.
7. Wait tMRD, then set MR0 Bit A8 to “1” to start DLL Reset.
8. Wait tMRD, then set Mode registers with appropriate values (especially an update of CL, CWL, and WR may be
necessary. After tMOD satisfied from any proceeding MRS command, a ZQCL command may also be issued
during or after tDLLK).
9. Wait for tMOD, then DRAM is ready for next command (remember to wait tDLLK after DLL Reset before applying
command requiring a locked DLL!). In addition, wait also for tZQoper in case a ZQCL command was issued.
Figure 11. DLL Switch Sequence from DLL-off to DLL on
CK#
Ta0 Ta1 Tb0 Tc0 Tc1 Td0 Te0 Tf1 Tg0T0
CK
Th0
COMMAND
CKE
ODT
Notes 1
Don't CareTIME BREAK
SRENOP NOP SRX MRS MRS MRS
VALID
VALID
tCKSRE
Notes 2 Notes 5 Notes 7
Notes 3 tCKSRX
Notes 4
tXS tMRD
tCKESR
NOTES:
1. Starting with Idle State
2. Enter SR
3. Change Frequency
4. Clock must be stable tCKSRX
5. Exit SR
6. Set DLL on by MR1 A0 = 0
7. Start DLL Reset by MR0 A8=1
8. Update Mode registers
9. Any valid command
ODT: Static LOW in case RTT_Nom and RTT_WR is enabled, otherwise static Low or High
Notes 6 Notes 8
tDLLK
ODTLoff + 1 * tCK tMRD
Notes 9
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Jitter Notes
Note 1. Unit ‘tCK(avg)’ represents the actual tCK(avg) of the input clock under operation. Unit ‘nCK’ represents one
clock cycle of the input clock, counting the actual clock edges.ex) tMRD = 4 [nCK] means; if one Mode
Register Set command is registered at Tm, another Mode Register Set command may be registered at
Tm+4, even if (Tm+4 - Tm) is 4 x tCK(avg) + tERR(4per),min.
Note 2. These parameters are measured from a command/address signal (CKE, CS#, RAS#, CAS#, WE#, ODT,
BA0, A0, A1, etc.) transition edge to its respective clock signal (CK/CK#) crossing. The spec values are not
affected by the amount of clock jitter applied (i.e. tJIT(per), tJIT(cc), etc.), as the setup and hold are relative
to the clock signal crossing that latches the command/address. That is, these parameters should be met
whether clock jitter is present or not.
Note 3. These parameters are measured from a data strobe signal (DQS(L/U), DQS(L/U)#) crossing to its respective
clock signal (CK, CK#) crossing. The spec values are not affected by the amount of clock jitter applied (i.e.
tJIT(per), tJIT(cc), etc.), as these are relative to the clock signal crossing. That is, these parameters should
be met whether clock jitter is present or not.
Note 4. These parameters are measured from a data signal (DM(L/U), DQ(L/U)0, DQ(L/U)1, etc.) transition edge to
its respective data strobe signal (DQS(L/U), DQS(L/U)#) crossing.
Note 5. For these parameters, the DDR3L SDRAM device supports tnPARAM [nCK] = RU{ tPARAM [ns] / tCK(avg)
[ns] }, which is in clock cycles, assuming all input clock jitter specifications are satisfied.
Note 6. When the device is operated with input clock jitter, this parameter needs to be derated by the actual
tERR(mper),act of the input clock, where 2 <= m <= 12. (output deratings are relative to the SDRAM input
clock.)
Note 7. When the device is operated with input clock jitter, this parameter needs to be derated by the actual
tJIT(per),act of the input clock. (output deratings are relative to the SDRAM input clock.)
Table 22. Input clock jitter spec parameter
Parameter
Symbol
-12
Unit
Min. Max.
Clock period jitter
tJIT (per)
-70 70
ps
Clock period jitter during DLL locking period
tJIT (per,lck)
-60 60
ps
Cycle to cycle clock period jitter
tJIT (cc)
140
ps
Cycle to cycle clock period jitter during DLL locking period
tJIT (cc,lck)
120
ps
Cumulative error across 2 cycles
tERR (2per)
-103 103
ps
Cumulative error across 3 cycles
tERR (3per)
-122 122
ps
Cumulative error across 4 cycles
tERR (4per)
-136 136
ps
Cumulative error across 5 cycles
tERR (5per)
-147 147
ps
Cumulative error across 6 cycles
tERR (6per)
-155 155
ps
Cumulative error across 7 cycles
tERR (7per)
-163 163
ps
Cumulative error across 8 cycles
tERR (8per)
-169 169
ps
Cumulative error across 9 cycles
tERR (9per)
-175 175
ps
Cumulative error across 10 cycles
tERR (10per)
-180 180
ps
Cumulative error across 11 cycles
tERR (11per)
-184 184
ps
Cumulative error across 12 cycles
tERR (12per)
-188 188
ps
Cumulative error across n cycles, n=13...50, inclusive
tERR (nper)
tERR (nper)min = (1+0.68ln(n)) * tJIT (per)min
tERR (nper)max = (1+0.68ln(n)) * tJIT (per)max
ps
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Input Clock frequency change
Once the DDR3L SDRAM is initialized, the DDR3L SDRAM requires the clock to be “stable” during almost all states
of normal operation. This means once the clock frequency has been set and is to be in the “stable state”, the clock
period is not allowed to deviate except for what is allowed for by the clock jitter and SSC (spread spectrum clocking)
specification.
The input clock frequency can be changed from one stable clock rate to another stable clock rate under two
conditions: (1) Self-Refresh mode and (2) Precharge Power-Down mode. Outside of these two modes, it is illegal to
change the clock frequency.
For the first condition, once the DDR3L SDRAM has been successfully placed in to Self-Refresh mode and tCKSRE
has been satisfied, the state of the clock becomes a don’t care. Once a don’t care, changing the clock frequency is
permissible, provided the new clock frequency is stable prior to tCKSRX. When entering and exiting Self-Refresh
mode of the sole purpose of changing the clock frequency, the Self-Refresh entry and exit specifications must still be
met. The DDR3L SDRAM input clock frequency is allowed to change only within the minimum and maximum
operating frequency specified for the particular speed grade.
The second condition is when the DDR3L SDRAM is in Precharge Power-Down mode (either fast exit mode or slow
exit mode). If the RTT_Nom feature was enabled in the mode register prior to entering Precharge power down mode,
the ODT signal must continuously be registered LOW ensuring RTT is in an off state. If the RTT_Nom feature was
disabled in the mode register prior to entering Precharge power down mode, RTT will remain in the off state. The
ODT signal can be registered either LOW or HIGH in this case. A minimum of tCKSRE must occur after CKE goes
LOW before the clock frequency may change. The DDR3L SDRAM input clock frequency is allowed to change only
within the minimum and maximum operating frequency specified for the particular speed grade. During the input
clock frequency change, ODT and CKE must be held at stable LOW levels. Once the input clock frequency is
changed, stable new clocks must be provided to the DRAM tCKSRX before precharge Power Down may be exited;
after Precharge Power Down is exited and tXP has expired, the DLL must be RESET via MRS. Depending on the
new clock frequency additional MRS commands may need to be issued to appropriately set the WR, CL, and CWL
with CKE continuously registered high. During DLL re-lock period, ODT must remain LOW and CKE must remain
HIGH. After the DLL lock time, the DRAM is ready to operate with new clock frequency.
Figure 12. Change Frequency during Precharge Power-down
CK#
T1 T2 Ta0 Tb0 Tc0 Tc1 Td0 Td1 Te0T0
ADDRESS
CK
Te1
COMMAND
ODT
NOPNOP NOP NOP NOP MRS NOP VALID
DLL
RESET
High-Z
High-z
DQS#
DQS
DQ
DM
NOTES
1. Applicable for both SLOW EXIT and FAST EXIT Precharge Power-down.
2. tAOFPD and tAOF must be statisfied and outputs High-Z prior to T1;refer to ODT timing section for exact requirements
3. If the RTT_NOM feature was enabled in the mode register prior to entering Precharge power down mode, the ODT
signal must continuously be registered LOW ensuring RTT is in an off state, as shown in Figure 9. If the RTT_NOM feature was disabled in the mode
register prior to entering Precharge power down mode, RTT will remain in the off state. The ODT signal can be registered either LOW or HIGH in this case.
tCH tCL
tCK
tCKSRE tCHb tCLb
tCKb
tCHb tCLb
tCKb
tCHb tCLb
tCKb
tCKSRX
tCKE
CKE
tIH tIS
VALID
tXP
Enter PRECHARGE
Power-Down Mode
tCPDED
PREVIOUS CLOCK FREQUENCY NEW CLOCK FREQUENCY
tAOFPD / tAOF
Frequency Change Exit PRECHARGE
Power-Down Mode
tDLLK
Don't Care
Indicates a break
in time scale
tIH
tIS
tIH
tIS
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Write Leveling
For better signal integrity, DDR3L memory adopted fly by topology for the commands, addresses, control signals,
and clocks. The fly by topology has benefits from reducing number of stubs and their length but in other aspect,
causes flight time skew between clock and strobe at every DRAM on DIMM. It makes it difficult for the Controller to
maintain tDQSS, tDSS, and tDSH specification. Therefore, the controller should support “write leveling” in DDR3L
SDRAM to compensate the skew.
The memory controller can use the “write leveling” feature and feedback from the DDR3L SDRAM to adjust the
DQS – DQS# to CK – CK# relationship. The memory controller involved in the leveling must have adjustable delay
setting on DQS – DQS# to align the rising edge of DQS – DQS# with that of the clock at the DRAM pin. DRAM
asynchronously feeds back CK – CK#, sampled with the rising edge of DQS – DQS#, through the DQ bus. The
controller repeatedly delays DQS – DQS# until a transition from 0 to 1 is detected. The DQS – DQS# delay
established though this exercise would ensure tDQSS specification.
Besides tDQSS, tDSS, and tDSH specification also needs to be fulfilled. One way to achieve this is to combine the
actual tDQSS in the application with an appropriate duty cycle and jitter on the DQS- DQS# signals. Depending on
the actual tDQSS in the application, the actual values for tDQSL and tDQSH may have to be better than the absolute
limits provided in “AC Timing Parameters” section in order to satisfy tDSS and tDSH specification.
DQS/DQS# driven by the controller during leveling mode must be determined by the DRAM based on ranks
populated. Similarly, the DQ bus driven by the DRAM must also be terminated at the controller.
One or more data bits should carry the leveling feedback to the controller across the DRAM configurations X16. On
a X16 device, both byte lanes should be leveled independently. Therefore, a separate feedback mechanism should
be available for each byte lane. The upper data bits should provide the feedback of the upper diff_DQS (diff_UDQS)
to clock relationship whereas the lower data bits would indicate the lower diff_DQS (diff_LDQS) to clock relationship.
Figure 13. Write Leveling Concept
CK#
T1 T2 T3 T4 T5 T6 T7T0
CK
Diff_DQS
DQ
Source
Destination
T0 T1 T2 T3 T4 T5 T6Tn
CK#
CK
Diff_DQS
0 0
DQ
Diff_DQS
1 1
Push DQS to capture
0-1 transition
0 or 1
0 or 1
0
1
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DRAM setting for write leveling and DRAM termination function in that mode
DRAM enters into Write leveling mode if A7 in MR1 set “High” and after finishing leveling, DRAM exits from write
leveling mode if A7 in MR1 set “Low”. Note that in write leveling mode, only DQS/DQS# terminations are activated
and deactivated via ODT pin not like normal operation.
Table 23. DRAM termination function in the leveling mode
ODT pin at DRAM
DQS, DQS# termination
DQs termination
De-asserted
off
off
Asserted
on
off
Note 1: In write leveling mode with its output buffer disabled (MR1[bit7]=1 with MR1[bit12]=1) all RTT_Nom settings are allowed;
in Write Leveling Mode with its output buffer enabled (MR1[bit7]=1 with MR1[bit12]=0) only RTT_Nom settings of RZQ/2,
RZQ/4, and RZQ/6 are allowed.
Procedure Description
Memory controller initiates Leveling mode of all DRAMs by setting bit 7 of MR1 to 1. With entering write leveling
mode, the DQ pins are in undefined driving mode. During write leveling mode, only NOP or Deselect commands are
allowed. As well as an MRS command to exit write leveling mode. Since the controller levels one rank at a time, the
output of other rank must be disabled by setting MR1 bit A12 to 1. Controller may assert ODT after tMOD, time at
which DRAM is ready to accept the ODT signal.
Controller may drive DQS low and DQS# high after a delay of tWLDQSEN, at which time DRAM has applied on-die
termination on these signals. After tDQSL and tWLMRD controller provides a single DQS, DQS# edge which is used
by the DRAM to sample CK – CK# driven from controller. tWLMRD(max) timing is controller dependent.
DRAM samples CK – CK# status with rising edge of DQS and provides feedback on all the DQ bits asynchronously
after tWLO timing. There is a DQ output uncertainty of tWLOE defined to allow mismatch on DQ bits; there are no
read strobes (DQS/DQS) needed for these DQs. Controller samples incoming DQ and decides to increment or
decrement DQS – DQS# delay setting and launches the next DQS/DQS# pulse after some time, which is controller
dependent. Once a 0 to 1 transition is detected, the controller locks DQS – DQS# delay setting and write leveling is
achieved for the device.
Figure 14. Timing details of Write Leveling sequence
(DQS – DQS# is capturing CK – CK# low at T1 and CK – CK# high at T2)
tWLMRD
Don't CareTIME BREAK
NOPMRS NOP NOP NOP NOP NOP NOP NOP NOP NOP
tWLS
tWLH
T1
tWLS tWLH
T2
NOP
Notes 1 Notes 2
tWLDQSEN
tDQSL
Notes 6 tDQSH
Notes 6
tDQSL
Notes 6 tDQSH
Notes 6
CK#
CK
COMMAND
ODT
Diff_DQS
Prime DQ
Notes 5
Notes 4
One Prime DQ:
Notes 3
Late Prime DQs
Early Prime DQs
All DQs are Prime:
Notes 3
Notes 3
Late Remaining DQs
Early Remaining DQs
tWLO
tWLO
tWLO
tWLOE
tWLO
tWLOE
tWLO
tMOD
tWLO
tWLMRD
tWLO
tWLO
tWLOE
UNDEFINED Driving MODE
NOTES
1. MRS: Load MR1 to enter write leveling mode.
2. NOP: NOP or Deselect.
3. DRAM has the option to drive leveling feedback on a prime DQ or all DQs. If feedback is driven only on one DQ, the remaining DQs must be driven low, as shown in above Figure,
and maintained at this state through out the leveling procedure.
4. diff_DQS is the differential data strobe (DQS, DQS#). Timing reference points are the zero crossings. DQS is shown with solid line, DQS# is shown with dotted line.
5. CK, CK# : CK is shown with solid dark line, where as CK# is drawn with dotted line.
6. DQS, DQS# needs to fulfill minimum pulse width requirements tDQSH(min) and tDQSL(min) as defined for regular Writes; the max pulse width is system dependent.
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Write Leveling Mode Exit
The following sequence describes how Write Leveling Mode should be exited:
1. After the last rising strobe edge (see ~T0), stop driving the strobe signals (see ~Tc0). Note: From now on, DQ pins
are in undefined driving mode, and will remain undefined, until tMOD after the respective MR command (Te1).
2. Drive ODT pin low (tIS must be satisfied) and keep it low (see Tb0).
3. After the RTT is switched off, disable Write Level Mode via MRS command (see Tc2).
4. After tMOD is satisfied (Te1), any valid command may be registered. (MR commands may be issued after tMRD
(Td1).
Figure 15. Timing details of Write Leveling exit
Don't CareTIME BREAK
NOPNOP NOP NOP NOP NOP NOP MRS NOP VALID NOP VALID
tWLO
tAOFmin
UNDEFINED Driving MODE
T1 T2 Ta0 Tb0 Tc0 Tc1 Tc2
T0 Td0 Td1 Te0 Te1
NOTES:
1. The DQ result = 1 between Ta0 and Tc0 is a result of the DQS, DQS# signals capturing CK high just after the T0 state.
MR1 VALID VALID
tMRD
RTT_NOM
Result = 1
TRANSITIONING
tAOFmax
tIS
ODTLoff
tMOD
CK#
CK
COMMAND
ADDRESS
ODT
RTT_DQS_DQS#
DQ
DQS_DQS#
RTT_DQ
Notes 1
ACTIVE Command
The ACTIVE command is used to open (or activate) a row in a particular bank for subsequent access. The value on
the BA0-BA2 inputs selects the bank, and the addresses provided on inputs A0-A13 selects the row. These rows
remain active (or open) for accesses until a precharge command is issued to that bank. A PRECHARGE command
must be issued before opening a different row in the same bank.
PRECHARGE Command
The PRECHARGE command is used to deactivate the open row in a particular bank or the open row in all banks.
The bank(s) will be available for a subsequent row activation a specified time (tRP) after the PRECHARGE
command is issued, except in the case of concurrent auto precharge, where a READ or WRITE command to a
different bank is allowed as long as it does not interrupt the data transfer in the current bank and does not violate any
other timing parameters. Once a bank has been precharged, it is in the idle state and must be activated prior to any
READ or WRITE commands being issued to that bank. A PRECHARGE command is allowed if there is no open row
in that bank (idle bank) or if the previously open row is already in the process of precharging. However, the
precharge period will be determined by the last PRECHARGE command issued to the bank.
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READ Operation
Read Burst Operation
During a READ or WRITE command DDR3L will support BC4 and BL8 on the fly using address A12 during the
READ or WRITE (AUTO PRECHARGE can be enabled or disabled).
A12=0, BC4 (BC4 = burst chop, tCCD=4)
A12=1, BL8
A12 will be used only for burst length control, not a column address.
Figure 16. READ Burst Operation RL=5 (AL=0, CL=5, BL=8)
Don't Care
NOPREAD NOP NOP NOP NOP NOP NOP NOP NOP NOP
NOTES:
1. BL8, RL = 5, AL = 0, CL = 5.
2. Dout n = data-out from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 during READ command at T0.
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
Bank,
Col n
TRANSITIONING DATA
tRPRE tRPST
Dout
n
Dout
n+1
Dout
n+2
Dout
n+3
Dout
n+4
Dout
n+5
Dout
n+6
Dout
n+7
RL = AL + CL
CL = 5
CK#
CK
DQS, DQS#
DQ
Notes 3
Notes 2
ADDRESS
Notes 4
COMMAND
Figure 17. READ Burst Operation RL=9 (AL=4, CL=5, BL=8)
Don't Care
NOPREAD NOP NOP NOP NOP NOP NOP NOP NOP NOP
NOTES:
1. BL8, RL = 9, AL = (CL-1), CL = 5.
2. Dout n = data-out from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 during READ command at T0.
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
Bank,
Col n
TRANSITIONING DATA
tRPRE
Dout
n
Dout
n+1
Dout
n+2
RL = AL + CL
AL = 4 CL = 5
CK#
CK
DQS, DQS#
DQ
Notes 3
Notes 2
ADDRESS
Notes 4
COMMAND
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READ Timing Definitions
Read timing is shown in the following figure and is applied when the DLL is enabled and locked.
Rising data strobe edge parameters:
tDQSCK min/max describes the allowed range for a rising data strobe edge relative to CK, CK#. tDQSCK is the
actual position of a rising strobe edge relative to CK, CK#. tQSH describes the DQS, DQS# differential output high
time. tDQSQ describes the latest valid transition of the associated DQ pins. tQH describes the earliest invalid
transition of the associated DQ pins.
Falling data strobe edge parameters:
tQSL describes the DQS, DQS# differential output low time. tDQSQ describes the latest valid transition of the
associated DQ pins. tQH describes the earliest invalid transition of the associated DQ pins.
tDQSQ; both rising/falling edges of DQS, no tAC defined.
Figure 18. READ timing Definition
tDQSCK
tDQSCK,min
CK#
CK
tDQSCK,max tDQSCK,max
Rising Strobe
Region
tDQSCK,min
DQS#
DQS
tDQSCK
tQSH tQSL
Rising Strobe
Region
Associated
DQ Pins
tQH tQH
tDQSQ tDQSQ
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Read Timing; Clock to Data Strobe relationship
Clock to Data Strobe relationship is shown in the following figure and is applied when the DLL is enabled and locked.
Rising data strobe edge parameters:
tDQSCK min/max describes the allowed range for a rising data strobe edge relative to CK and CK#. tDQSCK
is the actual position of a rising strobe edge relative to CK and CK#. tQSH describes the data strobe high
pulse width.
Falling data strobe edge parameters:
tQSL describes the data strobe low pulse width.
Figure 19. Clock to Data Strobe relationship
NOTES:
1. Within a burst, rising strobe edge is not necessarily fixed to be always at tDQSCK(min) or tDQSCK(max). Instead, rising strobe
edge can vary between tDQSCK(min) and tDQSCK(max).
2. Notwithstanding note 1, a rising strobe edge with tDQSCK(max) at T(n) can not be immediately followed by a rising strobe edge
with tDQSCK(min) at T(n+1). This is because other timing relationships (tQSH, tQSL) exist: if tDQSCK(n+1) < 0: tDQSCK(n) < 1.0 tCK -
(tQSHmin + tQSLmin) - | tDQSCK(n+1) |
3. The DQS, DQS# differential output high time is defined by tQSH and the DQS, DQS# differential output low time is defined by tQSL.
4. Likewise, tLZ(DQS)min and tHZ(DQS)min are not tied to tDQSCKmin (early strobe case) and tLZ(DQS)max and tHZ(DQS)max are
not tied to tDQSCKmax (late strobe case).
5. The minimum pulse width of read preamble is defined by tRPRE(min).
6. The maximum read postamble is bound by tDQSCK(min) plus tQSH(min) on the left side and tHZDSQ(max) on the right side.
7. The minimum pulse width of read postamble is defined by tRPST(min).
8. The maximum read preamble is bound by tLZDQS(min) on the left side and tDQSCK(max) on the right side.
CLK#
CLK
tLZ(DQS) min
DQS, DQS#
Late Strobe
DQS, DQS#
Early Strobe tRPRE
tLZ(DQS) max
tDQSCK (min)
tQSH tQSL
tDQSCK (min)
tQSH tQSL tQSH tQSL
tDQSCK (min) tDQSCK (min)
tRPST
tHZ(DQS) (min)
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
tDQSCK (max)
tRPRE tQSH tQSL
tDQSCK (max)
tQSH tQSL tQSH tQSL
tDQSCK (max) tDQSCK (max) tRPST
tHZ(DQS) (max)
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
RL Measured
to this point
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Read Timing; Data Strobe to Data Relationship
The Data Strobe to Data relationship is shown in the following figure and is applied when the DLL and enabled and
locked.
Rising data strobe edge parameters:
- tDQSQ describes the latest valid transition of the associated DQ pins.
- tQH describes the earliest invalid transition of the associated DQ pins.
Falling data strobe edge parameters:
- tDQSQ describes the latest valid transition of the associated DQ pins.
- tQH describes the earliest invalid transition of the associated DQ pins.
- tDQSQ; both rising/falling edges of DQS, no tAC defined
tDQSQ; both rising/falling edges of DQS, no tAC defined
Figure 20. Data Strobe to Data Relationship
T1 T2 T3 T4 T5 T6 T7 T8 T9T0 T10
RL = AL +CL
NOPREAD NOP NOP NOP NOP NOP NOP NOP NOP NOP
Bank,
Col n
tDQSQ (max)
Dout
n
Dout
n+1
Dout
n+2
Dout
n+3
Dout
n+4
Dout
n+5
Dout
n+6
Dout
n+7
Dout
n
Dout
n+1
Dout
n+2
Dout
n+3
Dout
n+4
Dout
n+5
Dout
n+6
Dout
n+7
CK#
ADDRESS
CK
COMMAND
DQS,DQS#
DQ
(Last data valid)
All DQs collectively
DQ
(First data no longer valid)
tRPRE tQH tQH
tDQSQ (max) tRPST
Notes 3
Notes 4
Notes 2
Notes 2
NOTES:
1. BL = 8, RL = 5 (AL = 0, CL = 5)
2. DOUT n = data-out from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 during READ command at T0.
5. Output timings are referenced to VDDQ/2, and DLL on for locking.
6. tDQSQ defines the skew between DQS,DQS# to Data and does not define DQS,DQS# to Clock.
7. Early Data transitions may not always happen at the same DQ. Data transitions of a DQ can vary (either early or late) within a burst.
Don't CareTRANSITIONING DATA
Dout
n
Dout
n+1
Dout
n+2
Dout
n+3
Dout
n+4
Dout
n+5
Dout
n+6
Dout
n+7
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Write Operation
DDR3L Burst Operation
During a READ or WRITE command, DDR3L will support BC4 and BL8 on the fly using address A12 during the READ
or WRITE (Auto Precharge can be enabled or disabled).
A12=0, BC4 (BC4 = Burst Chop, tCCD=4)
A12=1, BL8
A12 is used only for burst length control, not as a column address.
WRITE Timing Violations
Generally, if timing parameters are violated, a complete reset/initialization procedure has to be initiated to make sure
the DRAM works properly. However, it is desirable for certain minor violations that the DRAM is guaranteed not to
“hang up” and errors be limited to that particular operation.
For the following, it will be assumed that there are no timing violations with regard to the Write command itself
(including ODT, etc.) and that it does satisfy all timing requirements not mentioned below.
Data Setup and Hold Violations
Should the strobe timing requirements (tDS, tDH) be violated, for any of the strobe edges associated with a write
burst, then wrong data might be written to the memory location addressed with the offending WRITE command.
Subsequent reads from that location might result in unpredictable read data, however, the DRAM will work properly
otherwise.
Strobe to Strobe and Strobe to Clock Violations
Should the strobe timing requirements (tDQSH, tDQSL, tWPRE, tWPST) or the strobe to clock timing requirements
(tDSS, tDSH, tDQSS) be violated, for any of the strobe edges associated with a Write burst, then wrong data might
be written to the memory location addressed with the offending WRITE command. Subsequent reads from that
location might result in unpredictable read data, however the DRAM will work properly otherwise.
Write Timing Parameters
This drawing is for example only to enumerate the strobe edges that “belong” to a write burst. No actual timing
violations are shown here. For a valid burst all timing parameters for each edge of a burst need to be satisfied (not
only for one edge).
Refresh Command
The Refresh command (REF) is used during normal operation of the DDR3L SDRAMs. This command is not
persistent, so it must be issued each time a refresh is required. The DDR3L SDRAM requires Refresh cycles at an
average periodic interval of tREFI. When CS#, RAS#, and CAS# are held Low and WE# High at the rising edge of
the clock, the chip enters a Refresh cycle. All banks of the SDRAM must be precharged and idle for a minimum of
the precharge time tRP(min) before the Refresh Command can be applied. The refresh addressing is generated by
the internal refresh controller. This makes the address bits “Don’t Care” during a Refresh command. An internal
address counter suppliers the address during the refresh cycle. No control of the external address bus is required
once this cycle has started. When the refresh cycle has completed, all banks of the SDRAM will be in the
precharged (idle) state. A delay between the Refresh Command and the next valid command, except NOP or DES,
must be greater than or equal to the minimum Refresh cycle time tRFC(min).
In general, a Refresh command needs to be issued to the DDR3L SDRAM regularly every tREFI interval. To allow
for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is
provided. A maximum of 8 Refresh commands can be postponed during operation of the DDR3L SDRAM, meaning
that at no point in time more than a total of 8 Refresh commands are allowed to be postponed. In case that 8
Refresh commands are postponed in a row, the resulting maximum interval between the surrounding Refresh
commands is limited to 9 x tREFI. A maximum of 8 additional Refresh commands can be issued in advance (“pulled
in”), with each one reducing the number of regular Refresh commands required later by one. Note that pulling in
more than 8 Refresh commands in advance does not further reduce the number of regular Refresh commands
required later, so that the resulting maximum interval between two surrounding Refresh command is limited to 9 x
tREFI. Before entering Self-Refresh Mode, all postponed Refresh commands must be executed.
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Self-Refresh Operation
The Self-Refresh command can be used to retain data in the DDR3L SDRAM, even if the reset of the system is
powered down. When in the Self-Refresh mode, the DDR3L SDRAM retains data without external clocking. The
DDR3L SDRAM device has a built-in timer to accommodate Self-Refresh operation. The Self-Refresh Entry (SRE)
Command is defined by having CS#, RAS#, CAS#, and CKE held low with WE# high at the rising edge of the clock.
Before issuing the Self-Refreshing-Entry command, the DDR3L SDRAM must be idle with all bank precharge state
with tRP satisfied. Also, on-die termination must be turned off before issuing Self-Refresh-Entry command, by either
registering ODT pin low “ODTL + 0.5tCK” prior to the Self-Refresh Entry command or using MRS to MR1 command.
Once the Self-Refresh Entry command is registered, CKE must be held low to keep the device in Self-Refresh mode.
During normal operation (DLL on), MR1 (A0=0), the DLL is automatically disabled upon entering Self- Refresh and is
automatically enabled (including a DLL-RESET) upon exiting Self-Refresh.
When the DDR3L SDRAM has entered Self-Refresh mode, all of the external control signals, except CKE and
RESET#, are “don’t care”. For proper Self-Refresh operation, all power supply and reference pins (VDD, VDDQ,
VSS, VSSQ, VRefCA, and VRefDQ) must be at valid levels. The DRAM initiates a minimum of one Refresh
command internally within tCKE period once it enters Self-Refresh mode.
The clock is internally disabled during Self-Refresh operation to save power. The minimum time that the DDR3L
SDRAM must remain in Self-Refresh mode is tCKE. The user may change the external clock frequency or halt the
external clock tCKSRE after Self-Refresh entry is registered; however, the clock must be restarted and stable
tCKSRX before the device can exit Self-Refresh mode.
The procedure for exiting Self-Refresh requires a sequence of events. First, the clock must be stable prior to CKE
going back HIGH. Once a Self-Refresh Exit Command (SRX, combination of CKE going high and either NOP or
Deselect on command bus) is registered, a delay of at least tXS must be satisfied before a valid command not
requiring a locked DLL can be issued to the device to allow for any internal refresh in progress. Before a command
which requires a locked DLL can be applied, a delay of at least tXSDLL and applicable ZQCAL function
requirements [TBD] must be satisfied. Before a command that requires a locked DLL can be applied, a delay of at
least tXSDLL must be satisfied.
Depending on the system environment and the amount of time spent in Self-Refresh, ZQ calibration commands may
be required to compensate for the voltage and temperature drift as described in “ZQ Calibration Commands”. To
issue ZQ calibration commands, applicable timing requirements must be satisfied.
CKE must remain HIGH for the entire Self-Refresh exit period tXSDLL for proper operation except for Self-Refresh
re-entry. Upon exit from Self-Refresh, the DDR3L SDRAM can be put back into Self-Refresh mode after waiting at
least tXS period and issuing one refresh command (refresh period of tRFC). NOP or deselect commands must be
registered on each positive clock edge during the Self-Refresh exit interval tXS. ODT must be turned off during
tXSDLL. The use of Self-Refresh mode instructs the possibility that an internally times refresh event can be missed
when CKE is raised for exit from Self-Refresh mode. Upon exit from Self-Refresh, the DDR3L SDRAM requires a
minimum of one extra refresh command before it is put back into Self-Refresh mode.
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Power-Down Modes
Power-Down Entry and Exit
Power-Down is synchronously entered when CKE is registered low (along with NOP or Deselect command). CKE is
not allowed to go low while mode register set command, MPR operations, ZQCAL operations, DLL locking or
read/write operation are in progress. CKE is allowed to go low while any of other operation such as row activation,
precharge or auto precharge and refresh are in progress, but power-down IDD spec will not be applied until finishing
those operation.
The DLL should be in a locked state when power-down is entered for fastest power-down exit timing. If the DLL is
not locked during power-down entry, the DLL must be reset after exiting power-down mode for proper read operation
and synchronous ODT operation. DRAM design provides all AC and DC timing and voltage specification as well
proper DLL operation with any CKE intensive operations as long as DRAM controller complies with DRAM
specifications.
During Power-Down, if all banks are closed after any in progress commands are completed, the device will be in
precharge Power-Down mode; if any bank is open after in progress commands are completed, the device will be in
active Power-Down mode.
Entering Power-down deactivates the input and output buffers, excluding CK, CK, ODT, CKE, and RESET#. To
protect DRAM internal delay on CKE line to block the input signals, multiple NOP or Deselect commands are needed
during the CKE switch off and cycle(s) after, this timing period are defined as tCPDED. CKE_low will result in
deactivation of command and address receivers after tCPDED has expired.
Table 24. Power-Down Entry Definitions
Status of DRAM
MRS bit A12
DLL
PD Exit
Relevant Parameters
Active
(A Bank or more open)
Don't Care
On
Fast
tXP to any valid command.
Precharged
(All Banks Precharged)
0
Off
Slow
tXP to any valid command. Since it is in
precharge state, commands here will be ACT,
AR, MRS/EMRS, PR or PRA.
tXPDLL to commands who need DLL to
operate, such as RD, RDA or ODT control line.
Precharged
(All Banks Precharged)
1
On
Fast
tXP to any valid command.
Also the DLL is disabled upon entering precharge power-down (Slow Exit Mode), but the DLL is kept enabled during
precharge power-down (Fast Exit Mode) or active power-down. In power-down mode, CKE low, RESET# high, and a
stable clock signal must be maintained at the inputs of the DD3 SDRAM, and ODT should be in a valid state but all
other input signals are “Don’t care” (If RESET# goes low during Power-Down, the DRAM will be out of PD mode and
into reset state).
CKE low must be maintain until tCKE has been satisfied. Power-down duration is limited by 9 times tREFI of the
device. The power-down state is synchronously exited when CKE is registered high (along with a NOP or Deselect
command).CKE high must be maintained until tCKE has been satisfied. A valid, executable command can be
applied with power-down exit latency, tXP and/or tXPDLL after CKE goes high. Power-down exit latency is defined at
AC spec table of this datasheet.
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On-Die Termination (ODT)
ODT (On-Die Termination) is a feature of the DDR3L SDRAM that allows the DRAM to turn on/off termination
resistance. For x16 configuration, ODT is applied to each DQU, DQL, DQSU, DQSU#, DQSL, DQSL#, DMU and
DML signal via the ODT control pin. The ODT feature is designed to improve signal integrity of the memory channel
by allowing the DRAM controller to independently turn on/off termination resistance for any or all DRAM devices.
More details about ODT control modes and ODT timing modes can be found further down in this document.
The ODT feature is turned off and not supported in Self-Refresh mode.
A simple functional representation of the DRAM ODT feature is shown as below.
Figure 21. Functional representation of ODT
To other circuitry
like RCV,...
DQ, DQS, DM
ODT
VDDQ / 2
RTT
Switch
The switch is enabled by the internal ODT control logic, which uses the external ODT pin and other control
information. The value of RTT is determined by the settings of Mode Register bits. The ODT pin will be ignored if the
Mode Register MR1 and MR2 are programmed to disable ODT and in self-refresh mode.
ODT Mode Register and ODT Truth Table
The ODT Mode is enabled if either of MR1 {A2, A6, A9} or MR2 {A9, A10} are non-zero. In this case, the value of
RTT is determined by the settings of those bits.
Application: Controller sends WR command together with ODT asserted.
One possible application: The rank that is being written to provides termination.
DRAM turns ON termination if it sees ODT asserted (except ODT is disabled by MR)
DRAM does not use any write or read command decode information.
Table 25. Termination Turth Table
ODT pin
DRAM Termination State
0
OFF
1
On, (Off, if disabled by MR1 (A2, A6, A9) and MR2 (A9, A10) in gereral)
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Synchronous ODT Mode
Synchronous ODT mode is selected whenever the DLL is turned on and locked. Based on the power-down definition,
these modes are:
- Any bank active with CKE high
- Refresh with CKE high
- Idle mode with CKE high
- Active power down mode (regardless of MR0 bit A12)
- Precharge power down mode if DLL is enabled during precharge power down by MR0 bit A12
The direct ODT feature is not supported during DLL-off mode. The on-die termination resistors must be disabled by
continuously registering the ODT pin low and/or by programming the RTT_Nom bits MR1{A9,A6,A2} to {0,0,0} via a
mode register set command during DLL-off mode.
In synchronous ODT mode, RTT will be turned on ODTLon clock cycles after ODT is sampled high by a rising clock
edge and turned off ODTLoff clock cycles after ODT is registered low by a rising clock edge. The ODT latency is tied
to the write latency (WL) by: ODTLon = WL - 2; ODTLoff = WL-2.
ODT Latency and Posted ODT
In synchronous ODT Mode, the Additive Latency (AL) programmed into the Mode Register (MR1) also applies to the
ODT signal. The DRAM internal ODT signal is delayed for a number of clock cycles defined by the Additive Latency
(AL) relative to the external ODT signal. ODTLon = CWL + AL - 2; ODTLoff = CWL + AL - 2. For details, refer to
DDR3L SDRAM latency definitions.
Table 26. ODT Latency
Symbol
Parameter
DDR3L-1600
Unit
ODTLon
ODT turn on
Latency
WL – 2 = CWL + AL -2
tCK
ODTLoff
ODT turn off
Latency
WL – 2 = CWL + AL -2
tCK
Timing Parameters
In synchronous ODT mode, the following timing parameters apply: ODTLon, ODTLoff, tAON min/max, tAOF min/max.
Minimum RTT turn-on time (tAON min) is the point in time when the device leaves high impedance and ODT
resistance begins to turn on. Maximum RTT turn-on time (tAON max) is the point in time when the ODT resistance is
fully on. Both are measured from ODTLon.
Minimum RTT turn-off time (tAOF min) is the point in time when the device starts to turn off the ODT resistance.
Maximum RTT turn off time (tAOF max) is the point in time when the on-die termination has reached high
impedance. Both are measured from ODTLoff.
When ODT is asserted, it must remain high until ODTH4 is satisfied. If a Write command is registered by the
SDRAM with ODT high, then ODT must remain high until ODTH4 (BL=4) or ODTH8 (BL=8) after the write command.
ODTH4 and ODTH8 are measured from ODT registered high to ODT registered low or from the registration of a
write command until ODT is registered low.
ODT during Reads
As the DDR3L SDRAM cannot terminate and drive at the same time, RTT must be disabled at least half a clock
cycle before the read preamble by driving the ODT pin low appropriately. RTT may not be enabled until the end of
the post-amble as shown in the following figure. DRAM turns on the termination when it stops driving which is
determined by tHZ. If DRAM stops driving early (i.e. tHZ is early), then tAONmin time may apply. If DRAM stops
driving late (i.e. tHZ is late), then DRAM complies with tAONmax timing. Note that ODT may be disabled earlier
before the Read and enabled later after the Read than shown in this example.
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Figure 22. ODT must be disabled externally during Reads by driving ODT low
(CL=6; AL=CL-1=5; RL=AL+CL=11; CWL=5; ODTLon=CWL+AL-2=8; ODTLoff=CWL+AL-2=8)
NOPREAD NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
CK#
CK
T12 T13 T14
NOP NOP NOP
Don't CareTRANSITIONING DATA
T15
NOP
ODT
T16 T17
NOP NOP
ODTLon = CWL + AL - 2
ODTLoff = CWL + AL - 2
RL = AL + CL
tAOF(min)
tAOF(max) tAON(max)
VALID
RTT RTT_NOM RTT_NOM
Din
b
Din
b+1
Din
b+2
Din
b+3
Din
b+4
Din
b+5
Din
b+6
DQ
COMMAND
ADDRESS
DQS, DQS#
Din
b+7
Dynamic ODT
In certain application cases and to further enhance signal integrity on the data bus, it is desirable that the termination
strength of the DDR3L SDRAM can be changed without issuing an MRS command. This requirement is supported
by the “Dynamic ODT” feature as described as follows:
Functional Description
The Dynamic ODT Mode is enabled if bit (A9) or (A10) of MR2 is set to ‘1’. The function is described as follows:
Two RTT values are available: RTT_Nom and RTT_WR.
- The value for RTT_Nom is preselected via bits A[9,6,2] in MR1.
- The value for RTT_WR is preselected via bits A[10,9] in MR2.
During operation without write commands, the termination is controlled as follows:
- Nominal termination strength RTT_Nom is selected.
- Termination on/off timing is controlled via ODT pin and latencies ODTLon and ODTLoff.
When a Write command (WR, WRA, WRS4, WRS8, WRAS4, WRAS8) is registered, and if Dynamic ODT is
enabled, the termination is controlled as follows:
- A latency ODTLcnw after the write command, termination strength RTT_WR is selected.
- A latency ODTLcwn8 (for BL8, fixed by MRS or selected OTF) or ODTLcwn4 (for BC4, fixed by MRS or selected
OTF) after the write command, termination strength RTT_Nom is selected.
- Termination on/off timing is controlled via ODT pin and ODTLon, ODTLoff.
The following table shows latencies and timing parameters which are relevant for the on-die termination control in
Dynamic ODT mode.
The dynamic ODT feature is not supported at DLL-off mode. User must use MRS command to set RTT_WR, MR2
[A10,A9 = [0,0], to disable Dynamic ODT externally.
When ODT is asserted, it must remain high until ODTH4 is satisfied. If a Write command is registered by the
SDRAM with ODT high, then ODT must remain high until ODTH4 (BL=4) or ODTH8 (BL=8) after the Write
command. ODTH4 and ODTH8 are measured from ODT registered high to ODT registered low or from the
registration of Write command until ODT is register low.
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Table 27. Latencies and timing parameters relevant for Dynamic ODT
Name and
Description
Abbr.
Defined from
Defined to
Definition for all DDR3L
speed pin
Unit
ODT turn-on
Latency
ODTLon
registering external
ODT signal high
turning
termination on
ODTLon=WL-2
tCK
ODT turn-off
Latency
ODTLoff
registering external
ODT signal low
turning
termination off
ODTLoff=WL-2
tCK
ODT Latency for
changing from
RTT_Nom to
RTT_WR
ODTLcnw
registering external
write command
change RTT
strength from
RTT_Nom to
RTT_WR
ODTLcnw=WL-2
tCK
ODT Latency for
change from
RTT_WR to
RTT_Nom (BL=4)
ODTLcwn4
registering external
write command
change RTT
strength from
RTT_WR to
RTT_Nom
ODTLcwn4=4+ODTLoff
tCK
ODT Latency for
change from
RTT_WR to
RTT_Nom (BL=8)
ODTLcwn8
registering external
write command
change RTT
strength from
RTT_WR to
RTT_Nom
ODTLcwn8=6+ODTLoff
tCK (avg)
Minimum ODT high time
after ODT assertion
ODTH4
registering ODT high
ODT registered
low
ODTH4=4
tCK (avg)
Minimum ODT
high time
after Write (BL=4)
ODTH4
registering write with
ODT high
ODT registered
low
ODTH4=4
tCK (avg)
Minimum ODT
high time
after Write (BL=8)
ODTH8
registering write with
ODT high
ODT register
low
ODTH8=6
tCK (avg)
RTT change skew
tADC
ODTLcnw
ODTLcwn
RTT valid
tADC(min)=0.3tCK(avg)
tADC(max)=0.7tCK(avg)
tCK (avg)
Note 1: tAOF, nom and tADC, nom are 0.5tCK (effectively adding half a clock cycle to ODTLoff, ODTcnw, and ODTLcwn)
Asynchronous ODT Mode
Asynchronous ODT mode is selected when DRAM runs in DLLon mode, but DLL is temporarily disabled (i.e. frozen)
in precharge power-down (by MR0 bit A12). Based on the power down mode definitions, this is currently Precharge
power down mode if DLL is disabled during precharge power down by MR0 bit A12.
In asynchronous ODT timing mode, internal ODT command is NOT delayed by Additive Latency (AL) relative to the
external ODT command.
In asynchronous ODT mode, the following timing parameters apply: tAONPD min/max, tAOFPD min/max.
Minimum RTT turn-on time (tAONPD min) is the point in time when the device termination circuit leaves high
impedance state and ODT resistance begins to turn on. Maximum RTT turn on time (tAONPD max) is the point in
time when the ODT resistance is fully on.
tAONPDmin and tAONPDmax are measured from ODT being sampled high.
Minimum RTT turn-off time (tAOFPDmin) is the point in time when the devices termination circuit starts to turn off
the ODT resistance. Maximum ODT turn off time (tAOFPDmax) is the point in time when the on-die termination has
reached high impedance. tAOFPDmin and tAOFPDmax are measured from ODT being sample low.
Table 28. ODT timing parameters for Power Down (with DLL frozen) entry and exit
Description
Min
Max
ODT to RTT
turn-on delay
min{ ODTLon * tCK + tAONmin; tAONPDmin }
min{ (WL - 2) * tCK + tAONmin; tAONPDmin }
max{ ODTLon * tCK + tAONmax; tAONPDmax }
max{ (WL - 2) * tCK + tAONmax; tAONPFmax }
ODT to RTT
turn-off delay
min{ ODTLoff * tCK + tAOFmin; tAOFPDmin }
min{ (WL - 2) * tCK + tAOFmin; tAOFPDmin }
max{ ODTLoff * tCK + tAOFmax; tAOFPDmax }
max{ (WL - 2) * tCK + tAOFmax; tAOFPDmax }
tANPD
WL - 1
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Synchronous to Asynchronous ODT Mode Transition during Power-Down Entry
If DLL is selected to be frozen in Precharge Power Down Mode by the setting of bit A12 in MR0 to “0”, there is a
transition period around power down entry, where the DDR3L SDRAM may show either synchronous or
asynchronous ODT behavior.
The transition period is defined by the parameters tANPD and tCPDED(min). tANPD is equal to (WL-1) and is
counted backwards in time from the clock cycle where CKE is first registered low. tCPDED(min) starts with the clock
cycle where CKE is first registered low. The transition period begins with the starting point of tANPD and terminates
at the end point of tCPDED(min). If there is a Refresh command in progress while CKE goes low, then the transition
period ends at the later one of tRFC(min) after the Refresh command and the end point of tCPDED(min). Please
note that the actual starting point at tANPD is excluded from the transition period, and the actual end point at
tCPDED(min) and tRFC(min, respectively, are included in the transition period.
ODT assertion during the transition period may result in an RTT changes as early as the smaller of tAONPDmin and
(ODTLon*tck+tAONmin) and as late as the larger of tAONPDmax and (ODTLon*tCK+tAONmax). ODT de-assertion
during the transition period may result in an RTT change as early as the smaller of tAOFPDmin and
(ODTLoff*tCK+tAOFmin) and as late as the larger of tAOFPDmax and (ODTLoff*tCK+tAOFmax). Note that, if AL
has a large value, the range where RTT is uncertain becomes quite large. The following figure shows the three
different cases: ODT_A, synchronous behavior before tANPD; ODT_B has a state change during the transition
period; ODT_C shows a state change after the transition period.
Asynchronous to Synchronous ODT Mode transition during Power-Down Exit
If DLL is selected to be frozen in Precharge Power Down Mode by the setting of bit A12 in MR0 to “0”, there is also a
transition period around power down exit, where either synchronous or asynchronous response to a change in ODT
must be expected from the DDR3L SDRAM.
This transition period starts tANPD before CKE is first registered high, and ends tXPDLL after CKE is first registered
high. tANPD is equal to (WL -1) and is counted (backwards) from the clock cycle where CKE is first registered high.
ODT assertion during the transition period may result in an RTT change as early as the smaller of tAONPDmin and
(ODTLon* tCK+tAONmin) and as late as the larger of tAONPDmax and (ODTLon*tCK+tAONmax). ODT de-
assertion during the transition period may result in an RTT change as early as the smaller of tAOFPDmin and
(ODTLoff*tCK+tAOFmin) and as late as the larger of tAOFPDmax and (ODToff*tCK+tAOFmax). Note that if AL has
a large value, the range where RTT is uncertain becomes quite large. The following figure shows the three different
cases: ODT_C, asynchronous response before tANPD; ODT_B has a state change of ODT during the transition
period; ODT_A shows a state change of ODT after the transition period with synchronous response.
Asynchronous to Synchronous ODT Mode during short CKE high and short CKE low periods
If the total time in Precharge Power Down state or Idle state is very short, the transition periods for PD entry and PD
exit may overlap. In this case, the response of the DDR3L SDRAMs RTT to a change in ODT state at the input may
be synchronous or asynchronous from the state of the PD entry transition period to the end of the PD exit transition
period (even if the entry ends later than the exit period).
If the total time in Idle state is very short, the transition periods for PD exit and PD entry may overlap. In this case,
the response of the DDR3L SDRAMs RTT to a change in ODT state at the input may be synchronous or
asynchronous from the state of the PD exit transition period to the end of the PD entry transition period. Note that in
the following figure, it is assumed that there was no Refresh command in progress when Idle state was entered.
!
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ZQ Calibration Commands
ZQ Calibration Description
ZQ Calibration command is used to calibrate DRAM Ron and ODT values. DDR3L SDRAM needs longer time to
calibrate output driver and on-die termination circuits at initialization and relatively smaller time to perform periodic
calibrations.
ZQCL command is used to perform the initial calibration during power-up initialization sequence. This command may
be issued at any time by the controller depending on the system environment. ZQCL command triggers the
calibration engine inside the DRAM and once calibration is achieved the calibrated values are transferred from
calibration engine to DRAM IO which gets reflected as updated output driver and on-die termination values.
The first ZQCL command issued after reset is allowed a timing period of tZQinit to perform the full calibration and
the transfer of values. All other ZQCL commands except the first ZQCL command issued after RESET is allowed a
timing period of tZQoper.
ZQCS command is used to perform periodic calibrations to account for voltage and temperature variations. A shorter
timing window is provided to perform the calibration and transfer of values as defined by timing parameter tZQCS.
No other activities should be performed on the DRAM channel by the controller for the duration of tZQinit, tZQoper,
or tZQCS. The quiet time on the DRAM channel allows calibration of output driver and on-die termination values.
Once DRAM calibration is achieved, the DRAM should disable ZQ current consumption path to reduce power.
All banks must be precharged and tRP met before ZQCL or ZQCS commands are issued by the controller.
ZQ calibration commands can also be issued in parallel to DLL lock time when coming out of self refresh. Upon self-
refresh exit, DDR3L SDRAM will not perform an IO calibration without an explicit ZQ calibration command. The
earliest possible time for ZQ Calibration command (short or long) after self refresh exit is tXS.
In systems that share the ZQ resistor between devices, the controller must not allow any overlap of tZQoper, tZQinit,
or tZQCS between ranks.
Figure 23. ZQ Calibration Timing
CK# T1 Ta0 Ta1 Ta2 Ta3T0
CK
CKE
NOPZQCL NOP VALID
tZQinit or tZQoper
Don't CareTIME BREAK
VALID
Tb0 Tb1
ZQCS NOP
tZQCS
Tc0 Tc1
NOP NOP
ADDRESS
NOTES:
1. CKE must be continuously registered high during the calibration procedure.
2. On-die termination must be disabled via the ODT signal or MRS during the calibration procedure.
3. All devices connected to the DQ bus should be high impedance during the calibration procedure.
Tc2
NOP VALID
VALID VALID VALID
A10 VALID VALID VALID
VALID
VALID VALID
Notes 1
ODT VALID
VALID VALID
Notes 2
Hi-Z ACTIVITIES Hi-Z
Notes 3
COMMAND
DQ Bus ACTIVITIES
Notes 1
Notes 2
Notes 3
ZQ External Resistor Value, Tolerance, and Capacitive loading
In order to use the ZQ calibration function, a 240 ohm ±1% tolerance external resistor connected between the ZQ
pin and ground. The single resistor can be used for each SDRAM or one resistor can be shared between two
SDRAMs if the ZQ calibration timings for each SDRAM do not overlap. The total capacitive loading on the ZQ pin
must be limited.
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- Single-ended requirements for differential signals
Each individual component of a differential signal (CK, CK#, LDQS, UDQS, LDQS#, or UDQS#) has also to comply
with certain requirements for single-ended signals.
CK and CK# have to approximately reach VSEHmin / VSELmax (approximately equal to the ac-levels (VIH(ac) /
VIL(ac)) for ADD/CMD signals) in every half-cycle. LDQS, UDQS, LDQS#, UDQS# have to reach VSEHmin / VSELmax
(approximately the ac-levels (VIH(ac) / VIL(ac)) for DQ signals) in every half-cycle proceeding and following a valid
transition.
Note that the applicable ac-levels for ADD/CMD and DQ’s might be different per speed-bin etc. E.g., if VIH135(ac) /
VIL135(ac) is used for ADD/CMD signals, then these ac-levels apply also for the single-ended signals CK and CK#.
Table 29. Single-ended levels for CK, DQSL, DQSU, CK#, DQSL# or DQSU#
Symbol
Parameter
Min.
Max.
Unit
Note
VSEH
Single-ended high level for strobes
(VDD / 2) + 0.175
Note 3
V
1,2
Single-ended high level for CK, CK#
(VDD / 2) + 0.175
Note 3
V
1,2
VSEL
Single-ended low level for strobes
Note 3
(VDD / 2) - 0.175
V
1,2
Single-ended low level for CK, CK#
Note 3
(VDD / 2) - 0.175
V
1,2
Note 1. For CK, CK# use VIH/VIL(ac) of ADD/CMD; for strobes (DQSL, DQSL#, DQSU, DQSU#) use VIH/VIL(ac) of DQs.
Note 2. VIH(ac)/VIL(ac) for DQs is based on VREFDQ; VIH(ac)/VIL(ac) for ADD/CMD is based on VREFCA; if a reduced ac-
high or ac-low level is used for a signal group, then the reduced level applies also here.
Note 3. These values are not defined, however the single-ended signals CK, CK#, DQSL, DQSL#, DQSU, DQSU# need to be
within the respective limits (VIH(dc) max, VIL(dc)min) for single-ended signals as well as the limitations for overshoot
and undershoot.
- Differential Input Cross Point Voltage
To guarantee tight setup and hold times as well as output skew parameters with respect to clock and strobe, each
cross point voltage of differential input signals (CK, CK# and DQS, DQS#) must meet the requirements in the
following table. The differential input cross point voltage Vix is measured from the actual cross point of true and
complete signal to the midlevel between of VDD and VSS.
Table 30. Cross point voltage for differential input signals (CK, DQS)
Symbol
Parameter
Min.
Max.
Unit
Note
VIX(CK)
Differential Input Cross Point Voltage
relative to VDD/2 for CK, CK#
-150
150
mV
1
VIX(DQS)
Differential Input Cross Point Voltage
relative to VDD/2 for DQS, DQS#
-150
150
mV
1
Note 1. The relation between Vix Min/Max and VSEL/VSEH should satisfy following.
(VDD/2) + Vix (Min) - VSEL ≧ 25mV
VSEH - ((VDD/2) + Vix (Max)) ≧ 25mV
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- Slew Rate Definition for Differential Input Signals
Input slew rate for differential signals (CK, CK# and DQS, DQS#) are defined and measured as shown below.
Table 31. Differential Input Slew Rate Definition
Description
Measured
Defined by
From
To
Differential input slew rate for rising edge
(CK, CK# and DQS, DQS#)
VILdiffmax
VIHdiffmin
[VIHdiffmin-VILdiffmax] /
DeltaTRdiff
Differential input slew rate for falling edge
(CK, CK# and DQS, DQS#)
VIHdiffmin
VILdiffmax
[VIHdiffmin-VILdiffmax] /
DeltaTFdiff
NOTE: The differential signal (i.e., CK, CK# and DQS, DQS#) must be linear between these thresholds.
Table 32. Single-ended AC and DC Output Levels
Symbol
Parameter
Values
Unit
Note
VOH(DC)
DC output high measurement level (for IV curve linearity)
0.8 x VDDQ
V
VOM(DC)
DC output mid measurement level (for IV curve linearity)
0.5 x VDDQ
V
VOL(DC)
DC output low measurement level (for IV curve linearity)
0.2 x VDDQ
V
VOH(AC)
AC output high measurement level (for output SR)
VTT + 0.1 x VDDQ
V
1
VOL(AC)
AC output low measurement level (for output SR)
VTT - 0.1 x VDDQ
V
1
NOTE 1: The swing of ± 0.1 × VDDQ is based on approximately 50% of the static single-ended output high or low swing with a
driver impedance of 40 Ω and an effective test load of 25 Ω to VTT = VDDQ/2.
Table 33. Differential AC and DC Output Levels
Symbol
Parameter
Values
Unit
Note
VOHdiff(AC)
AC differential output high measurement level (for output SR)
+ 0.2 x VDDQ
V
1
VOLdiff(AC)
AC differential output low measurement level (for output SR)
- 0.2 x VDDQ
V
1
NOTE 1: The swing of ± 0.2 × VDDQ is based on approximately 50% of the static single-ended output high or low swing with a
driver impedance of 40 Ω and an effective test load of 25 Ω to VTT = VDDQ/2 at each of the differential outputs.
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- Single Ended Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and
measured between VOL(AC) and VOH(AC) for single ended signals as shown in Table.
Table 34. Output Slew Rate Definition (Single-ended)
Description
Measured
Defined by
From
To
Single-ended output slew rate for rising edge
VOL(AC)
VOH(AC)
[VOH(AC) - VOL(AC)] /
DeltaTRse
Single-ended output slew rate for falling edge
VOH(AC)
VOL(AC)
[VOH(AC) - VOL(AC)] /
DeltaTFse
NOTE: Output slew rate is verified by design and characterization, and may not be subject to production test.
Table 35. Output Slew Rate (Single-ended)
Symbol
Parameter
DDR3L-1600
Unit
Min.
Max.
SRQse
Single-ended Output Slew Rate
1.75
5(1)
V/ns
Description:
SR: Slew Rate
Q: Query Output (like in DQ, which stands for Data-in, Query-Output)
se: Single-ended Signals
For Ron = RZQ/7 setting
NOTE1: In two cases, a maximum slew rate of 6V/ns applies for a single DQ signal within a byte lane.
Case 1 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to
low or low to high) while all remaining DQ signals in the same byte lane are static (i.e. they stay at either high or low).
Case 2 is defined for a single DQ signal within a byte lane which is switching into a certain direction (either from high to
low or low to high) while all remaining DQ signals in the same byte lane are switching into the opposite direction (i.e.
from low to high or high to low respectively). For the remaining DQ signal switching into the opposite direction, the
regular maximum limit of 5 V/ns applies.
- Differential Output Slew Rate
With the reference load for timing measurements, output slew rate for falling and rising edges is defined and
measured between VOLdiff(AC) and VOHdiff(AC) for differential signals as shown in Table.
Table 36. Output Slew Rate Definition (Differential)
Description
Measured
Defined by
From
To
Differential output slew rate for rising edge
VOLdiff(AC)
VOHdiff(AC)
[VOHdiff(AC) - VOLdiff(AC)] /
DeltaTRdiff
Differential output slew rate for falling edge
VOHdiff(AC)
VOLdiff(AC)
[VOHdiff(AC) - VOLdiff(AC)] /
DeltaTFdiff
NOTE: Output slew rate is verified by design and characterization, and may not be subject to production test.
Table 37. Output Slew Rate (Differential)
Symbol
Parameter
DDR3L-1600
Unit
Min.
Max.
SRQdiff
Differential Output Slew Rate
3.5
12
V/ns
Description:
SR: Slew Rate
Q: Query Output (like in DQ, which stands for Data-in, Query-Output)
diff: Differential Signals
For Ron = RZQ/7 setting
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Reference Load for AC Timing and Output Slew Rate
The following figure represents the effective reference load of 25 ohms used in defining the relevant AC timing
parameters of the device as well as output slew rate measurements.
It is not intended as a precise representation of any particular system environment or a depiction of the actual load
presented by a production tester. System designers should use IBIS or other simulation tools to correlate the timing
reference load to a system environment. Manufacturers correlate to their production test conditions, generally one or
more coaxial transmission lines terminated at the tester electronics.
Figure 24. Reference Load for AC Timing and Output Slew Rate
DUT
DQ
DQS
DQS#
VDDQ
CK, CK# 25 Ohm
VTT = VDDQ/2
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Table 38. AC Overshoot/Undershoot Specification for Address and Control Pins
Parameter -12 Unit
Maximum peak amplitude allowed for overshoot area.
0.4
V
Maximum peak amplitude allowed for undershoot area.
0.4
V
Maximum overshoot area above VDD
0.33
V-ns
Maximum undershoot area below VSS
0.33
V-ns
Figure 25. AC Overshoot/Undershoot Specification for Address and Control Pins
VDD
Maximum
Amplitude
Undershoot
Area
Time (ns)
Volts (V)
Overshoot
Area
Maximum
Amplitude
VSS
Table 39. AC Overshoot/Undershoot Specification for Clock, Data, Strobe and Mask
Parameter -12 Unit
Maximum peak amplitude allowed for overshoot area.
0.4
V
Maximum peak amplitude allowed for undershoot area.
0.4
V
Maximum overshoot area above VDD
0.13
V-ns
Maximum undershoot area below VSS
0.13
V-ns
Figure 26. Clock, Data, Strobe and Mask Overshoot and Undershoot Definition
VDDQ
Maximum
Amplitude
Undershoot
Area
Time (ns)
Volts (V)
Overshoot
Area
Maximum
Amplitude
VSSQ
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- Address / Command Setup, Hold and Derating
For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet
tIS(base) and tIH(base) and tIH(base) value to the delta tIS and delta tIH derating value respectively.
Example: tIS (total setup time) = tIS(base) + delta tIS.
Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of Vref(dc) and
the first crossing of VIH(ac)min. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between
the last crossing of Vref(dc) and the first crossing of VIL(ac)max. If the actual signal is always earlier than the
nominal slew rate line between shaded ‘Vref(dc) to ac region’, use nominal slew rate for derating value. If the actual
signal is later than the nominal slew rate line anywhere between shaded ‘Vref(dc) to ac region’, the slew rate of the
tangent line to the actual signal from the ac level to dc level is used for derating value.
Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max
and the first crossing of Vref(dc). Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between
the last crossing of VIH(dc)min and the first crossing of Vref(dc). If the actual signal is always later than the nominal
slew rate line between shaded ‘dc to Vref(dc) region’, use nominal slew rate for derating value. If the actual signal is
earlier than the nominal slew rate line anywhere between shaded ‘dc to Vref(dc) region’, the slew rate of a tangent
line to the actual signal from the dc level to Vref(dc) level is used for derating value.
For a valid transition the input signal has to remain above/below VIH/IL(ac) for some time tVAC.
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached
VIH/IL(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and
reach VIH/IL(ac).
For slew rates in between the values listed in the following tables, the derating values may be obtained by linear
interpolation.
These values are typically not subject to production test. They are verified by design and characterization
Table 40. ADD/CMD Setup and Hold Base
Symbol
Reference
-12
Unit
tIS(base) AC160
VIH/L(ac)
60
ps
tIS(base) AC135
VIH/L(ac)
185
ps
tIH(base) DC90
VIH/L(dc)
130
ps
NOTE 1: (ac/dc referenced for 1V/ns Address/Command slew rate and 2 V/ns differential CK-CK# slew rate)
NOTE 2: The tIS(base) AC135 specifications are adjusted from the tIS(base) AC160 specification by adding an additional 100ps
of derating to accommodate for the lower alternate threshold of 135 mV and another 25 ps to account for the earlier
reference point [(160 mv - 135 mV) / 1 V/ns].
Table 41. Derating values DDR3L-1600 tIS/tIH – (AC160)
△tIS, △tIH derating in [ps] AC/DC based AC160 Threshold -> VIH(ac)=VREF(dc)+160mV, VIL(ac)=VREF(dc)-160mV
CK, CK# Differential Slew Rate
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
△tIS
△tIH
△tIS
△tIH
△tIS
△tIH
△tIS
△tIH
△tIS
△tIH
△tIS
△tIH
△tIS
△tIH
△tIS
△tIH
CMD/
ADD
Slew
Rate
V/ns
2.0
80
45
80
45
80
45
88
53
96
61
104
69
112
79
120
95
1.5
53
30
53
30
53
30
61
38
69
46
77
54
85
64
93
80
1.0
0
0
0
0
0
0
8
8
16
16
24
24
32
34
40
50
0.9
-1
-3
-1
-3
-1
-3
7
5
15
13
23
21
31
31
39
47
0.8
-3
-8
-3
-8
-3
-8
5
1
13
9
21
17
29
27
37
43
0.7
-5
-13
-5
-13
-5
-13
3
-5
11
3
19
11
27
21
35
37
0.6
-8
-20
-8
-20
-8
-20
0
-12
8
-4
16
4
24
14
32
30
0.5
-20
-30
-20
-30
-20
-30
-12
-22
-4
-14
4
-6
12
4
20
20
0.4
-40
-45
-40
-45
-40
-45
-32
-37
-24
-29
-16
-21
-8
-11
0
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Table 42. Derating values DDR3L-1600 tIS/tIH – (AC135)
△tIS, △tIH derating in [ps] AC/DC based Alternate AC135 Threshold -> VIH(ac)=VREF(dc)+135mV, VIL(ac)=VREF(dc)-135mV
CK, CK# Differential Slew Rate
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
△tIS
△tIH
△tIS
△tIH
△tIS
△tIH
△tIS
△tIH
△tIS
△tIH
△tIS
△tIH
△tIS
△tIH
△tIS
△tIH
CMD/
ADD
Slew
Rate
V/ns
2.0
68
45
68
45
68
45
76
53
84
61
92
69
100
79
108
95
1.5
45
30
45
30
45
30
53
38
61
46
69
54
77
64
85
80
1.0
0
0
0
0
0
0
8
8
16
16
24
24
32
34
40
50
0.9
2
-3
2
-3
2
-3
10
5
18
13
26
21
34
31
42
47
0.8
3
-8
3
-8
3
-8
11
1
19
9
27
17
35
27
43
43
0.7
6
-13
6
-13
6
-13
14
-5
22
3
30
11
38
21
46
37
0.6
9
-20
9
-20
9
-20
17
-12
25
-4
33
4
41
14
49
30
0.5
5
-30
5
-30
5
-30
13
-22
21
-14
29
-6
37
4
45
20
0.4
-3
-45
-3
-45
-3
-45
6
-37
14
-29
22
-21
30
-11
38
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- Data Setup, Hold, and Slew Rate De-rating
For all input signals the total tDS (setup time) and tDH (hold time) required is calculated by adding the data sheet
tDS(base) and tDH(base) value to the ΔtDS and ΔtDH derating value respectively.
Example: tDS (total setup time) = tDS(base) + ΔtDS.
Setup (tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of Vref(dc) and
the first crossing of VIH(ac)min. Setup (tDS) nominal slew rate for a falling signal is defined as the slew rate between
the last crossing of Vref(dc) and the first crossing of VIL(ac)max. If the actual signal is always earlier than the
nominal slew rate line between shaded ‘Vref(dc) to ac region’, use nominal slew rate for derating value. If the actual
signal is later than the nominal slew rate line anywhere between shaded ‘Vref(dc) to ac region’, the slew rate of the
tangent line to the actual signal from the ac level to dc level is used for derating value.
Hold (tDH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(dc)max
and the first crossing of Vref(dc). Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between
the last crossing of VIH(dc)min and the first crossing of Vref(dc). If the actual signal is always later than the nominal
slew rate line between shaded ‘dc level to Vref(dc) region’, use nominal slew rate for derating value. If the actual
signal is earlier than the nominal slew rate line anywhere between shaded ‘dc to Vref(dc) region’, the slew rate of a
tangent line to the actual signal from the dc level to Vref(dc) level is used for derating value.
For a valid transition the input signal has to remain above/below VIH/IL(ac) for some time tVAC.
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached
VIH/IL(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and
reach VIH/IL(ac).
For slew rates in between the values listed in the following tables, the derating values may be obtained by linear
interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
Table 43. Data Setup and Hold Base
Symbol
Reference
-12
Unit
tDS(base) AC135
VIH/L(ac)
25
ps
tDH(base) DC90
VIH/L(dc)
55
ps
NOTE 2: (ac/dc referenced for 1V/ns DQ- slew rate and 2 V/ns differential DQS slew rate)
Table 44. Derating values for DDR3L-1600 tDS/tDH – (AC135)
△tDS, △tDH derating in [ps] AC/DC based
DQS, DQS# Differential Slew Rate
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
△tDS
△tDH
DQ
Slew
Rate
V/ns
2.0
68
45
68
45
68
45
-
-
-
-
-
-
-
-
-
-
1.5
45
30
45
30
45
30
53
38
-
-
-
-
-
-
-
-
1.0
0
0
0
0
0
0
8
8
16
16
-
-
-
-
-
-
0.9
-
-
2
-3
2
-3
10
5
18
13
26
21
-
-
-
-
0.8
-
-
-
-
3
-8
11
1
19
9
27
17
35
27
-
-
0.7
-
-
-
-
-
-
14
-5
22
3
30
11
38
21
46
37
0.6
-
-
-
-
-
-
-
-
25
-4
33
4
41
14
49
30
0.5
-
-
-
-
-
-
-
-
-
-
29
-6
37
4
45
20
0.4
-
-
-
-
-
-
-
-
-
-
-
-
30
-11
38
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Timing Waveforms
Figure 27. MPR Readout of predefined pattern,BL8 fixed burst order, single readout
Don't CareTIME BREAK
MRSPREA READ NOP NOP NOP NOP NOP NOP NOP NOP MRS
tRP
NOTES:
1. RD with BL8 either by MRS or OTF.
2. Memory Controller must drive 0 on A[2:0].
T0 Ta Tb0 Tb1 Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7
CK#
CK
BA
A[1:0]
A[2]
A[11]
A12, BC#
A[9:3]
A10, AP
Tc8 Tc9 Td
MRS MRS VALID
tMOD Notes 1
tMPRR tMOD
3 VALID 3
0 0 VALID
1 0 0
00 VALID 00
0 VALID 0
0 VALID 0
0 VALID 0
0 VALID 0
A[13]
DQ
1
RL
Notes 2
Notes 2
DQS, DQS#
COMMAND
Figure 28. MPR Readout of predefined pattern,BL8 fixed burst order, back to back readout
Don't CareTIME BREAK
MRSPREA READ READ NOP NOP NOP NOP NOP NOP NOP NOP
tRP
NOTES:
1. RD with BL8 either by MRS or OTF.
2. Memory Controller must drive 0 on A[2:0].
T0 Ta Tb Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7 Tc8
CK#
CK
BA
A[1:0]
A[2]
A[11]
A12, BC#
A[9:3]
A10, AP
Tc9 Tc10 Td
NOP MRS VALID
tMOD Notes 1
tMPRR tMOD
3 VALID 3
0 0 VALID
1 0 0
00 VALID 00
0 VALID 0
0 VALID 0
0 VALID 0
0 VALID 0
A[13]
DQ
1
RL
Notes 2
Notes 2
Notes 1
tCCD
VALID
0
0
VALID
VALID
VALID
VALID
VALID
Notes 2
Notes 1 Notes 1
Notes 2
DQS, DQS#
COMMAND
RL
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Figure 29. MPR Readout of predefined pattern,BC4 lower nibble then upper nibble
Don't CareTIME BREAK
MRSPREA READ READ NOP NOP NOP NOP NOP NOP NOP MRS
tRP
NOTES:
1. RD with BC4 either by MRS or OTF.
2. Memory Controller must drive 0 on A[1:0].
3. A[2]=0 selects lower 4 nibble bits 0....3.
4. A[2]=1 selects upper 4 nibble bits 4....7.
T0 Ta Tb Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7 Tc8
CK#
CK
BA
A[1:0]
A[2]
A[11]
A12, BC#
A[9:3]
A10, AP
Tc9 Tc10 Td
NOP NOP VALID
tMOD Notes 1
tMPRR tMOD
3 VALID 3
0 0 VALID
1 0 0
00 VALID 00
0 VALID 0
0 VALID 0
0 VALID 0
0 VALID 0
A[13]
DQ
1
RL
Notes 2
Notes 3
Notes 1
tCCD
VALID
0
1
VALID
VALID
VALID
VALID
VALID
Notes 2
Notes 1 Notes 1
Notes 4
DQS, DQS#
COMMAND
RL
Figure 30. MPR Readout of predefined pattern,BC4 upper nibble then lower nibble
Don't CareTIME BREAK
MRSPREA READ READ NOP NOP NOP NOP NOP NOP NOP MRS
tRP
NOTES:
1. RD with BC4 either by MRS or OTF.
2. Memory Controller must drive 0 on A[1:0].
3. A[2]=0 selects lower 4 nibble bits 0....3.
4. A[2]=1 selects upper 4 nibble bits 4....7.
T0 Ta Tb Tc0 Tc1 Tc2 Tc3 Tc4 Tc5 Tc6 Tc7 Tc8
CK#
CK
BA
A[1:0]
A[2]
A[11]
A12, BC#
A[9:3]
A10, AP
Tc9 Tc10 Td
NOP NOP VALID
tMOD Notes 1
tMPRR tMOD
3 VALID 3
0 0 VALID
1 1 0
00 VALID 00
0 VALID 0
0 VALID 0
0 VALID 0
0 VALID 0
A[13]
DQ
1
RL
Notes 2
Notes 4
Notes 1
tCCD
VALID
0
0
VALID
VALID
VALID
VALID
VALID
Notes 2
Notes 1 Notes 1
Notes 3
DQS, DQS#
COMMAND
RL
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Figure 31. READ (BL8) to READ (BL8)
NOPREAD NOP NOP READ NOP NOP NOP NOP NOP NOP NOP
NOTES:
1. BL8, RL = 5 (CL = 5, AL = 0)
2. DOUT n (or b) = data-out from column n (or column b).
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 during READ commands at T0 and T4.
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
CK#
CK
DQ
T12 T13 T14
NOP NOP NOP
tCCD
Notes 3
Notes 4
Bank,
Col n
Bank,
Col b
Dout
n
Dout
n+1
Dout
n+2
Dout
n+3
Dout
n+4
Dout
n+5
Dout
n+6
Dout
n+7
Dout
b
Dout
b+1
Dout
b+2
Dout
b+3
Dout
b+4
Dout
b+5
Dout
b+6
Dout
b+7
tRPST
tRPRE
RL = 5 RL = 5
Don't CareTRANSITIONING DATA
Notes 2
DQS, DQS#
ADDRESS
COMMAND
Figure 32. Nonconsecutive READ (BL8) to READ (BL8)
NOPREAD NOP NOP NOP READ NOP NOP NOP NOP NOP NOP
NOTES:
1. BL8, RL = 5 (CL = 5, AL = 0), tCCD=5
2. DOUT n (or b) = data-out from column n (or column b)
3. NOP commands are shown for ease of illustration; other commands may be valid at these times
4. BL8 setting activated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 during READ commands at T0 and T4
5. DQS-DQS# is held logic low at T9
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
CK#
CK
DQ
T12 T13 T14
NOP NOP NOP
tCCD = 5
Notes 3
Notes 4
Bank,
Col n
Bank,
Col b
DO
n
DO
b
tRPST
tRPRE
RL = 5 RL = 5
Don't CareTRANSITIONING DATA
Notes 2
DQS, DQS#
ADDRESS
COMMAND
Notes 5
Figure 33. READ (BL4) to READ (BL4)
NOPREAD NOP NOP READ NOP NOP NOP NOP NOP NOP NOP
NOTES:
1. BC4, RL = 5 (CL = 5, AL = 0)
2. DOUT n (or b) = data-out from column n (or column b).
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by either MR0[A1:0 = 10] or MR0[A1:0 = 01] and A12 = 0 during READ commands at T0 and T4.
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
CK#
CK
DQ
T12 T13 T14
NOP NOP NOP
tCCD
Notes 3
Notes 4
Bank,
Col n
Bank,
Col b
Dout
n
Dout
n+1
Dout
n+2
Dout
n+3
Dout
b
Dout
b+1
Dout
b+2
Dout
b+3
tRPRE
RL = 5
RL = 5
Don't CareTRANSITIONING DATA
Notes 2
DQS, DQS#
ADDRESS
COMMAND
tRPST tRPST
tRPRE
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Figure 34. READ (BL8) to WRITE (BL8)
NOPREAD NOP NOP NOP READ NOP NOP NOP NOP NOP NOP
NOTES:
1. BL8, RL = 5 (CL = 5, AL = 0), tCCD=5
2. DOUT n (or b) = data-out from column n (or column b)
3. NOP commands are shown for ease of illustration; other commands may be valid at these times
4. BL8 setting activated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 during READ commands at T0 and T4
5. DQS-DQS# is held logic low at T9
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
CK#
CK
DQ
T12 T13 T14
NOP NOP NOP
tCCD = 5
Notes 3
Notes 4
Bank,
Col n
Bank,
Col b
DO
n
DO
b
tRPST
tRPRE
RL = 5 RL = 5
Don't CareTRANSITIONING DATA
Notes 2
DQS, DQS#
ADDRESS
COMMAND
Notes 5
Figure 35. READ (BL4) to WRITE (BL4) OTF
NOPREAD NOP NOP WRITE NOP NOP NOP NOP NOP NOP NOP
NOTES:
1. BC4, RL = 5 (CL = 5, AL = 0), WL = 5 (CWL = 5, AL = 0)
2. DOUT n = data-out from column, DIN b = data-in from column b.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by MR0[A1:0 = 01] and A12 = 0 during READ command at T0 and WRITE command at T4.
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
CK#
CK
DQ
T12 T13 T14
NOP NOP NOP
READ to WRITE Command Delay = RL + tCCD/2 + 2tCK - WL
Notes 3
Notes 4
Bank,
Col n
Bank,
Col b
Dout
n
Dout
n+1
Dout
n+2
Dout
n+3
Din
b
Din
b+1
Din
b+2
Din
b+3
tRPRE
RL = 5 WL = 5
Don't CareTRANSITIONING DATA
Notes 2
DQS, DQS#
ADDRESS
COMMAND
tRPST tWPRE
T15
NOP
tWPST
4 clocks
tWR
tWTR
Figure 36. READ (BL8) to READ (BL4) OTF
NOPREAD NOP NOP READ NOP NOP NOP NOP NOP NOP NOP
NOTES:
1. RL = 5 (CL = 5, AL = 0)
2. DOUT n (or b) = data-out from column n (or column b).
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by MR0[A1:0 = 01] and A12 = 1 during READ command at T0.
BC4 setting activated by MR0[A1:0 = 01] and A12 = 0 during READ command at T4.
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
CK#
CK
DQ
T12 T13 T14
NOP NOP NOP
tCCD
Notes 3
Notes 4
Bank,
Col n
Bank,
Col b
Dout
n
Dout
n+1
Dout
n+2
Dout
n+3
Dout
b
Dout
b+1
Dout
b+2
Dout
b+3
tRPRE
RL = 5
RL = 5
Don't CareTRANSITIONING DATA
Notes 2
DQS, DQS#
ADDRESS
COMMAND
tRPST
Dout
n+4
Dout
n+5
Dout
n+6
Dout
n+7
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Figure 37. READ (BL4) to READ (BL8) OTF
NOPREAD NOP NOP READ NOP NOP NOP NOP NOP NOP NOP
NOTES:
1. RL = 5 (CL = 5, AL = 0)
2. DOUT n (or b) = data-out from column n (or column b).
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by MR0[A1:0 = 01] and A12 = 0 during READ command at T0.
BL8 setting activated by MR0[A1:0 = 01] and A12 = 1 during READ command at T4.
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
CK#
CK
DQ
T12 T13 T14
NOP NOP NOP
tCCD
Notes 3
Notes 4
Bank,
Col n
Bank,
Col b
Dout
n
Dout
n+1
Dout
n+2
Dout
n+3
Dout
b+4
Dout
b+5
Dout
b+6
Dout
b+7
tRPRE
RL = 5
RL = 5
Don't CareTRANSITIONING DATA
Notes 2
DQS, DQS#
ADDRESS
COMMAND
tRPST
Dout
b
Dout
b+1
Dout
b+2
Dout
b+3
tRPST tRPRE
Figure 38. READ (BC4) to WRITE (BL8) OTF
NOPREAD NOP NOP WRITE NOP NOP NOP NOP NOP NOP NOP
NOTES:
1. BC4, RL = 5 (CL = 5, AL = 0), WL = 5 (CWL = 5, AL = 0)
2. DOUT n = data-out from column, DIN b = data-in from column b.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by MR0[A1:0 = 01] and A12 = 0 during READ command at T0 and WRITE command at T4.
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
CK#
CK
DQ
T12 T13 T14
NOP NOP NOP
READ to WRITE Command Delay = RL + tCCD/2 + 2tCK - WL
Notes 3
Notes 4
Bank,
Col n
Bank,
Col b
Dout
n
Dout
n+1
Dout
n+2
Dout
n+3
Din
b
Din
b+1
Din
b+2
Din
b+3
tRPRE
RL = 5 WL = 5
Don't CareTRANSITIONING DATA
Notes 2
DQS, DQS#
ADDRESS
COMMAND
tRPST tWPRE
T15
NOP
tWPST
4 clocks
tWR
tWTR
Din
b+4
Din
b+5
Din
b+6
Din
b+7
Figure 39. READ (BL8) to WRITE (BL4) OTF
NOPREAD NOP NOP NOP NOP WRITE NOP NOP NOP NOP NOP
NOTES:
1. RL = 5 (CL = 5, AL = 0), WL = 5 (CWL= 5, AL = 0)
2. DOUT n = data-out from column, DIN b = data-in from column b.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by MR0[A1:0 = 01] and A12 = 1 during READ command at T0.
BC4 setting activated by MR0[A1:0 = 01] and A12 = 0 during WRITE command at T6.
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
CK#
CK
DQ
T12 T13 T14
NOP NOP NOP
READ to WRITE Command Delay = RL + tCCD + 2tCK - WL
Notes 3
Notes 4
Bank,
Col n
Bank,
Col b
Dout
n
Dout
n+1
Dout
n+2
Dout
n+3
Din
b
Din
b+1
Din
b+2
Din
b+3
tRPRE
RL = 5 WL = 5
Don't CareTRANSITIONING DATA
Notes 2
DQS, DQS#
ADDRESS
COMMAND
tRPST tWPRE
T15
NOP
tWPST
Dout
n+4
Dout
n+5
Dout
n+6
Dout
n+7
4 clocks
tWR
tWTR
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Figure 40. READ to PRECHARGE, RL = 5, AL = 0, CL = 5, tRTP = 4, tRP = 5
READNOP NOP NOP NOP PRE NOP NOP NOP NOP ACT NOP
NOTES:
1. RL = 5 (CL = 5, AL = 0)
2. DOUT n = data-out from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. The example assumes tRAS.MIN is satisfied at Precharge command time (T5) and that tRC.MIN is satisfied at the next Active command time (T10).
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
CK#
CK
DQ
T12 T13 T14
NOP NOP NOP
RL = AL + CL
Bank a,
(or all)
Bank a,
Row b
DO
n
DO
n+1
DO
n+2
DO
n+3
Don't CareTRANSITIONING DATA
T15
NOP
tRP
tRTP
Bank a,
Col n
DQ DO
n
DO
n+1
DO
n+2
DO
n+3
BL4 Operation:
BL8 Operation:
DO
n+4
DO
n+5
DO
n+6
DO
n+7
DQS, DQS#
DQS, DQS#
ADDRESS
COMMAND
Figure 41. READ to PRECHARGE, RL = 8, AL = CL-2, CL = 5, tRTP = 6, tRP = 5
READNOP NOP NOP NOP NOP NOP NOP NOP NOP PRE NOP
NOTES:
1. RL = 8 (CL = 5, AL = CL - 2)
2. DOUT n = data-out from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. The example assumes tRAS.MIN is satisfied at Precharge command time (T10) and that tRC.MIN is satisfied at the next Active command time (T15).
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
CK#
CK
DQ
T12 T13 T14
NOP NOP NOP
AL = CL - 2 = 3
Bank a,
(or all)
DO
n
DO
n+1
DO
n+2
DO
n+3
Don't CareTRANSITIONING DATA
T15
ACT
tRTP
Bank a,
Col n
DQ DO
n
DO
n+1
DO
n+2
DO
n+3
BL4 Operation:
BL8 Operation:
DO
n+4
DO
n+5
DO
n+6
DO
n+7
Bank a,
Row b
CL = 5
tRP
DQS, DQS#
DQS, DQS#
ADDRESS
COMMAND
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Figure 42. Write Timing Definition and parameters
NOPWRITE NOP NOP NOP NOP NOP NOP NOP NOP NOP
NOTES:
1. BL8, WL = 5 (AL = 0, CWL = 5)
2. DIN n = data-in from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 during WRITE command at T0.
5. tDQSS must be met at each rising clock edge.
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
CK#
CK
DQ
WL = AL + CWL
Din
n
Din
n+2
Din
n+3
Don't CareTRANSITIONING DATA
Bank
Col n
DM
Notes 3
Notes 4
Notes 2
tDQSS(min) tWPRE(min)
tDQSH(min) tDQSL
tDQSS tDSH
tDQSH tDQSL tDQSH tDQSL tDQSH tDQSL tDQSH tDQSL(min)
tDSH tDSH tWPST(min)
tDSS tDSS tDSS tDSS tDSS
Din
n+4
Din
n+6
Din
n+7
DQ Din
n
Din
n+2
Din
n+3
DM
Notes 2
tDQSS(nominal) tWPRE(min)
tDQSH(min) tDQSL
tDSH
tDQSH tDQSL tDQSH tDQSL tDQSH tDQSL tDQSH tDQSL(min)
tDSH tDSH tDSH tWPST(min)
tDSS tDSS tDSS tDSS tDSS
Din
n+4
Din
n+6
Din
n+7
tDSH
DQ Din
n
Din
n+2
Din
n+3
DM
Notes 2
tDQSS(max) tWPRE(min)
tDQSH(min) tDQSL
tDSH
tDQSH tDQSL tDQSH tDQSL tDQSH tDQSL tDQSH tDQSL(min)
tDSH tDSH tDSH tWPST(min)
tDSS tDSS tDSS tDSS tDSS
Din
n+4
Din
n+6
Din
n+7
tDQSS
COMMAND
ADDRESS
DQS, DQS#
DQS, DQS#
DQS, DQS#
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Figure 43. WRITE Burst Operation WL = 5 (AL = 0, CWL = 5, BL8)
NOPWRITE NOP NOP NOP NOP NOP NOP NOP NOP NOP
NOTES:
1. BL8, WL = 5; AL = 0, CWL = 5.
2. DIN n = data-in from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 during WRITE command at T0.
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
CK#
CK
DQ
WL = AL + CWL
Din
n
Din
n+1
Din
n+2
Din
n+3
Don't CareTRANSITIONING DATA
tWPRE
Bank,
Col n
Notes 2
Din
n+4
Din
n+5
Din
n+6
Din
n+7
DQS, DQS#
COMMAND
ADDRESS
Notes 3
Notes 4
tWPST
Figure 44. WRITE Burst Operation WL = 9 (AL = CL-1, CWL = 5, BL8)
NOPWRITE NOP NOP NOP NOP NOP NOP NOP NOP NOP
NOTES:
1. BL8, WL = 9; AL = (CL - 1), CL = 5, CWL = 5.
2. DIN n = data-in from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 during WRITE command at T0.
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10
CK#
CK
DQ
AL = 4
Din
n
Din
n+1
Din
n+2
Din
n+3
Don't CareTRANSITIONING DATA
tWPRE
Bank,
Col n
Notes 2
Notes 3
Notes 4
DQS, DQS#
ADDRESS
COMMAND
CWL = 5
WL = AL + CWL
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Figure 45. WRITE(BC4) to READ (BC4) operation
NOPWRITE NOP NOP NOP NOP NOP NOP NOP NOP READ
NOTES:
1. BC4, WL = 5, RL = 5.
2. DIN n = data-in from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by MR0[A1:0 = 10] during WRITE command at T0 and READ command at Tn.
5. tWTR controls the write to read delay to the same device and starts with the first rising clock edge after the last write data shown at T7.
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 Tn
CK#
CK
DQ Din
n
Din
n+1
Din
n+2
Din
n+3
Don't CareTRANSITIONING DATA
Bank,
Col n
Notes 2
DQS, DQS#
COMMAND
ADDRESS
Notes 3
Notes 4
tWPST
tWTR
WL = 5 RL = 5
TIME BREAK
Notes 5
tWPRE
Figure 46. WRITE(BC4) to Precharge Operation
NOPWRITE NOP NOP NOP NOP NOP NOP NOP NOP PRE
NOTES:
1. BC4, WL = 5, RL = 5.
2. DIN n = data-in from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by MR0[A1:0 = 10] during WRITE command at T0.
5. The write recovery time (tWR) referenced from the first rising clock edge after the last write data shown at T7.
tWR specifies the last burst write cycle until the precharge command can be issued to the same bank .
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 Tn
CK#
CK
DQ Din
n
Din
n+1
Din
n+2
Din
n+3
Don't CareTRANSITIONING DATA
tWPRE
Bank,
Col n
Notes 2
DQS, DQS#
COMMAND
ADDRESS
Notes 3
Notes 4
tWPST
tWR
WL = 5
TIME BREAK
Notes 5
Figure 47. WRITE(BC4) OTF to Precharge operation
NOPWRITE NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP
NOTES:
1. BC4 OTF, WL = 5 (CWL = 5, AL = 0)
2. DIN n (or b) = data-in from column n.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 OTF setting activated by MR0[A1:0 = 01] and A12 = 0 during WRITE command at T0.
5. The write recovery time (tWR) starts at the rising clock edge T9 (4 clocks from T5).
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
CK#
CK
DQ
Ta0 Ta1 Ta2
PRE NOP NOP
Din
n
Din
n+1
Din
n+2
Din
n+3
Don't CareTRANSITIONING DATA
Bank
Col n VALID
4 Clocks tWR
Notes 3
Notes 2
ADDRESS
Notes 4
COMMAND
DQS, DQS#
tWPRE tWPST
TIME BREAK
WL = 5
Notes 5
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Figure 48. WRITE(BC8) to WRITE(BC8)
NOPWRITE NOP NOP WRITE NOP NOP NOP NOP NOP NOP NOP
NOTES:
1. BL8, WL = 5 (CWL = 5, AL = 0)
2. DIN n (or b) = data-in from column n (or column b).
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 during WRITE command at T0 and T4.
5. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from the first rising clock edge after the last write data shown at T13.
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
CK#
CK
DQ
T12 T13 T14
NOP NOP NOP
Din
n
Din
n+1
Din
n+2
Din
n+3
Don't CareTRANSITIONING DATA
Bank
Col n
Bank
Col b
4 Clocks
Notes 3
Notes 2
ADDRESS
Notes 4
COMMAND
DQS, DQS#
tWPRE tWPST
tCCD
Din
n+4
Din
n+5
Din
n+6
Din
n+7
Din
b
Din
b+1
Din
b+2
Din
b+3
Din
b+4
Din
b+5
Din
b+6
Din
b+7
tWR
tWTR
WL = 5 WL = 5
Figure 49. WRITE(BC4) to WRITE(BC4) OTF
NOPWRITE NOP NOP WRITE NOP NOP NOP NOP NOP NOP NOP
NOTES:
1. BC4, WL = 5 (CWL = 5, AL = 0)
2. DIN n (or b) = data-in from column n (or column b).
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by MR0[A1:0 = 01] and A12 = 0 during WRITE command at T0 and T4.
5. The write recovery time (tWR) and write timing parameter (tWTR) are referenced from the first rising clock edge at T13 (4 clocks from T9).
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
CK#
CK
DQ
T12 T13 T14
NOP NOP NOP
Din
n
Din
n+1
Din
n+2
Din
n+3
Don't CareTRANSITIONING DATA
Bank
Col n
Bank
Col b
4 Clocks
Notes 3
Notes 2
ADDRESS
Notes 4
COMMAND
DQS, DQS#
tWPRE tWPST
tCCD
Din
b
Din
b+1
Din
b+2
Din
b+3
tWR
tWTR
WL = 5 WL = 5
tWPST tWPRE
Figure 50. WRITE(BC8) to READ(BC4,BC8) OTF
NOPWRITE NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP
NOTES:
1. RL = 5 (CL = 5, AL = 0), WL = 5 (CWL = 5, AL = 0)
2. DIN n = data-in from column n; DOUT b = data-out from column b.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by either MR0[A1:0 = 00] or MR0[A1:0 = 01] and A12 = 1 during WRITE command at T0.
READ command at T13 can be either BC4 or BL8 depending on MR0[A1:0] and A12 status at T13.
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
CK#
CK
DQ
T12 T13 T14
NOP READ NOP
Din
n
Din
n+1
Din
n+2
Din
n+3
Don't CareTRANSITIONING DATA
Bank
Col n
Bank
Col b
Notes 3
Notes 2
ADDRESS
Notes 4
COMMAND
DQS, DQS#
tWPRE
Din
n+4
Din
n+5
Din
n+6
Din
n+7
RL = 5
tWTR
WL = 5
tWPST
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Figure 51. WRITE(BC4) to READ(BC4,BC8) OTF
NOPWRITE NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP
NOTES:
1. RL = 5 (CL = 5, AL = 0), WL = 5 (CWL =5, AL = 0)
2. DIN n = data-in from column n; DOUT b = data-out from column b.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by MR0[A1:0 = 01] and A12 = 0 during WRITE command at T0.
READ command at T13 can be either BC4 or BL8 depending on A12 status at T13.
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
CK#
CK
DQ
T12 T13 T14
NOP READ NOP
Din
n
Din
n+1
Din
n+2
Din
n+3
Don't CareTRANSITIONING DATA
Bank
Col n
Bank
Col b
Notes 3
Notes 2
ADDRESS
Notes 4
COMMAND
DQS, DQS#
tWPRE
RL = 5
tWTR
WL = 5
tWPST
4 Clocks
Figure 52. WRITE(BC4) to READ(BC4)
NOPWRITE NOP NOP NOP NOP NOP NOP NOP NOP NOP READ
NOTES:
1. RL = 5 (CL = 5, AL = 0), WL = 5 (CWL =5, AL = 0)
2. DIN n = data-in from column n; DOUT b = data-out from column b.
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by MR0[A1:0 = 10].
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
CK#
CK
DQ
T12 T13 T14
NOP NOP NOP
Din
n
Din
n+1
Din
n+2
Din
n+3
Don't CareTRANSITIONING DATA
Bank
Col n
Bank
Col b
Notes 3
Notes 2
ADDRESS
Notes 4
COMMAND
DQS, DQS#
tWPRE
RL = 5
tWTR
WL = 5
tWPST
Figure 53. WRITE(BC8) to WRITE(BC4) OTF
NOPWRITE NOP NOP WRITE NOP NOP NOP NOP NOP NOP NOP
NOTES:
1. WL = 5 (CWL = 5, AL = 0)
2. DIN n (or b) = data-in from column n (or column b).
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BL8 setting activated by MR0[A1:0 = 01] and A12 = 1 during WRITE command at T0.
BC4 setting activated by MR0[A1:0 = 01] and A12 = 0 during WRITE command at T4.
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
CK#
CK
DQ
T12 T13 T14
NOP NOP NOP
Din
n
Din
n+1
Din
n+2
Din
n+3
Don't CareTRANSITIONING DATA
Bank
Col n
Bank
Col b
Notes 3
Notes 2
ADDRESS
Notes 4
COMMAND
DQS, DQS#
tWPRE
Din
n+4
Din
n+5
Din
n+6
Din
n+7
tWTR
WL = 5
tWPST
tCCD tWR
4 Clocks
WL = 5
Din
b
Din
b+1
Din
b+2
Din
b+3
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Figure 54. WRITE(BC4) to WRITE(BC8) OTF
NOPWRITE NOP NOP WRITE NOP NOP NOP NOP NOP NOP NOP
NOTES:
1. WL = 5 (CWL = 5, AL = 0)
2. DIN n (or b) = data-in from column n (or column b).
3. NOP commands are shown for ease of illustration; other commands may be valid at these times.
4. BC4 setting activated by MR0[A1:0 = 01] and A12 = 0 during WRITE command at T0.
BL8 setting activated by MR0[A1:0 = 01] and A12 = 1 during WRITE command at T4.
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
CK#
CK
DQ
T12 T13 T14
NOP NOP NOP
Din
n
Din
n+1
Din
n+2
Din
n+3
Don't CareTRANSITIONING DATA
Bank
Col n
Bank
Col b
4 Clocks
Notes 3
Notes 2
ADDRESS
Notes 4
COMMAND
DQS, DQS#
tWPRE tWPST
tCCD
Din
b
Din
b+1
Din
b+2
Din
b+3
tWR
tWTR
WL = 5 WL = 5
tWPST tWPRE
Din
b+4
Din
b+5
Din
b+6
Din
b+7
Figure 55. Refresh Command Timing
NOPREF NOP REF NOP NOP VALID VALID VALID VALID VALID REF
NOTES:
1. Only NOP/DES commands allowed after Refresh command registered until tRFC(min) expires.
2. Time interval between two Refresh commands may be extended to a maximum of 9 x tREFI.
T0 T1 Ta0 Ta1 Tb0 Tb1 Tb2 Tb3 Tc0
CK#
CK
Tc1 Tc2 Tc3
VALID VALID VALID
Don't CareTRANSITIONING DATA
tRFC (min)
COMMAND
tRFC
tREFI (max. 9 * tREFI)
DRAM must be idle DRAM must be idle
TIME BREAK
Figure 56. Self-Refresh Entry/Exit Timing
CK#
T1 T2 Ta0 Tb0 Tc0 Tc1 Td0 TeoT0
CK
tCKSRE
Tf0
tCKESR
tXS
tXSDLL
NOP SRE NOP VALID
NOP
VALID
VALID
ODT
CKE
COMMAND
ADDR
tIS
Don't CareTIME BREAK
NOTES:
1. Only NOP or DES command.
2. Valid commands not requiring a locked DLL.
3. Valid commands requiring a locked DLL.
tCKSRX
VALID
tCPDED
tIS
VALID
SRX
Notes 1 Notes 2
VALID
VALID
tRP
ODTL
Enter Self
Refresh
Exit Self
Refresh
Notes 3
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Figure 57. Active Power-Down Entry and Exit Timing Diagram
CK#
T1 T2 Ta0 Ta1 Tb0 Tb1 Tc0T0
CK
CKE
NOPVALID NOP NOP NOP NOP VALID
tIS
tIH tIS
tIH
VALID VALID
VALID VALID
tCKE
tPD
tCPDED tXP
Enter
Power-Down Mode
Exit
Power-Down Mode
ADDRESS
COMMAND
Don't CareTIME BREAK
NOTE:
VALID command at T0 is ACT, NOP, DES or PRE with still one bank remaining
open after completion of the precharge command.
Figure 58. Power-Down Entry after Read and Read with Auto Precharge
NOP
RD or
RDA NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP
T0 T1 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Ta8 Tb0
CK#
CK
Tb1
VALID
Din
b
Din
b+1
Din
b+2
Din
b+3
Din
b+4
Din
b+5
Din
b+6
Din
b+7
tPD
tIS
RL = AL + CL
Don't CareTRANSITIONING DATA
ADDRESS
CKE
tCPDED
VALID
VALID VALID
COMMAND
DQS, DQS#
DQ BL8
Din
b
Din
b+1
Din
b+2
Din
b+3
DQ BC4
tRDPDEN
Power - Down Entry
TIME BREAK
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Figure 59. Power-Down Entry after Write with Auto Precharge
NOPWRITE NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP
T0 T1 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Tb0 Tb1
CK#
CK
Tb2
NOP
Din
b
Din
b+1
Din
b+2
Din
b+3
Din
b+4
Din
b+5
Din
b+6
Din
b+7
WR
tIS
WL = AL + CWL
Don't CareTRANSITIONING DATA
CKE
tCPDED
VALID
Bank,
Col n VALID
DQ BL8
Din
b
Din
b+1
Din
b+2
Din
b+3
DQ BC4
tWRAPDEN
Power - Down
Entry
TIME BREAK
Tc0 Tc1
NOP VALID
A10
tPD
NOTES:
1. WR is programmed through MR0.
Start Internal
Precharge
DQS, DQS#
ADDRESS
COMMAND
Notes 1
Figure 60. Power-Down Entry after Write
NOPWRITE NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP
T0 T1 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Ta7 Tb0 Tb1
CK#
CK
Tb2
NOP
Din
b
Din
b+1
Din
b+2
Din
b+3
Din
b+4
Din
b+5
Din
b+6
Din
b+7
tWR
tIS
WL = AL + CWL
Don't CareTRANSITIONING DATA
CKE
tCPDED
VALID
Bank,
Col n VALID
DQ BL8
Din
b
Din
b+1
Din
b+2
Din
b+3
DQ BC4
tWRPDEN
Power - Down
Entry
TIME BREAK
Tc0 Tc1
NOP VALID
A10
tPD
DQS, DQS#
ADDRESS
COMMAND
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Figure 61. Precharge Power-Down (Fast Exit Mode) Entry and Exit
CK#
T1 T2 Ta0 Ta1 Tb0 Tb1 Tc0T0
CK
CKE
NOPVALID NOP NOP NOP NOP VALID
tIS
tIS
tIH
VALID VALID
tCKE
tCPDED
Enter
Power-Down
Mode
Exit
Power-Down
Mode
COMMAND
Don't CareTIME BREAK
tPD tXP
Figure 62. Precharge Power-Down (Slow Exit Mode) Entry and Exit
CK#
T1 T2 Ta0 Ta1 Tb0 Tb1 Tc0T0
CK
CKE
NOPVALID NOP NOP NOP NOP VALID
tIS
tIS
tIH
VALID VALID
tCKE
tCPDED
Enter
Power-Down
Mode
Exit
Power-Down
Mode
COMMAND
Don't CareTIME BREAK
tPD tXP
Td0
VALID
VALID
tXPDLL
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Figure 63. Refresh Command to Power-Down Entry
CK#
T1 T2 T3 Ta0 Ta1T0
CK
CKE
REFVALID NOP NOP VALID
tIS tPD
VALID
tCPDED
Don't CareTIME BREAK
tREFPDEN
NOP
VALIDVALID VALID
ADDRESS
COMMAND
Figure 64. Active Command to Power-Down Entry
CK#
T1 T2 T3 Ta0 Ta1T0
CK
CKE
ACTIVE
VALID NOP NOP VALID
tIS tPD
VALID
tCPDED
Don't CareTIME BREAK
tACTPDEN
NOP
VALIDVALID VALID
ADDRESS
COMMAND
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Figure 65. Precharge, Precharge all command to Power-Down Entry
CK#
T1 T2 T3 Ta0 Ta1T0
CK
CKE
PRE or
PREA
VALID NOP NOP VALID
tIS tPD
VALID
tCPDED
Don't CareTIME BREAK
tPREPDEN
NOP
VALIDVALID VALID
ADDRESS
COMMAND
Figure 66. MRS Command to Power-Down Entry
CK#
T1 Ta0 Ta1 Tb0 Tb1T0
CK
CKE
NOPMRS NOP VALID
tIS tPD
VALID
tCPDED
Don't CareTIME BREAK
tMRSPDEN
NOP
VALID VALID
ADDRESS
COMMAND
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Figure 67. Synchronous ODT Timing Example
(AL = 3; CWL = 5; ODTLon = AL + CWL - 2 = 6; ODTLoff = AL + CWL - 2 = 6)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
CK#
CK
T12
tAON(min)
ODTH4, min
Don't CareTRANSITIONING DATA
ODT
AL = 3
T13 T14
CKE
T15
CWL - 2
ODTLoff = CWL + AL - 2
ODTLon = CWL + AL - 2
DRAM_RTT
tAON(max)
tAOF(min)
tAOF(max)
RTT_NOM
AL = 3
Figure 68. Synchronous ODT example with BL = 4, WL = 7
NOPNOP NOP NOP NOP NOP NOP WRS4 NOP NOP NOP NOP
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
CK#
CK
T12 T13 T14
NOP NOP NOP
ODTH4
Don't CareTRANSITIONING DATA
T15
NOP
ODTLoff = WL - 2
DRAM_RTT
ODT
COMMAND
CKE
T16 T17
NOP NOP
ODTH4min
ODTH4
ODTLon = WL - 2 ODTLon = WL - 2
ODTLoff = WL - 2
RTT_NOM
tAOF(min) tAON(max)
tAOF(max) tAON(min)
tAON(max)
tAON(min) tAOF(min)
tAOF(max)
Figure 69. Dynamic ODT Behavior with ODT being asserted before and after the write
NOPNOP NOP NOP WRS4 NOP NOP NOP NOP NOP NOP NOP
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
CK#
CK
T12 T13 T14
NOP NOP NOP
Don't CareTRANSITIONING DATA
T15
NOP
ODT
T16 T17
NOP NOP
ODTH4
ODTLon
VALID
RTT
Din
n
Din
n+1
Din
n+2
Din
n+3
DQ
ODTLoff
tADC(min)
tADC(max)
tAON(min)
ODTH4
ODTLcwn4
tAON(max)
RTT_NOM RTT_WR
tADC(min)
tADC(max)
tAOF(min)
tAOF(max)
RTT_NOM
ODTLcnw
WL
NOTES:
Example for BC4 (via MRS or OTF), AL = 0, CWL = 5. ODTH4 applies to first registering ODT high and to the registration of the Write command.
In this example, ODTH4 would be satisfied if ODT went low at T8 (4 clocks after the Write command).
DQS, DQS#
COMMAND
ADDRESS
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Figure 70. Dynamic ODT: Behavior without write command, AL = 0, CWL = 5
VALIDVALID VALID VALID VALID VALID VALID VALID VALID VALID VALID VALID
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
CK#
CK
Don't CareTRANSITIONING DATA
ODT
ODTLoff
ODTLon
RTT
DQ
tAON(min)
ODTH4
tAON(max)
tADC(min)
tADC(max)
NOTES:
1. ODTH4 is defined from ODT registered high to ODT registered low, so in this example, ODTH4 is satisfied.
2. ODT registered low at T5 would also be legal.
RTT_NOM
DQS, DQS#
ADDRESS
COMMAND
Figure 71. Dynamic ODT: Behavior with ODT pin being asserted together with write
command for a duration of 6 clock cycles
WRS8NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
CK#
CK
Don't CareTRANSITIONING DATA
ODT
ODTLoff
ODTLcnw
RTT
DQ
tAON(min)
ODTH8
tADC(max)
tAOF(min)
tAOF(max)
NOTES:
Example for BL8 (via MRS or OTF), AL = 0, CWL = 5. In this example, ODTH8 = 6 is exactly satisfied.
RTT_WR
VALID
ODTLon
ODTLcwn8
Din
b
Din
b+1
Din
b+2
Din
b+3
DQS, DQS#
ADDRESS
COMMAND
Din
b+4
Din
b+5
Din
b+6
Din
b+7
WL
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Figure 72. Dynamic ODT: Behavior with ODT pin being asserted together with write
command for a duration of 6 clock cycles, example for BC4 (via MRS or OTF),
AL = 0, CWL = 5.
WRS4NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
CK#
CK
Don't CareTRANSITIONING DATA
ODT
ODTLoff
ODTLcnw
RTT
DQ
tAON(min)
ODTH4
tADC(max)
tADC(min)
tADC(max)
NOTES:
1. ODTH4 is defined from ODT registered high to ODT registered low, so in this example, ODTH4 is satisfied. TRANSITIONING DON’T CARE
2. ODT registered low at T5 would also be legal.
VALID
ODTLon
ODTLcwn4
Din
n
Din
n+1
Din
n+2
Din
n+3
DQS, DQS#
ADDRESS
COMMAND
WL
RTT_WR
tAOF(min)
tAOF(max)
RTT_NOM
Figure 73. Dynamic ODT: Behavior with ODT pin being asserted together with write
command for a duration of 4 clock cycles
WRS4NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
CK#
CK
Don't CareTRANSITIONING DATA
ODT
ODTLoff
ODTLcnw
RTT
DQ
tAON(min)
ODTH4
tADC(max)
tAOF(min)
tAOF(max)
NOTES:
Example for BC4 (via MRS or OTF), AL = 0, CWL = 5. In this example, ODTH4 = 4 is exactly satisfied.
VALID
ODTLon
ODTLcwn4
Din
n
Din
n+1
Din
n+2
Din
n+3
DQS, DQS#
ADDRESS
COMMAND
WL
RTT_WR
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Figure 74. Asynchronous ODT Timings on DDR3L SDRAM with fast ODT transition
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
CK#
CK
T12 T13 T14
Don't CareTRANSITIONING DATA
T15 T16 T17
RTT
tAONPD(min)
tAONPD(max)
tIH tIS
tAOFPD(min)
tAOFPD(max)
CKE
ODT
tIH tIS
RTT
Figure 75. Synchronous to asynchronous transition during Precharge Power Down
(with DLL frozen) entry (AL = 0; CWL = 5; tANPD = WL - 1 = 4)
NOPNOP NOP NOP NOP NOP NOP NOP NOP NOP NOP
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
CK#
CK
T12
Don't CareTRANSITIONING DATA
RTT
PD entry transition period
tCPDED
tANPD
tCPDED(min)
CKE
tAOF(min)
tAOF(max)
RTT
ODTLoff
tAOFPD(min)
RTT
RTT
ODTLoff + tAOF(max)
ODTLoff + tAOF(min)
tAOFPD(max)
tAOFPD(min)
RTT
PD entry transition period tAOFPD(max)
RTT
First async.
ODT
Sync. or
async. ODT
Last sync.
ODT
COMMAND
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Figure 76. Synchronous to asynchronous transition after Refresh command
(AL = 0; CWL = 5; tANPD = WL - 1 = 4)
REFNOP NOP NOP NOP NOP NOP NOP NOP
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
CK#
CK
T12
Don't CareTRANSITIONING DATA
RTT
tRFC (min)
tCPDED(min)
CKE
tAOF(min)
tAOF(max)
RTT
ODTLoff
tAOFPD(min)
RTT
ODTLoff + tAOFPD(max)
ODTLoff + tAOFPD(min)
tAOFPD(max)
tAOFPD(min)
PD entry transition period
tAOFPD(max)
RTT
T13 Ta0 Ta1 Ta2 Ta3
tANPD
RTT
RTT
COMMAND
Last sync.
ODT
Sync. or
async. ODT
First async.
ODT
TIME BREAK
Figure 77. Asynchronous to synchronous transition during Precharge Power Down
(with DLL frozen) exit (CL = 6; AL = CL - 1; CWL = 5; tANPD = WL - 1 = 9)
NOPNOP NOP NOP NOP NOP NOP NOP NOP
T0 T1 T2 Ta0 Ta1 Ta2 Ta3 Ta4 Ta5 Ta6 Tb0 Tb1
CK#
CK
Tb2
Don't CareTRANSITIONING DATA
RTT
tXPDLL
tANPD
CKE
tAOFPD(min)
tAOFPD(max)
tAOFPD(min)
RTT
ODTLoff + tAOF(max)
ODTLoff + tAOF(min)
tAOFPD(max)
tAOF(min)
PD exit transition period
tAOF(max)
RTT
Tc0 Tc1 Tc2 Td0 Td1
RTT
RTT
RTT
ODTLoff
TIME BREAK
NOPNOP
NOPNOP
NOP
COMMAND
Last async.
ODT
Sync. or
async. ODT
First sync.
ODT
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Figure 78. Transition period for short CKE cycles, entry and exit period overlapping
(AL = 0, WL = 5, tANPD = WL - 1 = 4)
T0 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11
CK#
CK
T12
tANPD
Don't Care
CKE
T13 T14
CKE
PD exit transition period
NOPREF NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP NOP
tRFC (min)
PD entry transition period
tANPD tXPDLL
short CKE low transition period
COMMAND
tANPD
short CKE high transition period
tXPDLL
TIME BREAK
Figure 79. Power-Down Entry,Exit Clarifications-Case 1
CK#
T1 T2 Ta0 Ta1 Tb0T0
CK
CKE
NOPVALID NOP NOP
tIH
tPD
tCPDED
Don't CareTIME BREAK
NOP
VALID
ADDRESS
COMMAND
Tb1 Tb2
NOP NOP
tIS tIH tIS
tCPDED
tIS
tPD
tCKE
Enter
Power-Down
Mode
Exit
Power-Down
Mode
Enter
Power-Down
Mode
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Figure 80. Power-Down Entry,Exit Clarifications-Case 2
CK#
T1 T2 Ta0 Ta1 Tb0T0
CK
CKE
NOPVALID NOP NOP
tIH
tPD
tCPDED
Don't CareTIME BREAK
NOP
VALID
ADDRESS
COMMAND
Tb1 Tc0
NOP REF
tIS tIH tIS
tXPDLL
tXP
tCKE
Enter
Power-Down
Mode
Exit
Power-Down
Mode
Enter
Power-Down
Mode
Tc1 Td0
NOP NOP
Figure 81. Power-Down Entry,Exit Clarifications-Case 3
CK#
T1 T2 Ta0 Ta1 Tb0T0
CK
CKE
NOPREF NOP NOP
tIH
tPD
tCPDED
Don't CareTIME BREAK
NOP
Tb1 Tc0
NOP NOP
tIS tIH tIS
tRFC(min)
tXP
tCKE
Enter
Power-Down
Mode
Exit
Power-Down
Mode
Enter
Power-Down
Mode
Tc1 Td0
NOP NOP
ADDRESS
COMMAND
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Figure 82. 96-Ball FBGA Package 9x13x1.2mm(max) Outline Drawing Information
Symbol
Dimension in inch
Dimension in mm
Min
Nom
Max
Min
Nom
Max
A
--
--
0.047
--
--
1.20
A1
0.010
--
0.016
0.25
--
0.40
A2
0.004
0.006
0.008
0.10
0.15
0.20
D
0.350
0.354
0.358
8.90
9.00
9.10
E
0.508
0.512
0.516
12.90
13.00
13.10
D1
--
0.252
--
--
6.40
--
E1
--
0.472
--
--
12.00
--
F
--
0.126
--
--
3.20
--
e
--
0.031
--
--
0.80
--
b
0.016
0.018
0.020
0.40
0.45
0.50
D2
--
--
0.081
--
--
2.05
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PART NUMBERING SYSTEM
128M16=128Mx16
D3L=LPDDR3
B=B die version
12=800MHz!
Alliance Memory, Inc.
511 Taylor Way,
San Carlos, CA 94070
Tel: 650-610-6800
Fax: 650-620-9211
www.alliancememory.com
Copyright © Alliance Memory
All Rights Reserved
© Copyright 2007 Alliance Memory, Inc. All rights reserved. Our three-point logo, our name and Intelliwatt are
trademarks or registered trademarks of Alliance. All other brand and product names may be the trademarks of their
respective companies. Alliance reserves the right to make changes to this document and its products at any time
without notice. Alliance assumes no responsibility for any errors that may appear in this document. The data
contained herein represents Alliance's best data and/or estimates at the time of issuance. Alliance reserves the right
to change or correct this data at any time, without notice. If the product described herein is under development,
significant changes to these specifications are possible. The information in this product data sheet is intended to be
general descriptive information for potential customers and users, and is not intended to operate as, or provide, any
guarantee or warrantee to any user or customer. Alliance does not assume any responsibility or liability arising out of
the application or use of any product described herein, and disclaims any express or implied warranties related to the
sale and/or use of Alliance products including liability or warranties related to fitness for a particular purpose,
merchantability, or infringement of any intellectual property rights, except as express agreed to in Alliance's Terms
and Conditions of Sale (which are available from Alliance). All sales of Alliance products are made exclusively
according to Alliance's Terms and Conditions of Sale. The purchase of products from Alliance does not convey a
license under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of
Alliance or third parties. Alliance does not authorize its products for use as critical components in life-supporting
systems where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the
inclusion of Alliance products in such life-supporting systems implies that the manufacturer assumes all risk of such
use and agrees to indemnify Alliance against all claims arising from such use.
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I=Industrial
(-40° C~+95° C)
B = FBGA!Indicates!Pb!and!
Halogen!Free!
B I N
DRAM
XX
Packing Type
None:Tray
TR:Reel
128M16D3LB 12!
AS4C!
