256-Position SPI/I2C Selectable
Digital Potentiometer
Data Sheet
AD5161
Rev. B
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FEATURES
256-position
End-to-end resistance 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Compact MSOP-10 (3 mm × 4.9 mm) package
Pin selectable SPI/I2C compatible interface
Extra package address decode pin AD0
Full read/write of wiper register
Power-on preset to midscale
Single supply 2.7 V to 5.5 V
Low temperature coefficient 45 ppm/°C
Low power, IDD = 8 µA
Wide operating temperature −40°C to +125°C
SDO output allows multiple device daisy-chaining
Evaluation board available
APPLICATIONS
Mechanical potentiometer replacement in new designs
Transducer adjustment of pressure, temperature, position,
chemical, and optical sensors
RF amplifier biasing
Gain control and offset adjustment
GENERAL DESCRIPTION
The AD5161 provides a compact 3 mm × 4.9 mm packaged
solution for 256-position adjustment applications. These
devices perform the same electronic adjustment function as
mechanical potentiometers or variable resistors, with enhanced
resolution, solid-state reliability, and superior low temperature
coefficient performance.
The wiper settings are controllable through a pin selectable SPI
or I2C compatible digital interface, which can also be used to
read back the wiper register content. When the SPI mode is
used, the device can be daisy-chained (SDO to SDI), allowing
several parts to share the same control lines. In the I2C mode,
address pin AD0 can be used to place up to two devices on the
same bus. In this same mode, command bits are available to
reset the wiper position to midscale or to shut down the device
into a state of zero power consumption.
Operating from a 2.7 V to 5.5 V power supply and consuming
less than 5 µA allows for usage in portable battery-operated
applications.
FUNCTIONAL BLOCK DIAGRAM
WIPER
REGISTER
SDI/SDA
CLK/SCL
DIS
CS/AD0
GND
SDO/NCVDD
A
W
B
SPI OR I2C
INTERFACE
Figure 1.
PIN CONFIGURATION
1
2
3
4
5
10
9
8
7
6
A
B
CS/ADO
SDO/NC
SDI/SDA
DD
AD5161
TOP VIEW
(Not to Scale)
W
V
DIS
GND
CLK/SCL
Figure 2.
AD5161 Data Sheet
Rev. B | Page 2 of 20
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Pin Configuration ............................................................................. 1
Revision History ............................................................................... 2
Electrical Characteristics—5 kΩ Version ...................................... 3
Electrical Characteristics—10 kΩ, 50 kΩ, 100 kΩ Versions ....... 4
Timing Characteristics—5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ Versions 5
Absolute Maximum Ratings1 .......................................................... 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Typical Performance Characteristics ............................................. 8
Test Circuits ..................................................................................... 12
SPI Interface .................................................................................... 13
I2C Interface .................................................................................... 14
Theory of Operation ...................................................................... 15
Programming the Variable Resistor ......................................... 15
Programming the Potentiometer Divider ............................... 16
Pin Selectable Digital Interface ................................................. 16
Level Shifting for Bidirectional Interface ................................ 18
ESD Protection ........................................................................... 18
Terminal Voltage Operating Range ......................................... 18
Power-Up Sequence ................................................................... 18
Layout and Power Supply Bypassing ....................................... 18
Outline Dimensions ....................................................................... 19
Ordering Guide .......................................................................... 19
REVISION HISTORY
8/12—Rev. A to Rev. B
Changes to Applications Section .................................................... 1
Updated Outline Dimensions ....................................................... 19
4/09—Rev. 0 to Rev. A
Changes to Ordering Guide .......................................................... 19
5/03—Revision 0: Initial Version
Data Sheet AD5161
Rev. B | Page 3 of 20
ELECTRICAL CHARACTERISTICS—5 kΩ VERSION
VDD = 5 V ± 10%, or 3 V ± 10%; VA = +VDD; VB = 0 V; –40°C < TA < +125°C; unless otherwise noted.
Table 1.
Parameter Symbol Conditions Min Typ
1
Max Unit
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity
2
R-DNL R
, V
= no connect −1.5 ±0.1 +1.5 LSB
Resistor Integral Nonlinearity
2
R-INL R
, V
= no connect –4 ±0.75 +4 LSB
Nominal Resistor Tolerance3 ∆R
AB
T
= 25°C –30 +30 %
Resistance Temperature Coefficient ∆R
AB
/∆T V
= V
, Wiper = no connect 45 ppm/°C
Wiper Resistance R
W
50 120 Ω
DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs)
Resolution N 8 Bits
Differential Nonlinearity4 DNL –1.5 ±0.1 +1.5 LSB
Integral Nonlinearity
4
INL –1.5 ±0.6 +1.5 LSB
Voltage Divider Temperature Coefficient ∆V
W
/∆T Code = 0x80 15 ppm/°C
Full-Scale Error V
WFSE
Code = 0xFF –6 –2.5 0 LSB
Zero-Scale Error V
WZSE
Code = 0x00 0 +2 +6 LSB
RESISTOR TERMINALS
Voltage Range
5
V
A,B,W
GND V
DD
V
Capacitance6 A, B CA,B f = 1 MHz, measured to GND,
Code = 0x80
45 pF
Capacitance6 W CW f = 1 MHz, measured to GND,
Code = 0x80
60 pF
Shutdown Supply Current
7
I
DD_SD
V
= 5.5 V 0.01 1 µA
Common-Mode Leakage I
CM
V
= V
= V
/2 1 nA
DIGITAL INPUTS AND OUTPUTS
Input Logic High V
IH
2.4 V
Input Logic Low V
IL
0.8 V
Input Logic High V
IH
V
= 3 V 2.1 V
Input Logic Low V
IL
V
= 3 V 0.6 V
Input Current I
IL
V
= 0 V or 5 V ±1 µA
Input Capacitance
6
C
IL
5 pF
POWER SUPPLIES
Power Supply Range V
DD RANGE
2.7 5.5 V
Supply Current I
DD
V
= 5 V or V
= 0 V 3 8 µA
Power Dissipation8 P
DISS
V
= 5 V or V
= 0 V, V
= 5 V 0.2 mW
Power Supply Sensitivity PSS ∆VDD = +5 V ± 10%,
Code = Midscale
±0.02 ±0.05 %/%
DYNAMIC CHARACTERISTICS6, 9
Bandwidth –3dB BW_5K R
= 5 kΩ, Code = 0x80 1.2 MHz
Total Harmonic Distortion THD
W
V
= 1 V rms, V
= 0 V, f = 1 kHz 0.05 %
VW Settling Time
tS
1
µs
Resistor Noise Voltage Density e
N_WB
R
= 2.5 kΩ, RS = 0 6 nV/√Hz
AD5161 Data Sheet
Rev. B | Page 4 of 20
ELECTRICAL CHARACTERISTICS—10 kΩ, 50 kΩ, 100 kΩ VERSIONS
VDD = 5 V ± 10%, or 3 V ± 10%; VA = VDD; VB = 0 V; –40°C < TA < +125°C; unless otherwise noted.
Table 2.
Parameter Symbol Conditions Min Typ
1
Max Unit
DC CHARACTERISTICS—RHEOSTAT MODE
Resistor Differential Nonlinearity
2
R-DNL R
WB
, V
A
= no connect –1 ±0.1 +1 LSB
Resistor Integral Nonlinearity
2
R-INL R
WB
, V
A
= no connect –2 ±0.25 +2 LSB
Nominal Resistor Tolerance3 ∆R
AB
T
A
= 25°C –30 +30 %
Resistance Temperature Coefficient ∆RAB/∆T VAB = VDD,
Wiper = no connect
45 ppm/°C
Wiper Resistance R
W
V
DD
= 5 V 50 120 Ω
DC CHARACTERISTICS—POTENTIOMETER DIVIDER MODE (Specifications apply to all VRs)
Resolution N 8 Bits
Differential Nonlinearity4
DNL
–1
±0.1
+1
LSB
Integral Nonlinearity
4
INL –1 ±0.3 +1 LSB
Voltage Divider Temperature Coefficient ∆V
W
/∆T Code = 0x80 15 ppm/°C
Full-Scale Error V
WFSE
Code = 0xFF –3 –1 0 LSB
Zero-Scale Error V
WZSE
Code = 0x00 0 1 3 LSB
RESISTOR TERMINALS
Voltage Range5 V
A,B,W
GND V
DD
V
Capacitance6 A, B CA,B f = 1 MHz, measured to
GND, Code = 0x80
45 pF
Capacitance
6
W CW f = 1 MHz, measured to
GND, Code = 0x80
60 pF
Shutdown Supply Current7 I
DD_SD
V
DD
= 5.5 V 0.01 1 µA
Common-Mode Leakage I
CM
V
A
= V
B
= V
DD
/2 1 nA
DIGITAL INPUTS AND OUTPUTS
Input Logic High V
IH
2.4 V
Input Logic Low V
IL
0.8 V
Input Logic High V
IH
V
DD
= 3 V 2.1 V
Input Logic Low
VIL
VDD = 3 V
0.6
V
Input Current I
IL
V
IN
= 0 V or 5 V ±1 µA
Input Capacitance
6
C
IL
5 pF
POWER SUPPLIES
Power Supply Range V
DD RANGE
2.7 5.5 V
Supply Current I
DD
V
IH
= 5 V or V
IL
= 0 V 3 8 µA
Power Dissipation8 PDISS VIH = 5 V or VIL = 0 V,
V
DD
= 5 V
0.2 mW
Power Supply Sensitivity
PSS
∆V
DD
= +5 V ± 10%,
Code = Midscale
±0.02
±0.05
%/%
DYNAMIC CHARACTERISTICS6, 9
Bandwidth –3dB BW RAB = 10 kΩ/50 kΩ/100 kΩ,
Code = 0x80
600/100/40 kHz
Total Harmonic Distortion THDW VA =1 V rms, VB = 0 V,
f = 1 kHz, R
AB
= 10 kΩ
0.05 %
VW Settling Time (10 kΩ/50 kΩ/100 kΩ) tS VA = 5 V, VB = 0 V,
±1 LSB error band
2 µs
Resistor Noise Voltage Density e
N_WB
R
WB
= 5 kΩ, RS = 0 9 nV/√Hz
Data Sheet AD5161
Rev. B | Page 5 of 20
TIMING CHARACTERISTICS—5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ VERSIONS
VDD = +5V ± 10%, or +3V ± 10%; VA = VDD; VB = 0 V; –40°C < TA < +125°C; unless otherwise noted.
Table 3.
Parameter Symbol Conditions Min Typ
1
Max Unit
SPI INTERFACE TIMING CHARACTERISTICS6, 10 (Specifications Apply to All Parts)
Clock Frequency f
CLK
25 MHz
Input Clock Pulsewidth t
CH
, t
CL
Clock level high or low 20 ns
Data Setup Time t
DS
5 ns
Data Hold Time t
DH
5 ns
CS Setup Time tCSS 15 ns
CS High Pulsewidth tCSW 40 ns
CLK Fall to CS Fall Hold Time tCSH0 0 ns
CLK Fall to CS Rise Hold Time tCSH1 0 ns
CS Rise to Clock Rise Setup tCS1 10 ns
I
2
C INTERFACE TIMING CHARACTERISTICS
6, 11
(Specifications Apply to All Parts)
SCL Clock Frequency f
SCL
400 kHz
t
BUF
Bus Free Time between STOP and START t
1
1.3 µs
tHD;STA Hold Time (Repeated START ) t2 After this period, the first clock pulse is
generated.
0.6 µs
t
LOW
Low Period of SCL Clock t
3
1.3 µs
t
HIGH
High Period of SCL Clock t
4
0.6 50 µs
t
SU;STA
Setup Time for Repeated START Condition t
5
0.6 µs
t
HD ;DAT
Data Hold Time t
6
0.9 µs
tSU;DAT Data Setup Time
t7
100
ns
t
F
Fall Time of Both SDA and SCL Signals t
8
300 ns
t
R
Rise Time of Both SDA and SCL Signals t
9
300 ns
t
SU;STO
Setup Time for STOP Condition t
10
0.6 µs
NOTES
1 Typical specifications represent average readings at +25°C and VDD = 5 V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic.
3 VAB = VDD, Wiper (VW) = no connect.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions.
5 Resistor terminals A, B, W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test.
7 Measured at the A terminal. The A terminal is open circuited in shutdown mode.
8 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
9 All dynamic characteristics use VDD = 5 V.
10 See timing diagram for location of measured values. All input control voltages are specified with tR = tF = 2 ns (10% to 90% of 3 V) and timed from a voltage
level of 1.5 V.
11 See timing diagrams for locations of measured values.
AD5161 Data Sheet
Rev. B | Page 6 of 20
ABSOLUTE MAXIMUM RATINGS1
TA = 25°C, unless otherwise noted.
Table 4.
Parameter Value
V
DD
to GND –0.3 V to +7 V
V
A
, V
B
, V
W
to GND V
DD
I
MAX1
±20 mA
Digital Inputs and Output Voltage to GND 0 V to +7 V
Operating Temperature Range –40°C to +125°C
Maximum Junction Temperature (T
JMAX
) 150°C
Storage Temperature Range
–65°C to +150°C
Lead Temperature (Soldering, 10 sec) 300°C
Thermal Resistance
2
θ
JA
(10-Lead MSOP) 200°C/W
NOTES
1 Maximum terminal current is bounded by the maximum current handling of
the switches, maximum power dissipation of the package, and maximum
applied voltage across any two of the A, B, and W terminals at a given
resistance.
2 Package power dissipation = (TJMAX – TA)/θJA.
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
Data Sheet AD5161
Rev. B | Page 7 of 20
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
10
9
8
7
6
A
B
CS/ADO
SDO/NC
SDI/SDA
DD
AD5161
TOP VIEW
(Not to Scale)
W
V
DIS
GND
CLK/SCL
Figure 3. Pin Configuration
Table 5. Pin Function Description
Pin No. Mnemonic Description
1
A
A Terminal.
2 B B Terminal.
3 CS/AD0 Chip Select (CS) Input, Active Low. When CS returns high, data will be loaded into the DAC register.
Programmable address bit 0 (AD0) for multiple package decoding.
4 SDO/NC Serial Data Output (SDO). Open-drain transistor requires pull-up resistor.
No Connect (NC).
5 SDI/SDA Serial Data Input (SDI).
Serial Data Input/Output (SDA).
6 CLK/SCL Serial Clock Input. Positive edge triggered.
7 GND Digital Ground.
8 DIS Digital Interface Select (SPI/I2C Select). SPI when DIS = 0, I2C when DIS = 1.
9
VDD
Positive Power Supply.
10 W
W Terminal.
AD5161 Data Sheet
Rev. B | Page 8 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
CODE (Decimal)
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
1.0
320 96
64 128 160 192 224 256
RHEOSTAT MODE INL (LSB)
0.8
5V
3V
Figure 4. R-INL vs. Code vs. Supply Voltages
5V
3V
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
1.0
RHEOSTAT MODE DNL (LSB)
0.8
CODE (Decimal)
320 96
64 128 160 192 224 256
Figure 5. R-DNL vs. Code vs. Supply Voltages
_40°C
+25°C
+85°C
+125°C
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
1.0
POTENTIOMETER MODE INL (LSB)
0.8
CODE (Decimal)
320 96
64 128 160 192 224 256
Figure 6. INL vs. Code, VDD = 5 V
CODE (Decimal)
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
1.0
320 96
64 128 160 192 224 256
POTENTIOMETER MODE DNL (LSB)
0.8 –40°C
+25°C
+85°C
+125°C
Figure 7. DNL vs. Code, VDD = 5 V
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
1.0
POTENTIOMETER MODE INL (LSB)
0.8
CODE (Decimal)
320 96
64 128 160 192 224 256
5V
3V
Figure 8. INL vs. Code vs. Supply Voltages
5V
3V
CODE (Decimal)
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
320 96
64 128 160 192 224 256
POTENTIOMETER MODE DNL(LSB)
1.0
Figure 9. DNL vs. Code vs. Supply Voltages
Data Sheet AD5161
Rev. B | Page 9 of 20
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
1.0
RHEOSTAT MODE INL (LSB)
0.8
CODE (Decimal)
320 96
64 128 160 192 224 256
°C
+25°C
+85°C
+125°C
–40
Figure 10. R-INL vs. Code, VDD = 5 V
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
1.0
RHEOSTAT MODE DNL (LSB)
0.8
CODE (Decimal)
320 96
64 128 160 192 224 256
_40°C
+25°C
+85°C
+125°C
Figure 11. R-DNL vs. Code, VDD = 5 V
TEMPERATURE (°C)
0 40 80 120–40
0
1.5
FSE, FULL-SCALE ERROR (LSB)
0 40 80 120–40
1.0
2.5
V
DD
= 5.5V
V
DD
= 2.7V
2.0
0.5
Figure 12. Full-Scale Error vs. Temperature
0 40 80 120–40
0
1.5
ZSE, ZERO-SCALE ERROR (µA)
TEMPERATURE (°C)
0 40 80 120–40
1.0
2.5
V
DD
= 5.5V
V
DD
= 2.7V
2.0
0.5
Figure 13. Zero-Scale Error vs. Temperature
TEMPERATURE (°C)
0 40 80 120
–40
0.1
1
10
IDD SUPPLY CURRENT (µA)
VDD = 5.5V
VDD = 2.7V
Figure 14. Supply Current vs. Temperature
I
A
SHUTDOWN CURRENT (nA)
TEMPERATURE (°C)
00
70
20
10
30
40
50
60
40 80 120–40
V
DD
= 5V
Figure 15. Shutdown Current vs. Temperature
AD5161 Data Sheet
Rev. B | Page 10 of 20
CODE (Decimal)
–50
0
50
100
150
200
320 96
64 128 160 192 224 256
RHEOSTAT MODE TEMPCO (ppm/°C)
Figure 16. Rheostat Mode Tempco ∆RWB/∆T vs. Code
CODE (Decimal)
–20
0
20
40
60
80
100
120
140
160
320 96
64 128 160 192 224 256
POTENTIOMETER MODE TEMPCO (ppm/°C)
Figure 17. Potentiometer Mode Tempco ∆VWB/∆T vs. Code
1k 10k 100k 1M
0
–6
–
12
–
18
–
24
–
30
–
36
–
42
–
48
–
54
–
60
0x80
0x40
0x20
0x10
0x08
0x04
0x02
0x01
REF LEVEL
0.000dB
/DIV
6.000dB
MARKER 1 000 000.000Hz
MAG (A/R) –8.918dB
START 1 000.000Hz STOP 1 000 000.000Hz
Figure 18. Gain vs. Frequency vs. Code, RAB = 5 kΩ
1k 10k 100k 1M
0
–6
–12
–18
–24
–30
–36
–42
–48
–54
–60
0x80
0x40
0x20
0x10
0x08
0x04
0x02
0x01
REF LEVEL
0.000dB /DIV
6.000dB MARKER 510 634.725Hz
MAG (A/R) –9.049dB
START 1 000.000Hz STOP 1 000 000.000Hz
Figure 19. Gain vs. Frequency vs. Code, RAB = 10 kΩ
1k 10k 100k 1M
0
–6
–12
–18
–24
–30
–36
–42
–48
–54
–60
0x80
0x40
0x20
0x10
0x08
0x04
0x02
0x01
REF LEVEL
0.000dB /DIV
6.000dB MARKER 100 885.289Hz
MAG (A/R)
–9.014dB
START 1 000.000Hz STOP 1 000 000.000Hz
Figure 20. Gain vs. Frequency vs. Code, RAB = 50 kΩ
1k 10k 100k 1M
0
–6
–
12
–
18
–
24
–
30
–
36
–
42
–
48
–
54
–
60
0x80
0x40
0x20
0x10
0x08
0x04
0x02
0x01
REF LEVEL
0.000dB
/DIV
6.000dB
MARKER 54 089.173Hz
MAG (A/R) –9.052dB
START 1 000.000Hz STOP 1 000 000.000Hz
Figure 21. Gain vs. Frequency vs. Code, RAB = 100 kΩ
Data Sheet AD5161
Rev. B | Page 11 of 20
10k 100k 1M 10M
–5.5
–6.0
–6.5
–7.0
–7.5
–8.0
–8.5
–9.0
–9.5
–10.0
–10.5
REF LEVEL
–5.000dB /DIV
0.500dB
START 1 000.000Hz STOP 1 000 000.000Hz
R = 5kΩ
R = 10kΩ
R = 50kΩ
R = 100kΩ
5kΩ– 1.026 MHz
10kΩ– 511 MHz
50kΩ– 101 MHz
100kΩ– 54 MHz
Figure 22. –3 dB Bandwidth @ Code = 0x80
FREQUENCY (Hz)
10k
100 100k 1M1k
0
20
40
60
PSRR (dB)
CODE = 0x80, V
A
= V
DD
, V
B
= 0V
PSRR @ V
DD
= 3V DC ± 10% p-p AC
PSRR @ V
DD
= 5V DC ± 10% p-p AC
Figure 23. PSRR vs. Frequency
I
DD
(µA)
FREQUENCY (Hz)
10k
800
700
600
500
400
300
900
200
100
100k 1M 10M
0
CODE = 0x55
CODE = 0xFF
V
DD
= 5V
Figure 24. IDD vs. Frequency
VW
CLK
Ch 1 200mV
BW
Ch 2 5.00 V
BW
M 100ns A CH2 3.00 V
1
2
Figure 25. Digital Feedthrough
VW
CS
Ch 1 100mV
BW
Ch 2 5.00 V
BW
M 200ns A CH1 152mV
1
2
V
A
= 5V
V
B
= 0V
Figure 26. Midscale Glitch, Code 0x80–0x7F
VW
CS
Ch 1 5.00V BWCh 2 5.00 V BWM 200ns A CH1 3.00 V
1
2
VA = 5V
VB = 0V
Figure 27. Large Signal Settling Time, Code 0xFF–0x00
AD5161 Data Sheet
Rev. B | Page 12 of 20
TEST CIRCUITS
Figure 28 to Figure 36 illustrate the test circuits that define the test conditions used in the product specification tables.
V
MS
AW
B
DUT V+ = V
DD
1LSB = V+/2
N
V+
Figure 28. Test Circuit for Potentiometer Divider Nonlinearity Error (INL, DNL)
NO CONNECT
I
W
V
MS
AW
B
DUT
Figure 29. Test Circuit for Resistor Position Nonlinearity Error
(Rheostat Operation; R-INL, R-DNL)
V
MS1
I
W
= V
DD
/R
NOMINAL
V
MS2
V
W
R
W
= [V
MS1
– V
MS2
]/I
W
AW
B
DUT
Figure 30. Test Circuit for Wiper Resistance
∆V
∆V
∆V
∆V
MS
%
DD
%
PSS (%/%) =
V+ = V
DD
10%
PSRR (dB) = 20 LOG
MS
DD
( )
V
DD
V
A
V
MS
AW
B
V+
Figure 31. Test Circuit for Power Supply Sensitivity (PSS, PSSR)
OP279
W5V
B
V
OUT
OFFSET
GND OFFSET
BIAS
ADUT
V
IN
Figure 32. Test Circuit for Inverting Gain
B
A
V
IN
OP279
W
5V
V
OUT
OFFSET
GND
OFFSET
BIAS
DUT
Figure 33. Test Circuit for Noninverting Gain
+15V
–15V
W
A
2.5V B
V
OUT
OFFSET
GND
DUT AD8610
V
IN
Figure 34. Test Circuit for Gain vs. Frequency
W
B
V
SS
TO V
DD
DUT
I
SW
CODE = 0x00
R
SW
=0.1V
I
SW
0.1V
Figure 35. Test Circuit for Incremental ON Resistance
W
BV
CM
I
CM
A
NC
GND
NC
V
SS
V
DD
DUT
NC = NO CONNECT
Figure 36. Test Circuit for Common-Mode Leakage Current
Data Sheet AD5161
Rev. B | Page 13 of 20
SPI INTERFACE
Table 6. AD5161 Serial Data-Word Format
B7 B6 B5 B4 B3 B2 B1 B0
D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB
2
7
2
0
SDI
CLK
CS
VOUT
1
0
1
0
1
0
1
0
D7 D6 D5 D4 D3 D2 D1 D0
RDAC REGISTER LOAD
Figure 37. SPI Interface Timing Diagram (VA = 5 V, VB = 0 V, VW = VOUT)
t
CSHO
t
CSS
t
CL
t
CH
t
DS
t
CSW
t
S
t
CS1
t
CSH1
t
CH
SDI
CLK
CS
VOUT
1
0
1
0
1
0
VDD
0
±1LSB
(DATA IN)
Dx Dx
Figure 38. SPI Interface Detailed Timing Diagram (VA = 5 V, VB = 0 V, VW = VOUT)
AD5161 Data Sheet
Rev. B | Page 14 of 20
I2C INTERFACE
Table 7. Write Mode
S 0 1 0 1 1 0 AD0 W
A X RS SD X X X X X A D7 D6 D5 D4 D3 D2 D1 D0 A P
Slave Address Byte Instruction Byte Data Byte
Table 8. Read Mode
S 0 1 0 1 1 0 AD0 R A D7 D6 D5 D4 D3 D2 D1 D0 A P
Slave Address Byte Data Byte
S = Start Condition
P = Stop Condition
A = Acknowledge
X = Don’t Care
W = Write
R = Read
RS = Reset wiper to Midscale 80H
SD = Shutdown connects wiper to B terminal and open circuits
A terminal. It does not change contents of wiper register.
D7, D6, D5, D4, D3, D2, D1, D0 = Data Bits.
t
1
t
3
t
4
t
2
t
7
t
8
t
9
P S PS
t
10
t
5
t
9
t
8
SCL
SDA
t
2
t
6
Figure 39. I2C Interface Detailed Timing Diagram
SCL
FRAME 1 FRAME 2
START BY
MASTER
ACK BY
AD5161
SLAVE ADDRESS BYTE STOP BY
MASTER
INSTRUCTION BYTE
SDA 01011 0 AD0 R/W X RS X X X X X
191 9
D7 D6 D5 D4 D3 D2 D1 D0
ACK BY
AD5161 FRAME 3
DATA BYTE
19
ACK BY
AD5161
SD
Figure 40. Writing to the RDAC Register
NO ACK
BY MASTER
SCL
SDA 01 0 1 1 0 AD0 R/W D7 D6 D5 D4 D3 D2 D1 D0
1919
FRAME 1 FRAME 2
START BY
MASTER
ACK BY
AD5161
SLAVE ADDRESS BYTE RDAC REGISTER STOP BY
MASTER
Figure 41. Reading Data from a Previously Selected RDAC Register in Write Mode
Data Sheet AD5161
Rev. B | Page 15 of 20
THEORY OF OPERATION
The AD5161 is a 256-position digitally controlled variable
resistor (VR)1 device.
An internal power-on preset places the wiper at midscale during
power-on, which simplifies the fault condition recovery at power-up.
PROGRAMMING THE VARIABLE RESISTOR
Rheostat Operation
The nominal resistance of the RDAC between terminals A and
B is available in 5 kΩ, 10 kΩ, 50 kΩ, and 100 kΩ. The final two
or three digits of the part number determine the nominal resistance
value, e.g., 10 kΩ = 10; 50 kΩ = 50. The nominal resistance (RAB) of
the VR has 256 contact points accessed by the wiper terminal,
plus the B terminal contact. The 8-bit data in the RDAC latch is
decoded to select one of the 256 possible settings. Assume a 10 kΩ
part is used, the wiper’s first connection starts at the B terminal
for data 0x00. Since there is a 60 Ω wiper contact resistance, such
connection yields a minimum of 60 Ω resistance between
Terminals W and B. The second connection is the first tap point,
which corresponds to 99 Ω (RWB = RAB/256 + RW = 39 Ω + 60 Ω)
for data 0x01. The third connection is the next tap point,
representing 177 Ω (2 × 39 Ω + 60 Ω) for data 0x02 and so on. Each
LSB data value increase moves the wiper up the resistor ladder
until the last tap point is reached at 9961 Ω (RAB – 1 LSB + RW).
Figure 42 shows a simplified diagram of the equivalent RDAC
circuit where the last resistor string will not be accessed;
therefore, there is 1 LSB less of the nominal resistance at full
scale in addition to the wiper resistance.
B
RDAC
LATCH
AND
DECODER
W
A
R
S
R
S
R
S
R
S
SD BIT
D7
D6
D4
D5
D2
D3
D1
D0
Figure 42. AD5161 Equivalent RDAC Circuit
1 The terms digital potentiometer, VR, and RDAC are used interchangeably.
The general equation determining the digitally programmed
output resistance between W and B is
W
AB
WB RR
D
DR 256
)( (1)
where D is the decimal equivalent of the binary code loaded in
the 8-bit RDAC register, RAB is the end-to-end resistance, and
RW is the wiper resistance contributed by the on resistance of
the internal switch.
In summary, if RAB = 10 kΩ and the A terminal is open circuited,
the following output resistance RWB will be set for the indicated
RDAC latch codes.
Table 9. Codes and Corresponding RWB Resistance
D (Dec.) RWB (Ω) Output State
255 9,961 Full Scale (RAB – 1 LSB + RW)
128 5,060 Midscale
1 99 1 LSB
0 60 Zero Scale (Wiper Contact Resistance)
Note that in the zero-scale condition a finite wiper resistance of
60 Ω is present. Care should be taken to limit the current flow
between W and B in this state to a maximum pulse current of
no more than 20 mA. Otherwise, degradation or possible
destruction of the internal switch contact can occur.
Similar to the mechanical potentiometer, the resistance of the
RDAC between the wiper W and terminal A also produces a
digitally controlled complementary resistance RWA . When these
terminals are used, the B terminal can be opened. Setting the
resistance value for RWA starts at a maximum value of resistance
and decreases as the data loaded in the latch increases in value.
The general equation for this operation is
W
ABWA RR
D
DR
256
256
)( (2)
For RAB = 10 kΩ and the B terminal open circuited, the
following output resistance RWA will be set for the indicated
RDAC latch codes.
Table 10. Codes and Corresponding RWA Resistance
D (Dec.) RWA (Ω) Output State
255 99 Full Scale
128 5,060 Midscale
1 9,961 1 LSB
0 10,060 Zero Scale
Typical device to device matching is process lot dependent and
may vary by up to ±30%. Since the resistance element is processed
in thin film technology, the change in RAB with temperature has
a very low 45 ppm/°C temperature coefficient.
AD5161 Data Sheet
Rev. B | Page 16 of 20
PROGRAMMING THE POTENTIOMETER DIVIDER
Voltage Output Operation
The digital potentiometer easily generates a voltage divider at
wiper-to-B and wiper-to-A proportional to the input voltage at
A-to-B. Unlike the polarity of VDD to GND, which must be
positive, voltage across A-B, W-A, and W-B can be at either
polarity.
If ignoring the effect of the wiper resistance for approximation,
connecting the A terminal to 5 V and the B terminal to ground
produces an output voltage at the wiper-to-B starting at 0 V up
to 1 LSB less than 5 V. Each LSB of voltage is equal to the
voltage applied across terminal AB divided by the 256 positions
of the potentiometer divider. The general equation defining the
output voltage at VW with respect to ground for any valid input
voltage applied to terminals A and B is
B
A
WV
D
V
D
DV
256
256
256
)( −
+=
(3)
For a more accurate calculation, which includes the effect of
wiper resistance, VW, can be found as
B
WA
A
WB
W
V
DR
V
DR
DV
256
)
(
256
)(
)( +=
(4)
Operation of the digital potentiometer in the divider mode
results in a more accurate operation over temperature. Unlike
the rheostat mode, the output voltage is dependent mainly on
the ratio of the internal resistors RWA and RWB and not the
absolute values. Therefore, the temperature drift reduces to
15 ppm/°C.
PIN SELECTABLE DIGITAL INTERFACE
The AD5161 provides the flexibility of a selectable interface.
When the digital interface select (DIS) pin is tied low, the SPI
mode is engaged. When the DIS pin is tied high, the I2C mode
is engaged.
SPI Compatible 3-Wire Serial Bus (DIS = 0)
The AD5161 contains a 3-wire SPI compatible digital interface
(SDI, CS, and CLK). The 8-bit serial word must be loaded MSB
first. The format of the word is shown in Table 6.
The positive-edge sensitive CLK input requires clean transitions
to avoid clocking incorrect data into the serial input register.
Standard logic families work well. If mechanical switches are
used for product evaluation, they should be debounced by a
flip-flop or other suitable means. When CS is low, the clock
loads data into the serial register on each positive clock edge
(see Figure 37).
The data setup and data hold times in the specification table
determine the valid timing requirements. The AD5161 uses an
8-bit serial input data register word that is transferred to the
internal RDAC register when the CS line returns to logic high.
Extra MSB bits are ignored.
Daisy-Chain Operation
The serial data output (SDO) pin contains an open-drain
N-channel FET. This output requires a pull-up resistor in order
to transfer data to the next package’s SDI pin. This allows for
daisy-chaining several RDACs from a single processor serial
data line. The pull-up resistor termination voltage can be larger
than the VDD supply voltage. It is recommended to increase the
clock period when using a pull-up resistor to the SDI pin of the
following device because capacitive loading at the daisy-chain
node SDO-SDI between devices may induce time delay to
subsequent devices. Users should be aware of this potential
problem to achieve data transfer successfully (see Figure 43). If
two AD5161s are daisy-chained, a total of at least 16 bits of data
is required. The first eight bits, complying with the format
shown in Table 6, go to U2 and the second eight bits with the
same format go to U1. CS should be kept low until all 16 bits are
clocked into their respective serial registers. After this, CS is
pulled high to complete the operation and load the RDAC latch.
If the data word during the CS low period is greater than 16
bits, any additional MSBs will be discarded.
AD5161 AD5161
U2
µC
U1
CS
SDI CLKCLK SDO
CS CLK
SDISDO
SC
MOSI
V
DD
R
P
2.2kΩ
Figure 43. Daisy-Chain Configuration
I2C Compatible 2-Wire Serial Bus (DIS = 1)
The AD5161 can also be controlled via an I2C compatible serial
bus with DIS tied high. The RDACs are connected to this bus as
slave devices.
The first byte of the AD5161 is a slave address byte (see Table 7
and Table 8). It has a 7-bit slave address and a R/W bit. The six
MSBs of the slave address are 010110, and the following bit is
determined by the state of the AD0 pin of the device. AD0
allows the user to place up to two of the I2C compatible devices
on one bus.
The 2-wire I2C serial bus protocol operates as follows:
1. The master initiates data transfer by establishing a START
condition, which is when a high-to-low transition on the
SDA line occurs while SCL is high (see Figure 40). The
following byte is the slave address byte, which consists of
the 7-bit slave address followed by an R/W bit (this bit
determines whether data will be read from or written to
the slave device).
Data Sheet AD5161
Rev. B | Page 17 of 20
The slave whose address corresponds to the transmitted
address responds by pulling the SDA line low during the
ninth clock pulse (this is termed the acknowledge bit). At
this stage, all other devices on the bus remain idle while the
selected device waits for data to be written to or read from
its serial register. If the R/W bit is high, the master will read
from the slave device. On the other hand, if the R/W bit is
low, the master will write to the slave device.
2. A write operation contains an extra instruction byte that a
read operation does not contain. Such an instruction byte
in write mode follows the slave address byte. The first bit
(MSB) of the instruction byte is a don’t care.
The second MSB, RS, is the midscale reset. A logic high on
this bit moves the wiper to the center tap where RWA = RWB.
This feature effectively writes over the contents of the
register, and thus, when taken out of reset mode, the
RDAC will remain at midscale.
The third MSB, SD, is a shutdown bit. A logic high causes
an open circuit at terminal A while shorting the wiper to
terminal B. This operation yields almost 0 Ω in rheostat
mode or 0 V in potentiometer mode. It is important to
note that the shutdown operation does not disturb the
contents of the register. When brought out of shutdown,
the previous setting will be applied to the RDAC. Also,
during shutdown, new settings can be programmed. When
the part is returned from shutdown, the corresponding VR
setting will be applied to the RDAC.
The remainder of the bits in the instruction byte are don’t
cares (see Table 7).
3. After acknowledging the instruction byte, the last byte in
write mode is the data byte. Data is transmitted over the
serial bus in sequences of nine clock pulses (eight data bits
followed by an acknowledge bit). The transitions on the
SDA line must occur during the low period of SCL and
remain stable during the high period of SCL (see Table 7).
4. In the read mode, the data byte follows immediately after
the acknowledgment of the slave address byte. Data is
transmitted over the serial bus in sequences of nine clock
pulses (a slight difference with the write mode, where there
are eight data bits followed by an acknowledge bit).
Similarly, the transitions on the SDA line must occur
during the low period of SCL and remain stable during the
high period of SCL (see Figure 41).
5. When all data bits have been read or written, a STOP
condition is established by the master. A STOP condition is
defined as a low-to-high transition on the SDA line while
SCL is high. In write mode, the master will pull the SDA
line high during the tenth clock pulse to establish a STOP
condition (see Figure 40). In read mode, the master will
issue a No Acknowledge for the ninth clock pulse (i.e., the
SDA line remains high). The master will then bring the
SDA line low before the tenth clock pulse which goes high
to establish a STOP condition (see Figure 41).
A repeated write function gives the user flexibility to update the
RDAC output a number of times after addressing and instructing
the part only once. During the write cycle, each data byte will
update the RDAC output. For example, after the RDAC has
acknowledged its slave address and instruction bytes, the RDAC
output will update after these two bytes. If another byte is written to
the RDAC while it is still addressed to a specific slave device
with the same instruction, this byte will update the output of
the selected slave device. If different instructions are needed, the
write mode has to start again with a new slave address, instruction,
and data byte. Similarly, a repeated read function of the RDAC
is also allowed.
Readback RDAC Value
The AD5161 allows the user to read back the RDAC values in the
read mode. Refer to Table 7 and Table 8 for the programming format.
Multiple Devices on One Bus
Figure 44 shows two AD5161 devices on the same serial bus.
Each has a different slave address since the states of their AD0
pins are different. This allows each RDAC within each device to
be written to or read from independently. The master device
output bus line drivers are open-drain pull-downs in a fully I2C
compatible interface.
MASTER
AD5161
SDA SCL
RPRP
+5V
+5V
SDA
SCL
SDA SCL
AD5161
AD0 AD0
Figure 44. Multiple AD5161 Devices on One I2C Bus
AD5161 Data Sheet
Rev. B | Page 18 of 20
LEVEL SHIFTING FOR BIDIRECTIONAL INTERFACE
While most legacy systems may be operated at one voltage, a
new component may be optimized at another. When two systems
operate the same signal at two different voltages, proper level
shifting is needed. For instance, one can use a 3.3 V E2PROM to
interface with a 5 V digital potentiometer. A level shifting scheme is
needed to enable a bidirectional communication so that the setting
of the digital potentiometer can be stored to and retrieved from
the E2PROM. Figure 45 shows one of the implementations. M1
and M2 can be any N-channel signal FETs, or if VDD falls below
2.5 V, low threshold FETs such as the FDV301N.
E
2
PROM AD5161
SDA1
SCL1
D
G
R
P
R
P
3.3V 5V
S
M1 SCL2
SDA2
R
P
R
P
G
S
M2
V
DD1
= 3.3V V
DD2 =
5V
D
Figure 45. Level Shifting for Operation at Different Potentials
ESD PROTECTION
All digital inputs are protected with a series input resistor and
parallel Zener ESD structures shown in Figure 46 and Figure 47.
This applies to the digital input pins SDI/SDA, CLK/SCL, and
CS/AD0.
LOGIC
340Ω
Vss
Figure 46. ESD Protection of Digital Pins
A,B,W
VSS
Figure 47. ESD Protection of Resistor Terminals
TERMINAL VOLTAGE OPERATING RANGE
The AD5161 VDD and GND power supply defines the boundary
conditions for proper 3-terminal digital potentiometer
operation. Supply signals present on terminals A, B, and W that
exceed VDD or GND will be clamped by the internal forward
biased diodes (see Figure 48).
A
V
DD
B
W
V
SS
Figure 48. Maximum Terminal Voltages Set by VDD and VSS
POWER-UP SEQUENCE
Since the ESD protection diodes limit the voltage compliance at
terminals A, B, and W (see Figure 48), it is important to power
VDD/GND before applying any voltage to terminals A, B, and W;
otherwise, the diode will be forward biased such that VDD will
be powered unintentionally and may affect the rest of the user’s
circuit. The ideal power-up sequence is in the following order:
GND, VDD, digital inputs, and then VA/B/W. The relative order of
powering VA, VB, VW, and the digital inputs is not important as
long as they are powered after VDD/GND.
LAYOUT AND POWER SUPPLY BYPASSING
It is a good practice to employ compact, minimum lead length
layout design. The leads to the inputs should be as direct as
possible with a minimum conductor length. Ground paths
should have low resistance and low inductance.
Similarly, it is also a good practice to bypass the power supplies
with quality capacitors for optimum stability. Supply leads to
the device should be bypassed with disc or chip ceramic
capacitors of 0.01 µF to 0.1 µF. Low ESR 1 µF to 10 µF tantalum
or electrolytic capacitors should also be applied at the supplies
to minimize any transient disturbance and low frequency ripple
(see Figure 49). Note that the digital ground should also be
joined remotely to the analog ground at one point to minimize
the ground bounce.
AD5161
V
DD
C1
C3
GND
10µF0.1µF
+V
DD
Figure 49. Power Supply Bypassing
Data Sheet AD5161
Rev. B | Page 19 of 20
OUTLINE DIMENSIONS
COMPLIANT TO JEDEC STANDARDS MO-187-BA
091709-A
6°
0°
0.70
0.55
0.40
5
10
1
6
0.50 BSC
0.30
0.15
1.10 MAX
3.10
3.00
2.90
COPLANARITY
0.10
0.23
0.13
3.10
3.00
2.90
5.15
4.90
4.65
PIN 1
IDENTIFIER
15° MAX
0.95
0.85
0.75
0.15
0.05
Figure 50. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
ORDERING GUIDE
Model
1, 2
R
AB
(Ω) Temperature Package Description Package Option Branding
AD5161BRM5 5k –40°C to +125°C 10-Lead MSOP RM-10 D0C
AD5161BRM5-RL7 5k –40°C to +125°C 10-Lead MSOP RM-10 D0C
AD5161BRMZ5 5k –40°C to +125°C 10-Lead MSOP RM-10 D0C#
AD5161BRMZ5-RL7 5k –40°C to +125°C 10-Lead MSOP RM-10 D0C#
AD5161BRM10 10k –40°C to +125°C 10-Lead MSOP RM-10 D0D
AD5161BRM10-RL7 10k –40°C to +125°C 10-Lead MSOP RM-10 D0D
AD5161BRMZ10 10k –40°C to +125°C 10-Lead MSOP RM-10 D0D#
AD5161BRMZ10-RL7 10k –40°C to +125°C 10-Lead MSOP RM-10 D0D#
AD5161BRM50 50k –40°C to +125°C 10-Lead MSOP RM-10 D0E
AD5161BRM50-RL7 50k –40°C to +125°C 10-Lead MSOP RM-10 D0E
AD5161BRMZ50
50k
–40°C to +125°C
10-Lead MSOP
RM-10
D0E#
AD5161BRMZ50-RL7 50k –40°C to +125°C 10-Lead MSOP RM-10 D0E#
AD5161BRM100 100k –40°C to +125°C 10-Lead MSOP RM-10 D0F
AD5161BRM100-RL7 100k –40°C to +125°C 10-Lead MSOP RM-10 D0F
AD5161BRMZ100 100k –40°C to +125°C 10-Lead MSOP RM-10 D0F#
AD5161BRMZ100-RL7 100k –40°C to +125°C 10-Lead MSOP RM-10 D0F#
EVAL-AD5161EBZ See Note 2 Evaluation Board
1 Z = RoHS Compliant Part, # denotes RoHS compliant part may be top or bottom marked.
2 The EVAL-AD5161EBZ evaluation board is shipped with the 10 kΩ RAB resistor option; however, the board is compatible with all available resistor value options.
The AD5161 contains 2532 transistors. Die size: 30.7 mil × 76.8 mil = 2358 sq. mil.
AD5161 Data Sheet
Rev. B | Page 20 of 20
NOTES
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©2003–2012 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D03435-0-8/12(B)