MC74VHCT374ADWR2G - ON Semiconductor L.L.C.

January, 2006 − Rev. 4 1Publication Order Number:

MC74VHCT374A/D

MC74VHCT374A

Octal D−Type Flip−Flop

with 3−State Output

The MC74VHCT374A is an advanced high speed CMOS octal

flip−flop with 3−state output fabricated with silicon gate CMOS

technology. It achieves high speed operation similar to equivalent

Bipolar Schottky TTL while maintaining CMOS low power

dissipation.

This 8−bit D−type flip−flop is controlled by a clock input and an

output enable input. When the output enable input is high, the eight

outputs are in a high impedance state.

The internal circuit is composed of three stages, including a buffer

output which provides high noise immunity and stable output.

The VHCT inputs are compatible with TTL levels. This device can

be used as a level converter for interfacing 3.3 V to 5.0 V, because it

has full 5.0 V CMOS level output swings.

The VHCT374A input and output (when disabled) structures

provide protection when voltages between 0 V and 5.5 V are applied,

regardless of the supply voltage. These input and output structures

help prevent device destruction caused by supply

voltage−input/output voltage mismatch, battery backup, hot insertion,

etc.

Features

•High Speed: fmax = 140 MHz (Typ) at VCC = 5.0 V

•Low Power Dissipation: ICC = 4 mA (Max) at TA = 25°C

•TTL−Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V

•Power Down Protection Provided on Inputs and Outputs

•Balanced Propagation Delays

•Designed for 4.5 V to 5.5 V Operating Range

•Low Noise: VOLP = 1.6 V (Max)

•Pin and Function Compatible with Other Standard Logic Families

•Latchup Performance Exceeds 300 mA

•ESD Performance:

Human Body Model > 2000 V;

Machine Model > 200 V

•Chip Complexity: 276 FETs or 69 Equivalent Gates

•Pb−Free Packages are Available*

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

SOEIAJ−20

SUFFIX M

CASE 967

http://onsemi.com

See detailed ordering and shipping information in the package

dimensions section on page 4 of this data sheet.

ORDERING INFORMATION

MARKING

DIAGRAMS

74VHCT374

AWLYWWG

20

1

20

1

TSSOP−20

SUFFIX DT

CASE 948E

SOIC−20WB

SUFFIX DW

CASE 751D

VHCT

374A

ALYWG

G

1

20

1

VHCT374A

AWLYYWWG

A = Assembly Location

WL, L = Wafer Lot

YY, Y = Year

WW, W = Work Week

G or G= Pb−Free Package

(Note: Microdot may be in either location)

OE CP Q

L

HL, H,

X

H

L

No Change

Z

INPUTS OUTPUT

FUNCTION TABLE

D

H

L

X

MC74VHCT374A

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2

Figure 1. Logic Diagram

DATA

INPUTS

D0

D1

D2

D3

D4

D5

D6

D7 18

17

14

13

8

7

4

3

1

OE

19

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

16

15

12

9

6

5

2

NONINVERTING

OUTPUTS

11

CP

Figure 2. Pin Assignment

Q2

D1

D0

Q0

OE

GND

Q3

D3

D2

Q1 5

4

3

2

1

10

9

8

7

6

14

15

16

17

18

19

20

11

12

13

Q6

D6

D7

Q7

VCC

CP

Q4

D4

D5

Q5

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

MAXIMUM RATINGS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎ

Value

ÎÎÎ

Unit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage

ÎÎÎÎÎ

– 0.5 to + 7.0

ÎÎÎ

V

ÎÎÎÎ

Vin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage

ÎÎÎÎÎ

– 0.5 to + 7.0

ÎÎÎ

V

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Voltage Outputs in 3−State

High or Low State

ÎÎÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎÎÎ

– 0.5 to + 7.0

– 0.5 to VCC + 0.5

ÎÎÎ

Î

ÎÎÎ

V

ÎÎÎÎ

IIK

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Input Diode Current

ÎÎÎÎÎ

− 20

ÎÎÎ

mA

ÎÎÎÎ

IOK

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Output Diode Current (VOUT < GND; VOUT > VCC)

ÎÎÎÎÎ

±20

ÎÎÎ

mA

ÎÎÎÎ

Iout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Current, per Pin

ÎÎÎÎÎ

±25

ÎÎÎ

mA

ÎÎÎÎ

ICC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Current, VCC and GND Pins

ÎÎÎÎÎ

±75

ÎÎÎ

mA

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

PD

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Power Dissipation in Still Air, SOIC Package†

TSSOP Package†

ÎÎÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎÎÎ

500

450

ÎÎÎ

Î

ÎÎÎ

mW

ÎÎÎÎ

Tstg

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Storage Temperature

ÎÎÎÎÎ

– 65 to + 150

ÎÎÎ

_C

Maximum ratings are those values beyond which device damage can occur. Maximum ratings

applied to the device are individual stress limit values (not normal operating conditions) and are

not valid simultaneously. If these limits are exceeded, device functional operation is not implied,

damage may occur and reliability may be affected.

† Derating − SOIC Packages: – 7 mW/_C from 65_ to 125_C

TSSOP Package: − 6.1 mW/_C from 65_ to 125_C

RECOMMENDED OPERATING CONDITIONS

ÎÎÎÎ

Symbol

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎ

Min

ÎÎÎ

Max

ÎÎÎ

Unit

ÎÎÎÎ

VCC

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Supply Voltage

ÎÎÎ

4.5

ÎÎÎ

5.5

ÎÎÎ

V

ÎÎÎÎ

Vin

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Input Voltage

ÎÎÎ

0

ÎÎÎ

5.5

ÎÎÎ

V

ÎÎÎÎ

Vout

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC Output Voltage Outputs in 3−State

High or Low State

ÎÎÎ

0

ÎÎÎ

5.5

VCC

ÎÎÎ

V

ÎÎÎÎ

TA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Operating Temperature

ÎÎÎ

− 40

ÎÎÎ

+ 85

ÎÎÎ

_C

ÎÎÎÎ

tr, tf

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

Input Rise and Fall Time VCC =5.0V ±0.5V

ÎÎÎ

0

ÎÎÎ

20

ÎÎÎ

ns/V

This device contains protection

circuitry to guard against damage

due to high static voltages or electric

fields. However, precautions must

be taken to avoid applications of any

voltage higher than maximum rated

voltages to this high−impedance cir-

cuit. For proper operation, Vin and

Vout should be constrained to the

range GND v (Vin or Vout) v VCC.

Unused inputs must always be

tied to an appropriate logic voltage

level (e.g., either GND or VCC).

Unused outputs must be left open.

MC74VHCT374A

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3

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

DC ELECTRICAL CHARACTERISTICS

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

Symbo

l

ÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎ

Î

ÎÎÎ

VCC

V

ÎÎÎÎÎÎÎ

TA = 25°C

ÎÎÎÎÎÎ

TA = − 40 to 85°C

ÎÎ

Uni

t

ÎÎÎ

Min

ÎÎÎ

Typ

ÎÎÎ

Max

ÎÎÎ

Min

ÎÎÎÎ

Max

ÎÎÎÎ

VIH

ÎÎÎÎÎÎÎÎÎ

Minimum High−Level Input Voltage

ÎÎÎÎÎÎÎ

ÎÎÎ

4.5 to 5.5

ÎÎÎ

2.0

ÎÎÎ

2.0

ÎÎÎÎ

ÎÎ

V

ÎÎÎÎ

VIL

ÎÎÎÎÎÎÎÎÎ

Maximum Low−Level Input Voltage

ÎÎÎÎÎÎÎ

ÎÎÎ

4.5 to 5.5

ÎÎÎ

0.8

ÎÎÎ

ÎÎÎÎ

0.8

ÎÎ

V

ÎÎÎÎ

VOH

ÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎ

Minimum High−Level Output

Voltage Vin = VIH or VIL

ÎÎÎÎÎÎÎ

IOH = − 50mA

ÎÎÎ

4.5

ÎÎÎ

4.4

ÎÎÎ

4.5

ÎÎÎ

4.4

ÎÎÎÎ

ÎÎ

V

ÎÎÎÎ

ÎÎÎÎÎÎÎ

IOH = − 8mA

ÎÎÎ

4.5

ÎÎÎ

3.94

ÎÎÎ

3.80

ÎÎÎÎ

ÎÎ

ÎÎÎÎ

VOL

ÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎ

Maximum Low−Level Output

Voltage Vin = VIH or VIL

ÎÎÎÎÎÎÎ

IOL = 50mA

ÎÎÎ

4.5

ÎÎÎ

0.0

ÎÎÎ

0.1

ÎÎÎ

ÎÎÎÎ

0.1

ÎÎ

V

ÎÎÎÎ

ÎÎÎÎÎÎÎ

IOL = 8mA

ÎÎÎ

4.5

ÎÎÎ

0.36

ÎÎÎ

ÎÎÎÎ

0.44

ÎÎ

ÎÎÎÎ

Iin

ÎÎÎÎÎÎÎÎÎ

Maximum Input Leakage Current

ÎÎÎÎÎÎÎ

Vin = 5.5 V or GND

ÎÎÎ

0 to 5.5

ÎÎÎ

±0.1

ÎÎÎ

ÎÎÎÎ

±1.0

ÎÎ

mA

ÎÎÎÎ

IOZ

ÎÎÎÎÎÎÎÎÎ

Maximum 3−State Leak age Current

ÎÎÎÎÎÎÎ

Vin = VIL or VIH

Vout = VCC or GND

ÎÎÎ

5.5

ÎÎÎ

± 0.25

ÎÎÎ

ÎÎÎÎ

± 2.5

ÎÎ

mA

ÎÎÎÎ

ICC

ÎÎÎÎÎÎÎÎÎ

Maximum Quiescent Supply Current

ÎÎÎÎÎÎÎ

Vin = VCC or GND

ÎÎÎ

5.5

ÎÎÎ

4.0

ÎÎÎ

ÎÎÎÎ

40.0

ÎÎ

mA

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

ICCT

ÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎ

Quiescent Supply Current

ÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎ

ÎÎÎÎÎÎÎ

Per Input: VIN = 3.4V

Other Input: VCC or GND

ÎÎÎ

Î

ÎÎÎ

5.5

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

1.35

ÎÎÎ

Î

ÎÎÎ

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

1.50

ÎÎ

mA

ÎÎÎÎ

IOPD

ÎÎÎÎÎÎÎÎÎ

Output Leakage Current

ÎÎÎÎÎÎÎ

VOUT = 5.5V

ÎÎÎ

0

ÎÎÎ

0.5

ÎÎÎ

ÎÎÎÎ

5.0

ÎÎ

mA

ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ

AC ELECTRICAL CHARACTERISTICS (Input tr = tf = 3.0ns)

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

Symbo

l

ÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎ

Parameter

ÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎ

Test Conditions

ÎÎÎÎÎÎÎ

TA = 25°C

ÎÎÎÎÎÎ

TA = − 40 to 85°C

ÎÎ

Uni

t

ÎÎÎ

Min

ÎÎÎ

Typ

ÎÎÎ

Max

ÎÎÎ

Min

ÎÎÎÎ

Max

ÎÎÎÎ

fmax

ÎÎÎÎÎÎÎÎÎÎ

Maximum Clock Frequency

(50% Duty Cycle)

ÎÎÎÎÎÎÎÎÎ

VCC = 5.0 ± 0.5V CL = 15pF

CL = 50pF

ÎÎÎ

90

85

ÎÎÎ

140

130

ÎÎÎ

80

95

ÎÎÎÎ

ÎÎ

MHz

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

tPLH,

tPHL

ÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎ

Maximum Propagation Delay,

CP to Q

ÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎ

VCC = 5.0 ± 0.5V CL = 15pF

CL = 50pF

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

4.1

5.6

ÎÎÎ

Î

ÎÎÎ

9.4

10.4

ÎÎÎ

Î

ÎÎÎ

1.0

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

10.5

11.5

ÎÎ

ns

ÎÎÎÎ

tPZL,

tPZH

ÎÎÎÎÎÎÎÎÎÎ

Output Enable Time,

OE to Q

ÎÎÎÎÎÎÎÎÎ

VCC = 5.0 ± 0.5V CL = 15pF

RL = 1kWCL = 50pF

ÎÎÎ

6.5

7.3

ÎÎÎ

10.2

11.2

ÎÎÎ

1.0

ÎÎÎÎ

11.5

12.5

ÎÎ

ns

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

tPLZ,

tPHZ

ÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎ

Output Disable Time

OE to Q

ÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎ

VCC = 5.0 ± 0.5V CL = 50pF

RL = 1kW

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

7.0

ÎÎÎ

Î

ÎÎÎ

11.2

ÎÎÎ

Î

ÎÎÎ

1.0

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

12.0

ÎÎ

ns

ÎÎÎÎ

tOSLH,

tOSHL

ÎÎÎÎÎÎÎÎÎÎ

Output to Output Skew

ÎÎÎÎÎÎÎÎÎ

VCC = 5.0 ± 0.5V CL = 50pF

(Note 1)

ÎÎÎ

1.0

ÎÎÎ

ÎÎÎÎ

1.0

ÎÎ

ns

ÎÎÎÎ

Cin

ÎÎÎÎÎÎÎÎÎÎ

Maximum Input Capacitance

ÎÎÎÎÎÎÎÎÎ

ÎÎÎ

4

ÎÎÎ

10

ÎÎÎ

ÎÎÎÎ

10

ÎÎ

pF

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

Cout

ÎÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎÎ

Maximum 3−State Output Capacit anc e

(Output in High−Impedance Stat e)

ÎÎÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎ

Î

ÎÎÎÎÎÎÎÎÎ

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

9

ÎÎÎ

Î

ÎÎÎ

Î

ÎÎÎ

ÎÎÎÎ

Î

ÎÎ

Î

ÎÎÎÎ

ÎÎ

pF

C

PD

Power Dissipation Capacitance (Note 2)

Typical @ 25°C, VCC = 5.0V

pF

25

1. Parameter guaranteed by design. tOSLH = |tPLHm − tPLHn|, tOSHL = |tPHLm − tPHLn|.

2. CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without load.

Average operating current can be obtained by the equation: ICC(OPR) = CPD  VCC  fin + ICC/8 (per flip−flop). CPD is used to determine the

no−load dynamic power consumption; PD = CPD  VCC2  fin + ICC  VCC.

NOISE CHARACTERISTICS (Input tr = tf = 3.0ns, CL = 50pF, VCC = 5.0V)

Symbo

l

Parameter

TA = 25°C

Unit

Typ Max

VOLP Quiet Output Maximum Dynamic VOL 1.2 1.6 V

VOLV Quiet Output Minimum Dynamic VOL −1.2 −1.6 V

VIHD Minimum High Level Dynamic Input Voltage 2.0 V

VILD Maximum Low Level Dynamic Input Voltage 0.8 V

TIMING REQUIREMENTS (Input tr = tf = 3.0ns)

Symbo

l

Parameter Test Conditions

TA = 25°C TA = − 40 to 85°C

Uni

t

Typ Limit Limit

twMinimum Pulse Width, CP VCC = 5.0 ± 0.5 V 6.5 8.5 ns

tsu Minimum Setup Time, D to CP VCC = 5.0 ± 0.5 V 2.5 2.5 ns

thMinimum Hold Time, D to CP VCC = 5.0 ± 0.5 V 2.5 2.5 ns

MC74VHCT374A

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4

ORDERING INFORMATION

Device Package Shipping†

MC74VHCT374ADWR2 SOIC−20WB 1000 / Tape & Reel

MC74VHCT374ADWRG SOIC−20WB

(Pb−Free) 1000 / Tape & Reel

MC74VHCT374ADTR2 TSSOP−20* 2500 / Tape & Reel

MC74VHCT374ADTRG TSSOP−20* 2500 / Tape & Reel

MC74VHCT374AMEL SOEIAJ−20 2000 / Tape & Reel

MC74VHCT374AMELG SOEIAJ−20

(Pb−Free) 2000 / Tape & Reel

†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging

Specifications Brochure, BRD8011/D.

*This package is inherently Pb−Free.

Figure 3. Switching Waveform

3V

1.5V

CP

tPLH tPHL

Q

tW

1/fmax

1.5V

OE

Q

tPZL tPLZ

tPZH tPHZ

3V

HIGH

IMPEDANCE

VOL +0.3V

VOH −0.3V

HIGH

IMPEDANCE

1.5V

D

CP

3V

GND

VALID

th

tsu

1.5V

Q

Figure 4. Switching Waveform

Figure 5. Switching Waveform

GND

VOH

VOL

GND

3V

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5

Figure 6. Test Circuit

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

*Includes all probe and jig capacitance

CL*

TEST POINT

DEVICE

UNDER

TEST

OUTPUT

CONNECT TO VCC WHEN

TESTING tPLZ AND tPZL.

CONNECT TO GND WHEN

TESTING tPHZ AND tPZH.

1 kW

Figure 7. Test Circuit

Figure 8. Expanded Logic Diagram

D0

3

DQ

C

Q0

2

D1

4

DQ

C

Q1

5

D2

7

DQ

C

Q2

6

D3

8

DQ

C

Q3

9

D4

13

DQ

C

Q4

12

D5

14

DQ

C

Q5

15

D6

17

DQ

C

Q6

16

D7

18

DQ

C

Q7

19

CP

OE

11

1

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6

PACKAGE DIMENSIONS

20

1

11

10

B20X

H10X

C

L

18X A1

A

SEATING

PLANE

q

hX 45_

E

D

M

0.25 M

B

M

0.25 S

AS

B

T

eT

B

A

DIM MIN MAX

MILLIMETERS

A2.35 2.65

A1 0.10 0.25

B0.35 0.49

C0.23 0.32

D12.65 12.95

E7.40 7.60

e1.27 BSC

H10.05 10.55

h0.25 0.75

L0.50 0.90

q0 7

NOTES:

1. DIMENSIONS ARE IN MILLIMETERS.

2. INTERPRET DIMENSIONS AND TOLERANCES

PER ASME Y14.5M, 1994.

3. DIMENSIONS D AND E DO NOT INCLUDE MOLD

PROTRUSION.

4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.

5. DIMENSION B DOES NOT INCLUDE DAMBAR

PROTRUSION. ALLOWABLE PROTRUSION

SHALL BE 0.13 TOTAL IN EXCESS OF B

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

__

SOIC−20 WB

DW SUFFIX

CASE 751D−05

ISSUE G

DIM

A

MIN MAX MIN MAX

INCHES

6.60 0.260

MILLIMETERS

B4.30 4.50 0.169 0.177

C1.20 0.047

D0.05 0.15 0.002 0.006

F0.50 0.75 0.020 0.030

G0.65 BSC 0.026 BSC

H0.27 0.37 0.011 0.015

J0.09 0.20 0.004 0.008

J1 0.09 0.16 0.004 0.006

K0.19 0.30 0.007 0.012

K1 0.19 0.25 0.007 0.010

L6.40 BSC 0.252 BSC

M0 8 0 8

____

NOTES:

1. DIMENSIONING AND TOLERANCING

PER ANSI Y14.5M, 1982.

2. CONTROLLING DIMENSION:

MILLIMETER.

3. DIMENSION A DOES NOT INCLUDE

MOLD FLASH, PROTRUSIONS OR GATE

BURRS. MOLD FLASH OR GATE BURRS

SHALL NOT EXCEED 0.15 (0.006) PER

SIDE.

4. DIMENSION B DOES NOT INCLUDE

INTERLEAD FLASH OR PROTRUSION.

INTERLEAD FLASH OR PROTRUSION

SHALL NOT EXCEED 0.25 (0.010) PER

SIDE.

5. DIMENSION K DOES NOT INCLUDE

DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08

(0.003) TOTAL IN EXCESS OF THE K

DIMENSION AT MAXIMUM MATERIAL

CONDITION.

6. TERMINAL NUMBERS ARE SHOWN

FOR REFERENCE ONLY.

7. DIMENSION A AND B ARE TO BE

DETERMINED AT DATUM PLANE −W−.

ÍÍÍÍ

110

1120

PIN 1

IDENT

A

B

−T−

0.100 (0.004)

C

DGH

SECTION N−N

K

K1

JJ1

N

M

F

−W−

SEATING

PLANE

−V−

−U−

S

U

M

0.10 (0.004) V S

T

20X REFK

L

L/2

2X

S

U0.15 (0.006) T

DETAIL E

0.25 (0.010)

DETAIL E

6.40 0.252

−−− −−−

S

U0.15 (0.006) T

TSSOP−20

D5 SUFFIX

CASE 948E−02

ISSUE B

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PACKAGE DIMENSIONS

SOEIAJ−20

M SUFFIX

CASE 967−01

ISSUE A

DIM MIN MAX MIN MAX

INCHES

−−− 2.05 −−− 0.081

MILLIMETERS

0.05 0.20 0.002 0.008

0.35 0.50 0.014 0.020

0.15 0.25 0.006 0.010

12.35 12.80 0.486 0.504

5.10 5.45 0.201 0.215

1.27 BSC 0.050 BSC

7.40 8.20 0.291 0.323

0.50 0.85 0.020 0.033

1.10 1.50 0.043 0.059

0

0.70 0.90 0.028 0.035

−−− 0.81 −−− 0.032

A1

HE

Q1

LE

_10 _0

_10 _

NOTES:

1. DIMENSIONING AND TOLERANCING PER ANSI

Y14.5M, 1982.

2. CONTROLLING DIMENSION: MILLIMETER.

3. DIMENSIONS D AND E DO NOT INCLUDE

MOLD FLASH OR PROTRUSIONS AND ARE

MEASURED AT THE PARTING LINE. MOLD FLASH

OR PROTRUSIONS SHALL NOT EXCEED 0.15

(0.006) PER SIDE.

4. TERMINAL NUMBERS ARE SHOWN FOR

REFERENCE ONLY.

5. THE LEAD WIDTH DIMENSION (b) DOES NOT

INCLUDE DAMBAR PROTRUSION. ALLOWABLE

DAMBAR PROTRUSION SHALL BE 0.08 (0.003)

TOTAL IN EXCESS OF THE LEAD WIDTH

DIMENSION AT MAXIMUM MATERIAL CONDITION.

DAMBAR CANNOT BE LOCATED ON THE LOWER

RADIUS OR THE FOOT. MINIMUM SPACE

BETWEEN PROTRUSIONS AND ADJACENT LEAD

TO BE 0.46 ( 0.018).

HE

A1

LEQ1

_

c

A

ZD

E

20

110

11

b

M

0.13 (0.005)

e

0.10 (0.004)

VIEW P

DETAIL P

M

L

A

b

c

D

E

e

L

M

Z

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