Sample & Buy Product Folder Support & Community Tools & Software Technical Documents TPS92640, TPS92641 SNVS902A - OCTOBER 2012 - REVISED OCTOBER 2015 TPS9264x Synchronous Buck Controllers for Precision Dimming LED Drivers 1 Features 3 Description * * The TPS92640 and TPS92641 devices are highvoltage, synchronous NFET controllers for buckcurrent regulators. Output current regulation is based on valley current-mode operation using a controlled on-time architecture. This control method eases the design of loop compensation while maintaining nearly constant switching frequency. The TPS92640 and TPS92641 devices include a high-voltage start-up regulator that operates over a wide input range of 7 V to 85 V. The PWM controller is designed for high speed capability, including an oscillator frequency range up to 1 MHz. The deadtime between high side and low side gate driver is optimized to provide very high efficiency over a wide input operating voltage and output power range. The TPS92640 and TPS92641 devices accept both analog and PWM input signals, resulting in exceptional dimming control range. Linear response characteristics between input command and LED current is achieved with true zero LED current using low off-set error amplifier and proprietary PWM dimming logic. Both devices also include precision reference capable of supplying current to low power microcontroller. Protection features include cycle-by-cycle current protection, overvoltage protection, and thermal shutdown. The TPS92641 device includes a shunt FET dimming input and MOSFET driver for high resolution PWM dimming. 1 * * * * * * * VIN Range from 7 V to 85 V Wide Dimming Range - 500:1 Analog Dimming - 2500:1 Standard PWM Dimming - 20000:1 Shunt FET PWM Dimming Adjustable LED Current Sense Voltage 2-, 1-Apeak MOSFET Gate Drivers Shunt Dimming MOSFET Gate Driver (TPS92641) Programmable Switching Frequency Precision Voltage Reference 3 V 2% Input UVLO and Output OVP Low Power Shutdown Mode and Thermal Shutdown 2 Applications * * * * LED Driver / Constant Current Regulator Architectural LED Lighting Drivers Automotive LED Drivers General LED Illumination Device Information(1) PART NUMBER PACKAGE BODY SIZE (NOM) TPS92640 HTSSOP (14) 4.40 mm x 5.00 mm TPS92641 HTSSOP (16) 4.40 mm x 5.00 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Application Diagram VIN CIN1 RON RUDIM1 CIN2 VIN TPS92640/641 QHS HG RHG CON RON SW PWM RUDIM2 UDIM BOOT VOUT VCC VREF LG DBOOT RVOUT2 CVREF L CBOOT RUDIM3 RIADJ1 RLG IADJ *SDIM *TPS92641 ONLY *QSDIM CS RIADJ2 CCOMP COUT QLS RF COMP SDIM DAP GND CVCC RCS RVOUT1 SDRV 1 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. TPS92640, TPS92641 SNVS902A - OCTOBER 2012 - REVISED OCTOBER 2015 www.ti.com Table of Contents 1 2 3 4 5 6 7 Features .................................................................. Applications ........................................................... Description ............................................................. Revision History..................................................... Pin Configuration and Functions ......................... Specifications......................................................... 1 1 1 2 3 4 6.1 6.2 6.3 6.4 6.5 6.6 4 4 4 5 6 8 Absolute Maximum Ratings ..................................... ESD Ratings.............................................................. Recommended Operating Conditions ...................... Thermal Information .................................................. Electrical Characteristics .......................................... Typical Characteristics .............................................. Detailed Description ............................................ 10 7.1 Overview ................................................................. 10 7.2 Functional Block Diagram ....................................... 10 7.3 Feature Description................................................. 11 7.4 Device Functional Modes........................................ 18 8 Application and Implementation ........................ 19 8.1 Application Information............................................ 19 8.2 Typical Applications ............................................... 22 9 Power Supply Recommendations...................... 27 10 Layout................................................................... 28 10.1 Layout Guidelines ................................................. 28 10.2 Layout Example .................................................... 28 10.3 EMI and Noise Considerations ............................. 29 11 Device and Documentation Support ................. 30 11.1 11.2 11.3 11.4 11.5 Related Links ........................................................ Community Resources.......................................... Trademarks ........................................................... Electrostatic Discharge Caution ............................ Glossary ................................................................ 30 30 30 30 30 12 Mechanical, Packaging, and Orderable Information ........................................................... 30 4 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Original (October 2012) to Revision A * 2 Page Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1 Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92640 TPS92641 TPS92640, TPS92641 www.ti.com SNVS902A - OCTOBER 2012 - REVISED OCTOBER 2015 5 Pin Configuration and Functions TPS92640 PWP Package 14-Pin HTSSOP Top View TPS92641 PWP Package 16-Pin HTSSOP Top View VIN 1 14 HG RON 2 13 SW UDIM 3 12 BOOT VOUT 4 11 VCC VREF 5 10 LG IADJ 6 9 CS COMP 7 8 GND DAP VIN 1 16 HG RON 2 15 SW UDIM 3 14 BOOT VOUT 4 13 VCC VREF 5 12 LG IADJ 6 11 CS COMP 7 10 GND SDIM 8 9 SDRV DAP Pin Functions PIN NAME NO. (TPS92640) NO. (TPS92641) I/O DESCRIPTION BOOT 12 14 O Connect 100-nF ceramic capacitor to switch node and diode to VCC to provide boosted voltage for high-side gate drive. COMP 7 7 O Connect ceramic capacitor to GND to set loop compensation. CS 9 11 I Connect to positive terminal of sense resistor at the bottom of the LED stack. GND 8 10 -- System GND. Connect to DAP. HG 14 16 O Connect to gate of high-side NFET of buck regulator. Use series resistor to limit current slew-rate and mitigate EMI noise. IADJ 6 6 I Connect resistor divider from VREF to set analog dimming level. Use NTC resistor from pin to GND as resistor divider to implement thermal foldback operation. LG 10 12 O Connect to gate of low-side NFET of buck regulator. Use series resistor to limit current slew-rate and mitigate EMI noise. RON 2 2 I Connect a resistor to VIN and capacitor to GND to set switching frequency. SDIM -- 8 I PWM dimming input for shunt FET dimming. SDRV -- 9 O Connect to gate of external parallel NFET across LED load used for shunt dimming if desired. SW 13 15 O Connect to switch node of buck regulator. UDIM 3 3 I Connect resistor divider from VIN to set undervoltage lockout threshold. VCC 11 13 O Bypass with 2.2-F ceramic capacitor to provide bias supply for controller. VIN 1 1 I Connect to input voltage. Connect 1-F bypass capacitor VOUT 4 4 I Connect resistor divider from VOUT, scaled down feedback of VOUT. VREF 5 5 O System reference voltage. Bypass with 100-nF ceramic capacitor. DAP -- -- -- Place 6-9 vias from pad to GND plane for thermal relief. Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92640 TPS92641 Submit Documentation Feedback 3 TPS92640, TPS92641 SNVS902A - OCTOBER 2012 - REVISED OCTOBER 2015 www.ti.com 6 Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) VIN, UDIM, SW BOOT HG MIN MAX UNIT -0.3 90 V -1 mA -0.3 98.5 V -0.3 90 V -2.5 (Pulse < 100 ns) V +VCC V -2.5 (Pulse < 100 ns) V -0.3 LG, SDRV, CS VCC VREF, RON, COMP, VOUT, IADJ, SDIM GND VCC + 2.5 (Pulse < 100 ns) V -0.3 15 V -0.3 6 V -200 200 A -0.3 0.3 V -2.5 (Pulse < 100 ns) 2.5 (Pulse < 100 ns) V Continuous power dissipation Internally Limited Maximum lead temperature (soldering and reflow) (2) 260 C Maximum junction temperature -40 125 C Storage temperature -65 150 C (1) (2) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Refer to TI's packaging website for more detailed information and mounting techniques. 6.2 ESD Ratings VALUE UNIT TPS92640 PWP PACKAGE V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) 2000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) 1000 Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 (1) 2000 Charged-device model (CDM), per JEDEC specification JESD22C101 (2) 1000 V TPS92641 PWP PACKAGE V(ESD) (1) (2) Electrostatic discharge V JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. 6.3 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN VIN Input voltage TJ Junction temperature 4 Submit Documentation Feedback NOM MAX UNIT 7 85 V -40 125 C Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92640 TPS92641 TPS92640, TPS92641 www.ti.com SNVS902A - OCTOBER 2012 - REVISED OCTOBER 2015 6.4 Thermal Information TPS92640 THERMAL METRIC (1) TPS92641 PWP (HTSSOP) PWP (HTSSOP) 14 PINS 16 PINS UNIT RJA Junction-to-ambient thermal resistance 40.1 38.7 C/W RJC(top) Junction-to-case (top) thermal resistance 24.6 22.7 C/W RJB Junction-to-board thermal resistance 20.9 16.5 C/W JT Junction-to-top characterization parameter 0.6 0.6 C/W JB Junction-to-board characterization parameter 20.7 16.3 C/W RJC(bot) Junction-to-case (bottom) thermal resistance 2.5 1.7 C/W (1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953. Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92640 TPS92641 Submit Documentation Feedback 5 TPS92640, TPS92641 SNVS902A - OCTOBER 2012 - REVISED OCTOBER 2015 www.ti.com 6.5 Electrical Characteristics Unless otherwise specified VIN = 24 V. Typical specifications apply for TA = TJ = 25C. PARAMETER TEST CONDITIONS MIN (1) TYP (2) MAX (1) 7.86 8.5 9.14 48 63 78 mA 2 3 mA UNIT START-UP REGULATOR (VCC, VIN) VCCREG VCC Regulation ICC = 10 mA, VIN = 24 V, 85 V ICCLIM VCC Current Limit VCC = 0 V IQ Quiescent Current VUDIM = 3 V, Static VIN = 7 V, 24 V, 85 V ISD Shutdown Current VUDIM = 0 V VCC-UV VCC UVLO Threshold VCC-HYS VCC UVLO Hysteresis 100 VCC increasing 5.04 VCC decreasing 4.5 V A 5.9 4.9 0.17 V V REFERENCE VOLTAGE (VREF) VREF Reference Voltage No Load, VIN = 7 V, 24 V, 85 V IVREFLIM Current Limit VREF = 0 V 2.97 3.03 3.09 V 1.3 2.1 2.9 mA 600 V ERROR AMPLIFIER (CS, COMP) VCSREF CS Reference Voltage VCSREF-OFF Error Amp Input Offset Voltage ICOMP COMP Sink Current gM-CS With respect to GND VIADJ/10 -600 0 V 85 A COMP Source Current 110 A Transconductance 500 A/V (3) Linear Input Range See Transconductance Bandwidth -6-dB unloaded response (3) 125 mV 400 kHz 230 ns 235 ns 2.08 s TIMERS / OVERVOLTAGE PROTECTION (RON, VOUT) tOFF-MIN Minimum Off-time tON-MIN Minimum On-time CS = 0 V tON Programmed On-time RRON RON Pulldown Resistance tCL Current Limit Off-time tD-ON RON Thresh - HG Falling Delay VTH-OVP VOUT Overvoltage Threshold VHYS-OVP VOUT Overvoltage Hysteresis VVOUT = 2 V, RON = 25 k, CON = 1 nF 35 120 270 25 VOUT rising 2.85 3.05 s ns 3.25 0.13 V V GATE DRIVER (HG, LG, BOOT, SW) RSRC-LG LG Sourcing Resistance LG = High 1.5 6 RSNK-LG LG Sinking Resistance LG = Low 1 4.5 RSRC-HG HG Sourcing Resistance HG = High 3.9 6 RSNK-HG HG Sinking Resistance HG = Low 1.1 4.5 VTH-BOOT BOOT UVLO Threshold BOOT-SW rising 3.4 4.5 V VHYS-BOOT BOOT UVLO Hysteresis BOOT-SW falling 1.8 V TD-HL HG to LG deadtime HG fall to LG rise 60 ns TD-LH LG to HG deadtime LG fall to HG rise 60 ns (1) (2) (3) 6 1.9 All limits specified at room temperature (TYP values) and at temperature extremes (MIN/MAX values). All room temperature limits are 100% production tested. All limits at temperature extremes are specified via correlation using standard Statistical Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL). Typical numbers are at 25C and represent the most likely norm. These electrical parameters are specified by design, and are not verified by test. Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92640 TPS92641 TPS92640, TPS92641 www.ti.com SNVS902A - OCTOBER 2012 - REVISED OCTOBER 2015 Electrical Characteristics (continued) Unless otherwise specified VIN = 24 V. Typical specifications apply for TA = TJ = 25C. PARAMETER TEST CONDITIONS MIN (1) TYP (2) MAX (1) UNIT PWM DIMMING (SDIM, SDRV) (TPS92641 only) RSRC-DDRV SDRV Sourcing Resistance SDRV = High 5.6 30 tSDIM-RIS SDIM to SDRV Rising Delay SDIM rising 68 100 ns tSDIM -FALL SDIM to SDRV Falling Delay SDIM falling 29 70 ns VSDIM-RIS SDIM Rising Threshold SDIM rising 1.29 1.74 V VSDIM -FALL SDIM Falling Threshold SDIM falling RSDIM-PU SDIM Pullup Resistance 0.5 V 90 k ANALOG ADJUST (IADJ) VADJ-MAX IADJ Clamp Voltage RADJ IADJ Input Impedance 2.46 2.54 2.62 1 V M UNDERVOLTAGE / PWM (UDIM) VTH-UDIM UDIM Start-up Threshold IHYS-UDIM UDIM Hysteresis Current UDIM rising tUDIM-RIS UDIM to HG/LG Rising Delay tUDIM-FALL UDIM to HG/LG Falling Delay VUDIM-LP UDIM Low Power Threshold TUDIM-DET UDIM Shutdown Detect Timer 1.21 1.276 1.342 V 12 21 30 A UDIM rising 168 260 ns UDIM falling 174 280 UDIM falling 8.5 ns 370 mV 13 ms THERMAL SHUTDOWN TSD Thermal Shutdown Threshold See (3) 165 C THYS Thermal Shutdown Hysteresis See (3) 20 C Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92640 TPS92641 Submit Documentation Feedback 7 TPS92640, TPS92641 SNVS902A - OCTOBER 2012 - REVISED OCTOBER 2015 www.ti.com 6.6 Typical Characteristics Unless otherwise stated, -40C TA = TJ 125C, VIN = 24 V, VIADJ= 2 V, ILED = 1 A, CVCC = 2.2 F, CCOMP = 0.47 F 200.00 2.30 Shutdown Current, ISD(A) Quescient Current, IQ(mA) 2.50 25C 125C 2.10 1.90 -40C 1.70 160.00 120.00 80.00 -40C 40.00 1.50 0.00 0 10 20 30 40 50 60 70 80 Input Voltage, VIN(V) 90 0 10 20 30 40 50 Figure 1. Quescient Current, IQ vs Input Voltage, VIN 80 90 C001 Figure 2. Shutdown Current, ISDvs Input Voltage , VIN 125C 8.00 Reference Voltage, VREF(V) 8.50 25C -40C 7.50 7.00 6.50 3.04 3.02 -40C 25C 3.00 2.98 IVREF = 500PA IVCC = 10mA 6.00 2.96 0 10 20 30 40 50 60 70 80 Input Voltage, VIN(V) 90 0 10 20 30 40 50 60 70 80 Input Voltage, VIN(V) C001 90 C001 Figure 3. Start-Up Regulator, VCC vs Input Voltage, VIN Figure 4. Reference Voltage, VREF vs Input Voltage, VIN 280 280 Minimun Off-time, tOFF_MIN(ns) Minimun On-time, tON_MIN(ns) 70 3.06 125C -40C 260 25C 240 125C 220 200 -40C 260 25C 240 125C 220 200 0 10 20 30 40 50 60 Input Voltage, VIN(V) 70 80 90 Submit Documentation Feedback 0 10 20 30 40 50 60 Input Voltage, VIN(V) C001 Figure 5. Minimum On-time, tON_MIN vs Input Voltage, VIN 8 60 Input Voltage, VIN(V) C001 9.00 Startup Regulator, VCC(V) 25C 125C 70 80 90 C001 Figure 6. Minimum Off-time, tOFF_MIN vs Input Voltage, VIN Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92640 TPS92641 TPS92640, TPS92641 www.ti.com SNVS902A - OCTOBER 2012 - REVISED OCTOBER 2015 Typical Characteristics (continued) Unless otherwise stated, -40C TA = TJ 125C, VIN = 24 V, VIADJ= 2 V, ILED = 1 A, CVCC = 2.2 F, CCOMP = 0.47 F 1.100 100.0 90.0 1.050 8 LEDs Efficiency, (%) LED Current, ILED(A) 15 LEDs 1.000 15 LEDs 1 LED 0.950 fSW N+] 1RP ILED = 1A (Nom.) L = 68, 94mQ 1 LED 80.0 8 LEDs 70.0 fSW N+] 1RP ILED = 1A (Nom.) L = 68H, 94mQ QHS, QLS : SUD15N15-95 60.0 0.900 50.0 0 10 20 30 40 50 60 70 80 Input Voltage, VIN(V) 90 0 10 20 30 40 50 60 70 80 Input Voltage, VIN(V) C007 90 C008 Figure 8. Conversion Efficiency, vs Input Voltage, VIN Figure 7. LED Current, ILED vs Input Voltage, VIN 700 VIN : 50V/DIV Switching Frequency, fSW(kHz) 8 LEDs 600 500 400 15 LEDs 1 LED 300 VSW : 20V/DIV 200 fSW N+] 1RP ILED = 1A (Nom.) L = 68H, 94mQ 100 0 0 10 20 30 40 50 60 70 80 Input Voltgae, VIN(V) 90 C009 Figure 9. Converter Switching Frequency, fSW vs Input Voltage, VIN VIN = 48V VLED 32V (10 LEDs) ILED = 1A fSW 500kHz ILED : 500mA/DIV Time : 4ms/DIV Figure 10. Waveforms of Power-Up Transient VUDIM : 5V/DIV VSW : 20V/DIV VSW : 20V/DIV ILED : 500mA/DIV ILED : 500mA/DIV Time : 1Ps/DIV VIN = 48V VLED 32V (10 LEDs) ILED = 1A fSW 500kHz Figure 11. Waveforms of Steady-State Operation Time : 1ms/DIV VIN = 48V VLED 32V (10 LEDs) ILED = 1A fSW 500kHz fUDIM = 200Hz Figure 12. Waveforms of UDIM Operation (DDIM = 0.5) Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92640 TPS92641 Submit Documentation Feedback 9 TPS92640, TPS92641 SNVS902A - OCTOBER 2012 - REVISED OCTOBER 2015 www.ti.com 7 Detailed Description 7.1 Overview The TPS92640 and TPS92641 devices are synchronous N-channel MOSFET (NFET) controllers for step-down (buck) current regulators, which are ideal for driving LED loads. They can accept wide input voltage range allowing for greater flexibility in powering different series connected LED string combinations. The single current sense pin with low adjustable threshold voltage provides an excellent method for regulating LED current while maintaining high system efficiency. The TPS92640 and TPS92641 devices use valley current control with a controlled on-time architecture that allows the converter to be operated at nearly constant switching frequency without the need for slope compensation. The extremely accurate adjustable current sense threshold together with the synchronous operation provides the capability to amplitude (analog) dim the LED current with high contrast ratios. Excellent PWM dimming is attainable using the main NFETs or the external shunt FET driver (TPS92641 only). The TPS92640 and TPS92641 devices incorporate 2-, 1-A internal gate drivers and supports constant current operation up to 5 A. This simple controller contains all the features necessary to implement a high-efficiency, versatile LED driver with precise dimming response. 7.2 Functional Block Diagram VIN TPS92640, TPS92641 COMP THERMAL SHUTDOWN IADJ VOLTAGE REFERENCES VCC VCC BIAS REGULATOR VIN + - R VCC UVLO VCC VSW EA GATE DRIVE UVLO + + 13ms FILTER FSW R Q Shutdown S Q tON tOFF LGATE Enable UDIM DEAD TIME / LEVEL SHIFT tON_ Reset HG SW VCC DEAD TIME LOGIC RON H.S. Driver VSW 21A PWM_DIM / UVLO + - 1.276V BOOT SD CS 370mV VREF VDD PWM_DIM 2.54V 9R 370mV 1.276V 2.54V 3.03V L.S. Driver LG End tON + - GND tON_Reset LEB TIMER VOUT 3.05V OVP + - TPS92641 ONLY VDD VCC SDIM 1.276V 10 + - Submit Documentation Feedback PWM LOGIC SDRV Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92640 TPS92641 TPS92640, TPS92641 www.ti.com SNVS902A - OCTOBER 2012 - REVISED OCTOBER 2015 7.3 Feature Description VIN CIN1 RON RUDIM1 CIN2 VIN TPS92640/641 QHS HG RHG CON RON SW PWM RUDIM2 UDIM BOOT VOUT VCC RUDIM3 DBOOT RVOUT2 CVREF L CBOOT COUT QLS VREF RIADJ1 LG RLG IADJ *QSDIM CS RIADJ2 RF COMP CCOMP *SDIM *TPS92641 ONLY DAP SDIM GND CVCC RCS RVOUT1 SDRV Figure 13. Synchronous Buck LED Driver 7.3.1 Controlled On-Time Architecture The control architecture is a combination of valley current control and a one-shot on-timer that varies with input and output voltage. The TPS92640 and TPS92641 devices use a series resistor in the LED path to sense both average LED current and valley inductor current. During the time that the high side NFET is turned on (tON), the input voltage charges up the inductor. When it is turned off (tOFF) and the low side NFET is turned on, the inductor discharges. During both intervals, the current is supplied to the load keeping the LEDs forward biased. Figure 14 shows the inductor current (iL) waveform for a buck converter operating in continuous conduction mode (CCM). As the system changes input voltage or output voltage, duty cycle D is varied indirectly by changing both tON and tOFF to regulate IL and ultimately ILED. For any buck regulator, duty cycle, D, is calculated using Equation 1. TON V OUT D K u VIN TON TOFF VOUT VLED VCS where * VCS is the voltage measured at the CS pin of the IC and is the estimated or actual converter efficiency. Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92640 TPS92641 Submit Documentation Feedback (1) 11 TPS92640, TPS92641 SNVS902A - OCTOBER 2012 - REVISED OCTOBER 2015 www.ti.com Feature Description (continued) iL (t) IL-MAX IL uiL-PP IL-MIN tOFF tON = DT 0 t T Figure 14. Ideal CCM Buck Converter Inductor Current IL Waveform 7.3.2 Switching Frequency The on-time is determined based on the external resistor (RON) connected between RON and VIN pins in combination with a capacitor (CON) between RON and GND pins. The input voltage and the RON resistor set the current sourced into the RON capacitor which governs the ramp speed. The ramp threshold is proportional to scaled down feedback of VOUT at VOUT pin. The proportionality of VOUT is set by an external resistor divider (RVOUT1, RVOUT2) from VOUT. The switching frequency, fSW can be calculated based on on-time and off-time using Equation 2. R VOUT 2 VOUT u R VOUT 1 R VOUT 2 VIN C ON u t ON R ON VIN R ON fSW VIN u C ON u 1 T t ON R VOUT 2 u T R VOUT 1 R VOUT 2 t ON R VOUT 1 R VOUT 2 1 u R VOUT 2 R ON u C ON (2) Even though the on-time control is quasi-hysteretic, the input and output voltage proportionality creates a nearly constant switching frequency over the entire operating range. Quasi-hysteretic control minimizes the control loop compensation necessary in many switching regulators, simplifying the design process. It also mitigates current mode instability (also known as sub-harmonic oscillation) found in standard fixed frequency current mode control when operating near or above 50% duty cycle. The inductor current sensing and averaging mechanism in the valley detection control loop provides highly accurate LED current regulation over the entire operating range and temperature. 7.3.3 Average LED Current Average LED current regulation is set using a sense resistor in series with the LEDs. The internal error-amplifer regulates the voltage across the sense resistor (VCS) to the IADJ voltage divided by 10. The error amplifier input offset voltage has been minimized using auto-zero calibration technique as shown in . In this chopping scheme, the noninverting and inverting inputs and outputs change polarity every switching cycle to cancel the offset, providing near zero input offset voltage. 12 Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92640 TPS92641 TPS92640, TPS92641 www.ti.com SNVS902A - OCTOBER 2012 - REVISED OCTOBER 2015 Feature Description (continued) clk1 clk1 CS + gm clk1b IADJ COMP clk1b Adder 9R CCOMP R clk1 clk1 Figure 15. Working Principle of the Chopper OTA to Minimize Input Offset Voltage IADJ can be set to any value up to 2.54 V by connecting it to VREF through a resistor divider for static output current settings. IADJ can also be used to change the regulation point if connected to a controlled voltage source or potentiometer to provide analog dimming. It is also possible to configure IADJ to be used for thermal foldback functions. ILED VCS VCS R CS VIADJ 10 (3) (4) 7.3.4 Analog Dimming and True-Zero Operation In traditional Buck converters, discontinuous conduction mode (DCM) operation of inductor current results in loss of linearity at low dimming levels and limits the analog dimming range. When using TPS92640 and TPS92641 devices to implement synchronous buck converter, the inductor current is forced to maintain continuous conduction mode (CCM). As a result, it is possible to maintain linearity and achieve true-zero LED current operation with respect to analog dimming command. For true zero application, an external capacitor is required across the LED string to provide a negative current path for the inductor current loop. Figure 16 shows the inductor current (IL) and output voltage (VOUT) waveform for a buck converter operating at true zero average current level. iL t 'iL VOUT 'vOUT t DT T Figure 16. True Zero CCM Buck Converter Inductor Current IL and Output Voltage VOUT Waveform In true zero application (VIADJ=0 V), there will be a certain amount of ILED passing the LEDs even though the average inductor current is well-regulated at 0-A set-point. The shaped area in Figure 17 shows the current that will pass through the LED string (iLED). Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92640 TPS92641 Submit Documentation Feedback 13 TPS92640, TPS92641 SNVS902A - OCTOBER 2012 - REVISED OCTOBER 2015 www.ti.com Feature Description (continued) iLED t ILED = 0A 'iLED Figure 17. Output Current Waveform in True Zero Application with VIADJ = 0 V An external resistor, ROFF as shown in Figure 18 is recommended from VOUT to CS to shunt the positive current ripple while maintaining the operation of error amplifier to cancel input offset voltage. The shunt current (IOFF) should be at least half of the output current ripple to ensure proper operation. IOFF ROFF VOUT ! 0.5 u 'ILED ROFF RF RCS VOUT 0.5 u 'ILED RF RCS (5) VOUT LED+ COUT ILED ROFF LEDVCS V-CS CS RF RCS Figure 18. ROFF for True Zero Application The resistor ROFF also impacts the start-up behavior of the circuit as it creates an DC shift in the voltage sensed at CS pin. To ensure proper start-up sequence and monotonic LED current behavior, the voltage V'CS should exceed a threshold voltage based on the native offset of the error amplifier before VOUT exceeding the LED forward voltage, VLED. Assuming a worst case native off-set (non-chopping) of error amplifier to be less than 10 mV, the voltage V'CS must be greater than this threshold to initiate switching and auto-zero operation. Therefore, ROFF should be sized to also meet following condition. c VCS R OFF R F R CS VOUT u (c) R OFF RF R CS RF R CS * VOUT u (c) 0 .01 * ! 0 .01 RF R CS 1/4 RF !! R CS 100 u VOUT u RF (6) Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated R OFF 14 Product Folder Links: TPS92640 TPS92641 TPS92640, TPS92641 www.ti.com SNVS902A - OCTOBER 2012 - REVISED OCTOBER 2015 Feature Description (continued) To conclude, an external resistor (ROFF) from VOUT to CS pin is required for true zero application, where ROFF should be: R OFF V OUT min 0 . 5 u ' I LED RF R CS ; 100 u V OUT uRF 1/4 (7) 7.3.5 Undervoltage Lockout (UVLO) The UDIM pin of the TPS92640 and TPS92641 devices is a dual function input that features an accurate 1.276-V threshold with programmable hysteresis. This pin functions as both the PWM dimming input of the LEDs and as an input UVLO with built-in hysteresis. When the pin voltage rises and exceeds the 1.276-V threshold, 21 A (typical) of current is driven out of the UDIM pin into the resistor divider (RUDIM1, RUDIM2) providing programmable hysteresis. The UVLO turnon threshold, VTURN-ON, is defined using Equation 8. VTURN _ ON R RUDIM2 * 1.276V u UDIM1 RUDIM2 (c) (8) Once the input voltage is above VTURN_ON, the current source is active and the UVLO hysteresis is determined by Equation 9. VHYS 21PA u RUDIM1 (9) When using the UDIM pin for UVLO and PWM dimming concurrently, the UVLO circuit can have an extra resistor (RUDIM3) to set the hysteresis. This allows the standard resistor divider to have smaller values minimizing delays that can incur with additional external PWM dimming circuitry. In general, at least 3 V of hysteresis is preferable when PWM dimming if operating near the UVLO threshold. Under these conditions, the UVLO hysteresis is defined using Equation 10. VHYS 21PA u RUDIM1 (c) RUDIM 3 u RUDIM1 RUDIM 2 RUDIM 2 * (10) 7.3.6 PWM Dimming Using the UDIM Pin The UDIM pin can be driven with a PWM signal, which controls the synchronous NFET operation. The brightness of the LEDs can be varied by modulating the duty cycle (DDIM) of this signal using a Schottky diode with anode connected to UDIM pin, as shown in Figure 13. iLED (t) ILED-MAX ILED IDIM-LED JDDIM x TDIMJ t 0 JTDIMJ tOFF Figure 19. LED Current During UDIM Pin PWM Dimming Figure 19 shows the LED current waveform during PWM dimming where duty cycle (DDIM) is the percentage of the dimming period (TDIM) that the synchronous NFETs are switching. For the remainder of TDIM, the NFETs are disabled. The resulting dimmed LED current (IDIM_LED) is: IDIM _ LED DDIM u ILED (11) Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92640 TPS92641 Submit Documentation Feedback 15 TPS92640, TPS92641 SNVS902A - OCTOBER 2012 - REVISED OCTOBER 2015 www.ti.com Feature Description (continued) 7.3.7 External Shunt FET PWM Dimming Extremely high dimming range and linearity can be achieved by using TPS92641 device for Shunt FET dimming operation with SDIM and SDRV pin. When higher frequency and time resolution PWM dimming signal is applied to the SDIM pin, the SDRV pin provides an inverted signal of the same frequency and duty cycle that can be used to drive the gate of a Shunt NFET directly across the LED load. Because the output voltage will go to near zero when the Shunt NFET is turned on, the internal on-timer at the RON pin will switch to a fixed minimum ontime during the off-time of the dimming cycle. This method keeps the inductor current slewed up and the converter regulating, without the presence of extremely high switching frequencies. During the on-time of the dimming cycle, the converter will switch in its regular fashion with the programmed on-time at the RON pin. An internal resistor pulls the SDIM pin to logic high if left open. In this case, the SDRV driver will be off. iLED (t) ILED-MAX ILED IDIM-LED DDIM x TDIM t 0 TDIM tOFF Figure 20. Ideal LED Current During Shunt FET PWM Dimming Figure 20 shows the ideal LED current waveform during Shunt FET PWM dimming which is very similar to the internal PWM dimming described and shown previously except with much faster rise and fall of the LED current. With this method, only the speed of the parallel Shunt NFET limits the dimming frequency and dimming duty cycle. 7.3.8 VCC Regulation and Start-up The TPS92640 and TPS92641 devices include a high voltage, low-dropout bias regulator. When power is applied, the regulator is enabled and sources current into an external capacitor (CVCC) connected to the VCC pin. The recommended bypass capacitance for the VCC regulator is 2.2 F to 3.3 F. This capacitor should be rated for 10 V or greater and an X7R dielectric ceramic is recommended. The output of the VCC regulator is monitored by an internal UVLO circuit that protects the device from attempting to operate with insufficient supply voltage, and the supply current is also internally current-limited. When VIN is close or lower than 8.5 V, the regulator will enter the by-pass mode and the VCC will closely follow VIN. This linear regulator is the primary heat source generator of the device. The amount of heat generated is a function of input voltage (VIN), switching frequency (FSW) and the characteristics of the power MOSFET used. The thermal handling capability of the device imposes a limit on the maximum switching frequency can be used, especially when VIN is higher than 48 V and high current power MOSFET is used. 7.3.9 Precision Reference The device includes a precision 3-V reference. This can be used in conjunction with a resistor divider to set voltage levels for the IADJ pin and other external circuitry requiring a reference. It can also be used to supply current to low power micro-controllers. The source current capability from VREF pin is internally limited 2.1 mA. For the VREF regulator, TI recommends a bypass capacitance from 0.1 F to 1 F. 7.3.10 Control Loop Compensation Compensating the TPS92640 and TPS92641 devices is relatively simple for most applications. The only compensation needed is a compensation capacitor, CCOMP across the COMP pin and ground to place a lowfrequency dominant pole in the system. The pole must be placed low enough to ensure adequate phase margin at the crossover frequency. For most of the applications, CCOMP of 100 nF to 470 nF is good enough. Additionally, TI recommends a high quality ceramic capacitor with X7R dielectric rated for 25 V. 16 Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92640 TPS92641 TPS92640, TPS92641 www.ti.com SNVS902A - OCTOBER 2012 - REVISED OCTOBER 2015 Feature Description (continued) 7.3.11 Overcurrent Protection The TPS92640 and TPS92641 devices has overcurrent protection to protect the high side NFET (HS-NFET) along with the rest of the system from overcurrent conditions. This peak current limit of 1.28 V (with VIN = 85 V at room temperature) is sensed across the high side FET RDS-ON (from SW to VIN). If the threshold is reached or exceeded, HS-NFET will turn off and the low side NFET (LS-NFET) will turn on for approximately 800 ns. Then HS-NFET will turn on again, if the threshold is still reached or exceeded, both FETs are shutoff for 270-s typical. Figure 21 shows the waveforms of HG and LG under overcurrent protection. J270 sJ J270 sJ HG LG Figure 21. HG and LG Waveforms Under Overcurrent Protection 7.3.12 Overvoltage Protection (OVP) The TPS92640 and TPS92641 devices have programmable overvoltage protection by using the resistor divider at the VOUT pin. The OVP limit, VOVP_ON, is defined using Equation 12. VOVP _ ON R R VOUT 2 * 3.05 V u VOUT1 R VOUT 2 (c) (12) If the output voltage reaches VOVP_ON, the HG, LG and SDRV pins are pulled low to prevent damage to the LEDs or the rest of the circuit. The OVP circuit has a fixed hysteresis of 100 mV before the driver attempts to switch again. 7.3.13 Boot Undervoltage Lockout (UVLO) The BOOT UVLO circuit is implemented to ensure proper operation of the high-side gate driver under all operating conditions. The switching operation is commenced once the BOOT voltage exceeds 3.4 V above the SW pin. Comparator hysteresis of 1.8 V is included to prevent false tripping due to high-frequency switching noise. When the BOOT falls below the low voltage threshold (1.6 V typical), the high side NFET is disabled by pulling HG pin to SW pin. The next turnon transition of low-side NFET pulls SW pin down and charges the BOOT capacitor (CBOOT) through VCC. Normal operation is commenced once BOOT capacitor (CBOOT) is charged above BOOT UVLO turnon threshold of 3.4 V. The boostrap circuit behavior impacts the circuit behavior near dropout (VIN= VOUT) conditions. A minimum offtime is implemented to restrict the maximum duty cycle and maintain charge on the external BOOT capacitor, CBOOT. As the input voltage, VIN, approachs close to the output voltage, VOUT, the output current will fall with the switching frequency, as in conventional Buck regulator. This behavior ensures smooth operation in and out of dropout region while ensuring proper operation of high side gate driver and bootstrap circuit. Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92640 TPS92641 Submit Documentation Feedback 17 TPS92640, TPS92641 SNVS902A - OCTOBER 2012 - REVISED OCTOBER 2015 www.ti.com 7.4 Device Functional Modes 7.4.1 Low Power Shutdown Using the UDIM Pin The TPS92640 and TPS92641 devices can be placed into a low power shutdown mode by grounding the UDIM pin directly (any voltage below 370 mV) for more than 13 ms (typical). 7.4.2 Thermal Shutdown Internal thermal shutdown circuitry is provided to protect the device in the event that the maximum junction temperature is exceeded. The threshold for thermal shutdown is 165C with a 20C hysteresis (both values typical). During thermal shutdown the NFETs and drivers are disabled. 18 Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92640 TPS92641 TPS92640, TPS92641 www.ti.com SNVS902A - OCTOBER 2012 - REVISED OCTOBER 2015 8 Application and Implementation NOTE Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI's customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality. 8.1 Application Information 8.1.1 Switching Frequency Switching frequency is selected based on the trade-offs between efficiency, solution size/cost and the range of output voltage that can be regulated. Many applications place limits on switching frequency due to EMI sensitiviy. The on-time of the TPS92640 and TPS92641 devices can be programmed for switching frequencies ranging from the tens of kHz to over 1 MHz. This on-time varies in proportion to both VIN and VOUT, as described in Switching Frequency. However, in practice the switching frequency will shift in response to large swings in input or output voltage. The maximum switching frequency is limited only by the minimum on-time and minimum offtime requirements. 8.1.2 LED Ripple Current The LED manufacturers generally recommend values of current ripple, ILED, to achieve optimal optical efficiency. The peak-to-peak current ripple values typically range from 10% to 40% of DC current, ILED. Higher LED ripple current allows the use of smaller inductors, smaller output capacitors, or no output capacitors at all. Lower ripple current requires more inductance, higher switching frequency, or additional output capacitance. Based on the LED current ripple specification and desired switching frequency, the inductor value can be calculated using Equation 13. V IN V OUT L u t ON ' I LED (13) It is important to ensure that the rated inductor saturation current is greater than the worst case operating current (ILED+ILED/2) under the wide operating temperature range. 8.1.3 Buck Converters Without Output Capacitor A Buck regulator is ideal for regulating current because of the direct connection between the inductor and the LED load. Because the current is being regulated, not voltage, a buck current regulator is free of load current transients, and has no need of output capacitance to supply the load and maintain output voltage. This is of great benefit when driving LEDs as large electrolytic capacitors impact the lifetimes and PWM dimming performance. The output capacitor can be eliminated by using a large inductor or higher switching frequency as discussed in LED Ripple Current A capacitor placed in parallel with the LED or array of LEDs can be used to reduce iLED while keeping the same average current through both the inductor and the LED array. With this topology the inductance can be lowered, making the magnetics smaller and less expensive. Alternatively, the circuit can be run at lower frequency with the same inductor value, improving the efficiency and expanding the range of output voltage that can be regulated. Figure 22 shows the equivalent impedances presented to the iL-PP when an output capacitor, COUT, and its equivalent series resistance (RESR) are placed in parallel with the LED array. Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92640 TPS92641 Submit Documentation Feedback 19 TPS92640, TPS92641 SNVS902A - OCTOBER 2012 - REVISED OCTOBER 2015 www.ti.com Application Information (continued) 'iL-PP uiCOUT COUT rD uiLED-PP RESR Figure 22. LED Ripple Current With COUT To calculate the respective ripple currents, the LED array is represented as the dynamic resistance, (rD). LED's dynamic resistance is not always specified on the manufacturer's data sheet, but it can be calculated as the inverse slope of the LED's VLED vs ILED curve at the operating point. However, this method only gives an rough estimate of rD. Total dynamic resistance for a string of n LEDs connected in series can be calculated as the rD of one device multiplied by n. Inductor ripple current, iL-PP is still calculated as before. The following equations can then be used to estimate peak-to-peak LED current ripple, iLED-PP, when using a parallel capacitor: 'iL PP 1 'iLED PP Z COUT rD 2 u S u fSW u COUT 1 Z COUT (14) The calculation for ZCOUT assumes that the shape of the inductor ripple current is approximately sinusoidal. Small values of COUT that do not significantly reduce iLED-PP can also be used to control EMI generated by the switching action of the TPS92640 and TPS92641 devices. EMI reduction becomes more important as the length of the connections between the LED and the rest of the circuit increase. 8.1.4 Input Capacitor Input capacitor is selected using requirements for minimum capacitance and rms ripple current. The input capacitor supply pulses of current approximately equal to ILED while the high-side NFET is on, and is charged up by the input voltage while the high-side NFET is off. Switching converters such as the TPS92640 and TPS92641 devices have a negative input impedance due to the decrease in input current as input voltage increases. This inverse proportionality of input current to input voltage can cause oscillations (sometimes called power supply interaction) if the magnitude of the negative input impedance is greater than the input filter impedance. Minimum capacitance can be selected by comparing the input impedance to the converter's negative resistance; however, this requires accurate calculation of the input voltage source inductance and resistance, quantities which can be difficult to determine. An alternative method to select the minimum input capacitance (CIN-MIN) is to select the maximum voltage ripple (vIN-MAX), which can be tolerated. vIN-MAX is equal to the change in voltage across CIN during tON when it supplies the load current. A good starting point for selection of CIN is to use an input voltage ripple of 2% to 10% of VIN. CIN-MIN can be selected using Equation 15. * 1 t OFF ILED u ILED u t ON (c) fSW CIN _ MIN 'v IN _ MAX 'v IN _ MAX (15) TI recommends a minimum input capacitance at least 75% greater than the CIN-MIN value. To determine the RMS input current rating (IIN-RMS), use Equation 16. IIN RMS 20 ILED u D u 1 D Submit Documentation Feedback ILED u fSW u t ON u t OFF (16) Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92640 TPS92641 TPS92640, TPS92641 www.ti.com SNVS902A - OCTOBER 2012 - REVISED OCTOBER 2015 Application Information (continued) Because this approximation assumes there is no inductor ripple current, the value should be increased by 1030% depending on the amount of ripple that is expected. Ceramic capacitors are the best choice for the input to the TPS92640 and TPS92641 devices due to their high ripple current rating, low ESR, low cost, and small size compared to other types. When selecting a ceramic capacitor, special attention must be paid to the operating conditions of the application. Ceramic capacitors can lose one-half or more of their capacitance at their rated DC voltage bias and also lose capacitance with extremes in temperature. Make sure to check any recommended deratings and also verify if there is any significant change in capacitance at the operating input voltage and the operating temperature. 8.1.5 NFETs The TPS92640 and TPS92641 devices require two external NFETs for the switching regulator. The FETs should have a voltage rating at least 20% higher than the maximum input voltage to ensure safe operation during the ringing of the switch node. In practice, all switching converters have some ringing at the switch node due to the diode parasitic capacitance and the lead inductance. The NFETs should also have a current rating at least 50% higher than the average transistor current. Once NFETs are chosen, the power rating is verified by calculating the power loss. Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92640 TPS92641 Submit Documentation Feedback 21 TPS92640, TPS92641 SNVS902A - OCTOBER 2012 - REVISED OCTOBER 2015 www.ti.com 8.2 Typical Applications 8.2.1 TPS92640: Design Procedure VIN CIN1 RON RUDIM1 CIN2 VIN TPS92640 QHS HG RHG CON RON SW PWM RUDIM2 UDIM BOOT VOUT VCC L CBOOT RUDIM3 DBOOT RVOUT2 CVREF QLS VREF RIADJ1 COUT LG RLG IADJ RIADJ2 DAP COMP CCOMP CS RF GND RCS CVCC RVOUT1 Figure 23. TPS92640 Design Procedure Schematic 8.2.1.1 Design Requirements * * * * * * * * * * VIN VLED Number of LEDs in Series ILED fSW VCS iLED-PP VIN-PP VTURN-ON VHYS 8.2.1.2 Detailed Design Procedure 8.2.1.2.1 Set Output Voltage Feedback Ratio For the desired output (VOUT), RVOUT1 and RVOUT2 is calculated first with the desired feedback voltage, VVOUT at approximately 2.5 V: 22 Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92640 TPS92641 TPS92640, TPS92641 www.ti.com SNVS902A - OCTOBER 2012 - REVISED OCTOBER 2015 Typical Applications (continued) R VOUT2 R VOUT1 R VOUT2 VOUT u R VOUT2 R VOUT1 R VOUT2 VOUT VLED 2 .5 V 2 .5 VOUT ILED u R SNS (17) 8.2.1.2.2 Set Switching Frequency The switching frequency is set as follows: R VOUT1 R VOUT 2 R VOUT 2 fSW R ON u CON (18) 8.2.1.2.3 Set Average LED Current The average LED current (ILED) is set by: VIADJ ILED 10 u R CS VIADJ VREF u VREF 3.03 V RIADJ2 RIADJ1 RIADJ2 (19) 8.2.1.2.4 Set Inductor Ripple Current First, the expected duty cycle, D must be determined: VOUT D : expected efficiency K u VIN (20) With the inductor ripple current, iL-PP specified and the expected duty cycle, the inductance (L) can be chosen: L VIN VOUT u D 'iL PP u fSW (21) 8.2.1.2.5 Set LED Ripple Current and Determine Output Capacitance, COUT The LED ripple current (iLED-PP ) is specified. With the target ripple current determined, the output capacitance (COUT) can be chosen using Equation 22. 'iL PP COUT 8 u fSW u rD u 'iLED PP (22) 8.2.1.2.6 Choose N-Channel MOSFETs The suggested minimum voltage rating, VT-MAX and current rating, IT-MAX are: VT MAX IT MAX 1.2 u VIN MAX 1.5 u DMAX u ILED (23) Selecting a proper power MOSFET is critical in a power application, other than the SOA limits, the gate characteristic and the RDSON can affect the system performance seriousely. Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92640 TPS92641 Submit Documentation Feedback 23 TPS92640, TPS92641 SNVS902A - OCTOBER 2012 - REVISED OCTOBER 2015 www.ti.com Typical Applications (continued) Also, the peak current limit (ILIMIT) is governed by: ILIMIT | 1.28 V RDSON VIN = 85V, at room temperature (24) Both the current limit threshold and MOSFET RDSON are loosely specified and can vary a lot with temperature, input voltage and other operating conditions. 8.2.1.2.7 Choose Input Capacitance Input capacitance is necessary to provide instantaneous current to the discontinuous portions of the circuit during the high side NFET on-time. The allowable input voltage ripple (vIN-PP) is specified at approximately 3% Pk-Pk of VIN. The minimum required capacitance (CIN_MIN) to achieve this specification is: ILED u D CIN _ MIN 'v IN PP u fSW (25) The necessary RMS input current rating (IIN-RMS) can be approximated as follows: IIN RMS ILED u D u 1 D (26) 8.2.1.2.8 Set the Turnon Voltage and Undervoltage Lockout Hysteresis With the desired turnon threshold voltage (VTURN_ON) stated, the resistor divider network composing with RUDIM1 and RUDIM2 can be calculated with the equation in below. R RUDIM2 * VTURN _ ON 1.276V u UDIM1 RUDIM2 (c) RUDIM2 1.276V u RUDIM1 VTURN _ ON 1.276 V (27) Then RUDIM3 is optional and recommended for PWM. The RUDIM3 can be calculated based on Equation 10 to provide the desired undervoltage lockout hysteresis (VHYS). 24 Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92640 TPS92641 TPS92640, TPS92641 www.ti.com SNVS902A - OCTOBER 2012 - REVISED OCTOBER 2015 Typical Applications (continued) 8.2.2 TPS92640 - PWM Dimming Application VIN CIN1 RON RUDIM1 CIN2 VIN TPS92640 QHS HG RHG CON RON SW PWM RUDIM2 UDIM BOOT VOUT VCC RUDIM3 DBOOT RVOUT2 CVREF L CBOOT RIADJ1 QLS VREF LG RLG IADJ DAP RIADJ2 CCOMP COUT COMP CS RF GND RCS CVCC RVOUT1 Figure 24. PWM Dimming Using UDIM Pin Schematic 8.2.2.1 Design Requirements * * * * * * * * * * VIN = 48 V 10% VLED = 3.25 V, 325-m dynamic resistance 10 LEDs in Series, rD = 3.25 ILED = 1 A fSW = 500 kHz VCS = 200 mV iLED-PP 300 mA VIN-PP 1.5 V VTURN-ON = 40 V VHYS = 15 V 8.2.2.2 Detailed Design Procedure 8.2.2.2.1 Calculate Operating Points Calculate the operating points using Equation 28 to Equation 30, and assume approximately 90% conversion efficiency ( = 0.9). VOUT = n x VLED + 200mV = 10 x 3.25V + 200mV = 32.7V Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92640 TPS92641 (28) Submit Documentation Feedback 25 TPS92640, TPS92641 SNVS902A - OCTOBER 2012 - REVISED OCTOBER 2015 www.ti.com Typical Applications (continued) D= DMAX VOUT 32.7 = = 0.76 x VIN 0.9 x 48V VOUT 32.7 = = = 0.84 x VIN-MIN 0.9 x 43.2V (29) (30) 8.2.2.2.2 Output Voltage Feedback Calculate the VOUT pin resistors by setting RVOUT2 = 10 k and calculating RVOUT1. RVOUT1 = RVOUT2 x VOUT 10k x 32.7V - RVOUT2 = - 10k 2.5V 2.5V 0.8k (31) Choose RVOUT1 = 120 k. 8.2.2.2.3 Switching Frequency Using the values calculated above choose a value of CON = 1 nF and calculate the value of RON: RON RVOUT1 + RVOUT2 120k + 10k RVOUT2 10k = = = 26k CON x fSW 1nF x 500kHz (32) Choose the closest standard resistor value of RON = 26.1 k. 8.2.2.2.4 Set the Feedback Reference and LED Current To get a value of VCS = 200 mV VIADJ must be set to 2 V. Choose a value of RIADJ1 = 10 k and solve for RIADJ2: RIADJ2 = VIADJ x RIADJ1 2V x 10k = = 19.4k VREF - VIADJ 3.03V - 2V (33) Choose the standard resistor value of RIADJ2 = 19.6 k and solve for RCS using Equation 34. RCS = VIADJ 2V = 10 x 1A 10 x ILED (34) RCS = 0.2 is a standard resistor value. 8.2.2.2.5 Calculate the Inductor Value Because this is a PWM dimming application, TI does not recommend much output capacitance for faster current rise and fall times, so the inductor ripple current should be close to the 300-mA peak-to-peak LED ripple current. Calculate and inductor value that will give you 350-mA peak-to-peak inductor ripple current or less: L= (VIN - VOUT ) x D (48V - 32.7V) x 0.76 = iL-PP x fSW 350mA x 500kHz H (35) Choose the standard value of L = 68 H which results in an actual iL-PP of 342 mA. 8.2.2.2.6 Calculate the Output Capacitor Value Given the actual inductor ripple current of 342-mA peak-to-peak, use Equation 36 to calculate the required output capacitor value. COUT = iL-PP 342mA = = 88nF 8 x rD x iLED-PP x fSW 8x3.25 x 300mA x 500kHz (36) Choose COUT = 0.1 F. 8.2.2.2.7 Calculate the MOSFET Parameters The MOSFETs must have a minimum voltage and current rating for the application. The minimum ratings are calculated using Equation 37 and Equation 38. 26 Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92640 TPS92641 TPS92640, TPS92641 www.ti.com SNVS902A - OCTOBER 2012 - REVISED OCTOBER 2015 Typical Applications (continued) VT-MAX = 1.2 x VIN-MAX = 1.2 x 52.8V = 63V (37) IT-MAX = 1.5 x DMAX x ILED = 1.5 x 0.84 x 1A = 1.26A (38) Choose MOSFETs that have a drain-to-source voltage rating of greater than 63 V and a current rating greater than 1.26 A. 8.2.2.2.8 Calculate the Minimum Input Capacitance The minimum input capacitance to achieve 1.5-V peak-to-peak input voltage ripple is calculated using Equation 39. CIN_MIN = ILED x D 1A x 0.76 = 1.5V x 500kHz VIN-PP x fSW F (39) For PWM dimming applications more input voltage ripple will be present at the PWM dimming frequency. For these applications, TI recommends using 10 times the amount of minimum input capacitance or more. Choose CIN = 10 F. 8.2.2.2.9 Undervoltage Lockout and Hysteresis Choose a value of RUDIM1 = 100 k and calculate the values of RUDIM2 and RUDIM3 using Equation 40 and Equation 41. RUDIM2 = RUDIM3 = 1.276V x RUDIM1 1.276V x 100k = VTURN-ON - 1.276V 40V - 1.276V l = 3.3k VHYS 15V - RUDIM1 p x RUDIM2 - 100k p x 3.24k l A A = 100k - 3.24k RUDIM1 + RUDIM2 (40) = 19.3k (41) Choose the nearest standard resistor values of RUDIM2 = 3.32 k and RUDIM3 = 19.1 k. 8.2.2.3 Application Curve Figure 25. UDIM Dimming Waveform 9 Power Supply Recommendations Any DC output power supply may be used provided it has a high enough voltage and current range for the particular application required. Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92640 TPS92641 Submit Documentation Feedback 27 TPS92640, TPS92641 SNVS902A - OCTOBER 2012 - REVISED OCTOBER 2015 www.ti.com 10 Layout 10.1 Layout Guidelines The performance of any switching converter depends as much upon the layout of the PCB as the component selection. Following a few simple guidelines will maximize noise rejection and minimize the generation of EMI within the circuit. Discontinuous currents are the most likely to generate EMI, therefore take care when routing these paths. The main path for discontinuous current in the TPS92640 and TPS92641 buck converters contain the input capacitor (CIN), the low side MOSFET (QLS), and the high side MOSFET (QHS). This loop should be kept as small as possible and the connections between all three components should be short and thick to minimize parasitic inductance. In particular, the switch node (where L, QLS and QHS connect) should be just large enough to connect the components without excessive heating from the current it carries. The current sense trace (CS pin) should be run along with a ground plane or have differential traces run for CS and ground. In some applications, the LED or LED array can be far away (several inches or more) from the circuit, or on a separate PCB connected by a wiring harness. When an output capacitor is used and the LED array is large or separated from the rest of the converter, the output capacitor should be placed close to the LEDs to reduce the effects of parasitic inductance on the AC impedance of the capacitor. 10.2 Layout Example Note critical paths and component placement: Minimize power loop containing discontinuous currents Minimize signal current loops (components close to IC) x Ground plane under IC for signal routing helps minimize noise coupling discontinuous switching frequency currents VIN Input Power GND 1 2 3 VIN HG RON SW UDIM BOOT 14 13 12 VOUT LED+ 4 5 VOUT VCC VREF LG 11 10 LED- 6 7 CS IADJ COMP GND 9 8 DAP Power Ground Figure 26. Layout Recommendation 28 Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92640 TPS92641 TPS92640, TPS92641 www.ti.com SNVS902A - OCTOBER 2012 - REVISED OCTOBER 2015 10.3 EMI and Noise Considerations In synchronous rectifier, the high speed gate drive signals can generate significant conducted and radiated EMI. This noise can couple with high impedance nodes of the IC and result in undesirable operation. A small (4 to 10 ) resistors, RHG and RLG, in series with the gate drive signals are recommended to slow the slew-rate of the SW node and reduce the noise signature. They also improve the robustness of the circuit by reducing the noise coupling in to sensitive nodes such as UDIM, CS, RON and IADJ. In other to further reduce EMI signature, good PCB layout techniques must be implemented. The loop area between the synchronous NFET, inductor and output capacitor should be minimized to reduce radiated EMI due to switching action. The trace lengths of high impedance nodes (UDIM, CS, RON and IADJ) should be minimized and shielded from switching noise. The parasitic capacitance between switching node and ground node should be minimized to reduce common mode noise. Other common layout techniques such as star ground and noise suppression using local bypass capacitors should be followed to maximize noise rejection and minimize EMI within the circuit. Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92640 TPS92641 Submit Documentation Feedback 29 TPS92640, TPS92641 SNVS902A - OCTOBER 2012 - REVISED OCTOBER 2015 www.ti.com 11 Device and Documentation Support 11.1 Related Links The table below lists quick access links. Categories include technical documents, support and community resources, tools and software, and quick access to sample or buy. Table 1. Related Links PARTS PRODUCT FOLDER SAMPLE & BUY TECHNICAL DOCUMENTS TOOLS & SOFTWARE SUPPORT & COMMUNITY TPS92640 Click here Click here Click here Click here Click here TPS92641 Click here Click here Click here Click here Click here 11.2 Community Resources The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2ETM Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support. 11.3 Trademarks E2E is a trademark of Texas Instruments. All other trademarks are the property of their respective owners. 11.4 Electrostatic Discharge Caution These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. 11.5 Glossary SLYZ022 -- TI Glossary. This glossary lists and explains terms, acronyms, and definitions. 12 Mechanical, Packaging, and Orderable Information The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. 30 Submit Documentation Feedback Copyright (c) 2012-2015, Texas Instruments Incorporated Product Folder Links: TPS92640 TPS92641 PACKAGE OPTION ADDENDUM www.ti.com 29-Jun-2015 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) TPS92640PWP/NOPB ACTIVE HTSSOP PWP 14 94 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 TP92640 PWP TPS92640PWPR/NOPB ACTIVE HTSSOP PWP 14 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 TP92640 PWP TPS92640PWPT/NOPB ACTIVE HTSSOP PWP 14 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 TP92640 PWP TPS92641PWP/NOPB ACTIVE HTSSOP PWP 16 92 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 TP92641 PWP TPS92641PWPR/NOPB ACTIVE HTSSOP PWP 16 2500 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 TP92641 PWP TPS92641PWPT/NOPB ACTIVE HTSSOP PWP 16 250 Green (RoHS & no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 125 TP92641 PWP (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 29-Jun-2015 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 6-Nov-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing TPS92640PWPR/NOPB HTSSOP PWP 14 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 2500 330.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1 TPS92640PWPT/NOPB HTSSOP PWP 14 250 178.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1 TPS92641PWPR/NOPB HTSSOP PWP 16 2500 330.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1 TPS92641PWPT/NOPB HTSSOP PWP 16 250 178.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 6-Nov-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS92640PWPR/NOPB HTSSOP PWP 14 2500 367.0 367.0 35.0 TPS92640PWPT/NOPB HTSSOP PWP 14 250 210.0 185.0 35.0 TPS92641PWPR/NOPB HTSSOP PWP 16 2500 367.0 367.0 35.0 TPS92641PWPT/NOPB HTSSOP PWP 16 250 210.0 185.0 35.0 Pack Materials-Page 2 MECHANICAL DATA PWP0014A MXA14A (Rev A) www.ti.com PACKAGE OUTLINE PWP0016A PowerPAD TM HTSSOP - 1.2 mm max height SCALE 2.400 PLASTIC SMALL OUTLINE C 6.6 TYP 6.2 SEATING PLANE PIN 1 ID AREA A 0.1 C 14X 0.65 16 1 2X 4.55 5.1 4.9 NOTE 3 8 9 B 4.5 4.3 16X 0.30 0.19 0.1 C A B (0.15) TYP SEE DETAIL A 4X 0.166 MAX NOTE 5 2X 1.34 MAX NOTE 5 THERMAL PAD 3.3 2.7 17 0.25 GAGE PLANE 1.2 MAX 0.15 0.05 0 -8 0.75 0.50 (1) 3.3 2.7 DETAIL A TYPICAL 4214868/A 02/2017 PowerPAD is a trademark of Texas Instruments. NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. Reference JEDEC registration MO-153. 5. Features may not be present. www.ti.com EXAMPLE BOARD LAYOUT PWP0016A PowerPAD TM HTSSOP - 1.2 mm max height PLASTIC SMALL OUTLINE (3.4) NOTE 9 SOLDER MASK DEFINED PAD (3.3) 16X (1.5) SYMM SEE DETAILS 1 16 16X (0.45) (1.1) TYP 17 SYMM (3.3) (5) NOTE 9 14X (0.65) 8 9 ( 0.2) TYP VIA (1.1) TYP METAL COVERED BY SOLDER MASK (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:10X SOLDER MASK OPENING METAL UNDER SOLDER MASK METAL SOLDER MASK OPENING EXPOSED METAL 0.05 MAX ALL AROUND EXPOSED METAL 0.05 MIN ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS PADS 1-16 4214868/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. 8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004). 9. Size of metal pad may vary due to creepage requirement. www.ti.com EXAMPLE STENCIL DESIGN PWP0016A PowerPAD TM HTSSOP - 1.2 mm max height PLASTIC SMALL OUTLINE (3.3) BASED ON 0.125 THICK STENCIL 16X (1.5) (R0.05) TYP 1 16 16X (0.45) (3.3) BASED ON 0.125 THICK STENCIL 17 SYMM 14X (0.65) 9 8 SYMM METAL COVERED BY SOLDER MASK (5.8) SEE TABLE FOR DIFFERENT OPENINGS FOR OTHER STENCIL THICKNESSES SOLDER PASTE EXAMPLE EXPOSED PAD 100% PRINTED SOLDER COVERAGE BY AREA SCALE:10X STENCIL THICKNESS SOLDER STENCIL OPENING 0.1 0.125 0.15 0.175 3.69 X 3.69 3.3 X 3.3 (SHOWN) 3.01 X 3.01 2.79 X 2.79 4214868/A 02/2017 NOTES: (continued) 10. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 11. 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