VIN
RON
UDIM
VOUT
VREF
IADJ
COMP
SDIM
HG
SW
BOOT
VCC
LG
CS
GND
SDRV
DAP
TPS92640/641
PWM
*SDIM
VIN
CIN1
CIN2
RUDIM1
RUDIM2 RUDIM3
CON
RON
RVOUT2
CVREF RIADJ1
RIADJ2
CCOMP
RHG
RLG
CBOOT
DBOOT
RF
CVCC RCS
L
QHS
QLS
*QSDIM
COUT
RVOUT1
*TPS92641 ONLY
Product
Folder
Sample &
Buy
Technical
Documents
Tools &
Software
Support &
Community
TPS92640
,
TPS92641
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TPS9264x Synchronous Buck Controllers for Precision Dimming LED Drivers
1 Features 3 Description
The TPS92640 and TPS92641 devices are high-
1 VIN Range from 7 V to 85 V voltage, synchronous NFET controllers for buck-
Wide Dimming Range current regulators. Output current regulation is based
500:1 Analog Dimming on valley current-mode operation using a controlled
on-time architecture. This control method eases the
2500:1 Standard PWM Dimming design of loop compensation while maintaining nearly
20000:1 Shunt FET PWM Dimming constant switching frequency. The TPS92640 and
Adjustable LED Current Sense Voltage TPS92641 devices include a high-voltage start-up
regulator that operates over a wide input range of 7 V
2-Ω, 1-Apeak MOSFET Gate Drivers to 85 V. The PWM controller is designed for high
Shunt Dimming MOSFET Gate Driver (TPS92641) speed capability, including an oscillator frequency
Programmable Switching Frequency range up to 1 MHz. The deadtime between high side
Precision Voltage Reference 3 V ±2% and low side gate driver is optimized to provide very
high efficiency over a wide input operating voltage
Input UVLO and Output OVP and output power range. The TPS92640 and
Low Power Shutdown Mode and Thermal TPS92641 devices accept both analog and PWM
Shutdown input signals, resulting in exceptional dimming control
range. Linear response characteristics between input
2 Applications command and LED current is achieved with true zero
LED current using low off-set error amplifier and
LED Driver / Constant Current Regulator proprietary PWM dimming logic. Both devices also
Architectural LED Lighting Drivers include precision reference capable of supplying
Automotive LED Drivers current to low power microcontroller. Protection
features include cycle-by-cycle current protection,
General LED Illumination overvoltage protection, and thermal shutdown. The
TPS92641 device includes a shunt FET dimming
input and MOSFET driver for high resolution PWM
dimming.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
TPS92640 HTSSOP (14) 4.40 mm × 5.00 mm
TPS92641 HTSSOP (16) 4.40 mm × 5.00 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Diagram
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPS92640
,
TPS92641
SNVS902A OCTOBER 2012REVISED OCTOBER 2015
www.ti.com
Table of Contents
7.4 Device Functional Modes........................................ 18
1 Features.................................................................. 18 Application and Implementation ........................ 19
2 Applications ........................................................... 18.1 Application Information............................................ 19
3 Description............................................................. 18.2 Typical Applications ............................................... 22
4 Revision History..................................................... 29 Power Supply Recommendations...................... 27
5 Pin Configuration and Functions......................... 310 Layout................................................................... 28
6 Specifications......................................................... 410.1 Layout Guidelines ................................................. 28
6.1 Absolute Maximum Ratings ..................................... 410.2 Layout Example .................................................... 28
6.2 ESD Ratings.............................................................. 410.3 EMI and Noise Considerations ............................. 29
6.3 Recommended Operating Conditions ...................... 411 Device and Documentation Support................. 30
6.4 Thermal Information.................................................. 511.1 Related Links ........................................................ 30
6.5 Electrical Characteristics .......................................... 611.2 Community Resources.......................................... 30
6.6 Typical Characteristics.............................................. 811.3 Trademarks........................................................... 30
7 Detailed Description............................................ 10 11.4 Electrostatic Discharge Caution............................ 30
7.1 Overview................................................................. 10 11.5 Glossary................................................................ 30
7.2 Functional Block Diagram....................................... 10 12 Mechanical, Packaging, and Orderable
7.3 Feature Description................................................. 11 Information ........................................................... 30
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Original (October 2012) to Revision A Page
Added ESD Ratings table, Feature Description section, Device Functional Modes,Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1
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Product Folder Links: TPS92640 TPS92641
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VIN
RON
UDIM
VOUT
VREF
IADJ
COMP
SDIM
HG
DAP
SW
BOOT
VCC
LG
CS
GND
SDRV
1
2
3
4
5
6
7
14
13
12
11
10
9
8
VIN
RON
UDIM
VOUT
VREF
IADJ
COMP
HG
DAP
SW
BOOT
VCC
LG
CS
GND
TPS92640
,
TPS92641
www.ti.com
SNVS902A OCTOBER 2012REVISED OCTOBER 2015
5 Pin Configuration and Functions
TPS92640 PWP Package TPS92641 PWP Package
14-Pin HTSSOP 16-Pin HTSSOP
Top View Top View
Pin Functions
PIN I/O DESCRIPTION
NO. NO.
NAME (TPS92640) (TPS92641)
Connect 100-nF ceramic capacitor to switch node and diode to VCC to provide
BOOT 12 14 O boosted voltage for high-side gate drive.
COMP 7 7 O Connect ceramic capacitor to GND to set loop compensation.
CS 9 11 I Connect to positive terminal of sense resistor at the bottom of the LED stack.
GND 8 10 System GND. Connect to DAP.
Connect to gate of high-side NFET of buck regulator. Use series resistor to limit
HG 14 16 O current slew-rate and mitigate EMI noise.
Connect resistor divider from VREF to set analog dimming level. Use NTC
IADJ 6 6 I resistor from pin to GND as resistor divider to implement thermal foldback
operation.
Connect to gate of low-side NFET of buck regulator. Use series resistor to limit
LG 10 12 O current slew-rate and mitigate EMI noise.
RON 2 2 I Connect a resistor to VIN and capacitor to GND to set switching frequency.
SDIM 8 I PWM dimming input for shunt FET dimming.
Connect to gate of external parallel NFET across LED load used for shunt
SDRV 9 O dimming if desired.
SW 13 15 O Connect to switch node of buck regulator.
UDIM 3 3 I Connect resistor divider from VIN to set undervoltage lockout threshold.
VCC 11 13 O Bypass with 2.2-µF ceramic capacitor to provide bias supply for controller.
VIN 1 1 I Connect to input voltage. Connect 1-µF bypass capacitor
VOUT 4 4 I Connect resistor divider from VOUT, scaled down feedback of VOUT.
VREF 5 5 O System reference voltage. Bypass with 100-nF ceramic capacitor.
DAP Place 6-9 vias from pad to GND plane for thermal relief.
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SNVS902A OCTOBER 2012REVISED OCTOBER 2015
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
–0.3 90 V
VIN, UDIM, SW –1 mA
BOOT –0.3 98.5 V
–0.3 90 V
HG –2.5 (Pulse < 100 ns) V
–0.3 +VCC V
LG, SDRV, CS –2.5 (Pulse < 100 ns) V
VCC + 2.5 (Pulse < 100 ns) V
VCC –0.3 15 V
–0.3 6 V
VREF, RON, COMP, VOUT, IADJ, SDIM –200 200 µA
–0.3 0.3 V
GND –2.5 (Pulse < 100 2.5 (Pulse < 100 ns) V
ns)
Continuous power dissipation Internally Limited
Maximum lead temperature (soldering and reflow) (2) 260 °C
Maximum junction temperature –40 125 °C
Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Refer to TI’s packaging website for more detailed information and mounting techniques.
6.2 ESD Ratings VALUE UNIT
TPS92640 PWP PACKAGE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22- ±1000
C101(2)
TPS92641 PWP PACKAGE
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000
V(ESD) Electrostatic discharge V
Charged-device model (CDM), per JEDEC specification JESD22- ±1000
C101(2)
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT
VIN Input voltage 7 85 V
TJJunction temperature –40 125 °C
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6.4 Thermal Information TPS92640 TPS92641
THERMAL METRIC(1) PWP (HTSSOP) PWP (HTSSOP) UNIT
14 PINS 16 PINS
RθJA Junction-to-ambient thermal resistance 40.1 38.7 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 24.6 22.7 °C/W
RθJB Junction-to-board thermal resistance 20.9 16.5 °C/W
ψJT Junction-to-top characterization parameter 0.6 0.6 °C/W
ψJB Junction-to-board characterization parameter 20.7 16.3 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 2.5 1.7 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
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SNVS902A OCTOBER 2012REVISED OCTOBER 2015
www.ti.com
6.5 Electrical Characteristics
Unless otherwise specified VIN = 24 V. Typical specifications apply for TA= TJ= 25°C.
PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT
START-UP REGULATOR (VCC, VIN)
VCCREG VCC Regulation ICC = 10 mA, VIN = 24 V, 85 V 7.86 8.5 9.14 V
ICCLIM VCC Current Limit VCC = 0 V 48 63 78 mA
VUDIM = 3 V,
IQQuiescent Current 2 3 mA
Static VIN = 7 V, 24 V, 85 V
ISD Shutdown Current VUDIM = 0 V 100 µA
VCC increasing 5.04 5.9
VCC-UV VCC UVLO Threshold V
VCC decreasing 4.5 4.9
VCC-HYS VCC UVLO Hysteresis 0.17 V
REFERENCE VOLTAGE (VREF)
VREF Reference Voltage No Load, VIN = 7 V, 24 V, 85 V 2.97 3.03 3.09 V
IVREFLIM Current Limit VREF = 0 V 1.3 2.1 2.9 mA
ERROR AMPLIFIER (CS, COMP)
VCSREF CS Reference Voltage With respect to GND VIADJ/10 V
VCSREF-OFF Error Amp Input Offset Voltage –600 0 600 µV
ICOMP COMP Sink Current 85 µA
COMP Source Current 110 µA
gM-CS Transconductance 500 µA/V
Linear Input Range See (3) ±125 mV
Transconductance Bandwidth –6-dB unloaded response(3) 400 kHz
TIMERS / OVERVOLTAGE PROTECTION (RON, VOUT)
tOFF-MIN Minimum Off-time CS = 0 V 230 ns
tON-MIN Minimum On-time 235 ns
VVOUT = 2 V, RON = 25 kΩ, CON = 1
tON Programmed On-time 2.08 µs
nF
RRON RON Pulldown Resistance 35 120 Ω
tCL Current Limit Off-time 270 µs
tD-ON RON Thresh - HG Falling Delay 25 ns
VTH-OVP VOUT Overvoltage Threshold VOUT rising 2.85 3.05 3.25 V
VHYS-OVP VOUT Overvoltage Hysteresis 0.13 V
GATE DRIVER (HG, LG, BOOT, SW)
RSRC-LG LG Sourcing Resistance LG = High 1.5 6 Ω
RSNK-LG LG Sinking Resistance LG = Low 1 4.5 Ω
RSRC-HG HG Sourcing Resistance HG = High 3.9 6 Ω
RSNK-HG HG Sinking Resistance HG = Low 1.1 4.5 Ω
VTH-BOOT BOOT UVLO Threshold BOOT-SW rising 1.9 3.4 4.5 V
VHYS-BOOT BOOT UVLO Hysteresis BOOT-SW falling 1.8 V
TD-HL HG to LG deadtime HG fall to LG rise 60 ns
TD-LH LG to HG deadtime LG fall to HG rise 60 ns
(1) All limits specified at room temperature (TYP values) and at temperature extremes (MIN/MAX values). All room temperature limits are
100% production tested. All limits at temperature extremes are specified via correlation using standard Statistical Quality Control (SQC)
methods. All limits are used to calculate Average Outgoing Quality Level (AOQL).
(2) Typical numbers are at 25°C and represent the most likely norm.
(3) These electrical parameters are specified by design, and are not verified by test.
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,
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SNVS902A OCTOBER 2012REVISED OCTOBER 2015
Electrical Characteristics (continued)
Unless otherwise specified VIN = 24 V. Typical specifications apply for TA= TJ= 25°C.
PARAMETER TEST CONDITIONS MIN(1) TYP(2) MAX(1) UNIT
PWM DIMMING (SDIM, SDRV) (TPS92641 only)
RSRC-DDRV SDRV Sourcing Resistance SDRV = High 5.6 30 Ω
tSDIM-RIS SDIM to SDRV Rising Delay SDIM rising 68 100 ns
tSDIM -FALL SDIM to SDRV Falling Delay SDIM falling 29 70 ns
VSDIM-RIS SDIM Rising Threshold SDIM rising 1.29 1.74 V
VSDIM -FALL SDIM Falling Threshold SDIM falling 0.5 V
RSDIM-PU SDIM Pullup Resistance 90 kΩ
ANALOG ADJUST (IADJ)
VADJ-MAX IADJ Clamp Voltage 2.46 2.54 2.62 V
RADJ IADJ Input Impedance 1 MΩ
UNDERVOLTAGE / PWM (UDIM)
VTH-UDIM UDIM Start-up Threshold UDIM rising 1.21 1.276 1.342 V
IHYS-UDIM UDIM Hysteresis Current 12 21 30 µA
tUDIM-RIS UDIM to HG/LG Rising Delay UDIM rising 168 260 ns
tUDIM-FALL UDIM to HG/LG Falling Delay UDIM falling 174 280 ns
VUDIM-LP UDIM Low Power Threshold 370 mV
TUDIM-DET UDIM Shutdown Detect Timer UDIM falling 8.5 13 ms
THERMAL SHUTDOWN
TSD Thermal Shutdown Threshold See (3) 165 °C
THYS Thermal Shutdown Hysteresis See (3) 20 °C
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200
220
240
260
280
0 10 20 30 40 50 60 70 80 90
Input Voltage, VIN(V)
C001
125°C
25°C
-40°C
200
220
240
260
280
0 10 20 30 40 50 60 70 80 90
Input Voltage, VIN(V)
C001
125°C
25°C
-40°C
6.00
6.50
7.00
7.50
8.00
8.50
9.00
0 10 20 30 40 50 60 70 80 90
Startup Regulator, VCC(V)
Input Voltage, VIN(V)
C001
125°C
25°C
-40°C
IVCC = 10mA
2.96
2.98
3.00
3.02
3.04
3.06
0 10 20 30 40 50 60 70 80 90
Reference Voltage, VREF(V)
Input Voltage, VIN(V)
C001
125°C
25°C -40°C
IVREF = 500PA
1.50
1.70
1.90
2.10
2.30
2.50
0 10 20 30 40 50 60 70 80 90
Quescient Current, IQ(mA)
Input Voltage, VIN(V)
C001
125°C 25°C
-40°C
0.00
40.00
80.00
120.00
160.00
200.00
0 10 20 30 40 50 60 70 80 90
Shutdown Current, ISD(µA)
Input Voltage, VIN(V)
C001
125°C 25°C
-40°C
TPS92640
,
TPS92641
SNVS902A OCTOBER 2012REVISED OCTOBER 2015
www.ti.com
6.6 Typical Characteristics
Unless otherwise stated, –40°C TA= TJ125°C, VIN = 24 V, VIADJ= 2 V, ILED = 1 A, CVCC = 2.2 μF, CCOMP = 0.47 μF
Figure 1. Quescient Current, IQvs Input Voltage, VIN Figure 2. Shutdown Current, ISDvs Input Voltage , VIN
Figure 3. Start-Up Regulator, VCC vs Input Voltage, VIN Figure 4. Reference Voltage, VREF vs Input Voltage, VIN
Figure 5. Minimum On-time, tON_MIN vs Input Voltage, VIN Figure 6. Minimum Off-time, tOFF_MIN vs Input Voltage, VIN
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VIN = 48V
VLED § 32V (10 LEDs)
ILED = 1A
fSW § 500kHz
ILED : 500mA/DIV
VSW : 20V/DIV
Time : 1Ps/DIV
VIN = 48V
VLED § 32V (10 LEDs)
ILED = 1A
fSW § 500kHz
fUDIM = 200Hz
ILED : 500mA/DIV
VSW : 20V/DIV
VUDIM : 5V/DIV
Time : 1ms/DIV
VIN : 50V/DIV
VSW : 20V/DIV
ILED : 500mA/DIV VIN = 48V
VLED § 32V (10 LEDs)
ILED = 1A
fSW § 500kHz
Time : 4ms/DIV
0
100
200
300
400
500
600
700
0 10 20 30 40 50 60 70 80 90
Input Voltgae, VIN(V)
C009
1 LED
8 LEDs
15 LEDs
fSW §N+]1RP
ILED = 1A (Nom.)
L = 68µH, 94mQ
0.900
0.950
1.000
1.050
1.100
0 10 20 30 40 50 60 70 80 90
LED Current, ILED(A)
Input Voltage, VIN(V)
C007
1 LED
8 LEDs
15 LEDs
fSW §N+]1RP
ILED = 1A (Nom.)
L = 68µ, 94mQ
50.0
60.0
70.0
80.0
90.0
100.0
0 10 20 30 40 50 60 70 80 90
Efficiency, (%)
Input Voltage, VIN(V)
C008
1 LED
8 LEDs
15 LEDs
fSW §N+]1RP
ILED = 1A (Nom.)
L = 68µH, 94mQ
QHS, QLS : SUD15N15-95
TPS92640
,
TPS92641
www.ti.com
SNVS902A OCTOBER 2012REVISED OCTOBER 2015
Typical Characteristics (continued)
Unless otherwise stated, –40°C TA= TJ125°C, VIN = 24 V, VIADJ= 2 V, ILED = 1 A, CVCC = 2.2 μF, CCOMP = 0.47 μF
Figure 7. LED Current, ILED vs Input Voltage, VIN Figure 8. Conversion Efficiency, ηvs Input Voltage, VIN
Figure 9. Converter Switching Frequency, fSW vs Input Figure 10. Waveforms of Power-Up Transient
Voltage, VIN
Figure 11. Waveforms of Steady-State Operation Figure 12. Waveforms of UDIM Operation (DDIM = 0.5)
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Product Folder Links: TPS92640 TPS92641
H.S.
Driver
VCC
SW
BOOT
End tON
SDIM
VOUT
RON
UDIM
CS
VIN
GND
OVP
SD
HG
SDRV
VREF
VOLTAGE
REFERENCES
370mV
1.276V
2.54V 3.03V
VCC BIAS
REGULATOR
VIN
VCC
VDD
VCC UVLO
THERMAL
SHUTDOWN
LOGIC
GATE DRIVE UVLO
VSW
Q
Q
R
S
DEAD TIME /
LEVEL SHIFT
VSW
tON
tOFF
LGATE Enable
DEAD
TIME
VCC
LG
TPS92640, TPS92641
VCC
+
-
3.05V
+
-
LEB TIMER
tON_Reset
tON_ Reset
TPS92641 ONLY
IADJ
COMP
L.S.
Driver
+
-
1.276V
PWM_DIM / UVLO
21µA
+
-
+
-
PWM_DIM
9R
R
2.54V EA
FSW
+
-
VDD
1.276V
PWM
LOGIC
+
-
370mV 13ms FILTER Shutdown
TPS92640
,
TPS92641
SNVS902A OCTOBER 2012REVISED OCTOBER 2015
www.ti.com
7 Detailed Description
7.1 Overview
The TPS92640 and TPS92641 devices are synchronous N-channel MOSFET (NFET) controllers for step-down
(buck) current regulators, which are ideal for driving LED loads. They can accept wide input voltage range
allowing for greater flexibility in powering different series connected LED string combinations. The single current
sense pin with low adjustable threshold voltage provides an excellent method for regulating LED current while
maintaining high system efficiency. The TPS92640 and TPS92641 devices use valley current control with a
controlled on-time architecture that allows the converter to be operated at nearly constant switching frequency
without the need for slope compensation. The extremely accurate adjustable current sense threshold together
with the synchronous operation provides the capability to amplitude (analog) dim the LED current with high
contrast ratios. Excellent PWM dimming is attainable using the main NFETs or the external shunt FET driver
(TPS92641 only). The TPS92640 and TPS92641 devices incorporate 2-Ω, 1-A internal gate drivers and supports
constant current operation up to 5 A. This simple controller contains all the features necessary to implement a
high-efficiency, versatile LED driver with precise dimming response.
7.2 Functional Block Diagram
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IN
OUT
OFFON
ON V
V
TT T
DuK
CSLEDOUT VVV
VIN
RON
UDIM
VOUT
VREF
IADJ
COMP
SDIM
HG
SW
BOOT
VCC
LG
CS
GND
SDRV
DAP
TPS92640/641
PWM
*SDIM
VIN
CIN1
CIN2
RUDIM1
RUDIM2 RUDIM3
CON
RON
RVOUT2
CVREF RIADJ1
RIADJ2
CCOMP
RHG
RLG
CBOOT
DBOOT
RF
CVCC RCS
L
QHS
QLS
*QSDIM
COUT
RVOUT1
*TPS92641 ONLY
TPS92640
,
TPS92641
www.ti.com
SNVS902A OCTOBER 2012REVISED OCTOBER 2015
7.3 Feature Description
Figure 13. Synchronous Buck LED Driver
7.3.1 Controlled On-Time Architecture
The control architecture is a combination of valley current control and a one-shot on-timer that varies with input
and output voltage. The TPS92640 and TPS92641 devices use a series resistor in the LED path to sense both
average LED current and valley inductor current. During the time that the high side NFET is turned on (tON), the
input voltage charges up the inductor. When it is turned off (tOFF) and the low side NFET is turned on, the
inductor discharges. During both intervals, the current is supplied to the load keeping the LEDs forward biased.
Figure 14 shows the inductor current (iL) waveform for a buck converter operating in continuous conduction mode
(CCM). As the system changes input voltage or output voltage, duty cycle D is varied indirectly by changing both
tON and tOFF to regulate ILand ultimately ILED. For any buck regulator, duty cycle, D, is calculated using
Equation 1.
where
VCS is the voltage measured at the CS pin of the IC and ηis the estimated or actual converter efficiency. (1)
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ONON2VOUT
2VOUT1VOUT
SW
ON
2VOUT1VOUT
2VOUTON
IN
ON
ON
IN
ON
2VOUT1VOUT
2VOUT
OUT
ON
ON
IN
CR 1
RRR
T
1
f
tRR R
T
t
V
C
R
V
tRR R
V
C
R
V
u
u
uu
u
u
u
t
iL (t)
ûiL-PP
IL-MAX
IL-MIN
IL
0
T
tOFF
tON = DT
TPS92640
,
TPS92641
SNVS902A OCTOBER 2012REVISED OCTOBER 2015
www.ti.com
Feature Description (continued)
Figure 14. Ideal CCM Buck Converter Inductor Current ILWaveform
7.3.2 Switching Frequency
The on-time is determined based on the external resistor (RON) connected between RON and VIN pins in
combination with a capacitor (CON) between RON and GND pins. The input voltage and the RON resistor set the
current sourced into the RON capacitor which governs the ramp speed. The ramp threshold is proportional to
scaled down feedback of VOUT at VOUT pin. The proportionality of VOUT is set by an external resistor divider
(RVOUT1, RVOUT2) from VOUT. The switching frequency, fSW can be calculated based on on-time and off-time using
Equation 2.
(2)
Even though the on-time control is quasi-hysteretic, the input and output voltage proportionality creates a nearly
constant switching frequency over the entire operating range. Quasi-hysteretic control minimizes the control loop
compensation necessary in many switching regulators, simplifying the design process. It also mitigates current
mode instability (also known as sub-harmonic oscillation) found in standard fixed frequency current mode control
when operating near or above 50% duty cycle. The inductor current sensing and averaging mechanism in the
valley detection control loop provides highly accurate LED current regulation over the entire operating range and
temperature.
7.3.3 Average LED Current
Average LED current regulation is set using a sense resistor in series with the LEDs. The internal error-amplifer
regulates the voltage across the sense resistor (VCS) to the IADJ voltage divided by 10. The error amplifier input
offset voltage has been minimized using auto-zero calibration technique as shown in . In this chopping scheme,
the noninverting and inverting inputs and outputs change polarity every switching cycle to cancel the offset,
providing near zero input offset voltage.
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iL
t
DT
T
'iL
'vOUT
VOUT
t
10
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VIADJ
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clk1b
CCOMP
clk1
clk1
clk1b
9R R
CS
IADJ Adder
COMP
TPS92640
,
TPS92641
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SNVS902A OCTOBER 2012REVISED OCTOBER 2015
Feature Description (continued)
Figure 15. Working Principle of the Chopper OTA to Minimize Input Offset Voltage
IADJ can be set to any value up to 2.54 V by connecting it to VREF through a resistor divider for static output
current settings. IADJ can also be used to change the regulation point if connected to a controlled voltage source
or potentiometer to provide analog dimming. It is also possible to configure IADJ to be used for thermal foldback
functions.
(3)
(4)
7.3.4 Analog Dimming and True-Zero Operation
In traditional Buck converters, discontinuous conduction mode (DCM) operation of inductor current results in loss
of linearity at low dimming levels and limits the analog dimming range. When using TPS92640 and TPS92641
devices to implement synchronous buck converter, the inductor current is forced to maintain continuous
conduction mode (CCM). As a result, it is possible to maintain linearity and achieve true-zero LED current
operation with respect to analog dimming command. For true zero application, an external capacitor is required
across the LED string to provide a negative current path for the inductor current loop. Figure 16 shows the
inductor current (IL) and output voltage (VOUT) waveform for a buck converter operating at true zero average
current level.
Figure 16. True Zero CCM Buck Converter Inductor Current ILand Output Voltage VOUT Waveform
In true zero application (VIADJ=0 V), there will be a certain amount of ILED passing the LEDs even though the
average inductor current is well-regulated at 0-A set-point. The shaped area in Figure 17 shows the current that
will pass through the LED string (iLED).
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FOUTOFF
CSF
CSF
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iLED
ILED = 0A
TPS92640
,
TPS92641
SNVS902A OCTOBER 2012REVISED OCTOBER 2015
www.ti.com
Feature Description (continued)
Figure 17. Output Current Waveform in True Zero Application with VIADJ =0V
An external resistor, ROFF as shown in Figure 18 is recommended from VOUT to CS to shunt the positive current
ripple while maintaining the operation of error amplifier to cancel input offset voltage. The shunt current (IOFF)
should be at least half of the output current ripple to ensure proper operation.
(5)
Figure 18. ROFF for True Zero Application
The resistor ROFF also impacts the start-up behavior of the circuit as it creates an DC shift in the voltage sensed
at CS pin. To ensure proper start-up sequence and monotonic LED current behavior, the voltage V'CS should
exceed a threshold voltage based on the native offset of the error amplifier before VOUT exceeding the LED
forward voltage, VLED. Assuming a worst case native off-set (non-chopping) of error amplifier to be less than ±10
mV, the voltage V'CS must be greater than this threshold to initiate switching and auto-zero operation. Therefore,
ROFF should be sized to also meet following condition.
(6)
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LEDDIMLED_DIM IDI u
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I5.0
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minR
TPS92640
,
TPS92641
www.ti.com
SNVS902A OCTOBER 2012REVISED OCTOBER 2015
Feature Description (continued)
To conclude, an external resistor (ROFF) from VOUT to CS pin is required for true zero application, where ROFF
should be:
(7)
7.3.5 Undervoltage Lockout (UVLO)
The UDIM pin of the TPS92640 and TPS92641 devices is a dual function input that features an accurate 1.276-V
threshold with programmable hysteresis. This pin functions as both the PWM dimming input of the LEDs and as
an input UVLO with built-in hysteresis. When the pin voltage rises and exceeds the 1.276-V threshold, 21 µA
(typical) of current is driven out of the UDIM pin into the resistor divider (RUDIM1, RUDIM2) providing programmable
hysteresis. The UVLO turnon threshold, VTURN-ON, is defined using Equation 8.
(8)
Once the input voltage is above VTURN_ON, the current source is active and the UVLO hysteresis is determined by
Equation 9.
(9)
When using the UDIM pin for UVLO and PWM dimming concurrently, the UVLO circuit can have an extra resistor
(RUDIM3) to set the hysteresis. This allows the standard resistor divider to have smaller values minimizing delays
that can incur with additional external PWM dimming circuitry. In general, at least 3 V of hysteresis is preferable
when PWM dimming if operating near the UVLO threshold. Under these conditions, the UVLO hysteresis is
defined using Equation 10.
(10)
7.3.6 PWM Dimming Using the UDIM Pin
The UDIM pin can be driven with a PWM signal, which controls the synchronous NFET operation. The brightness
of the LEDs can be varied by modulating the duty cycle (DDIM) of this signal using a Schottky diode with anode
connected to UDIM pin, as shown in Figure 13.
Figure 19. LED Current During UDIM Pin PWM Dimming
Figure 19 shows the LED current waveform during PWM dimming where duty cycle (DDIM) is the percentage of
the dimming period (TDIM) that the synchronous NFETs are switching. For the remainder of TDIM, the NFETs are
disabled. The resulting dimmed LED current (IDIM_LED) is:
(11)
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tOFF
iLED (t)
ILED-MAX
t
IDIM-LED
0
DDIM x TDIM
TDIM
ILED
TPS92640
,
TPS92641
SNVS902A OCTOBER 2012REVISED OCTOBER 2015
www.ti.com
Feature Description (continued)
7.3.7 External Shunt FET PWM Dimming
Extremely high dimming range and linearity can be achieved by using TPS92641 device for Shunt FET dimming
operation with SDIM and SDRV pin. When higher frequency and time resolution PWM dimming signal is applied
to the SDIM pin, the SDRV pin provides an inverted signal of the same frequency and duty cycle that can be
used to drive the gate of a Shunt NFET directly across the LED load. Because the output voltage will go to near
zero when the Shunt NFET is turned on, the internal on-timer at the RON pin will switch to a fixed minimum on-
time during the off-time of the dimming cycle. This method keeps the inductor current slewed up and the
converter regulating, without the presence of extremely high switching frequencies. During the on-time of the
dimming cycle, the converter will switch in its regular fashion with the programmed on-time at the RON pin. An
internal resistor pulls the SDIM pin to logic high if left open. In this case, the SDRV driver will be off.
Figure 20. Ideal LED Current During Shunt FET PWM Dimming
Figure 20 shows the ideal LED current waveform during Shunt FET PWM dimming which is very similar to the
internal PWM dimming described and shown previously except with much faster rise and fall of the LED current.
With this method, only the speed of the parallel Shunt NFET limits the dimming frequency and dimming duty
cycle.
7.3.8 VCC Regulation and Start-up
The TPS92640 and TPS92641 devices include a high voltage, low-dropout bias regulator. When power is
applied, the regulator is enabled and sources current into an external capacitor (CVCC) connected to the VCC pin.
The recommended bypass capacitance for the VCC regulator is 2.2 µF to 3.3 µF. This capacitor should be rated
for 10 V or greater and an X7R dielectric ceramic is recommended. The output of the VCC regulator is monitored
by an internal UVLO circuit that protects the device from attempting to operate with insufficient supply voltage,
and the supply current is also internally current-limited. When VIN is close or lower than 8.5 V, the regulator will
enter the by-pass mode and the VCC will closely follow VIN. This linear regulator is the primary heat source
generator of the device. The amount of heat generated is a function of input voltage (VIN), switching frequency
(FSW) and the characteristics of the power MOSFET used. The thermal handling capability of the device imposes
a limit on the maximum switching frequency can be used, especially when VIN is higher than 48 V and high
current power MOSFET is used.
7.3.9 Precision Reference
The device includes a precision 3-V reference. This can be used in conjunction with a resistor divider to set
voltage levels for the IADJ pin and other external circuitry requiring a reference. It can also be used to supply
current to low power micro-controllers. The source current capability from VREF pin is internally limited 2.1 mA.
For the VREF regulator, TI recommends a bypass capacitance from 0.1 µF to 1 µF.
7.3.10 Control Loop Compensation
Compensating the TPS92640 and TPS92641 devices is relatively simple for most applications. The only
compensation needed is a compensation capacitor, CCOMP across the COMP pin and ground to place a low-
frequency dominant pole in the system. The pole must be placed low enough to ensure adequate phase margin
at the crossover frequency. For most of the applications, CCOMP of 100 nF to 470 nF is good enough.
Additionally, TI recommends a high quality ceramic capacitor with X7R dielectric rated for 25 V.
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¸
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u 2VOUT
2VOUT1VOUT
ON_OVP RRR
V05.3V
J270sJ
HG
LG
J270sJ
TPS92640
,
TPS92641
www.ti.com
SNVS902A OCTOBER 2012REVISED OCTOBER 2015
Feature Description (continued)
7.3.11 Overcurrent Protection
The TPS92640 and TPS92641 devices has overcurrent protection to protect the high side NFET (HS-NFET)
along with the rest of the system from overcurrent conditions. This peak current limit of 1.28 V (with VIN = 85 V at
room temperature) is sensed across the high side FET RDS-ON (from SW to VIN). If the threshold is reached or
exceeded, HS-NFET will turn off and the low side NFET (LS-NFET) will turn on for approximately 800 ns. Then
HS-NFET will turn on again, if the threshold is still reached or exceeded, both FETs are shutoff for 270-µs
typical. Figure 21 shows the waveforms of HG and LG under overcurrent protection.
Figure 21. HG and LG Waveforms Under Overcurrent Protection
7.3.12 Overvoltage Protection (OVP)
The TPS92640 and TPS92641 devices have programmable overvoltage protection by using the resistor divider
at the VOUT pin. The OVP limit, VOVP_ON, is defined using Equation 12.
(12)
If the output voltage reaches VOVP_ON, the HG, LG and SDRV pins are pulled low to prevent damage to the LEDs
or the rest of the circuit. The OVP circuit has a fixed hysteresis of 100 mV before the driver attempts to switch
again.
7.3.13 Boot Undervoltage Lockout (UVLO)
The BOOT UVLO circuit is implemented to ensure proper operation of the high-side gate driver under all
operating conditions. The switching operation is commenced once the BOOT voltage exceeds 3.4 V above the
SW pin. Comparator hysteresis of 1.8 V is included to prevent false tripping due to high-frequency switching
noise. When the BOOT falls below the low voltage threshold (1.6 V typical), the high side NFET is disabled by
pulling HG pin to SW pin. The next turnon transition of low-side NFET pulls SW pin down and charges the BOOT
capacitor (CBOOT) through VCC. Normal operation is commenced once BOOT capacitor (CBOOT) is charged
above BOOT UVLO turnon threshold of 3.4 V.
The boostrap circuit behavior impacts the circuit behavior near dropout (VIN= VOUT) conditions. A minimum off-
time is implemented to restrict the maximum duty cycle and maintain charge on the external BOOT capacitor,
CBOOT. As the input voltage, VIN, approachs close to the output voltage, VOUT, the output current will fall with the
switching frequency, as in conventional Buck regulator. This behavior ensures smooth operation in and out of
dropout region while ensuring proper operation of high side gate driver and bootstrap circuit.
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7.4 Device Functional Modes
7.4.1 Low Power Shutdown Using the UDIM Pin
The TPS92640 and TPS92641 devices can be placed into a low power shutdown mode by grounding the UDIM
pin directly (any voltage below 370 mV) for more than 13 ms (typical).
7.4.2 Thermal Shutdown
Internal thermal shutdown circuitry is provided to protect the device in the event that the maximum junction
temperature is exceeded. The threshold for thermal shutdown is 165°C with a 20°C hysteresis (both values
typical). During thermal shutdown the NFETs and drivers are disabled.
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